.gitignore

@@ -88,7 +88,6 @@ util/*/.dependencies
 util/*/.test
 util/amdfwtool/amdfwtool
 util/archive/archive
-util/bimgtool/bimgtool
 util/bincfg/bincfg
 util/board_status/board-status
 util/bucts/bucts
@@ -118,6 +117,7 @@ util/msrtool/msrtool
 util/nvramtool/.dependencies
 util/nvramtool/nvramtool
 util/optionlist/Options.wiki
+util/pmh7tool/pmh7tool
 util/romcc/build
 util/runfw/googlesnow
 util/superiotool/superiotool

.gitmodules

@@ -1,39 +1,44 @@
 [submodule "3rdparty/blobs"]
 	path = 3rdparty/blobs
-	url = https://github.com/coreboot/blobs.git
+	url = https://review.coreboot.org/blobs.git
 	update = none
 	ignore = dirty
 [submodule "util/nvidia-cbootimage"]
 	path = util/nvidia/cbootimage
-	url = https://github.com/coreboot/nvidia-cbootimage.git
+	url = https://review.coreboot.org/nvidia-cbootimage.git
 [submodule "vboot"]
 	path = 3rdparty/vboot
-	url = https://github.com/coreboot/vboot.git
+	url = https://review.coreboot.org/vboot.git
 [submodule "arm-trusted-firmware"]
 	path = 3rdparty/arm-trusted-firmware
-	url = https://github.com/coreboot/arm-trusted-firmware.git
+	url = https://review.coreboot.org/arm-trusted-firmware.git
 [submodule "3rdparty/chromeec"]
 	path = 3rdparty/chromeec
-	url = https://github.com/coreboot/chrome-ec.git
+	url = https://review.coreboot.org/chrome-ec.git
 [submodule "libhwbase"]
 	path = 3rdparty/libhwbase
-	url = https://github.com/coreboot/libhwbase.git
+	url = https://review.coreboot.org/libhwbase.git
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
-	url = https://github.com/coreboot/libgfxinit.git
+	url = https://review.coreboot.org/libgfxinit.git
 [submodule "3rdparty/fsp"]
 	path = 3rdparty/fsp
-	url = https://github.com/coreboot/fsp.git
+	url = https://review.coreboot.org/fsp.git
 	update = none
 	ignore = dirty
 [submodule "opensbi"]
 	path = 3rdparty/opensbi
-	url = https://github.com/coreboot/opensbi.git
+	url = https://review.coreboot.org/opensbi.git
 [submodule "intel-microcode"]
 	path = 3rdparty/intel-microcode
-	url = https://github.com/coreboot/intel-microcode.git
+	url = https://review.coreboot.org/intel-microcode.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/ffs"]
 	path = 3rdparty/ffs
-	url = https://github.com/coreboot/ffs.git
+	url = https://review.coreboot.org/ffs.git
+[submodule "3rdparty/amd_blobs"]
+	path = 3rdparty/amd_blobs
+	url = https://review.coreboot.org/amd_blobs.git
+	update = none
+	ignore = dirty

CHANGELOG.md

@@ -12,6 +12,14 @@ official [coreboot repository](https://review.coreboot.org/cgit/coreboot.git)
 Please use [pce-fw-builder](https://github.com/pcengines/pce-fw-builder)
 
 ## [Unreleased]
+
+## [v4.11.0.1] - 2019-12-08
+### Changed
+- rebased with official coreboot repository commit 9f56eed
+
+### Fixed
+- issue with temperature not showing on pfSense dashboard
+
 ## [v4.10.0.3] - 2019-11-08
 ### Changed
 - rebased with official coreboot repository commit 2d90cb1
@@ -348,7 +356,8 @@ redundant code which was similar for APU2/3/5 boards.
 - turn off D4 and D5 leds on boot
 - enable power on after power failure
 
-[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.10.0.3...develop
+[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.11.0.1...develop
+[v4.11.0.1]: https://github.com/pcengines/coreboot/compare/v4.10.0.3...v4.11.0.1
 [v4.10.0.3]: https://github.com/pcengines/coreboot/compare/v4.10.0.2...v4.10.0.3
 [v4.10.0.2]: https://github.com/pcengines/coreboot/compare/v4.10.0.1...v4.10.0.2
 [v4.10.0.1]: https://github.com/pcengines/coreboot/compare/v4.10.0.0...v4.10.0.1

Documentation/arch/riscv/index.md

@@ -19,6 +19,9 @@ On entry to a stage or payload (including SELF payloads),
 * all harts are running.
 * A0 is the hart ID.
 * A1 is the pointer to the Flattened Device Tree (FDT).
+* A2 contains the additional program calling argument:
+  - cbmem_top for ramstage
+  - the address of the payload for opensbi
 
 ## Additional payload handoff requirements
 The location of cbmem should be placed in a node in the FDT.

Documentation/contributing/project_ideas.md

@@ -64,7 +64,7 @@ across architectures.
 ### Mentors
 * Timothy Pearson <tpearson@raptorengineering.com>
 
-## Support QEMU AArch64 or MIPS
+## Support QEMU AArch64
 Having QEMU support for the architectures coreboot can boot helps with
 some (limited) compatibility testing: While QEMU generally doesn't need
 much hardware init, any CPU state changes in the boot flow will likely
@@ -105,7 +105,7 @@ would help to ensure code quality and make the runtime code more robust.
 ### Mentors
 * Werner Zeh <werner.zeh@gmx.net>
 
-## Port payloads to ARM, AArch64, MIPS or RISC-V
+## Port payloads to ARM, AArch64 or RISC-V
 While we have a rather big set of payloads for x86 based platforms, all other
 architectures are rather limited. Improve the situation by porting a payload
 to one of the platforms, for example GRUB2, U-Boot (the UI part), Tianocore,

Documentation/drivers/index.md

@@ -5,3 +5,4 @@ and plugin devices, significantly reducing integration complexity and
 they allow to easily reuse existing code accross platforms.
 
 * [IPMI KCS](ipmi_kcs.md)
+* [SMMSTORE](smmstore.md)

Documentation/drivers/smmstore.md

@@ -0,0 +1,123 @@
+# SMM based flash storage driver
+
+This documents the API exposed by the x86 system management based
+storage driver.
+
+## SMMSTORE
+
+SMMSTORE is a SMM mediated driver to read from, write to and erase a
+predefined region in flash. It can be enabled by setting
+`CONFIG_SMMSTORE=y` in menuconfig.
+
+This can be used by the OS or the payload to implement persistent
+storage to hold for instance configuration data, without needing
+to implement a (platform specific) storage driver in the payload
+itself.
+
+The API provides append-only semantics for key/value pairs.
+
+## API
+
+### Storage region
+
+By default SMMSTORE will operate on a separate FMAP region called
+`SMMSTORE`. The default generated FMAP will include such a region.
+On systems with a locked FMAP, e.g. in an existing VBOOT setup
+with a locked RO region, the option exists to add a cbfsfile
+called `smm_store` in the `RW_LEGACY` (if CHROMEOS) or in the
+`COREBOOT` FMAP regions. It is recommended for new builds using
+a handcrafted FMD that intend to make use of SMMSTORE to include a
+sufficiently large `SMMSTORE` FMAP region. It is recommended to
+align the `SMMSTORE` region to 64KiB for the largest flash erase
+op compatibility.
+
+When a default generated FMAP is used the size of the FMAP region
+is equal to `CONFIG_SMMSTORE_SIZE`. UEFI payloads expect at least
+64KiB. Given that the current implementation lacks a way to rewrite
+key-value pairs at least a multiple of this is recommended.
+
+### generating the SMI
+
+SMMSTORE is called via an SMI, which is generated via a write to the
+IO port defined in the smi_cmd entry of the FADT ACPI table. `%al`
+contains `APM_CNT_SMMSTORE=0xed` and is written to the smi_cmd IO
+port. `%ah` contains the SMMSTORE command. `%ebx` contains the
+parameter buffer to the SMMSTORE command.
+
+### Return values
+
+If a command succeeds, SMMSTORE will return with
+`SMMSTORE_RET_SUCCESS=0` on `%eax`. On failure SMMSTORE will return
+`SMMSTORE_RET_FAILURE=1`. For unsupported SMMSTORE commands
+`SMMSTORE_REG_UNSUPPORTED=2` is returned.
+
+**NOTE1**: The caller **must** check the return value and should make
+no assumption on the returned data if `%eax` does not contain
+`SMMSTORE_RET_SUCCESS`.
+
+**NOTE2**: If the SMI returns without changing `%ax` assume that the
+SMMSTORE feature is not installed.
+
+### Calling arguments
+
+SMMSTORE supports 3 subcommands that are passed via `%ah`, the additional
+calling arguments are passed via `%ebx`.
+
+**NOTE**: The size of the struct entries are in the native word size of
+smihandler. This means 32 bits in almost all cases.
+
+
+#### - SMMSTORE_CMD_CLEAR = 1
+
+This clears the `SMMSTORE` storage region. The argument in `%ebx` is
+unused.
+
+#### - SMMSTORE_CMD_READ = 2
+
+The additional parameter buffer `%ebx` contains a pointer to
+the following struct:
+
+```C
+struct smmstore_params_read {
+	void *buf;
+	ssize_t bufsize;
+};
+```
+
+INPUT:
+- `buf`: is a pointer to where the data needs to be read
+- `bufsize`: is the size of the buffer
+
+OUTPUT:
+- `buf`
+- `bufsize`: returns the amount of data that has actually been read.
+
+#### - SMMSTORE_CMD_APPEND = 3
+
+SMMSTORE takes a key-value approach to appending data. key-value pairs
+are never updated, they are always appended. It is up to the caller to
+walk through the key-value pairs after reading SMMSTORE to find the
+latest one.
+
+The additional parameter buffer `%ebx` contains a pointer to
+the following struct:
+
+```C
+struct smmstore_params_append {
+	void *key;
+	size_t keysize;
+	void *val;
+	size_t valsize;
+};
+```
+
+INPUT:
+- `key`: pointer to the key data
+- `keysize`: size of the key data
+- `val`: pointer to the value data
+- `valsize`: size of the value data
+
+## External links
+
+* [A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI](https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_bios_implementing_uefi_authenticated_variables_in_smm_with_edkii.pdf)
+Note, this differs significantly from coreboot's implementation.

Documentation/mainboard/facebook/fbg1701.md

@@ -14,8 +14,7 @@ Mainboard menu.
 
 This board currently requires:
 fsp blob	3rdparty/fsp/BraswellFspBinPkg/FspBin/BSWFSP.fd
-Microcode	Intel Braswell cpuid 1046C4 version 410
-		(Used pre-built binary retrieved from Intel site)
+Microcode	3rdparty/intel-microcode/intel-ucode/06-4c-04
 
 ## Flashing coreboot
 

Documentation/mainboard/facebook/monolith.md

@@ -0,0 +1,78 @@
+# Facebook Monolith
+
+This page describes how to run coreboot on the Facebook Monolith.
+
+Please note: the coreboot implementation for this boards is in it's Alpha state and isn't fully 
+tested yet.
+
+## Required blobs
+
+This board currently requires:
+fsp blobs	3rdparty/fsp/KabylakeFspBinPkg/Fsp_M.fd
+		3rdparty/fsp/KabylakeFspBinPkg/Fsp_S.fd
+
+Microcode	3rdparty/intel-microcode/intel-ucode
+
+## Flashing coreboot
+
+### Internal programming
+
+The SPI flash can be accessed using [flashrom].
+
+### External programming
+
+The system has an internal flash chip which is a 16 MiB soldered SOIC-8 chip.
+Specifically, it's a Winbond W25Q128JVSIQ (3.3V).
+
+The system has an external flash chip which is a 16 MiB soldered SOIC-8 chip.
+Specifically, it's a Winbond W25Q128JVSIM (3.3V).
+
+Flashing of these devices is very difficult, disassembling the system destroys the cooling
+solution. Wires need to be connected to be able to flash using an external programmer.
+
+## Known issues
+
+- None
+
+## Untested
+
+- Hardware monitor
+- SDIO
+- Full Embedded Controller support
+- eMMC
+- SATA
+
+## Working
+
+- USB
+- Gigabit Ethernet
+- Graphics (Using FSP GOP)
+- flashrom
+- PCIe
+- EC serial port
+- SMBus
+- Initialization with FSP
+- SeaBIOS payload (commit a5cab58e9a3fb6e168aba919c5669bea406573b4)
+- TianoCore payload (commit a5cab58e9a3fb6e168aba919c5669bea406573b4)
+
+All of the above has been briefly tested by booting Linux from the TianoCore payload.
+SeaBios has been checked to the extend that it runs to the boot selection and provides display
+output.
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| SoC              | Intel Kaby Lake U                                 |
++------------------+--------------------------------------------------+
+| CPU              | Intel i3-7100U                                   |
++------------------+--------------------------------------------------+
+| Super I/O, EC    | ITE8256                                          |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel Management Engine                          |
++------------------+--------------------------------------------------+
+```
+
+[W25Q128JVSIQ]: https://www.winbond.com/resource-files/w25q128jv%20revf%2003272018%20plus.pdf
+[W25Q128JVSIM]: https://www.winbond.com/resource-files/w25q128jv%20dtr%20revb%2011042016.pdf
+[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/index.md

@@ -32,6 +32,7 @@ The boards in this section are not real mainboards, but emulators.
 ## Facebook
 
 - [FBG-1701](facebook/fbg1701.md)
+- [Monolith](facebook/monolith.md)
 
 ## Foxconn
 
@@ -95,10 +96,6 @@ The boards in this section are not real mainboards, but emulators.
 
 - [T440p](lenovo/t440p.md)
 
-## Portwell
-
-- [PQ7-M107](portwell/pq7-m107.md)
-
 ## MSI
 
 - [MS-7707](msi/ms7707/ms7707.md)

Documentation/mainboard/portwell/pq7-m107.md

@@ -14,8 +14,7 @@ menu.
 
 This board currently requires:
 fsp blob	3rdparty/fsp/BraswellFspBinPkg/FspBin/BSWFSP.fd
-Microcode	Intel Braswell cpuid 1046C4 version 410
-		(Used pre-built binary retrieved from Intel site)
+Microcode	3rdparty/intel-microcode/intel-ucode/06-4c-04
 
 ## Flashing coreboot
 

Documentation/mainboard/supermicro/x10slm-f.md

@@ -68,7 +68,7 @@ region is not readable even by the host.
 The main firmware flash chip is an SOIC-8 package located near the CMOS
 battery and SATA ports. It should come with a sticker attached that
 states the firmware revision (e.g. "X10SLH 4.424"). The chip model is
-an N25Q128A, and the datasheet can be found [here][N25Q128A].
+an N25Q128A ([datasheet][N25Q128A]).
 
 As with [internal programming](#internal-programming), [flashrom] works
 reliably:
@@ -87,8 +87,7 @@ way without issue.
 
 This board has an ASPEED [AST2400], which has BMC functionality. The
 BMC firmware resides in a 32 MiB SOIC-16 chip just above the [AST2400].
-This chip is an MX25L25635F, whose datasheet can be found
-[here][MX25L25635F].
+This chip is an MX25L25635F ([datasheet][MX25L25635F]).
 
 ### Removing the BMC functionality