CHANGELOG.md

@@ -13,6 +13,23 @@ Please use [pce-fw-builder](https://github.com/pcengines/pce-fw-builder)
 
 ## [Unreleased]
 
+## [v4.11.0.6] - 2020-04-26
+### Changed
+- rebased with official coreboot repository commit d6f7ec5
+- [updated sortbootorder to v4.6.18](https://github.com/pcengines/sortbootorder/blob/master/CHANGELOG.md#v4618---2020-04-26)
+- reverted changes to ACPI CPU definitions causing BSD systems to
+  [not probe CPU frequency driver](https://github.com/pcengines/coreboot/issues/389)
+- reverted changes with PCIe reset logic causing
+  [mPCIe2 slot connected modules to not appear in OS](https://github.com/pcengines/coreboot/issues/388)
+
+### Added
+- PCIe power management features runtime configuration
+- [IOMMU IVRS generation expanded with IVHD type 11h for newer Xen](https://review.coreboot.org/c/coreboot/+/40042)
+
+### Fixed
+- [memtest hang on apu1](https://github.com/pcengines/coreboot/issues/395)
+- [TPM2 detection on FreeBSD 12.1](https://review.coreboot.org/c/coreboot/+/39699)
+
 ## [v4.11.0.5] - 2020-03-27
 ### Changed
 - rebased with official coreboot repository commit 90557f4
@@ -395,7 +412,8 @@ redundant code which was similar for APU2/3/5 boards.
 - turn off D4 and D5 leds on boot
 - enable power on after power failure
 
-[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.11.0.5...develop
+[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.11.0.6...develop
+[v4.11.0.6]: https://github.com/pcengines/coreboot/compare/v4.11.0.5...v4.11.0.6
 [v4.11.0.5]: https://github.com/pcengines/coreboot/compare/v4.11.0.4...v4.11.0.5
 [v4.11.0.4]: https://github.com/pcengines/coreboot/compare/v4.11.0.3...v4.11.0.4
 [v4.11.0.3]: https://github.com/pcengines/coreboot/compare/v4.11.0.2...v4.11.0.3

Documentation/mainboard/asrock/h110m-dvs.md

@@ -31,8 +31,6 @@ make distclean
 touch .config
 ./util/scripts/config --enable VENDOR_ASROCK
 ./util/scripts/config --enable BOARD_ASROCK_H110M_DVS
-./util/scripts/config --enable CONFIG_ADD_FSP_BINARIES
-./util/scripts/config --enable CONFIG_FSP_USE_REPO
 ./util/scripts/config --set-str REALTEK_8168_MACADDRESS "xx:xx:xx:xx:xx:xx"
 make olddefconfig
 ```

Documentation/mainboard/hp/8760w.md

@@ -2,6 +2,9 @@
 
 This page describes how to run coreboot on the [HP EliteBook 8760w].
 
+The coreboot code for this laptop is still not merged, you need to
+checkout the [code on gerrit] to build coreboot for the laptop.
+
 ## Flashing coreboot
 
 ```eval_rst
@@ -29,7 +32,7 @@ This page describes how to run coreboot on the [HP EliteBook 8760w].
 ## Required proprietary blobs
 
 - Intel Firmware Descriptor, ME and GbE firmware
-- EC: please read [EliteBook Series](elitebook_series)
+- EC: please read [HP Laptops with KBC1126 Embedded Controller](hp_kbc1126_laptops)
 
 ## Flashing instructions
 
@@ -80,3 +83,4 @@ clip to read and flash the chip.
 ```
 
 [HP EliteBook 8760w]: https://support.hp.com/us-en/product/hp-elitebook-8760w-mobile-workstation/5071180
+[code on gerrit]: https://review.coreboot.org/c/coreboot/+/30936

Documentation/mainboard/hp/elitebook_series.md → Documentation/mainboard/hp/hp_kbc1126_laptops.md

@@ -1,13 +1,14 @@
-# HP EliteBook series
+# HP Laptops with KBC1126 Embedded Controller
 
 This document is about HP EliteBook series laptops up to Ivy Bridge era
 which use SMSC KBC1126 as embedded controller.
 
-## EC
+SMSC KBC1126 (and older similar chips like KBC1098) has been used in
+HP EliteBooks for many generations.  BIOS and EC firmware share an SPI
+flash chip in these laptops, so we need to put firmware blobs for the
+EC to the coreboot image.
 
-SMSC KBC1098/KBC1126 has been used in HP EliteBooks for many generations.
-They use similar EC firmware that will load other code and data from the
-SPI flash chip, so we need to put some firmware blobs to the coreboot image.
+## EC firmware extraction and coreboot building
 
 The following document takes EliteBook 2760p as an example.
 
@@ -32,27 +33,24 @@ Chipset --->
       (2760p-fw2.bin) KBC1126 filename #2 path and filename
 ```
 
-## Super I/O
+## Porting guide for HP laptops with KBC1126
 
-EliteBook 8000 series laptops have SMSC LPC47n217 Super I/O to provide
-a serial port and a parallel port, you can debug the laptop via this
-serial port.
-
-## porting
-
-To port coreboot to an HP EliteBook laptop, you need to do the following:
+To port coreboot to an HP laptop with KBC1126, you need to do the
+following:
 
 - select Kconfig option `EC_HP_KBC1126`
-- select Kconfig option `SUPERIO_SMSC_LPC47N217` if there is LPC47n217 Super I/O
+- select Kconfig option `SUPERIO_SMSC_LPC47N217` if there is LPC47n217
+  Super I/O, usually in EliteBook 8000 series, which can be used for
+  debugging via serial port
 - initialize EC and Super I/O in romstage
 - add EC and Super I/O support to devicetree.cb
 
 To get the related values for EC in devicetree.cb, you need to extract the EFI
 module EcThermalInit from the vendor UEFI firmware with [UEFITool]. Usually,
 `ec_data_port`, `ec_cmd_port` and `ec_ctrl_reg` has the following values:
 
-- For xx60 series: 0x60, 0x64, 0xca
-- For xx70 series: 0x62, 0x66, 0x81
+- For EliteBook xx60 series: 0x60, 0x64, 0xca
+- For EliteBook xx70 series: 0x62, 0x66, 0x81
 
 You can use [radare2] and the following [r2pipe] Python script to find
 these values from the EcThermalInit EFI module:

Documentation/mainboard/index.md

@@ -58,7 +58,7 @@ The boards in this section are not real mainboards, but emulators.
 
 ### EliteBook series
 
-- [EliteBook common](hp/elitebook_series.md)
+- [HP Laptops with KBC1126 EC](hp/hp_kbc1126_laptops.md)
 - [EliteBook 8760w](hp/8760w.md)
 
 ## Intel
@@ -75,10 +75,6 @@ The boards in this section are not real mainboards, but emulators.
 - [T4xx common](lenovo/t4xx_series.md)
 - [X2xx common](lenovo/x2xx_series.md)
 
-## Libretrend
-
-- [LT1000](libretrend/lt1000.md)
-
 ### Arrandale series
 
 - [T410](lenovo/t410.md)
@@ -107,6 +103,10 @@ The boards in this section are not real mainboards, but emulators.
 
 - [T440p](lenovo/t440p.md)
 
+## Libretrend
+
+- [LT1000](libretrend/lt1000.md)
+
 ## MSI
 
 - [MS-7707](msi/ms7707/ms7707.md)

Documentation/mainboard/lenovo/Ivy_Bridge_series.md

@@ -76,3 +76,18 @@ region. The update is then written into the EC once.
 
 [fl]: flashlayout_Ivy_Bridge.svg
 
+## Reducing Intel Managment Engine firmware size
+
+It is possible to reduce the Intel ME firmware size to free additional
+space for the `bios` region. This is usually referred to as *cleaning the ME* or
+*stripping the ME*.
+After reducing the Intel ME firmware size you must modify the original IFD,
+[split the resulting coreboot ROM](#splitting-the-coreboot-rom) and then write
+each ROM using an [external programmer].
+Have a look at [me_cleaner] for more information.
+
+Tests on Lenovo W530 showed no issues with a stripped and shrunken ME firmware.
+
+
+[me_cleaner]: ../../northbridge/intel/sandybridge/me_cleaner.md
+[external programmer]: ../../flash_tutorial/index.md

Documentation/mainboard/lenovo/Sandy_Bridge_series.md

@@ -47,11 +47,11 @@ region. The update is then written into the EC once.
 ## Reducing Intel Managment Engine firmware size
 
 It is possible to reduce the Intel ME firmware size to free additional
-space for the `bios` region. This is usually refered to as *cleaning the ME* or
+space for the `bios` region. This is usually referred to as *cleaning the ME* or
 *stripping the ME*.
 After reducing the Intel ME firmware size you must modify the original IFD
 and then write a full ROM using an [external programmer].
-Have a look at the [me_cleaner] for more information.
+Have a look at [me_cleaner] for more information.
 
 Tests on Lenovo X220 showed no issues with a stripped ME firmware.
 

Documentation/mainboard/lenovo/ivb_internal_flashing.md

@@ -102,7 +102,7 @@ Replace the last line (`command.com`) with this (change path to the
 
 Save the file, then unmount the partition:
 
-    sudo unmount /mnt
+    sudo umount /mnt
 
 Write this image to a USB drive (replace `/dev/sdX` with your USB drive
 device name):

Documentation/mainboard/lenovo/t440p.md

@@ -31,8 +31,6 @@ the laptop able to power on.
 ## Known Issues
 
 - No audio output when using a headphone
-- The touchpad is misconfigured, the 3 keys on top are all identified
-  as left button
 - Cannot get the mainboard serial number from the mainboard: the OEM
   UEFI firmware gets the serial number from an "emulated EEPROM" via
   I/O port 0x1630/0x1634, but it's still unknown how to make it work

Documentation/releases/coreboot-4.12-relnotes.md

@@ -10,6 +10,69 @@ notes.
 * The chip and board additions and removals will be updated right
   before the release, so those do not need to be added.
 
+Deprecations
+------------
+
+For the 4.12 release a few features on x86 became mandatory. These are
+relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK.
+
+### Relocatable ramstage
+
+Relocatable stages are a feature implemented only on x86, where stages
+can be relocated at runtime. This is used to place ramstage in a better
+location that does not collide with memory the OS or the payload tends
+to use. The rationale behind making this mandatory is that you always
+want cbmem to be cached so it's a good location to run ramstage from.
+It avoids using lower memory altogether so the OS can make use of it
+and no backing up needs to happen on S3 resume.
+
+### Postcar stage
+
+With Postcar stage tearing down Cache-as-Ram is done in a separate
+stage. This means that romstage has a clean program boundary and
+that all variables in romstage can be accessed via their linked
+addresses without runtime resolution. There is no need to link
+global and static variables via the CAR\_GLOBAL macro and no need
+to access them with car\_set/get\_var/ptr functions.
+
+### C\_ENVIRONMENT\_BOOTBLOCK
+
+Historically the bootblock on x86 platforms has been compiled with
+romcc. This means that the generated code only uses CPU registers
+and therefore no stack. This 20K+ LOC compiler is limited and hard
+to maintain and so is the code that one has to write in that
+environment. A different solution is to set up Cache-as-Ram in the
+bootblock and run GCC compiled code in the bootblock. The advantages
+are increased flexibility and consistency with other architectures as
+well as other stages: e.g. printing to console is possible and
+VBOOT can run before romstage, making romstage updatable via RW FMAP
+regions.
+
+### Platforms dropped from master
+
+The following platforms did not implement those feature are dropped
+from master to allow the master branch to move on:
+- AMDFAM10
+- all FSP1.0 platforms: BROADWELL_DE, FSP_BAYTRAIL, RANGELEY
+- VIA VX900
+- TODO (AMD?)
+
+In particular on FSP1.0 it is impossible to implement POSTCAR stage.
+The reason is that FSP1.0 relocates the CAR region to the HOB before
+returning to coreboot. This means that after FSP returns to coreboot
+accessing variables via their original address is not possible. One
+way of obtaining that behavior would be to set up Cache-as-Ram again
+(but with open source code) and copy the relocated data from the HOB
+there. This solution is deemed too hacky. Maybe a lesson can be
+learned from this: blobs should not interfere with the execution
+environment, as this makes proper integration much harder.
+
+### 4.11_branch
+
+Given that some platforms supported by FSP1.0 are being produced and
+popular, the 4.11 release was made into a branch in which further
+development can happen.
+
 Significant changes
 -------------------
 

Documentation/security/vboot/index.md

@@ -231,7 +231,7 @@ More details are available in `3rdparty/vboot/README`.
 #  The keys were made using the following command
 #
 #        3rdparty/vboot/scripts/keygeneration/create_new_keys.sh  \
-#                --4k --4k-root --output $PWD/keys
+#                --output $PWD/keys
 #
 #
 #  The "magic" numbers below are derived from the GBB section in

Documentation/soc/intel/fsp/index.md

@@ -45,6 +45,11 @@ those are fixed. If possible a workaround is described here as well.
   * Workaround: Disable internal UART manually after calling FSP
   * Issue on public tracker: [Issue 10]
 
+### CoffeeLakeFsp
+* Disabling the internal graphics causes a crash in FSP-M
+  * 7.0.68.40 and older version
+  * Workaround: Set "tconfig->PanelPowerEnable = 0"
+  * Issue on public tracker: [Issue 49]
 
 ## Open Source Intel FSP specification
 
@@ -72,4 +77,5 @@ those are fixed. If possible a workaround is described here as well.
 [Issue 22]: https://github.com/IntelFsp/FSP/issues/22
 [Issue 35]: https://github.com/IntelFsp/FSP/issues/35
 [Issue 41]: https://github.com/IntelFsp/FSP/issues/41
+[Issue 49]: https://github.com/IntelFsp/FSP/issues/49
 

Documentation/util.md

@@ -10,8 +10,6 @@ available targets. `bash`
 * __amdtools__ - A set of tools to compare extended) K8 memory
 settings. `Perl`
 * __archive__ - Concatenate files and create an archive `C`
-* __mksunxiboot__ - A simple tool to generate bootable image for sunxi
-platform. `C`
 * __autoport__ - Automated porting coreboot to Sandy Bridge/Ivy Bridge
 platforms `Go`
 * __bincfg__ - Compiler/Decompiler for data blobs with specs `Lex`
@@ -26,11 +24,11 @@ file `Python`
 	* _fmaptool_ - Converts plaintext fmd files into fmap blobs `C`
 	* _rmodtool_ - Creates rmodules `C`
 	* _ifwitool_ - For manipulating IFWI `C`
-* __cbmem__ - Cbmem console log reader `C`
-* __checklist__ - Board implementation checklist generator `Make`
-* __chromeos__ - These scripts can be used to extract System Agent
-reference code and other blobs (e.g. mrc.bin, refcode, VGA option roms)
-from a Chrome OS recovery image. `C`
+* __cbmem__ - CBMEM parser to read e.g. timestamps and console log `C`
+* __chromeos__ - These scripts can be used to access Chrome OS
+resources, for example to extract System Agent reference code and other
+blobs (e.g. mrc.bin, refcode, VGA option roms) from a Chrome OS
+recovery image. `C`
 * __crossgcc__ - A cross toolchain builder for -elf toolchains (ie. no
 libc support)
 * __docker__ - Dockerfiles for _coreboot-sdk_, _coreboot-jenkins-node_,
@@ -62,8 +60,6 @@ specified base and size `Python`
 	* _mbncat.py_ - Generate ipq8064 uber SBL `Python`
 	* *mbn_tools.py* - Contains all MBN Utilities for image
 generation `Python`
-* __k8resdump__ - This program will dump the IO/memory/PCI resources
-from the K8 memory controller `C`
 * __kbc1126__ - Tools used to dump the two blobs from the factory
 firmware of many HP laptops with 8051-based SMSC KBC1098/KBC1126
 embedded controller and insert them to the firmware image. `C`
@@ -78,6 +74,8 @@ partial deblobbing of Intel ME/TXE firmware images `Python`
 * __nvidia__ - nvidia blob parsers
 * __nvramtool__ - Reads and writes coreboot parameters and displaying
 information from the coreboot table in CMOS/NVRAM. `C`
+* __pgtblgen__ - Generates page tables based on fixed physical address.
+`C`
 * __pmh7tool__ - Dumps, reads and writes PMH7 registers on Lenovo
 ThinkPads. PMH7 is used for switching on and off the power of some
 devices on the board such as dGPU. `C`
@@ -91,14 +89,14 @@ can be passed to SPIKE, the RISC-V reference emulator.`Bash`
 	* _sifive-gpt.py_ - Wraps the bootblock in a GPT partition for
 SiFive's bootrom. `Python3`
 * __rockchip__ - Generate Rockchip idblock bootloader. `Python2`
-* __romcc__ - Compile a C source file generating a binary that does not
-implicitly use RAM. `C`
 * __sconfig__ - coreboot device tree compiler `Lex` `Yacc`
 * __scripts__
 	* _config_ - Manipulate options in a .config file from the
 command line `Bash`
 	* _cross-repo-cherrypick_ - Pull in patches from another tree
 from a gerrit repository. `Shell`
+	* _decode_spd.sh_ - Decodes Serial Presence Detect (SPD) files
+into various human readable formats.
 	* _dts-to-fmd.sh_ -Converts a depthcharge fmap.dts into an
 fmaptool compatible .fmd format `Bash`
 	* _find-unused-kconfig-symbols.sh_ - Points out Kconfig
@@ -116,15 +114,21 @@ file `Perl`
 	* _ucode_h_to_bin.sh_ - Microcode conversion tool `Bash`
 	* _update_submodules_ - Check all submodules for updates `Bash`
 * __showdevicetree__ - Compile and dump the device tree `C`
+* __spdtool__ - Dumps SPD ROMs from a given blob to separate files
+using known patterns and reserved bits. Useful for analysing firmware
+that holds SPDs on boards that have soldered down DRAM. `python`
 * __spkmodem_recv__ - Decode spkmodem signals `C`
 * __superiotool__ - A user-space utility to detect Super I/O of a
 mainboard and provide detailed information about the register contents
 of the Super I/O. `C`
+* __smcbiosinfo__ - Generates SMC biosinfo for BMC BIOS updates `C`
 * __testing__ - coreboot test targets `Make`
 * __uio_usbdebug__ - Debug coreboot's usbdebug driver inside a running
 operating system (only Linux at this time). `C`
 * __util_readme__ - Creates README.md of description files in `./util`
 subdirectories `Bash`
+* __vboot_list__ - Tools to generate a list of vboot enabled devices to
+the documentation `Bash`
 * __vgabios__ - emulated vga driver for qemu `C`
 * __x86__ - Generates 32-bit PAE page tables based on a CSV input file.
 `Go`