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59 changes: 3 additions & 56 deletions .gitignore
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@@ -1,6 +1,3 @@
payloads/libpayload/install/
payloads/nvramcui/build
payloads/nvramcui/libpayload
junit.xml
abuild*.xml
.config
Expand Down Expand Up @@ -67,7 +64,8 @@ site-local
*.pyc
*.sw[po]
/*.rom
coreboot-builds*/
.test
.dependencies

# Development friendly files
tags
Expand All @@ -79,60 +77,9 @@ tags
xgcc/
tarballs/

#
# KDE editors create lots of backup files whenever
# a file is edited, so just ignore them
# editor backup files, temporary files, IDE project files
*~
*.kate-swp
# Ignore Kdevelop project file
*.kdev4

util/*/.dependencies
util/*/.test
util/amdfwtool/amdfwtool
util/archive/archive
util/bincfg/bincfg
util/board_status/board-status
util/bucts/bucts
util/cbfstool/cbfs-compression-tool
util/cbfstool/cbfstool
util/cbfstool/fmaptool
util/cbfstool/ifwitool
util/cbfstool/rmodtool
util/cbmem/.dependencies
util/cbmem/cbmem
util/ectool/ectool
util/futility/futility
util/genprof/genprof
util/getpir/getpir
util/ifdtool/ifdtool
util/intelmetool/intelmetool
util/inteltool/.dependencies
util/inteltool/inteltool
util/intelp2m/intelp2m
util/intelp2m/generate/gpio.h
util/intelvbttool/intelvbttool
util/msrtool/Makefile
util/msrtool/Makefile.deps
util/msrtool/msrtool
util/nvramtool/.dependencies
util/nvramtool/nvramtool
util/pmh7tool/pmh7tool
util/runfw/googlesnow
util/superiotool/superiotool
util/vgabios/testbios
util/autoport/autoport
util/kbc1126/kbc1126_ec_dump
util/kbc1126/kbc1126_ec_insert
util/spd_tools/*/gen_spd
util/spd_tools/*/gen_part_id

Documentation/*.aux
Documentation/*.idx
Documentation/*.log
Documentation/*.toc
Documentation/*.out
Documentation/*.pdf
Documentation/_build

doxygen/*
2 changes: 1 addition & 1 deletion .gitlab-ci.yml
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Expand Up @@ -77,7 +77,7 @@ check_dependencies:

.run_regression: &run_regression
image:
name: 3mdeb/rf-docker:1.0.0
name: 3mdeb/rf-docker:1.1.0
# https://docs.gitlab.com/ee/ci/docker/using_docker_images.html#overriding-the-entrypoint-of-an-image
# https://gitlab.com/gitlab-org/gitlab-runner/-/issues/2692
# use EMPTY ENTRYPOINT for docker >17.06
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2 changes: 1 addition & 1 deletion 3rdparty/vboot
Submodule vboot updated from 4c523e to 9d4053
13 changes: 9 additions & 4 deletions CHANGELOG.md
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Expand Up @@ -13,17 +13,21 @@ Please use [pce-fw-builder](https://github.com/pcengines/pce-fw-builder)

## [Unreleased]

## [v4.13.0.1] - 2020-11-25
### Changed
- rebased with official coreboot repository commit 9b7dc76

## [v4.12.0.6] - 2020-10-29
## Changed
### Changed
- rebased with official coreboot repository commit 43439f6

## Fixed
### Fixed
- the option in runtime config to reverse PCI addressing order, now not only
mPCIe devices, but NICs are reversed as well. The WoL capable NIC should be
the first booting in iPXE when the reverse option is enabled.

## [v4.12.0.5] - 2020-09-25
## Changed
### Changed
- rebased with official coreboot repository commit da3375e
- added apu6 build target

Expand Down Expand Up @@ -469,7 +473,8 @@ redundant code which was similar for APU2/3/5 boards.
- turn off D4 and D5 leds on boot
- enable power on after power failure

[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.12.0.6...develop
[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.13.0.1...develop
[v4.13.0.1]: https://github.com/pcengines/coreboot/compare/v4.12.0.6...v4.13.0.1
[v4.12.0.6]: https://github.com/pcengines/coreboot/compare/v4.12.0.5...v4.12.0.6
[v4.12.0.5]: https://github.com/pcengines/coreboot/compare/v4.12.0.4...v4.12.0.5
[v4.12.0.4]: https://github.com/pcengines/coreboot/compare/v4.12.0.3...v4.12.0.4
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7 changes: 7 additions & 0 deletions Documentation/.gitignore
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*.aux
*.idx
*.log
*.toc
*.out
*.pdf
_build
10 changes: 5 additions & 5 deletions Documentation/lib/fw_config.md
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Expand Up @@ -73,18 +73,18 @@ return true.

## Firmware Configuration Value

The 32bit value used as the firmware configuration bitmask is meant to be determined at runtime
The 64-bit value used as the firmware configuration bitmask is meant to be determined at runtime
but could also be defined at compile time if needed.

There are two supported sources for providing this information to coreboot.

### CBFS

The value can be provided with a 32bit raw value in CBFS that is read by coreboot. The value
The value can be provided with a 64-bit raw value in CBFS that is read by coreboot. The value
can be set at build time but also adjusted in an existing image with `cbfstool`.

To enable this select the `CONFIG_FW_CONFIG_CBFS` option in the build configuration and add a
raw 32bit value to CBFS with the name of the current prefix at `CONFIG_FW_PREFIX/fw_config`.
raw 64-bit value to CBFS with the name of the current prefix at `CONFIG_FW_PREFIX/fw_config`.

When `fw_config_probe_device()` or `fw_config_probe()` is called it will look for the specified
file in CBFS use the value it contains when matching fields and options.
Expand Down Expand Up @@ -291,8 +291,8 @@ field and option to check.
struct fw_config {
const char *field_name;
const char *option_name;
uint32_t mask;
uint32_t value;
uint64_t mask;
uint64_t value;
};
```

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47 changes: 47 additions & 0 deletions Documentation/mainboard/clevo/n130wu/index.md
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# Clevo N130WU

## Hardware
### Technology
```eval_rst
+------------------+--------------------------------+
| CPU | Intel i7-8550U |
+------------------+--------------------------------+
| PCH | Intel Sunrise Point LP |
+------------------+--------------------------------+
| EC / Super IO | ITE IT8587E |
+------------------+--------------------------------+
| Coprocessor | Intel ME |
+------------------+--------------------------------+
```

### Flash chip
```eval_rst
+---------------------+-----------------+
| Type | Value |
+=====================+=================+
| Model | GD25Q64B |
+---------------------+-----------------+
| Socketed flash | no |
+---------------------+-----------------+
| Size | 8 MiB |
+---------------------+-----------------+
| In circuit flashing | Yes |
+---------------------+-----------------+
| Package | SOIC-8 |
+---------------------+-----------------+
| Write protection | No |
+---------------------+-----------------+
| Dual BIOS feature | No |
+---------------------+-----------------+
| Internal flashing | Yes |
+---------------------+-----------------+
```

## Board status
### Working
### Not Working
### Work in progress
### Untested

## Also known as
* TUXEDO InfinityBook Pro 13 v3
156 changes: 156 additions & 0 deletions Documentation/mainboard/hp/folio_9480m.md
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# HP EliteBook Folio 9480m

This page is about the notebook [HP EliteBook Folio 9480m].

## Release status

HP EliteBook Folio 9480m was released in 2014 and is now end of life.
It can be bought from a secondhand market like Taobao or eBay.

## Required proprietary blobs

The following blobs are required to operate the hardware:

1. EC firmware
2. Intel ME firmware
3. mrc.bin

HP EliteBook Folio 9480m uses SMSC MEC1322 as its embedded controller.
The EC firmware is stored in the flash chip, but we don't need to touch it
or use it in the coreboot build process.

Intel ME firmware is in the flash chip. It is not needed when building coreboot.

The Haswell memory reference code binary is needed when building coreboot.
Please see [mrc.bin](../../northbridge/intel/haswell/mrc.bin).

## Programming

Before flashing, remove the battery and the hard drive cover according to the
[Maintenance and Service Guide] of this laptop.

![Two flash chips of HP EliteBook Folio 9480m](folio_9480m_flash.webp)

HP EliteBook Folio 9480m has two flash chips, a 16MiB system flash, and a 2MiB
private flash. To install coreboot, we need to program both flash chips.
Read [HP Sure Start] for detailed information.

To access the system flash, we need to connect the AC adapter to the machine,
then clip on the flash chip with an SOIC-8 clip. An [STM32-based flash programmer]
made with an STM32 development board is tested to work.

To access the private flash chip, we can use a ch341a based flash programmer and
flash the chip with the AC adapter disconnected.

Before flashing coreboot, we need to do the following:

1. Erase the private flash to disable the IFD protection
2. Modify the IFD to shrink the BIOS region, so that we'll not use or override
the protected bootblock and PEI region, as well as the EC firmware

To erase the private flash chip, attach it with the flash programmer via the SOIC-8 clip,
then run:

flashrom -p <programmer> --erase

To modify the IFD, we need a new flash layout. The flash layout of the OEM firmware is:

00000000:00000fff fd
00001000:00002fff gbe
00003000:005fffff me
00600000:00ffffff bios

The default coreboot configuration sets the flash chip size to 12MiB, so set the end of the
BIOS region to 0xbfffff in the new layout. The modified IFD is as follows (Platform Data
region pd is the region protected by HP Sure Start):

00000000:00000fff fd
00001000:00002fff gbe
00003000:005fffff me
00600000:00bfffff bios
00eb5000:00ffffff pd

Write the above layout in a file, and use ifdtool to modify the IFD of a flash image.
Suppose the above layout file is ``layout.txt`` and the origin content of the system flash
is in ``factory-sys.rom``, run:

ifdtool -n layout.txt factory-sys.rom

Then a flash image with a new IFD will be in ``factory-sys.rom.new``.

Flash the IFD of the system flash:

flashrom -p <programmer> --ifd -i fd -w factory-sys.rom.new

Then flash the coreboot image:

# first extend the 12M coreboot.rom to 16M
fallocate -l 16M build/coreboot.rom
flashrom -p <programmer> --ifd -i bios -w build/coreboot.rom

After coreboot is installed, the coreboot firmware can be updated with internal flashing:

flashrom -p internal --ifd -i bios --noverify-all -w build/coreboot.rom

## Debugging

The board can be debugged with EHCI debug. The EHCI debug port is the USB port on the left.

## Test status

### Known issues

- GRUB payload freezes just like previous EliteBook laptops
- Sometimes the PCIe WLAN module can not be found in the OS after booting to the system
- Sometimes all the USB devices can not be found in the OS after S3 resume

### Untested

- Fingerprint reader
- Smart Card reader

### Working

- i5-4310U CPU with 4G+4G memory
- SATA and M.2 SATA disk
- Ethernet
- WLAN
- WWAN
- SD card reader
- USB
- Keyboard and touchpad
- DisplayPort
- VGA
- Dock
- Audio output from speaker and headphone jack
- Webcam
- TPM
- EC ACPI
- S3 resume
- Arch Linux with Linux 5.8.9
- Memory initialization with mrc.bin version 1.6.1 Build 2
- Graphics initialization with libgfxinit
- Payload: SeaBIOS, Tianocore
- EC firmware
- KBC Revision 92.15 from OEM firmware version 01.33
- KBC Revision 92.17 from OEM firmware version 01.50
- Internal flashing under coreboot

## Technology

```eval_rst
+------------------+-----------------------------+
| CPU | Intel Haswell-ULT |
+------------------+-----------------------------+
| PCH | Intel Lynx Point Low Power |
+------------------+-----------------------------+
| EC | SMSC MEC1322 |
+------------------+-----------------------------+
| Coprocessor | Intel Management Engine |
+------------------+-----------------------------+
```

[HP EliteBook Folio 9480m]: https://support.hp.com/us-en/product/hp-elitebook-folio-9480m-notebook-pc/7089926
[Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c05228980
[STM32-based flash programmer]: https://github.com/dword1511/stm32-vserprog
[HP Sure Start]: hp_sure_start.md
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