Showing 993 changed files with 27,286 additions and 6,971 deletions.
diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs
diff --git a/3rdparty/vboot b/3rdparty/vboot
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -13,6 +13,13 @@ Please use [pce-fw-builder](https://github.com/pcengines/pce-fw-builder)
 
 ## [Unreleased]
 
+## [v4.13.0.2] - 2020-12-28
+### Changed
+- rebased with official coreboot repository commit 8edb48b
+
+### Fixed
+- [Serial number calculation on APU1](https://github.com/pcengines/coreboot/issues/436)
+
 ## [v4.13.0.1] - 2020-11-25
 ### Changed
 - rebased with official coreboot repository commit 9b7dc76
@@ -473,7 +480,8 @@ redundant code which was similar for APU2/3/5 boards.
 - turn off D4 and D5 leds on boot
 - enable power on after power failure
 
-[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.13.0.1...develop
+[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.13.0.2...develop
+[v4.13.0.2]: https://github.com/pcengines/coreboot/compare/v4.13.0.1...v4.13.0.2
 [v4.13.0.1]: https://github.com/pcengines/coreboot/compare/v4.12.0.6...v4.13.0.1
 [v4.12.0.6]: https://github.com/pcengines/coreboot/compare/v4.12.0.5...v4.12.0.6
 [v4.12.0.5]: https://github.com/pcengines/coreboot/compare/v4.12.0.4...v4.12.0.5

diff --git a/Documentation/cbfstool/index.md b/Documentation/cbfstool/index.md
@@ -0,0 +1,5 @@
+# cbfstool
+
+Contents:
+
+* [Handling memory mapped boot media](mmap_windows.md)
diff --git a/Documentation/cbfstool/mmap_windows.md b/Documentation/cbfstool/mmap_windows.md
@@ -0,0 +1,77 @@
+# cbfstool: Handling memory mapped boot media
+
+`cbfstool` is a utility used for managing coreboot file system (CBFS)
+components in a ROM image. x86 platforms are special since they have
+the SPI flash boot media memory mapped into host address space at
+runtime. This requires `cbfstool` to deal with two separate address
+spaces for any CBFS components that are eXecute-In-Place (XIP) - one
+is the SPI flash address space and other is the host address space
+where the SPI flash gets mapped.
+
+By default, all x86 platforms map a maximum of 16MiB of SPI flash at
+the top of 4G in host address space. If the flash is greater than
+16MiB, then only the top 16MiB of the flash is mapped in the host
+address space. If the flash is smaller than 16MiB, then the entire SPI
+flash is mapped at the top of 4G and the rest of the space remains
+unused.
+
+In more recent platforms like Tiger Lake (TGL), it is possible to map
+more than 16MiB of SPI flash. Since the host address space has legacy
+fixed device addresses mapped below `4G - 16M`, the SPI flash is split
+into separate windows when being mapped to the host address space.
+Default decode window of maximum 16MiB size still lives just below the
+4G boundary. The additional decode window is free to live in any
+available MMIO space that the SoC chooses.
+
+Following diagram shows different combinations of SPI flash being
+mapped into host address space when using multiple windows:
+
+![MMAP window combinations with different flash sizes][mmap_windows]
+
+*(a) SPI flash of size 16MiB (b) SPI flash smaller than 16MiB (c) SPI flash
+of size (16MiB+ext window size) (d) SPI flash smaller than (16MiB+ext
+window size)*
+
+The location of standard decode window is fixed in host address space
+`(4G - 16M) to 4G`. However, the platform is free to choose where the
+extended window lives in the host address space. Since `cbfstool`
+needs to know the exact location of the extended window, it allows the
+platform to pass in two parameters `ext-win-base` and `ext-win-size`
+that provide the base and the size of the extended window in host
+address space.
+
+`cbfstool` creates two memory map windows using the knowledge about the
+standard decode window and the information passed in by the platform
+about the extended decode window. These windows are useful in
+converting addresses from one space to another (flash space and host
+space) when dealing with XIP components.
+
+## Assumptions
+
+1. Top 16MiB is still decoded in the fixed decode window just below 4G
+   boundary.
+1. Rest of the SPI flash below the top 16MiB is mapped at the top of
+   the extended window. Even though the platform might support a
+   larger extended window, the SPI flash part used by the mainboard
+   might not be large enough to be mapped in the entire window. In
+   such cases, the mapping is assumed to be in the top part of the
+   extended window with the bottom part remaining unused.
+
+## Example
+
+If the platform supports extended window and the SPI flash size is
+greater, then `cbfstool` creates a mapping for the extended window as
+well.
+
+```
+ext_win_base = 0xF8000000
+ext_win_size = 32 * MiB
+ext_win_limit = ext_win_base + ext_win_size - 1 = 0xF9FFFFFF
+```
+
+If SPI flash is 32MiB, then top 16MiB is mapped from `0xFF000000 -
+0xFFFFFFFF` whereas the bottom 16MiB is mapped from `0xF9000000 -
+0xF9FFFFFF`. The extended window `0xF8000000 - 0xF8FFFFFF` remains
+unused.
+
+[mmap_windows]: mmap_windows.svg
diff --git a/Documentation/cbfstool/mmap_windows.svg b/Documentation/cbfstool/mmap_windows.svg
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
@@ -89,15 +89,15 @@ The boards in this section are not real mainboards, but emulators.
 - [X2xx common](lenovo/x2xx_series.md)
 - [vboot](lenovo/vboot.md)
 
-### Arrandale series
-
-- [T410](lenovo/t410.md)
-
 ### GM45 series
 
 - [X200 / T400 / T500 / X301 common](lenovo/montevina_series.md)
 - [X301](lenovo/x301.md)
 
+### Arrandale series
+
+- [T410](lenovo/t410.md)
+
 ### Sandy Bridge series
 
 - [T420](lenovo/t420.md)

diff --git a/Documentation/mainboard/lenovo/montevina_series.md b/Documentation/mainboard/lenovo/montevina_series.md
@@ -9,6 +9,15 @@ the chip in your machine through flashrom:
 Note that this does not allow you to determine whether the chip is in a SOIC-8
 or a SOIC-16 package.
 
+## Installing with ME firmware
+
+To install coreboot and keep ME working, you don't need to do anything special
+with the flash descriptor. Only flash the `bios` region externally and don't
+touch any other regions:
+```console
+# flashrom -p YOUR_PROGRAMMER -w coreboot.rom --ifd -i bios
+```
+
 ## Installing without ME firmware
 
 ```eval_rst
@@ -127,15 +136,6 @@ Chipset --->
 
 Then build coreboot and flash whole `build/coreboot.rom` to the chip.
 
-## Installing with ME firmware
-
-To install coreboot and keep ME working, you don't need to do anything special
-with the flash descriptor. Just flash only `bios` externally and don't touch any
-other regions:
-```console
-# flashrom -p YOUR_PROGRAMMER -w coreboot.rom --ifd -i bios
-```
-
 ## Flash layout
 
 The flash layouts of the OEM firmware are as follows:

diff --git a/Documentation/mainboard/ocp/deltalake.md b/Documentation/mainboard/ocp/deltalake.md
@@ -9,23 +9,25 @@ build/test/release cycle.
 OCP Delta Lake server platform is a component of multi-host server system
 Yosemite-V3. Both were announced by Facebook and Intel in [OCP virtual summit 2020].
 
-Delta Lake server is a single socket Cooper Lake Scalable Processor server.
+Delta Lake server is a single socket Cooper Lake Scalable Processor (CPX-SP) server.
 
 Yosemite-V3 has multiple configurations. Depending on configurations, it may
 host up to 4 Delta Lake servers in one sled.
 
-The Yosemite-V3 program has reached DVT exit. Facebook, Intel and partners
+The Yosemite-V3 program is in PVT phase. Facebook, Intel and partners
 jointly develop FSP/coreboot/LinuxBoot stack on Delta Lake as an alternative
-solution. This development is moving toward EVT exit equivalent status.
+solution. This development reached EVT exit equivalent status.
 
 ## Required blobs
 
 This board currently requires:
 - FSP blob: The blob (Intel Cooper Lake Scalable Processor Firmware Support Package)
   is not yet available to the public. It will be made public some time after the MP
-  (Mass Production) of CooperLake Scalable Processor when the FSP is mature.
+  (Mass Production) of CPX-SP.
 - Microcode: Available through github.com:otcshare/Intel-Generic-Microcode.git.
-- ME binary: Not yet available to the public.
+- ME binary: Ignition binary will be made public some time after the MP
+  of CPX-SP.
+- ACM binaries: only required for CBnT enablement.
 
 ## Payload
 - LinuxBoot: This is necessary only if you use LinuxBoot as coreboot payload.
@@ -48,6 +50,16 @@ To power off/on the host:
 To connect to console through SOL (Serial Over Lan):
     sol-util slotx
 
+## Firmware configurations
+[ChromeOS VPD] is used to store most of the firmware configurations.
+RO_VPD region holds default values, while RW_VPD region holds customized
+values.
+
+VPD variables supported are:
+- firmware_version: This variable holds overall firmware version. coreboot
+  uses that value to populate smbios type 1 version field.
+- DeltaLake specific VPDs: check mb/ocp/deltalake/vpd.h.
+
 ## Working features
 The solution is developed using LinuxBoot payload with Linux kernel 5.2.9, and [u-root]
 as initramfs.
@@ -61,8 +73,12 @@ as initramfs.
     - Type 8 -- Port Connector Information
     - Type 9 -- PCI Slot Information
     - Type 11 -- OEM String
+    - Type 16 -- Physical Memory Array
+    - Type 17 -- Memory Device
+    - Type 19 -- Memory Array Mapped Address
     - Type 32 -- System Boot Information
     - Type 38 -- IPMI Device Information
+    - Type 41 -- Onboard Devices Extended Information
     - Type 127 -- End-of-Table
 - BMC integration:
     - BMC readiness check
@@ -71,6 +87,12 @@ as initramfs.
     - POST complete pin acknowledgement
     - Check BMC version: ipmidump -device
 - SEL record generation
+- Converged Bootguard and TXT (CBnT)
+    - TPM
+    - Bootguard profile 0T
+    - TXT
+    - SRTM (verified through tboot)
+    - memory secret clearance upon ungraceful shutdown
 - Early serial output
 - port 80h direct to GPIO
 - ACPI tables: APIC/DMAR/DSDT/FACP/FACS/HPET/MCFG/SPMI/SRAT/SLIT/SSDT
@@ -87,44 +109,41 @@ as initramfs.
 - Power button
 - localboot
 - netboot from IPv6
-- TPM
+- basic memory hardware error injection/detection (SMI handler not upstreamed)
+- basic PCIe hardware error injection/detection (SMI handler not upstreamed)
 
 ## Stress/performance tests passed
-- OS warm reboot (300 cycles)
-- DC reboot (300 cycles)
-- AC reboot (300 cycle)
+- OS warm reboot (1000 cycles)
+- DC reboot (1000 cycles)
+- AC reboot (1000 cycle)
 - Mprime test (6 hours)
 - StressAppTest (6 hours)
 - Ptugen (6 hours)
-- MLC (Intel Memory Latency Check)
+
+## Performance tests on par with traditional firmware
+- coremark
+- SpecCPU
 - Linkpack
 - Iperf(IPv6)
 - FIO
 
-## Firmware configurations
-[ChromeOS VPD] is used to store most of the firmware configurations.
-RO_VPD region holds default values, while RW_VPD region holds customized
-values.
-
-VPD variables supported are:
-- firmware_version: This variable holds overall firmware version. coreboot
-  uses that value to populate smbios type 1 version field.
-- DeltaLake specific VPDs: check mb/ocp/deltalake/vpd.h.
+## Other tests passed
+- Power
+- Thermal
 
 ## Known issues
-- spsInfoLinux64 command fail to return ME version.
-- fwts test failures related to mtrr.
-- kernel error message related to SleepButton ACPI event.
+- MLC (Intel Memory Latency Check) and stream performance issue
+- HECI access at OS run time:
+    - spsInfoLinux64 command fail to return ME version
+    - ptugen command fail to get memory power
 
 ## Feature gaps
-- SMBIOS:
-    - Type 16 -- Physical Memory Array
-    - Type 17 -- Memory Device
-    - Type 19 -- Memory Array Mapped Address
-    - Type 41 -- Onboard Devices Extended Information
-- Verified measurement through CBnT
-- Boot guard of CBnT
-- RO_VPD region as well as other RO regions are not write protected.
+- flashrom command not able to update ME region
+- ACPI APEI tables
+- PCIe hotplug, Virtual Pin Ports
+- PCIe Live Error Recovery
+- RO_VPD region as well as other RO regions are not write protected
+- Not able to selectively enable/disable core
 
 ## Technology
 

diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md
@@ -7,6 +7,7 @@ Controller etc.
 ## Supported boards
 
 - [X11SSH-TF](x11ssh-tf/x11ssh-tf.md)
+- [X11SSH-F](x11ssh-f/x11ssh-f.md)
 - [X11SSM-F](x11ssm-f/x11ssm-f.md)
 
 ## Required proprietary blobs
@@ -30,14 +31,12 @@ Look at the [flashing tutorial] and the board-specific section.
 
 These issues apply to all boards. Have a look at the board-specific issues, too.
 
-- TianoCore doesn't work with Aspeed NGI, as it's text mode only (Fix is WIP CB:35726)
 - MRC caching does not work on cold boot with Intel SPS (see [Intel FSP2.0])
 
 ## ToDo
 
 - Fix issues above
 - Fix issues in board specific sections
-- Fix TODOs mentioned in code
 - Add more boards! :-)
 
 ## Technology

diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md
@@ -33,10 +33,6 @@ in a 32 MiB SOIC-16 chip in the corner of the mainboard near the [AST2400]. This
 
 See general issue section.
 
-## ToDo
-
-- Fix TODOs mentioned in code
-
 ## Technology
 
 ```eval_rst

diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md
@@ -4,18 +4,22 @@ This section details how to run coreboot on the [Supermicro X11SSM-F].
 
 ## Flashing coreboot
 
-The board can be flashed externally. FTDI FT2232H and FT232H based programmers worked.
+The board can be flashed externally. FTDI FT2232H and FT232H based programmers worked. For this,
+one needs to add a diode between VCC and the flash chip. The flash IC [MX25L12873F] can be found
+near PCH PCIe Slot 4.
 
-The flash IC [MX25L12873F] can be found near PCH PCIe Slot 4. It is socketed on retail boards.
-
-For doing ISP (In-System-Programming) one needs to add a diode between VCC and the flash chip.
+Flashing is also possible through the BMC web interface, when a valid license was entered.
 
 ## BMC (IPMI)
 
 This board has an ASPEED [AST2400], which has BMC/[IPMI] functionality. The BMC firmware resides in a
 32 MiB SOIC-16 chip in the corner of the mainboard near the PCH PCIe Slot 4. This chip is a
 [MX25L25635F].
 
+## Disabling LAN firmware
+
+To disable the proprietary LAN firmware, the undocumented jumper J6 can be set to 2-3.
+
 ## Tested and working
 
 - GRUB2 payload with Debian testing and kernel 5.2
@@ -32,14 +36,9 @@ This board has an ASPEED [AST2400], which has BMC/[IPMI] functionality. The BMC
 ## Known issues
 
 - See general issue section
-- "only partially covers this bridge" info from Linux kernel (what does that mean?)
 - LNXTHERM missing
 - S3 resume not working
 
-## ToDo
-
-- Fix TODOs mentioned in code
-
 ## Technology
 
 ```eval_rst

diff --git a/Documentation/util.md b/Documentation/util.md
@@ -20,7 +20,7 @@ status repository `Bash` `Go`
 * __cavium__ - Devicetree_convert Tool to convert a DTB to a static C
 file `Python`
 * __cbfstool__
-	* _cbfstool_ - For manipulating CBFS file `C`
+	* [_cbfstool_](cbfstool/index.md) - For manipulating CBFS file `C`
 	* _fmaptool_ - Converts plaintext fmd files into fmap blobs `C`
 	* _rmodtool_ - Creates rmodules `C`
 	* _ifwitool_ - For manipulating IFWI `C`