Showing 1,309 changed files with 112,710 additions and 28,849 deletions.
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
@@ -65,7 +65,7 @@ check_dependencies:
     - docker
   before_script:
     - apt-get update
-    - apt-get install curl
+    - apt-get -y install curl
   script:
     - ls -al ${RELEASE_DIR}
     - curl -u ${UPLOADER_USERNAME}:${UPLOADER_PASSWORD} -X MKCOL ${UPLOADER_URL}/releases/
@@ -232,3 +232,11 @@ publish:apu6:
   <<: *publish_rom
   variables:
     PLATFORM: apu6
+
+regression:apu6:
+  <<: *run_regression
+  variables:
+    PLATFORM: apu6
+    CONFIG: apu6
+    RTE_IP: $RTE_IP_APU6
+    AUTOFILL: 1
diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs
diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware
diff --git a/3rdparty/blobs b/3rdparty/blobs
diff --git a/3rdparty/chromeec b/3rdparty/chromeec
diff --git a/3rdparty/intel-sec-tools b/3rdparty/intel-sec-tools
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -13,6 +13,10 @@ Please use [pce-fw-builder](https://github.com/pcengines/pce-fw-builder)
 
 ## [Unreleased]
 
+## [v4.13.0.5] - 2021-04-07
+### Changed
+- rebased with official coreboot repository commit e7a68ec
+
 ## [v4.13.0.4] - 2021-02-24
 ### Changed
 - rebased with official coreboot repository commit c79fc47
@@ -488,7 +492,8 @@ redundant code which was similar for APU2/3/5 boards.
 - turn off D4 and D5 leds on boot
 - enable power on after power failure
 
-[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.13.0.4...develop
+[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.13.0.5...develop
+[v4.13.0.5]: https://github.com/pcengines/coreboot/compare/v4.13.0.4...v4.13.0.5
 [v4.13.0.4]: https://github.com/pcengines/coreboot/compare/v4.13.0.3...v4.13.0.4
 [v4.13.0.3]: https://github.com/pcengines/coreboot/compare/v4.13.0.2...v4.13.0.3
 [v4.13.0.2]: https://github.com/pcengines/coreboot/compare/v4.13.0.1...v4.13.0.2

diff --git a/Documentation/acpi/devicetree.md b/Documentation/acpi/devicetree.md
@@ -30,7 +30,7 @@ device pci 15.0 on
 	chip drivers/i2c/generic
 		register "hid" = ""ELAN0000""
 		register "desc" = ""ELAN Touchpad""
-		register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)"
+		register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)"
 		register "wake" = "GPE0_DW0_21"
 		device i2c 15 on end
 	end
@@ -60,7 +60,7 @@ Scope (\_SB.PCI0.I2C0)
             I2cSerialBusV2 (0x0015, ControllerInitiated, 400000,
                 AddressingMode7Bit, "\\_SB.PCI0.I2C0",
                 0x00, ResourceConsumer, , Exclusive, )
-            Interrupt (ResourceConsumer, Edge, ActiveLow, ExclusiveAndWake, ,, )
+            Interrupt (ResourceConsumer, Level, ActiveLow, ExclusiveAndWake, ,, )
             {
                 0x0000002D,
             }
@@ -136,7 +136,7 @@ corresponds to **const char *desc** and in ASL:
 It also adds the interrupt,
 
 ```
-    Interrupt (ResourceConsumer, Edge, ActiveLow, ExclusiveAndWake, ,, )
+    Interrupt (ResourceConsumer, Level, ActiveLow, ExclusiveAndWake, ,, )
     {
         0x0000002D,
     }
@@ -145,15 +145,15 @@ It also adds the interrupt,
 which comes from:
 
 ```
-    register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)"
+    register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)"
 ```
 
-The GPIO pin IRQ settings control the "Edge", "ActiveLow", and
-"ExclusiveAndWake" settings seen above (edge means it is an edge-triggered
-interrupt as opposed to level-triggered; active low means the interrupt is
-triggered on a falling edge).
+The GPIO pin IRQ settings control the "Level", "ActiveLow", and
+"ExclusiveAndWake" settings seen above (level means it is a level-triggered
+interrupt as opposed to edge-triggered; active low means the interrupt is
+triggered when the signal is low).
 
-Note that the ACPI_IRQ_WAKE_EDGE_LOW macro informs the platform that the GPIO
+Note that the ACPI_IRQ_WAKE_LEVEL_LOW macro informs the platform that the GPIO
 will be routed through SCI (ACPI's System Control Interrupt) for use as a wake
 source.  Also note that the IRQ names are SoC-specific, and you will need to
 find the names in your SoC's header file.  The ACPI_* macros are defined in

diff --git a/Documentation/acpi/gpio.md b/Documentation/acpi/gpio.md
@@ -159,7 +159,6 @@ for the GPIO.
 	 */
 	acpigen_write_if_and(Local5, TX_BIT);
 	acpigen_write_store_args(ONE_OP, LOCAL0_OP);
-	acpigen_pop_len();
 	acpigen_write_else();
 	acpigen_write_store_args(ZERO_OP, LOCAL0_OP);
 	acpigen_pop_len();

diff --git a/Documentation/contributing/coding_style.md b/Documentation/contributing/coding_style.md
@@ -5,12 +5,26 @@ coreboot project. It is in many ways exactly the same as the Linux
 kernel coding style. In fact, most of this document has been copied from
 the [Linux kernel coding style](http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/plain/Documentation/CodingStyle?id=HEAD)
 
-Please at least consider the points made here.
-
-First off, I'd suggest printing out a copy of the GNU coding standards,
-and NOT read it. Burn them, it's a great symbolic gesture.
-
-Anyway, here goes:
+The guidelines in this file should be seen as a strong suggestion, and
+should overrule personal preference. But they may be ignored in
+individual instances when there are good practical reasons to do so, and
+reviewers are in agreement.
+
+Any style questions that are not mentioned in here should be decided
+between the author and reviewers on a case-by-case basis. When modifying
+existing files, authors should try to match the prevalent style in that
+file -- otherwise, they should try to match similar existing files in
+coreboot.
+
+Bulk style changes to existing code ("cleanup patches") should avoid
+changing existing style choices unless they actually violate this style
+guide, or there is broad consensus that the new version is an
+improvement. By default the style choices of the original author should
+be honored. (Note that `checkpatch.pl` is not part of this style guide,
+and neither is `clang-format`. These tools can be useful to find
+potential issues or simplify formatting in new submissions, but they
+were not designed to directly match this guide and may have false
+positives. They should not be bulk-applied to change existing code.)
 
 ## Indentation
 
@@ -837,14 +851,16 @@ pointers; they use NULL or the ERR_PTR mechanism to report failure.
 Headers and includes
 ---------------
 
-Headers should always be included at the top of the file, preferrably in
-alphabetical order. Includes should always use the `#include <file.h>`
-notation, except for rare cases where a file in the same directory that
-is not part of a normal include path gets included (e.g. local headers
-in mainboard directories), which should use `#include "file.h"`. Headers
-that can be included from both assembly files and .c files should keep
-all C code wrapped in `#ifndef __ASSEMBLER__` blocks, including includes
-to other headers that don't follow that provision.
+Headers should always be included at the top of the file. Includes should
+always use the `#include <file.h>` notation, except for rare cases where a file
+in the same directory that is not part of a normal include path gets included
+(e.g. local headers in mainboard directories), which should use `#include
+"file.h"`. Local "file.h" includes should always come separately after all
+<file.h> includes.  Headers that can be included from both assembly files and
+.c files should keep all C code wrapped in `#ifndef __ASSEMBLER__` blocks,
+including includes to other headers that don't follow that provision. Where a
+specific include order is required for technical reasons, it should be clearly
+documented with comments.
 
 Files should generally include every header they need a definition from
 directly (and not include any unnecessary extra headers). Excepted from

diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
@@ -176,6 +176,7 @@ The boards in this section are not real mainboards, but emulators.
 
 ## System76
 
+- [Gazelle 15](system76/gaze15.md)
 - [Lemur Pro](system76/lemp9.md)
 - [Oryx Pro 5](system76/oryp5.md)
 

diff --git a/Documentation/mainboard/lenovo/montevina_series.md b/Documentation/mainboard/lenovo/montevina_series.md
@@ -44,7 +44,7 @@ $ ifdtool -x backup.rom
 
 Now you need to patch the flash descriptor. You can either [modify the one from
 your backup with **ifdtool**](#modifying-flash-descriptor-using-ifdtool), or
-[generate a completely new one with **bincfg**](#creating-a-new-flash-descriptor-using-bincfg).
+[use one from the coreboot repository](#using-checked-in-flash-descriptor-via-bincfg).
 
 #### Modifying flash descriptor using ifdtool
 
@@ -59,7 +59,7 @@ the `new_layout.txt` file:
 |                           |                           |                           |
 |    00000000:00000fff fd   |    00000000:00000fff fd   |    00000000:00000fff fd   |
 |    00001000:00002fff gbe  |    00001000:00002fff gbe  |    00001000:00002fff gbe  |
-|    00003000:003fffff bios |    00003000:007fffff bios |    00003000:01ffffff bios |
+|    00003000:003fffff bios |    00003000:007fffff bios |    00003000:00ffffff bios |
 |    00fff000:00000fff pd   |    00fff000:00000fff pd   |    00fff000:00000fff pd   |
 |    00fff000:00000fff me   |    00fff000:00000fff me   |    00fff000:00000fff me   |
 +---------------------------+---------------------------+---------------------------+
@@ -88,10 +88,12 @@ $ mv flashregion_0_flashdescriptor.bin.new.new flashregion_0_flashdescriptor.bin
 
 Continue to the [Configuring coreboot](#configuring-coreboot) section.
 
-#### Creating a new flash descriptor using bincfg
+#### Using checked-in flash descriptor via bincfg
 
-There is a tool to generate a modified flash descriptor called **bincfg**. Go to
-`util/bincfg` and build it:
+There is a copy of an X200's flash descriptor checked into the coreboot
+repository. It is supposed to work for the T400/T500 as well. The descriptor
+can be converted back to its binary form using a tool called **bincfg**. Go
+to `util/bincfg` and build it:
 ```console
 $ cd util/bincfg
 $ make
@@ -106,11 +108,11 @@ If your flash is not 8 MiB, you need to change values of `flcomp_density1` and
 +=================+=======+=======+========+
 | flcomp_density1 | 0x3   | 0x4   | 0x5    |
 +-----------------+-------+-------+--------+
-| flreg1_limit    | 0x3ff | 0x7ff | 0x1fff |
+| flreg1_limit    | 0x3ff | 0x7ff | 0xfff  |
 +-----------------+-------+-------+--------+
 ```
 
-Then create the flash descriptor:
+Then convert the flash descriptor:
 ```console
 $ make gen-ifd-x200
 ```
@@ -125,7 +127,7 @@ to flash descriptor and gbe dump.
 ```
 Mainboard --->
     ROM chip size (8192 KB (8 MB)) # According to your chip
-    (0x7fd000) Size of CBFS filesystem in ROM # or 0x3fd000 for 4 MiB chip / 0x1ffd000 for 16 MiB chip
+    (0x7fd000) Size of CBFS filesystem in ROM # or 0x3fd000 for 4 MiB chip / 0xffd000 for 16 MiB chip
 
 Chipset --->
     [*] Add Intel descriptor.bin file

diff --git a/Documentation/mainboard/ocp/deltalake.md b/Documentation/mainboard/ocp/deltalake.md
@@ -58,6 +58,11 @@ values.
 VPD variables supported are:
 - firmware_version: This variable holds overall firmware version. coreboot
   uses that value to populate smbios type 1 version field.
+- bmc_bootorder_override: When it's set to 1 IPMI OEM command can override boot
+  order. The boot order override is done in the u-root LinuxBoot payload.
+- systemboot_log_level: u-root package systemboot log levels, would be mapped to
+  quiet/verbose in systemboot as that is all we have for now. 5 to 8 would be mapped
+  to verbose, 0 to 4 and 9 would be mapped to quiet.
 - DeltaLake specific VPDs: check mb/ocp/deltalake/vpd.h.
 
 ## Working features

diff --git a/Documentation/mainboard/purism/librem_14.md b/Documentation/mainboard/purism/librem_14.md
@@ -0,0 +1,113 @@
+# Purism Librem 14
+
+This page describes how to run coreboot on the [Purism Librem 14].
+
+```eval_rst
++------------------+------------------------------------------------------+
+| CPU              | Intel Core i7-10710U                                 |
++------------------+------------------------------------------------------+
+| PCH              | Comet Lake LP Premium (Comet Lake-U)                 |
++------------------+------------------------------------------------------+
+| EC               | ITE IT8528E                                          |
++------------------+------------------------------------------------------+
+| Coprocessor      | Intel Management Engine (CSME 14.x)                  |
++------------------+------------------------------------------------------+
+```
+
+![](librem_14.webp)
+![](librem_14_flash.jpg)
+![](librem_14_ec_flash.jpg)
+
+## Required proprietary blobs
+
+To build a minimal working coreboot image some blobs are required (assuming
+only the BIOS region is being modified).
+
+```eval_rst
++-----------------+---------------------------------+---------------------+
+| Binary file     | Apply                           | Required / Optional |
++=================+=================================+=====================+
+| FSP-M, FSP-S    | Intel Firmware Support Package  | Required            |
++-----------------+---------------------------------+---------------------+
+| microcode       | CPU microcode                   | Required            |
++-----------------+---------------------------------+---------------------+
+```
+
+FSP-M and FSP-S are obtained after splitting the CometLake1 FSP binary
+(done automatically by the coreboot build system and included into the
+image) from the `3rdparty/fsp` submodule.
+
+Microcode updates are automatically included into the coreboot image by the
+build system from the `3rdparty/intel-microcode` submodule. Official Purism
+release images may include newer microcode, which is instead pulled from
+Purism's [purism-blobs] repository.
+
+A VGA Option ROM is not required to boot, as the Librem 14 uses libgfxinit.
+
+## Intel Management Engine
+
+The Librem 14 uses version 14.x of the Intel Management Engine (ME) /
+Converged Security Engine (CSE). The ME/CSE is disabled using the High
+Assurance Platform (HAP) bit, which puts the ME into a disabled state after
+platform bring-up (BUP) and disables all PCI/HECI interfaces.
+This can be verified checking the coreboot console log, using coreboot’s
+cbmem utility:
+
+    `sudo ./cbmem -1 | grep 'ME:'`
+
+provided coreboot has been patched to output the ME status even when the
+PCI device is not visible/active (as it is in Purism's release builds).
+
+## Flashing coreboot
+
+### Internal programming
+
+The main SPI flash can be accessed using [flashrom]. No official flashrom
+release supports the CometLake-U SoC yet, so it must be built from source.
+Version v1.2-107-gb1f858f or later is needed. Firmware an be easily
+flashed with internal programmer (either BIOS region or full image).
+
+### External programming
+
+The system has an internal flash chip which is a 16 MiB soldered SOIC-8
+chip, and has a diode attached to the VCC line for in-system programming.
+This chip is located on the bottom side of the board, in between the CPU
+heatsink and the left cooling fan, just above the left SO-DIMM slot.
+
+One has to remove all 9 screws from the bottom cover, then disconnect the
+battery from the mainboard (bottom left of mainboard). Use a SOIC-8 chip
+clip to program the chip (a Gigadevice GD25Q127C (3.3V) - [datasheet][GD25Q127C]).
+
+The EC firmware is stored on a separate SOIC-8 chip (a Gigadevices GD25Q80C),
+located underneath the Wi-Fi module, below the left cooling fan.
+
+## Known issues
+
+ * Automatic detection of external audio input/output via the 3.5mm jack
+   does not currently work.
+ * PL1/PL2 limited to 15W/20W by charger and battery discharge capability,
+   not SoC or thermal design.
+
+## Working
+
+ * Internal display with libgfxinit, VGA option ROM, or FSP/GOP init
+ * External displays via HDMI, USB-C Alt-Mode
+ * SeaBIOS (1.14), Tianocore (CorebootPayloadPkg), and Heads payloads
+ * Ethernet, m.2 2230 Wi-Fi
+ * System firmware updates via flashrom
+ * M.2 storage (NVMe, SATA III)
+ * Built-in audio (speakers, microphone)
+ * SMBus (reading SPD from DIMMs)
+ * Initialization with FSP 2.0 (CometLake1)
+ * S3 Suspend/Resume
+ * Booting PureOS 10.x, Debian 11.x, Qubes 4.0.4, Windows 10 20H2
+
+## Not working / untested
+
+ * N/A
+
+
+[Purism Librem 14]: https://puri.sm/products/librem-14/
+[purism-blobs]: https://source.puri.sm/coreboot/purism-blobs
+[GD25Q127C]: https://www.gigadevice.com/datasheet/gd25q127c/
+[flashrom]: https://flashrom.org/Flashrom
diff --git a/Documentation/mainboard/purism/librem_14.webp b/Documentation/mainboard/purism/librem_14.webp
diff --git a/Documentation/mainboard/purism/librem_14_ec_flash.jpg b/Documentation/mainboard/purism/librem_14_ec_flash.jpg
diff --git a/Documentation/mainboard/purism/librem_14_flash.jpg b/Documentation/mainboard/purism/librem_14_flash.jpg
diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md
@@ -7,7 +7,7 @@ Controller etc.
 ## Supported boards
 
 - [X11SSH-TF](x11ssh-tf/x11ssh-tf.md)
-- [X11SSH-F](x11ssh-f/x11ssh-f.md)
+- [X11SSH-F/LN4F](x11ssh-f/x11ssh-f.md)
 - [X11SSM-F](x11ssm-f/x11ssm-f.md)
 
 ## Required proprietary blobs