Showing 923 changed files with 26,150 additions and 11,664 deletions.
diff --git a/.gitmodules b/.gitmodules
@@ -35,6 +35,7 @@
 	url = https://review.coreboot.org/intel-microcode.git
 	update = none
 	ignore = dirty
+	branch = main
 [submodule "3rdparty/ffs"]
 	path = 3rdparty/ffs
 	url = https://review.coreboot.org/ffs.git

diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs
diff --git a/3rdparty/fsp b/3rdparty/fsp
diff --git a/3rdparty/intel-sec-tools b/3rdparty/intel-sec-tools
diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit
diff --git a/3rdparty/libhwbase b/3rdparty/libhwbase
diff --git a/3rdparty/vboot b/3rdparty/vboot
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -12,6 +12,10 @@ official [coreboot repository](https://review.coreboot.org/cgit/coreboot.git)
 Please use [pce-fw-builder](https://github.com/pcengines/pce-fw-builder)
 
 ## [Unreleased]
+## [v4.14.0.2] - 2021-06-28
+### Changed
+- rebased with official coreboot repository commit 1c43d92
+
 ## [v4.14.0.1] - 2021-05-27
 ### Changed
 - rebased with official coreboot repository commit 6a936fc
@@ -508,7 +512,8 @@ redundant code which was similar for APU2/3/5 boards.
 - turn off D4 and D5 leds on boot
 - enable power on after power failure
 
-[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.14.0.1...develop
+[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.14.0.2...develop
+[v4.14.0.2]: https://github.com/pcengines/coreboot/compare/v4.13.0.1...v4.14.0.2
 [v4.14.0.1]: https://github.com/pcengines/coreboot/compare/v4.13.0.6...v4.14.0.1
 [v4.13.0.6]: https://github.com/pcengines/coreboot/compare/v4.13.0.5...v4.13.0.6
 [v4.13.0.5]: https://github.com/pcengines/coreboot/compare/v4.13.0.4...v4.13.0.5

diff --git a/Documentation/community/forums.md b/Documentation/community/forums.md
@@ -11,11 +11,13 @@ You can subscribe on its
 read its
 [archives](https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/).
 
-## IRC
+## Real time chat
 
-We also have a
-[real time chat](https://webchat.freenode.net?channels=%23coreboot)
-on the Freenode IRC network's #coreboot channel.
+We also have a real time chat room on [IRC](ircs://irc.libera.chat/#coreboot),
+also bridged to [Matrix](https://matrix.to/#/#coreboot:libera.chat) and a
+[Discord](https://discord.gg/JqT8NM5Zbg) presence. You can also find us on
+[OSF Slack](https://osfw.slack.com/), which has channels on many open source
+firmware related topics.
 
 ## Fortnightly coreboot leadership meeting
 

diff --git a/Documentation/index.md b/Documentation/index.md
@@ -183,6 +183,7 @@ Contents:
 * [Mainboard](mainboard/index.md)
 * [Payloads](lib/payloads/index.md)
 * [Libraries](lib/index.md)
+* [Options](lib/option.md)
 * [Security](security/index.md)
 * [SuperIO](superio/index.md)
 * [Vendorcode](vendorcode/index.md)

diff --git a/Documentation/infrastructure/index.md b/Documentation/infrastructure/index.md
@@ -3,4 +3,4 @@
 This section contains documentation about coreboot infrastructure
 
 ## Jenkins builders and builds
-[Setting up Jenkins build machines](builders.md)
+* [Setting up Jenkins build machines](builders.md)
diff --git a/Documentation/lib/flashmap.md b/Documentation/lib/flashmap.md
@@ -17,7 +17,8 @@ something else) should have its own Flashmap section, and everything else should
 normally go into CBFS.
 
 The Flashmap itself starts with a header `struct fmap` and followed by a list of
-section descriptions in `struct fmap_area`.
+section descriptions in `struct fmap_area`. All fields in those structures are
+in little endian format.
 
 ### Header
 The header `struct fmap` has following fields:

diff --git a/Documentation/lib/option.md b/Documentation/lib/option.md
@@ -0,0 +1,31 @@
+# Option API
+
+The option API around the `set_option(const char *name, void *val)` and
+`get_option(void *dest, const char *name)` functions deprecated in favor
+of a type-safe API.
+
+Historically, options were stored in RTC battery-backed CMOS RAM inside
+the chipset on PC platforms. Nowadays, options can also be stored in the
+same flash chip as the boot firmware or through some BMC interface.
+
+The new type-safe option framework can be used by calling
+`enum cb_err set_uint_option(const char *name, unsigned int value)` and
+`unsigned int get_uint_option(const char *name, const unsigned int fallback)`.
+
+The default setting is `OPTION_BACKEND_NONE`, which disables any runtime
+configurable options. If supported by a mainboard, the `USE_OPTION_TABLE`
+and `USE_MAINBOARD_SPECIFIC_OPTION_BACKEND` choices are visible, and can
+be selected to enable runtime configurability.
+
+# Mainboard-specific option backend
+
+Mainboards with a mainboard-specific (vendor-defined) method to access
+options can select `HAVE_MAINBOARD_SPECIFIC_OPTION_BACKEND` to provide
+implementations of the option API accessors. To allow choosing between
+multiple option backends, the mainboard-specific implementation should
+only be built when `USE_MAINBOARD_SPECIFIC_OPTION_BACKEND` is selected.
+
+Where possible, using a generic, mainboard-independent mechanism should
+be preferred over reinventing the wheel in mainboard-specific code. The
+mainboard-specific approach should only be used when the option storage
+mechanism has to satisfy externally-imposed, vendor-defined constraints.
diff --git a/Documentation/mainboard/asus/p8h77-v.jpg b/Documentation/mainboard/asus/p8h77-v.jpg
diff --git a/Documentation/mainboard/asus/p8h77-v.md b/Documentation/mainboard/asus/p8h77-v.md
@@ -0,0 +1,81 @@
+# ASUS P8Z77-V
+
+This page describes how to run coreboot on the [ASUS P8H77-V].
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+----------------+
+| Type                | Value          |
++=====================+================+
+| Socketed flash      | yes            |
++---------------------+----------------+
+| Model               | W25Q64FVA1Q    |
++---------------------+----------------+
+| Size                | 8 MiB          |
++---------------------+----------------+
+| Package             | DIP-8          |
++---------------------+----------------+
+| Write protection    | yes            |
++---------------------+----------------+
+| Dual BIOS feature   | no             |
++---------------------+----------------+
+| Internal flashing   | no             |
++---------------------+----------------+
+```
+
+The flash IC is located beside the SATA ports (circled):
+![](p8z77-v.jpg)
+
+### How to flash
+
+The main SPI flash cannot be written because the vendor firmware disables BIOSWE
+and enables BLE/SMM_BWP flags in BIOS_CNTL for their latest BIOSes. An external
+programmer is required. You must flash standalone, flashing in-circuit doesn't
+work. The flash chip is socketed, so it's easy to remove and reflash.
+
+## Working
+
+- PS/2 keyboard with SeaBIOS 1.14.0 and Debian GNU/Linux with kernel 5.10.28
+- Integrated Ethernet NIC
+- S3 Suspend to RAM
+- USB2 on rear and front panel connectors
+- USB3
+- Integrated SATA
+- CPU Temp sensors (tested PSensor on GNU/Linux)
+- Native raminit
+- Integrated graphics with libgfxinit (VGA/DVI-D/HDMI tested and working)
+- PCIe in PCIe-16x slots
+- Debug output from serial port
+
+## Untested
+
+- EHCI debugging
+- S/PDIF audio
+- PS/2 mouse
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
++------------------+--------------------------------------------------+
+| Southbridge      | bd82x6x                                          |
++------------------+--------------------------------------------------+
+| CPU              | model_206ax                                      |
++------------------+--------------------------------------------------+
+| Super I/O        | Nuvoton NCT6779D                                 |
++------------------+--------------------------------------------------+
+| EC               | None                                             |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel Management Engine                          |
++------------------+--------------------------------------------------+
+```
+
+## Extra resources
+
+- [Flash chip datasheet][W25Q64FVA1Q]
+
+[ASUS P8H77-V]: https://www.asus.com/supportonly/p8h77v/helpdesk_knowledge/
+[W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
+[flashrom]: https://flashrom.org/Flashrom
diff --git a/Documentation/mainboard/asus/p8z77-v.jpg b/Documentation/mainboard/asus/p8z77-v.jpg
diff --git a/Documentation/mainboard/asus/p8z77-v.md b/Documentation/mainboard/asus/p8z77-v.md
@@ -0,0 +1,112 @@
+# ASUS P8Z77-V
+
+This page describes how to run coreboot on the [ASUS P8Z77-V].
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+----------------+
+| Type                | Value          |
++=====================+================+
+| Socketed flash      | yes            |
++---------------------+----------------+
+| Model               | W25Q64FVA1Q    |
++---------------------+----------------+
+| Size                | 8 MiB          |
++---------------------+----------------+
+| Package             | DIP-8          |
++---------------------+----------------+
+| Write protection    | yes            |
++---------------------+----------------+
+| Dual BIOS feature   | no             |
++---------------------+----------------+
+| Internal flashing   | no             |
++---------------------+----------------+
+```
+
+The flash IC is located between the black and white PCI Express x16 slots (circled):
+![](p8z77-v.jpg)
+
+### How to flash
+
+The main SPI flash cannot be written because the vendor firmware disables BIOSWE
+and enables BLE/SMM_BWP flags in BIOS_CNTL for their latest BIOSes. An external
+programmer is required. You must flash standalone, flashing in-circuit doesn't
+work. The flash chip is socketed, so it's easy to remove and reflash.
+
+## Working
+
+- PS/2 keyboard with SeaBIOS 1.14.0 and Debian GNU/Linux with kernel 5.10.28
+- Integrated Ethernet NIC
+- S3 Suspend to RAM
+- USB2 on rear and front panel connectors
+- USB3 (Z77's and ASMedia's works)
+- Integrated SATA of Z77
+- Integrated SATA of ASM1061 (works under GNU/Linux but not under SeaBIOS)
+- CPU Temp sensors (tested PSensor on GNU/Linux)
+- TPM on TPM-header (tested tpm-tools with TPM 1.2 Infineon SLB9635TT12)
+- Native raminit
+- Integrated graphics with libgfxinit (VGA/DVI-D/HDMI tested and working)
+- PCIe in PCIe-16x/8x slots (tested using an S3 Matrix GPU)
+- Debug output from serial port
+- Atheros AR9485 half-height mini PCIe WNIC adapted with Wi-Fi Go! Adapter
+- Default PCIe config (PCIEX_16_3 as 1x, PCIe Port 4 to ASM1061 SATA, see below
+  for other potential options)
+
+## Untested
+
+- EHCI debugging
+- S/PDIF audio
+- PS/2 mouse
+
+## Not working
+
+- PCIEX_1_2 (expected under default PCIe config)
+- Other PCIe configs (see below)
+
+## PCIe config
+On Asus vendor firmware, other than the default config already supported here,
+there remain another two configs: "PCIEX_16_3 as x4, with PCIEX_1_1, PCIEX_1_2
+and onboard ASM1061 disabled" and "PCIEX_16_3 as x1, but PCIe Port 4 to PCIEX_1_2,
+with onboard ASM1061 disabled".
+
+Configuring PCIEX_16_3 as x4 needs to program 0x3 to the LSB of PCHSTRP9, but
+also needs to configure GPIOs in the Super I/O chip different than the default
+config in this board's override tree.
+
+Configuring PCIe Port 4 to PCIEX_1_2 needs to configure GPIOs in the Super I/O
+chip differently than the default config.
+
+I have tried a lot, but sadly I am unable to produce the same result as the vendor
+firmware.
+
+## Asus Wi-Fi Go!
+Asus Wi-Fi Go! has several versions. P8Z77-V has the earliest version.
+See [Asus Wi-Fi Go! v1].
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
++------------------+--------------------------------------------------+
+| Southbridge      | bd82x6x                                          |
++------------------+--------------------------------------------------+
+| CPU              | model_206ax                                      |
++------------------+--------------------------------------------------+
+| Super I/O        | Nuvoton NCT6779D                                 |
++------------------+--------------------------------------------------+
+| EC               | None                                             |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel Management Engine                          |
++------------------+--------------------------------------------------+
+```
+
+## Extra resources
+
+- [Flash chip datasheet][W25Q64FVA1Q]
+
+[ASUS P8Z77-V]: https://www.asus.com/supportonly/p8z77v/helpdesk_knowledge/
+[W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
+[flashrom]: https://flashrom.org/Flashrom
+[Asus Wi-Fi Go! v1]: ./wifigo_v1.md
diff --git a/Documentation/mainboard/asus/wifigo_v1.md b/Documentation/mainboard/asus/wifigo_v1.md
@@ -0,0 +1,40 @@
+# Asus Wi-Fi Go! v1
+
+In this version, a standard half-length mPCIe card is mounted on the Asus Wi-Fi
+Go! daughter board, and the daughter board is connected to the motherboard
+through a proprietary 16-1 pin connector.
+![](wifigo_v1_connector.jpg)
+
+I managed to grope the most pinout of the proprietary connector.
+See [Mini PCIe pinout] for more info.
+
+```eval_rst
++------------+----------+-----------+------------+----------+-----------+
+| WIFIGO Pin | Usage    | mPCIe pin | WIFIGO Pin | Usage    | mPCIe pin |
++============+==========+===========+============+==========+===========+
+| 1          | 3.3v     | (many)    | 2          | REFCLK-  | 11        |
++------------+----------+-----------+------------+----------+-----------+
+| 3          | GND      | (many)    | 4          | REFCLK+  | 13        |
++------------+----------+-----------+------------+----------+-----------+
+| 5          | WAKE#    | 1         | 6          | PERn0    | 23        |
++------------+----------+-----------+------------+----------+-----------+
+| 7          | (absent) |           | 8          | PERp0    | 25        |
++------------+----------+-----------+------------+----------+-----------+
+| 9          | GND      |           | 10         | PETn0    | 31        |
++------------+----------+-----------+------------+----------+-----------+
+| 11         | PERST#   | 20        | 12         | PETp0    | 33        |
++------------+----------+-----------+------------+----------+-----------+
+| 13         | GND      |           | 14         | (USBD-?) | (36?)     |
++------------+----------+-----------+------------+----------+-----------+
+| 15         | 3.3v     |           | 16         | (USBD+?) | (38?)     |
++------------+----------+-----------+------------+----------+-----------+
+```
+
+There are two kinds of daughter boards using this connector. One among them has
+one MMCX antenna connector, the other has two antenna connectors and USB lane
+wired (this kind may be called BT Go!). I can only obtain the former, so I
+cannot confirm the exact way the USB data lane gets wired.
+![](wifigo_v1_board.jpg)
+
+## Extra resources
+[Mini PCIe pinout]: https://pinoutguide.com/Slots/mini_pcie_pinout.shtml
diff --git a/Documentation/mainboard/asus/wifigo_v1_board.jpg b/Documentation/mainboard/asus/wifigo_v1_board.jpg
diff --git a/Documentation/mainboard/asus/wifigo_v1_connector.jpg b/Documentation/mainboard/asus/wifigo_v1_connector.jpg
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
@@ -21,7 +21,9 @@ This section contains documentation about coreboot on specific mainboards.
 - [P5Q](asus/p5q.md)
 - [P8H61-M LX](asus/p8h61-m_lx.md)
 - [P8H61-M Pro](asus/p8h61-m_pro.md)
+- [P8H77-V](asus/p8h77-v.md)
 - [P8Z77-M Pro](asus/p8z77-m_pro.md)
+- [P8Z77-V](asus/p8z77-v.md)
 
 ## Cavium
 
@@ -153,6 +155,7 @@ The boards in this section are not real mainboards, but emulators.
 
 ## Purism
 
+- [Librem 14](purism/librem_14.md)
 - [Librem Mini](purism/librem_mini.md)
 
 ## Protectli

diff --git a/Documentation/mainboard/supermicro/flashing_on_vendorbmc.md b/Documentation/mainboard/supermicro/flashing_on_vendorbmc.md
@@ -34,7 +34,7 @@ message on updating the BIOS.
 ## Flashing with disabled ME
 
 If ME is disabled via `me_cleaner` or the ME recovery jumper, it is still
-possible to flash remotely with the [`Supermicro Update Manager`](SUM) (`SUM`).
+possible to flash remotely with the [`Supermicro Update Manager`][SUM] (`SUM`).
 
 ```sh
 ./sum -i <remote BMC IP> -u <user> -p <password> -c UpdateBios --reboot \

diff --git a/Documentation/security/vboot/list_vboot.md b/Documentation/security/vboot/list_vboot.md
@@ -172,6 +172,8 @@
 - Homestar
 - Lazor
 - Marzipan
+- Mrbland
+- Pazquel
 - Pompom
 - Trogdor
 - Veyron_Jaq (Haier Chromebook 11)

diff --git a/Documentation/technotes/index.md b/Documentation/technotes/index.md
@@ -3,4 +3,5 @@
 * [Dealing with Untrusted Input in SMM](2017-02-dealing-with-untrusted-input-in-smm.md)
 * [Rebuilding coreboot image generation](2015-11-rebuilding-coreboot-image-generation.md)
 * [Unit testing coreboot](2020-03-unit-testing-coreboot.md)
+* [Unit Test Code Coverage](2021-05-code-coverage.md)
 * [Address Sanitizer](asan.md)