Showing 682 changed files with 16,135 additions and 14,551 deletions.
diff --git a/3rdparty/vboot b/3rdparty/vboot
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -12,6 +12,10 @@ official [coreboot repository](https://review.coreboot.org/cgit/coreboot.git)
 Please use [pce-fw-builder](https://github.com/pcengines/pce-fw-builder)
 
 ## [Unreleased]
+## [v4.14.0.3] - 2021-07-29
+### Changed
+- rebased with official coreboot repository commit c049c80
+
 ## [v4.14.0.2] - 2021-06-28
 ### Changed
 - rebased with official coreboot repository commit 1c43d92
@@ -512,7 +516,8 @@ redundant code which was similar for APU2/3/5 boards.
 - turn off D4 and D5 leds on boot
 - enable power on after power failure
 
-[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.14.0.2...develop
+[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.14.0.3-rc1...develop
+[v4.14.0.3]: https://github.com/pcengines/coreboot/compare/v4.13.0.2...v4.14.0.3-rc1
 [v4.14.0.2]: https://github.com/pcengines/coreboot/compare/v4.13.0.1...v4.14.0.2
 [v4.14.0.1]: https://github.com/pcengines/coreboot/compare/v4.13.0.6...v4.14.0.1
 [v4.13.0.6]: https://github.com/pcengines/coreboot/compare/v4.13.0.5...v4.13.0.6

diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md
@@ -66,25 +66,6 @@ across architectures.
 ### Mentors
 * Timothy Pearson <tpearson@raptorengineering.com>
 
-## Add Kernel Address Sanitizer functionality to coreboot
-The Kernel Address Sanitizer (KASAN) is a runtime dynamic memory error detector.
-The idea is to check every memory access (variables) for its validity
-during runtime and find bugs like stack overflow or out-of-bounds accesses.
-Implementing this stub into coreboot like "Undefined behavior sanitizer support"
-would help to ensure code quality and make the runtime code more robust.
-
-### Requirements
-* knowledge in the coreboot build system and the concept of stages
-* the KASAN feature can be improved in a way so that the memory space needed
-  during runtime is not on a fixed address provided during compile time but
-  determined during runtime. For this to achieve a small patch to the GCC will
-  be helpful. Therefore minor GCC knowledge would be beneficial.
-* Implementation can be initially done in QEMU and improved on different
-  mainboards and platforms
-
-### Mentors
-* Werner Zeh <werner.zeh@gmx.net>
-
 ## Port payloads to ARM, AArch64 or RISC-V
 While we have a rather big set of payloads for x86 based platforms, all other
 architectures are rather limited. Improve the situation by porting a payload

diff --git a/Documentation/drivers/dptf.md b/Documentation/drivers/dptf.md
@@ -311,3 +311,19 @@ table for a given temperature threshold.
 1) Hysteresis - The amount of hysteresis implemented in either circuitry or
    the firmware that reads the temperature sensor (in degrees C).
 2) Name - This name is applied to the _STR property of the sensor
+
+## OEM Variables
+Platform vendors can define an array of OEM-specific values as OEM variables
+to be used under DPTF policy. There are total six OEM variables available.
+These can be used in AP policy for more specific actions. These OEM variables
+can be defined as below mentioned example and can be used any variable between
+[0], [1],...,[5]. Platform vendors can enable and use this for specific platform
+by defining OEM variables macro under board variant.
+
+Example:
+```C
+register "oem_data.oem_variables" = "{
+   [1] = 0x6,
+   [3] = 0x1
+}"
+```
diff --git a/Documentation/getting_started/kconfig.md b/Documentation/getting_started/kconfig.md
@@ -55,10 +55,6 @@ command line.
 - savedefconfig - Creates a ‘defconfig’ file, stripping out all of the symbols
   that were left as default values.  This is very useful for debugging, and is
   how config files should be saved.
-- silentoldconfig - This evaluates the .config file the same way that the
-  oldconfig target does, but does not print out each question as it is
-  evaluated.  It still stops to query the user if an option with no answer in
-  the .config file is found.
 
 
 ### Targets not typically used in coreboot

diff --git a/Documentation/mainboard/asus/p8c_ws.jpg b/Documentation/mainboard/asus/p8c_ws.jpg
diff --git a/Documentation/mainboard/asus/p8c_ws.md b/Documentation/mainboard/asus/p8c_ws.md
@@ -0,0 +1,94 @@
+# ASUS P8C WS
+
+This page describes how to run coreboot on the [ASUS P8H77-V].
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+----------------+
+| Type                | Value          |
++=====================+================+
+| Socketed flash      | yes            |
++---------------------+----------------+
+| Model               | W25Q64FVA1Q    |
++---------------------+----------------+
+| Size                | 8 MiB          |
++---------------------+----------------+
+| Package             | DIP-8          |
++---------------------+----------------+
+| Write protection    | no             |
++---------------------+----------------+
+| Dual BIOS feature   | no             |
++---------------------+----------------+
+| Internal flashing   | yes            |
++---------------------+----------------+
+```
+
+The flash IC is located beside the SATA ports (circled):
+![](p8c_ws.jpg)
+
+### How to flash
+
+Unlike ordinary desktop boards, the BIOS version 3202 of ASUS P8C WS does not
+apply any write protection, so the main SPI flash can be accessed using
+[flashrom], and the whole flash is writable.
+
+The following command may be used to flash coreboot. (To do so, linux kernel
+should be started with `iomem=relaxed`)
+
+```
+# flashrom -p internal -w coreboot.rom
+```
+
+The flash chip is a socketed DIP-8 SPI flash, so it's also easy to remove and
+flash externally.
+
+## Working
+- Intel Xeon E3-1225 V2 with 4 M391B1G73BH0-YK0 UDIMMs, ECC confirmed active
+- PS/2 keyboard with SeaBIOS 1.14.0 and Debian GNU/Linux with kernel 5.10.40
+- Both Onboard NIC
+- S3 Suspend to RAM
+- USB2 on rear and front panel connectors
+- USB3
+- Integrated SATA
+- CPU Temp sensors (tested PSensor on GNU/Linux)
+- LPC TPM on TPM-header (tested tpm-tools with TPM 1.2 Infineon SLB9635TT12)
+- Native raminit
+- Integrated graphics with libgfxinit (both analog and digital output from DVI-I)
+- Nvidia Quadro 600 in all PCIe-16x slots
+- Compex WLM200NX (Qualcomm Atheros AR9220) in PCI slot
+- Onboard IEEE1394 controller under PCI bus
+- Debug output from serial port
+
+## Untested
+
+- EHCI debugging
+- S/PDIF audio
+- PS/2 mouse
+- LPT port
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
++------------------+--------------------------------------------------+
+| Southbridge      | bd82x6x                                          |
++------------------+--------------------------------------------------+
+| CPU              | model_206ax                                      |
++------------------+--------------------------------------------------+
+| Super I/O        | Nuvoton NCT6776F                                 |
++------------------+--------------------------------------------------+
+| EC               | None                                             |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel Management Engine                          |
++------------------+--------------------------------------------------+
+```
+
+## Extra resources
+
+- [Flash chip datasheet][W25Q64FVA1Q]
+
+[ASUS P8C WS]: https://www.asus.com/supportonly/p8c_ws/helpdesk_knowledge/
+[W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
+[flashrom]: https://flashrom.org/Flashrom
diff --git a/Documentation/mainboard/emulation/qemu-i440fx.md b/Documentation/mainboard/emulation/qemu-i440fx.md
@@ -15,7 +15,7 @@ processor supports x86_64 instructions (long mode).
 The qemu-i440fx mainboard has been ported to x86_64 and will serve as
 reference platform to enable additional platforms.
 
-To enable the support set the Kconfig option ``CONFIG_CPU_QEMU_X86_64=y``.
+To enable the support set the Kconfig option ``CONFIG_USE_EXP_X86_64_SUPPORT=y``.
 
 ## Installing qemu
 

diff --git a/Documentation/mainboard/emulation/qemu-q35.md b/Documentation/mainboard/emulation/qemu-q35.md
@@ -15,7 +15,7 @@ processor supports x86_64 instructions (long mode).
 The qemu-q35 mainboard has been ported to x86_64 and will serve as
 reference platform to enable additional platforms.
 
-To enable the support set the Kconfig option ``CONFIG_CPU_QEMU_X86_64=y``.
+To enable the support set the Kconfig option ``CONFIG_USE_EXP_X86_64_SUPPORT=y``.
 
 ## Installing qemu
 

diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
@@ -19,6 +19,7 @@ This section contains documentation about coreboot on specific mainboards.
 - [A88XM-E](asus/a88xm-e.md)
 - [F2A85-M](asus/f2a85-m.md)
 - [P5Q](asus/p5q.md)
+- [P8C WS](asus/p8c_ws.md)
 - [P8H61-M LX](asus/p8h61-m_lx.md)
 - [P8H61-M Pro](asus/p8h61-m_pro.md)
 - [P8H77-V](asus/p8h77-v.md)

diff --git a/Makefile b/Makefile
@@ -37,7 +37,7 @@ KCONFIG_AUTOADS := $(obj)/cb-config.ads
 KCONFIG_AUTOHEADER := $(obj)/config.h
 KCONFIG_AUTOCONFIG := $(obj)/auto.conf
 KCONFIG_DEPENDENCIES := $(obj)/auto.conf.cmd
-KCONFIG_SPLITCONFIG := $(obj)/config
+KCONFIG_SPLITCONFIG := $(obj)/config/
 KCONFIG_TRISTATE := $(obj)/tristate.conf
 KCONFIG_NEGATIVES := 1
 KCONFIG_STRICT := 1
@@ -196,7 +196,8 @@ real-all: real-target
 .DELETE_ON_ERROR:
 
 $(KCONFIG_AUTOHEADER): $(KCONFIG_CONFIG) $(objutil)/kconfig/conf
-	+$(MAKE) oldconfig
+	$(MAKE) olddefconfig
+	$(MAKE) syncconfig
 
 $(KCONFIG_AUTOCONFIG): $(KCONFIG_AUTOHEADER)
 	true

diff --git a/Makefile.inc b/Makefile.inc
@@ -1090,7 +1090,7 @@ TS_OPTIONS := -j $(CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE)
 endif
 
 ifneq ($(CONFIG_UPDATE_IMAGE),y)
-$(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $(IFITTOOL) $$(cpu_ucode_cbfs_file) $(obj)/fmap.fmap $(obj)/fmap.desc
+$(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $(obj)/fmap.fmap $(obj)/fmap.desc
 	$(CBFSTOOL) $@.tmp create -M $(obj)/fmap.fmap -r $(shell cat $(obj)/fmap.desc)
 ifeq ($(CONFIG_ARCH_X86),y)
 	$(CBFSTOOL) $@.tmp add \
@@ -1146,7 +1146,7 @@ add_intermediate = \
 	$(1): $(obj)/coreboot.pre $(2) | $(INTERMEDIATE) \
 	$(eval INTERMEDIATE+=$(1)) $(eval PHONY+=$(1))
 
-$(obj)/coreboot.rom: $(obj)/coreboot.pre $(RAMSTAGE) $(CBFSTOOL) $$(INTERMEDIATE)
+$(obj)/coreboot.rom: $(obj)/coreboot.pre $(CBFSTOOL) $(IFITTOOL) $$(INTERMEDIATE)
 	@printf "    CBFS       $(subst $(obj)/,,$(@))\n"
 # The full ROM may be larger than the CBFS part, so create an empty
 # file (filled with \377 = 0xff) and copy the CBFS image over it.

diff --git a/configs/config.cavium_cn8100_sff_evb_bdk_verbose_fit_payload_support b/configs/config.cavium_cn8100_sff_evb_bdk_verbose_fit_payload_support
@@ -1,4 +1,5 @@
 CONFIG_VENDOR_CAVIUM=y
+CONFIG_BOARD_CAVIUM_CN8100_SFF_EVB=y
 CONFIG_CAVIUM_BDK_VERBOSE_INIT=y
 CONFIG_CAVIUM_BDK_VERBOSE_DRAM=y
 CONFIG_CAVIUM_BDK_VERBOSE_DRAM_TEST=y

diff --git a/configs/config.emulation_qemu_aarch64_fit_support_timestamps b/configs/config.emulation_qemu_aarch64_fit_support_timestamps
@@ -1,3 +1,4 @@
+CONFIG_VENDOR_EMULATION=y
 CONFIG_COLLECT_TIMESTAMPS=y
 CONFIG_TIMESTAMPS_ON_CONSOLE=y
 CONFIG_MAINBOARD_VENDOR="Emulation"

diff --git a/configs/config.emulation_qemu_riscv_rv64 b/configs/config.emulation_qemu_riscv_rv64
@@ -1,2 +1,3 @@
+CONFIG_VENDOR_EMULATION=y
 CONFIG_BOARD_EMULATION_QEMU_RISCV_RV64=y
 CONFIG_RISCV_OPENSBI=y
diff --git a/configs/config.emulation_qemu_x86_i440fx_asan b/configs/config.emulation_qemu_x86_i440fx_asan
@@ -1 +1,3 @@
+CONFIG_VENDOR_EMULATION=y
+CONFIG_BOARD_EMULATION_QEMU_X86_I440FX=y
 CONFIG_ASAN=y
diff --git a/configs/config.emulation_qemu_x86_i440fx_debug b/configs/config.emulation_qemu_x86_i440fx_debug
@@ -1,3 +1,5 @@
+CONFIG_VENDOR_EMULATION=y
+CONFIG_BOARD_EMULATION_QEMU_X86_I440FX=y
 CONFIG_GDB_STUB=y
 CONFIG_GDB_WAIT=y
 CONFIG_FATAL_ASSERTS=y

diff --git a/configs/config.emulation_qemu_x86_i440fx_noserial b/configs/config.emulation_qemu_x86_i440fx_noserial
@@ -1,3 +1,5 @@
+CONFIG_VENDOR_EMULATION=y
+CONFIG_BOARD_EMULATION_QEMU_X86_I440FX=y
 CONFIG_COLLECT_TIMESTAMPS=y
 # CONFIG_POST_IO is not set
 # CONFIG_POST_DEVICE is not set

diff --git a/configs/config.emulation_qemu_x86_i440fx_x86_64 b/configs/config.emulation_qemu_x86_i440fx_x86_64
@@ -1 +1,3 @@
-CONFIG_CPU_QEMU_X86_64=y
+CONFIG_VENDOR_EMULATION=y
+CONFIG_BOARD_EMULATION_QEMU_X86_I440FX=y
+CONFIG_USE_EXP_X86_64_SUPPORT=y
diff --git a/configs/config.emulation_qemu_x86_q35_smm_tseg b/configs/config.emulation_qemu_x86_q35_smm_tseg
@@ -1,3 +1,4 @@
+CONFIG_VENDOR_EMULATION=y
 CONFIG_BOARD_EMULATION_QEMU_X86_Q35=y
 CONFIG_CPU_QEMU_X86_PARALLEL_MP=y
 CONFIG_CPU_QEMU_X86_TSEG_SMM=y

diff --git a/configs/config.facebook_fbg1701.mboot_vboot b/configs/config.facebook_fbg1701.mboot_vboot
@@ -1,4 +1,5 @@
 CONFIG_VENDOR_FACEBOOK=y
+CONFIG_BOARD_FACEBOOK_FBG1701=y
 CONFIG_ONBOARD_SAMSUNG_MEM=y
 CONFIG_CPU_MICROCODE_CBFS_LOC=0xFFF8B000
 CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y

diff --git a/configs/config.foxconn_g41m b/configs/config.foxconn_g41m
@@ -0,0 +1,3 @@
+CONFIG_VENDOR_FOXCONN=y
+CONFIG_BOARD_FOXCONN_G41M=y
+CONFIG_USE_EXP_X86_64_SUPPORT=y
diff --git a/configs/config.hp_compaq_8200_elite_sff_pc.x86_64 b/configs/config.hp_compaq_8200_elite_sff_pc.x86_64
@@ -0,0 +1,3 @@
+CONFIG_VENDOR_HP=y
+CONFIG_BOARD_HP_COMPAQ_8200_ELITE_SFF_PC=y
+CONFIG_USE_EXP_X86_64_SUPPORT=y
diff --git a/configs/config.libretrend_lt1000 b/configs/config.libretrend_lt1000
@@ -1,4 +1,5 @@
 CONFIG_VENDOR_LIBRETREND=y
+CONFIG_BOARD_LIBRETREND_LT1000=y
 CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
 CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
 CONFIG_TPM2=y

diff --git a/configs/config.ocp_deltalake_cbnt b/configs/config.ocp_deltalake_cbnt
@@ -1,4 +1,5 @@
 CONFIG_VENDOR_OCP=y
+CONFIG_BOARD_OCP_DELTALAKE=y
 CONFIG_INTEL_TXT_BIOSACM_FILE="3rdparty/intel-sec-tools/testdata/fake_acm/biosacm_cbnt_fake.bin"
 CONFIG_INTEL_TXT_LOGGING=y
 CONFIG_INTEL_CBNT_SUPPORT=y

diff --git a/configs/config.pcengines_apu1 b/configs/config.pcengines_apu1
@@ -1,13 +1,21 @@
-CONFIG_LOCALVERSION="v4.14.0.2"
+CONFIG_LOCALVERSION="v4.14.0.3"
 CONFIG_VENDOR_PCENGINES=y
+CONFIG_CBFS_SIZE=0x00200000
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+CONFIG_BOTTOMIO_POSITION=0x80000000
+CONFIG_UART_PCI_ADDR=0x0
 CONFIG_NO_GFX_INIT=y
+CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
+CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
 CONFIG_TPM2=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
+CONFIG_POST_IO_PORT=0x80
 CONFIG_SEABIOS_REVISION=y
 CONFIG_SEABIOS_REVISION_ID="rel-1.14.0.1"
 CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder"
 CONFIG_SEABIOS_DEBUG_LEVEL=0
+CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
 # CONFIG_PXE_SERIAL_CONSOLE is not set

diff --git a/configs/config.pcengines_apu2 b/configs/config.pcengines_apu2
@@ -1,16 +1,25 @@
-CONFIG_LOCALVERSION="v4.14.0.2"
+CONFIG_LOCALVERSION="v4.14.0.3"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_PXE_ROM_ID="8086,157b"
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
 CONFIG_BOARD_PCENGINES_APU2=y
+CONFIG_BOTTOMIO_POSITION=0xD0000000
+CONFIG_UART_PCI_ADDR=0x0
+CONFIG_HUDSON_SATA_MODE=2
+CONFIG_AGESA_BINARY_PI_LOCATION=0xFFE00000
 CONFIG_NO_GFX_INIT=y
+CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
+CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
 CONFIG_TPM2=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
+CONFIG_POST_IO_PORT=0x80
 CONFIG_SEABIOS_REVISION=y
 CONFIG_SEABIOS_REVISION_ID="rel-1.14.0.1"
 CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y
 CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_DEBUG_LEVEL=0
+CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
 # CONFIG_PXE_SERIAL_CONSOLE is not set

diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu3
@@ -1,16 +1,25 @@
-CONFIG_LOCALVERSION="v4.14.0.2"
+CONFIG_LOCALVERSION="v4.14.0.3"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
-CONFIG_BOARD_PCENGINES_APU3=y
 CONFIG_PXE_ROM_ID="8086,1539"
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+CONFIG_BOARD_PCENGINES_APU3=y
+CONFIG_BOTTOMIO_POSITION=0xD0000000
+CONFIG_UART_PCI_ADDR=0x0
+CONFIG_HUDSON_SATA_MODE=2
+CONFIG_AGESA_BINARY_PI_LOCATION=0xFFE00000
 CONFIG_NO_GFX_INIT=y
+CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
+CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
 CONFIG_TPM2=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
+CONFIG_POST_IO_PORT=0x80
 CONFIG_SEABIOS_REVISION=y
 CONFIG_SEABIOS_REVISION_ID="rel-1.14.0.1"
 CONFIG_SEABIOS_BOOTORDER_IN_FMAP=y
 CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_DEBUG_LEVEL=0
+CONFIG_SEABIOS_SERCON_PORT_ADDR=0x3f8
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
 # CONFIG_PXE_SERIAL_CONSOLE is not set