Showing 1,129 changed files with 24,657 additions and 9,663 deletions.
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
@@ -91,7 +91,7 @@ check_dependencies:
   stage: run_regression
   tags:
     - local
-  timeout: 12h
+  timeout: 24h
   script:
     - bash -x .gitlab-ci/regression.sh
   only:

diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware
diff --git a/3rdparty/chromeec b/3rdparty/chromeec
diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode
diff --git a/3rdparty/qc_blobs b/3rdparty/qc_blobs
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -12,6 +12,15 @@ official [coreboot repository](https://review.coreboot.org/cgit/coreboot.git)
 Please use [pce-fw-builder](https://github.com/pcengines/pce-fw-builder)
 
 ## [Unreleased]
+## [v4.14.0.4] - 2021-09-06
+### Changed
+- rebased with official coreboot repository commit d9f5d90
+- enabled EHCI controller by default on apu3-apu6 platforms
+- [updated sortbootorder to v4.6.22](https://github.com/pcengines/sortbootorder/blob/master/CHANGELOG.md#v4622---2021-09-06)
+
+### Added
+- safeguard against setting watchdog timeout too low
+
 ## [v4.14.0.3] - 2021-07-29
 ### Changed
 - rebased with official coreboot repository commit c049c80
@@ -516,8 +525,9 @@ redundant code which was similar for APU2/3/5 boards.
 - turn off D4 and D5 leds on boot
 - enable power on after power failure
 
-[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.14.0.3-rc1...develop
-[v4.14.0.3]: https://github.com/pcengines/coreboot/compare/v4.13.0.2...v4.14.0.3-rc1
+[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.14.0.4...develop
+[v4.14.0.4]: https://github.com/pcengines/coreboot/compare/v4.13.0.3...v4.14.0.4
+[v4.14.0.3]: https://github.com/pcengines/coreboot/compare/v4.13.0.2...v4.14.0.3
 [v4.14.0.2]: https://github.com/pcengines/coreboot/compare/v4.13.0.1...v4.14.0.2
 [v4.14.0.1]: https://github.com/pcengines/coreboot/compare/v4.13.0.6...v4.14.0.1
 [v4.13.0.6]: https://github.com/pcengines/coreboot/compare/v4.13.0.5...v4.13.0.6

diff --git a/Documentation/drivers/soundwire.md b/Documentation/drivers/soundwire.md
@@ -375,7 +375,7 @@ chip and can be decoded for this table with the codec datasheet and board schema
  * @version: SoundWire specification version from &enum soundwire_version.
  * @link_id: Zero-based SoundWire Link Number.
  * @unique_id: Unique ID for multiple devices.
- * @manufacturer_id: Manufacturer ID from include/device/mipi_ids.h.
+ * @manufacturer_id: Manufacturer ID from include/mipi/ids.h.
  * @part_id: Vendor defined part ID.
  * @class: MIPI class encoding in &enum mipi_class.
  */

diff --git a/Documentation/getting_started/kconfig.md b/Documentation/getting_started/kconfig.md
@@ -1188,7 +1188,7 @@ https://github.com/martinlroth/language-kconfig
 ## Syntax Checking:
 
 The Kconfig utility does some basic syntax checking on the Kconfig tree.
-Running "make silentoldconfig" will show any errors that the Kconfig utility
+Running "make oldconfig" will show any errors that the Kconfig utility
 sees.
 
 ### util/kconfig_lint

diff --git a/Documentation/mainboard/ocp/deltalake.md b/Documentation/mainboard/ocp/deltalake.md
@@ -63,7 +63,7 @@ VPD variables supported are:
 - systemboot_log_level: u-root package systemboot log levels, would be mapped to
   quiet/verbose in systemboot as that is all we have for now. 5 to 8 would be
   mapped to verbose, 0 to 4 and 9 would be mapped to quiet.
-- VPDs affecting coreboot are listed/documented in src/mainboard/ocp/deltalake/vpd.h.
+- VPDs affecting coreboot are listed/documented in [src/mainboard/ocp/deltalake/vpd.h].
 
 ## Working features
 The solution is developed using LinuxBoot payload with Linux kernel 5.2.9,
@@ -117,8 +117,12 @@ and [u-root] as initramfs.
 - Power button
 - localboot
 - netboot from IPv6
-- basic memory hardware error injection/detection (SMI handlers not upstreamed)
-- basic PCIe hardware error injection/detection (SMI handlers not upstreamed)
+- RAS (SMI handlers not upstreamed)
+    - EINJ/HEST
+    - error injection through ITP
+    - memory error handling
+    - PCIe error handling
+    - PCIe live error recovery (LER)
 
 ## Stress/performance tests passed
 - OS warm reboot (1000 cycles)
@@ -154,7 +158,6 @@ and [u-root] as initramfs.
 - flashrom command not able to update ME region
 - ACPI BERT table
 - PCIe hotplug through VPP (Virtual Pin Ports)
-- PCIe Live Error Recovery
 - RO_VPD region as well as other RO regions are not write protected
 - Not able to selectively enable/disable core
 
@@ -176,3 +179,4 @@ and [u-root] as initramfs.
 [All about u-root]: https://github.com/linuxboot/book/tree/master/u-root
 [u-root]: https://u-root.org/
 [ChromeOS VPD]: https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/README.md
+[src/mainboard/ocp/deltalake/vpd.h]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/src/mainboard/ocp/deltalake/vpd.h
diff --git a/Documentation/mainboard/supermicro/x9sae.jpg b/Documentation/mainboard/supermicro/x9sae.jpg
diff --git a/Documentation/mainboard/supermicro/x9sae.md b/Documentation/mainboard/supermicro/x9sae.md
@@ -0,0 +1,108 @@
+# Supermicro X9SAE and X9SAE-V
+
+This page describes how to run coreboot on the Supermicro [X9SAE] and [X9SAE-V]
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+----------------+
+| Type                | Value          |
++=====================+================+
+| Socketed flash      | occasionally   |
++---------------------+----------------+
+| Model               | W25Q128FVSG    |
++---------------------+----------------+
+| Size                | 16 MiB         |
++---------------------+----------------+
+| Package             | SOIC-8         |
++---------------------+----------------+
+| Write protection    | no             |
++---------------------+----------------+
+| Dual BIOS feature   | no             |
++---------------------+----------------+
+| Internal flashing   | yes            |
++---------------------+----------------+
+```
+
+The flash IC is located between the PCH and the front panel connector,
+(circled) sometimes it is socketed.
+![](x9sae.jpg)
+
+### How to flash
+
+Unlike ordinary desktop boards, the BIOS version 2.00 of X9SAE-V does not
+apply any write protection, so the main SPI flash can be accessed using
+[flashrom], and the whole flash is writable.
+
+Note: If you are going to modify the ME region via internal programming, you had
+better disable ME functionalities as much as possible in the vendor firmware
+first, otherwise ME may write something back and break the firmware you write.
+
+The following command may be used to flash coreboot. (To do so, linux kernel
+could be started with `iomem=relaxed` or unload the `lpc_ich` kernel module)
+
+Now you can [flash internally](/flash_tutorial/int_flashrom.md). It is
+recommended to flash only the `bios` region (use `--ifd -i bios -N` flashrom
+arguments), in order to minimize the chances of messing something up in the
+beginning.
+
+The flash chip is a SOIC-8 SPI flash, and may be socketed, so it's also easy
+to do in-system programming, or remove and flash externally if it is socketed.
+
+## Difference between X9SAE and X9SAE-V
+On X9SAE PCI-E slot 4 is absent. Lane 9~16 of PCI-E slot 6 on X9SAE are wired
+to slot 4 on X9SAE-V. Unlike ASUS P8C WS, there is no dynamic switch on X9SAE-V,
+so on X9SAE-V slot 6 can work as x8 at most.
+
+On X9SAE-V device pci 01.1 appears even if not defined in devicetree.cb, so it
+seems that it shall not appear on X9SAE even if it is defined.
+
+## Working (on my X9SAE-V)
+- Intel Xeon E3-1225 V2 with 4 M391B1G73BH0-YK0 UDIMMs, ECC confirmed active
+- PS/2 keyboard with SeaBIOS 1.14.0 and Debian GNU/Linux with kernel 5.10.46
+- Use PS/2 keyboard and mouse simutaneously with a PS/2 Y-cable
+- Both Onboard NIC
+- S3 Suspend to RAM
+- USB2 on rear and front panel connectors
+- USB3
+- Integrated SATA
+- CPU Temp sensors (tested PSensor on GNU/Linux)
+- LPC TPM on TPM-header (tested tpm-tools with TPM 1.2 Infineon SLB9635TT12)
+- Native raminit
+- Integrated graphics with libgfxinit
+- Nvidia Quadro 600 in all PCIe-16x slots
+- Compex WLM200NX (Qualcomm Atheros AR9220) in PCI slot
+- Debug output from serial port
+
+## Untested
+
+- EHCI debugging
+- S/PDIF audio
+- PS/2 mouse
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
++------------------+--------------------------------------------------+
+| Southbridge      | bd82x6x                                          |
++------------------+--------------------------------------------------+
+| CPU              | model_206ax                                      |
++------------------+--------------------------------------------------+
+| Super I/O        | Nuvoton NCT6776F                                 |
++------------------+--------------------------------------------------+
+| EC               | None                                             |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel Management Engine                          |
++------------------+--------------------------------------------------+
+```
+
+## Extra resources
+
+- [Flash chip datasheet][W25Q128FVSG]
+
+[X9SAE]: https://www.supermicro.com/products/motherboard/xeon/c216/x9sae.cfm
+[X9SAE-V]:  https://www.supermicro.com/products/motherboard/xeon/c216/x9sae-v.cfm
+[W25Q128FVSG]: https://static.chipdip.ru/lib/093/DOC001093213.pdf
+[flashrom]: https://flashrom.org/Flashrom
diff --git a/Documentation/northbridge/intel/sandybridge/nri_features.md b/Documentation/northbridge/intel/sandybridge/nri_features.md
@@ -84,6 +84,6 @@
 +---------------------------+----------------------+-------------+---------+---------------------+
 | **ECC support**                                                                                |
 +---------------------------+----------------------+-------------+---------+---------------------+
-|                       ECC |                  yes |          no |         |                     |
+|                       ECC |                  yes |         yes |     yes | Since coreboot 4.13 |
 +---------------------------+----------------------+-------------+---------+---------------------+
 ```
diff --git a/Documentation/releases/coreboot-4.15-relnotes.md b/Documentation/releases/coreboot-4.15-relnotes.md
@@ -19,4 +19,11 @@ By using newer coreboot features like board variants and override devicetrees,
 lots of code can now be shared. This should ease maintenance and also make it
 easier for newcomers to add support for even more mainboards.
 
+### Changed default setting for Intel chipset lockdown
+
+Previously, the default behaviour for Intel chipset lockdown was to let the FSP
+do it. Since all related mainboards used the coreboot mechanisms for chipset
+lockdown, the default behaviour was changed to that.
+
+
 ### Add significant changes here
diff --git a/Documentation/security/vboot/list_vboot.md b/Documentation/security/vboot/list_vboot.md
@@ -176,6 +176,7 @@
 - Pazquel
 - Pompom
 - Trogdor
+- Wormdingler
 - Veyron_Jaq (Haier Chromebook 11)
 - Veyron_Jerry (Hisense Chromebook 11)
 - Veyron_Mighty (Haier Chromebook 11(edu))

diff --git a/Documentation/soc/intel/broadwell/blobs.md b/Documentation/soc/intel/broadwell/blobs.md
@@ -0,0 +1,41 @@
+# Blobs used in Intel Broadwell boards
+
+All Broadwell boards supported by coreboot require two proprietary blobs.
+In a coreboot image of a Broadwell board, the blobs are named `mrc.bin` and
+`refcode` in CBFS.
+
+`mrc.bin` is run in romstage to initialize the memory. It is placed at a fixed
+address in CBFS and is loaded at a fixed address in memory.
+
+`refcode` is run in ramstage to initialize the system agent and the PCH. It is
+a relocatable ELF object.
+
+## Obtaining the blobs
+
+Both `mrc.bin` and `refcode` can be obtained from a coreboot image of a Broadwell
+board, for example a Purism Librem 13 v1 coreboot image from [MrChromebox].
+
+    cbfstool coreboot_*.rom extract -f broadwell-mrc.bin -n mrc.bin
+    cbfstool coreboot_*.rom extract -m x86 -f broadwell-refcode.elf -n fallback/refcode
+
+## SPD Addresses
+
+The SPD addresses in Broadwell `pei_data` struct are similar to [Haswell].
+
+## Intel GbE support
+
+Unlike Haswell boards, the `pei_data` struct of Broadwell doesn't have `gbe_enable`
+field. For boards with an Intel GbE device, a modification of `refcode` is needed,
+otherwise `refcode` will disable the Intel GbE device and the OS cannot find it
+in the list of PCI devices.
+
+## Use Broadwell SoC code for Haswell ULT boards
+
+Haswell ULT boards can use Broadwell SoC code. To use Broadwell code for Haswell ULT
+boards, `devicetree.cb` file and `pei_data` code need to be ported to Broadwell, and
+build the code with Broadwell `mrc.bin` and `refcode` instead of using Haswell `mrc.bin`.
+
+Broadwell SoC code doesn't support non-ULT Haswell or non-ULT Broadwell boards.
+
+[MrChromebox]: https://mrchromebox.tech/
+[Haswell]: ../../../northbridge/intel/haswell/mrc.bin.md
diff --git a/Documentation/soc/intel/broadwell/index.md b/Documentation/soc/intel/broadwell/index.md
@@ -0,0 +1,7 @@
+# Intel Broadwell documentation
+
+This section describes the Intel Broadwell SoC.
+
+## Proprietary blobs
+
+- [mrc.bin and refcode](blobs.md)
diff --git a/Documentation/soc/intel/index.md b/Documentation/soc/intel/index.md
@@ -6,6 +6,7 @@ This section contains documentation about coreboot on specific Intel SOCs.
 
 - [Common code development strategy](code_development_model/code_development_model.md)
 - [FSP](fsp/index.md)
+- [Broadwell](broadwell/index.md)
 - [Ice Lake/9th Gen Core-i series](icelake/index.md)
 - [MP Initialization](mp_init/mp_init.md)
 - [Microcode Updates](microcode.md)

diff --git a/Documentation/tutorial/part3.md b/Documentation/tutorial/part3.md
@@ -381,6 +381,6 @@ invoking Cmocka test are described
                      cmocka_unit_test(i2c_read_field_test),
              };
 
-             return cmocka_run_group_tests(tests, NULL, NULL);
+             return cb_run_group_tests(tests, NULL, NULL);
      }
 ```