Showing 1,290 changed files with 27,407 additions and 15,576 deletions.
64 changes: 64 additions & 0 deletions .gitlab-ci.yml
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Expand Up @@ -9,6 +9,7 @@ stages:
- build_rom
- sign_rom
- publish_rom
- check_hw_matrix
- run_regression

check_dependencies:
Expand Down Expand Up @@ -75,6 +76,27 @@ check_dependencies:
only:
- tags

.check_hw_matrix: &check_hw_matrix
image:
name: 3mdeb/rf-docker:1.1.0
# https://docs.gitlab.com/ee/ci/docker/using_docker_images.html#overriding-the-entrypoint-of-an-image
# https://gitlab.com/gitlab-org/gitlab-runner/-/issues/2692
# use EMPTY ENTRYPOINT for docker >17.06
entrypoint: [""]
variables:
PLATFORM:
RTE_IP:
CONFIG:
FIRMWARE_VERSION: $CI_COMMIT_REF_NAME
stage: check_hw_matrix
tags:
- local
timeout: 6h
script:
- bash -x .gitlab-ci/check_hw_matrix.sh
only:
- tags

.run_regression: &run_regression
image:
name: 3mdeb/rf-docker:1.1.0
Expand Down Expand Up @@ -113,6 +135,13 @@ publish:apu1:
variables:
PLATFORM: apu1

check_hw_matrix:apu1:
<<: *check_hw_matrix
variables:
PLATFORM: apu1
CONFIG: apu1
RTE_IP: $RTE_IP_APU1

regression:apu1:
<<: *run_regression
variables:
Expand All @@ -137,6 +166,13 @@ publish:apu2:
variables:
PLATFORM: apu2

check_hw_matrix:apu2:
<<: *check_hw_matrix
variables:
PLATFORM: apu2
CONFIG: apu2
RTE_IP: $RTE_IP_APU2

regression:apu2:
<<: *run_regression
variables:
Expand All @@ -161,6 +197,13 @@ publish:apu3:
variables:
PLATFORM: apu3

check_hw_matrix:apu3:
<<: *check_hw_matrix
variables:
PLATFORM: apu3
CONFIG: apu3
RTE_IP: $RTE_IP_APU3

regression:apu3:
<<: *run_regression
variables:
Expand All @@ -185,6 +228,13 @@ publish:apu4:
variables:
PLATFORM: apu4

check_hw_matrix:apu4:
<<: *check_hw_matrix
variables:
PLATFORM: apu4
CONFIG: apu4
RTE_IP: $RTE_IP_APU4

regression:apu4:
<<: *run_regression
variables:
Expand All @@ -209,6 +259,13 @@ publish:apu5:
variables:
PLATFORM: apu5

check_hw_matrix:apu5:
<<: *check_hw_matrix
variables:
PLATFORM: apu5
CONFIG: apu5
RTE_IP: $RTE_IP_APU5

regression:apu5:
<<: *run_regression
variables:
Expand All @@ -233,6 +290,13 @@ publish:apu6:
variables:
PLATFORM: apu6

check_hw_matrix:apu6:
<<: *check_hw_matrix
variables:
PLATFORM: apu6
CONFIG: apu6
RTE_IP: $RTE_IP_APU6

regression:apu6:
<<: *run_regression
variables:
Expand Down
19 changes: 19 additions & 0 deletions .gitlab-ci/check_hw_matrix.sh
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@@ -0,0 +1,19 @@
#!/bin/bash

git clone https://$GITLAB_ROBOT_USERNAME:$GITLAB_ROBOT_TOKEN@$TESTS_REPO_GIT
cd $TESTS_REPO_DIR

git checkout hw-matrix-check

sed -i 's+git@gitlab.com:3mdeb/rte/rtectrl-rest-api.git+https://'$GITLAB_ROBOT_USERNAME':'$GITLAB_ROBOT_TOKEN'@gitlab.com/3mdeb/rte/rtectrl-rest-api.git+' .gitmodules
sed -i 's+git@gitlab.com:3mdeb/rte/snipeit-rest-api.git+https://'$GITLAB_ROBOT_USERNAME':'$GITLAB_ROBOT_TOKEN'@gitlab.com/3mdeb/rte/snipeit-rest-api.git+' .gitmodules
git submodule update --init --checkout

# legacy or mainline?
if [[ $FIRMWARE_VERSION =~ v4\.0.* ]]; then
export FIRMWARE="l"
else
export FIRMWARE="m"
fi

bash -cx "./check_hw_matrix.sh"
2 changes: 1 addition & 1 deletion 3rdparty/amd_blobs
Submodule amd_blobs updated from f63876 to 22ce1b
2 changes: 1 addition & 1 deletion 3rdparty/chromeec
Submodule chromeec updated from 4c21b5 to e486b3
2 changes: 1 addition & 1 deletion 3rdparty/vboot
Submodule vboot updated from 13f601 to 25b949
8 changes: 8 additions & 0 deletions CHANGELOG.md
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Expand Up @@ -12,6 +12,14 @@ official [coreboot repository](https://review.coreboot.org/cgit/coreboot.git)
Please use [pce-fw-builder](https://github.com/pcengines/pce-fw-builder)

## [Unreleased]
## [v4.15.0.3] - 2022-02-11
### Changed
- Rebased with official coreboot repository commit 36425312ee
- Added checking hardware matrix before regression tests

### Fixed
- The hard disk not visible in the Seabios Boot Menu

## [v4.15.0.2] - 2021-12-27
### Changed
- rebased with official coreboot repository commit 3990da0b
Expand Down
47 changes: 47 additions & 0 deletions Documentation/getting_started/gpio.md
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Expand Up @@ -162,6 +162,53 @@ The first is configuring a pin as an output, when it was designed to be an
input. There is a real risk in this case of short-circuiting a component which
could cause catastrophic failures, up to and including your mainboard!

### Intel SoCs

As per Intel Platform Controller Hub (PCH) EDS since Skylake, a GPIO PAD register
supports four different types of GPIO reset as:

| PAD Reset Config | Platform Reset | GPP | GPD |
|-------------------------------------------------|----------------|-----|-----|
| 00 - Power Good (GPP: RSMRST, GPD: DSW_PWROK) | Warm Reset | N | N |
| | Cold Reset | N | N |
| | S3/S4/S5 | N | N |
| | Global Reset | N | N |
| | Deep Sx | Y | N |
| | G3 | Y | N |
| 01 - Deep | Warm Reset | Y | Y |
| | Cold Reset | Y | Y |
| | S3/S4/S5 | N | N |
| | Global Reset | Y | Y |
| | Deep Sx | Y | Y |
| | G3 | Y | Y |
| 10 - Host Reset/PLTRST | Warm Reset | Y | Y |
| | Cold Reset | Y | Y |
| | S3/S4/S5 | Y | Y |
| | Global Reset | Y | Y |
| | Deep Sx | Y | Y |
| | G3 | Y | Y |
| 11 - Resume Reset (GPP: Reserved, GPD: RSMRST) | Warm Reset | - | N |
| | Cold Reset | - | N |
| | S3/S4/S5 | - | N |
| | Global Reset | - | N |
| | Deep Sx | - | Y |
| | G3 | - | Y |

Each GPIO Community has a Pad Configuration Lock register for a GPP allowing locking
specific register fields in the PAD configuration register.

The Pad Config Lock registers reset type is default hardcoded to **Power Good** and
it's **not** configurable by GPIO PAD DW0.PadRstCfg. Hence, it may appear that for a GPP,
the Pad Reset Config (DW0 Bit 31) is configured differently from `Power Good`.

This would create confusion where the Pad configuration is returned to its `default`
value but remains `locked`, this would prevent software to reprogram the GPP.
Additionally, this means software can't rely on GPIOs being reset by PLTRST# or Sx entry.

Hence, as per GPIO BIOS Writers Guide (BWG) it's recommended to change the Pad Reset
Configuration for lock GPP as `Power Good` so that pad configuration and lock bit are
always in sync and can be reset at the same time.

## Soft Straps

Soft straps, that can be configured by the vendor in the Intel Flash Image Tool
Expand Down
177 changes: 177 additions & 0 deletions Documentation/mainboard/acer/g43t-am3.md
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@@ -0,0 +1,177 @@
# Acer G43T-AM3

The Acer G43T-AM3 is a microATX-sized desktop board. It was used for the
Acer models Aspire M3800, Aspire M5800 and possibly more.

## Technology

```eval_rst
+------------------+--------------------------------------------------+
| Northbridge | Intel G43 (called x4x in coreboot code) |
+------------------+--------------------------------------------------+
| Southbridge | Intel ICH10R (called i82801jx in coreboot code) |
+------------------+--------------------------------------------------+
| CPU socket | LGA 775 |
+------------------+--------------------------------------------------+
| RAM | 4 x DDR3-1066 |
+------------------+--------------------------------------------------+
| SuperIO | ITE IT8720F |
+------------------+--------------------------------------------------+
| Audio | Realtek ALC888S |
+------------------+--------------------------------------------------+
| Network | Intel 82567V-2 Gigabit Ethernet |
+------------------+--------------------------------------------------+
```

There is no serial port. Serial console output is possible by soldering
to a point at the corresponding Super I/O pin and patching the
mainboard-specific code accordingly.

## Status

### Working

Tests were done with SeaBIOS 1.14.0 and slackware64-live from 2019-07-12
(linux-4.19.50).

+ Intel Core 2 processors at up to FSB 1333
+ All four DIMM slots at 1066 MHz (tested 2x2GB + 2x4GB)
+ Integrated graphics (libgfxinit)
+ HDMI and VGA ports
+ Both PCI slots
+ Both PCI-e slots
+ USB (8 internal, 4 external)
+ All six SATA ports
+ Onboard Ethernet
+ Onboard sound card with output on the rear stereo connector
+ PS/2 mouse and keyboard
+ With SeaBIOS, use CONFIG_SEABIOS_PS2_TIMEOUT, tested: 500
+ With FILO it works without further settings
+ Temperature readings from the Super I/O (including the CPU temperature
via PECI)
+ Super I/O EC automatic fan control
+ S3 suspend/resume
+ Poweroff

### Not working

+ DDR3 memory with 512Mx8 chips (G43 limitation)
+ 4x4GB of DDR3 memory (works, but showed a single bit error within one
pass of Memtest86+ 5.01)
+ Super I/O voltage reading conversions

### Untested

+ Other audio jacks or the front panel header
+ S/PDIF output
+ On-board Firewire
+ Wake-on-LAN

## Flashing coreboot

```eval_rst
+-------------------+---------------------+
| Type | Value |
+===================+=====================+
| Socketed flash | No |
+-------------------+---------------------+
| Model | Macronix MX25L1605D |
+-------------------+---------------------+
| Size | 2 MiB |
+-------------------+---------------------+
| Package | 8-Pin SOP |
+-------------------+---------------------+
| Write protection | No |
+-------------------+---------------------+
| Dual BIOS feature | No |
+-------------------+---------------------+
| Internal flashing | Yes |
+-------------------+---------------------+
```

The flash is divided into the following regions, as obtained with
`ifdtool -f rom.layout backup.rom`:
```
00000000:00001fff fd
00100000:001fffff bios
00006000:000fffff me
00002000:00005fff gbe
```

In general, flashing is possible internally and from an external header. It
might be necessary to specify the chip type; `MX25L1605D/MX25L1608D/MX25L1673E`
is the correct one, not `MX25L1605`.

### Internal flashing

Internal access to the flash chip is unrestricted. When installing coreboot,
only the BIOS region should be updated by passing the `--ifd` and `-i bios`
parameters to flashrom. A full backup is advisable.

Here is an example:

```
$ sudo flashrom \
-p internal \
-c "MX25L1605D/MX25L1608D/MX25L1673E" \
-r backup.rom
$ sudo flashrom \
-p internal \
-c "MX25L1605D/MX25L1608D/MX25L1673E" \
--ifd -i bios \
-w coreboot.rom
```

```eval_rst
In addition to the information here, please see the
:doc:`../../flash_tutorial/index`.
```

### External flashing

The SPI flash chip on this board can be flashed externally through the
SPI_ROM1 header while the board is off and disconnected from power. There
seems to be a diode that prevents the external programmer from powering the
whole board.

The signal assigment on the header is identical to the pinout of the flash
chip. The pinout diagram below is valid when the PCI slots are on the left
and the CPU is on the right. Note that HOLD# and WP# must be pulled high
(to VCC) to be able to flash the chip.

+---+---+
SPI_CSn <- | x | x | -> VCC
+---+---+
SPI_MISO <- | x | x | -> HOLDn
+---+---+
WPn <- | x | x | -> SPI_CLK
+---+---+
GND <- | x | x | -> SPI_MOSI
+---+---+

## Intel Management Engine

The Intel Management Engine (ME) can be disabled by setting the ME_DISABLE
jumper on the board. It pulls GPIO33 on the ICH10 low, causing the "Flash
Descriptor Security Override Strap" to be set. This disables the ME and also
disables any read/write restrictions to the flash chip that may be set in the
Intel Flash Descriptor (IFD) (none on this board). Note that changing this
jumper only comes into effect when starting the board from a shutdown or
suspend state, not during normal operation.

To completely remove the ME blob from the flash image and to decrease the size
of the ME region, thus increasing the size of the BIOS region, `me_cleaner` can
be used with the `-t`, `-r` and `-S` options.

## Fan control

There are two fan connectors that can be controlled individually. CPU_FAN
can only control a fan by a PWM signal and SYS_FAN only by voltage. See
the mainboard's `devicetree.cb` file for how coreboot configures the Super
I/O to control the fans.

## Variants

Various similar mainboards exist, like the Acer Q45T-AM. During a discussion
in #coreboot on IRC, ECS was suspected to be the original designer of this
series of mainboards. They have similar models such as the ECS G43T-WM.