Showing 629 changed files with 7,573 additions and 27,364 deletions.
1 change: 1 addition & 0 deletions .checkpatch.conf
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Expand Up @@ -22,6 +22,7 @@
--ignore PRINTK_WITHOUT_KERN_LEVEL
--ignore ASSIGN_IN_IF
--ignore UNNECESSARY_ELSE
--ignore GERRIT_CHANGE_ID

# FILE_PATH_CHANGES seems to not be working correctly. It will
# choke on added / deleted files even if the MAINTAINERS file
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1 change: 1 addition & 0 deletions .gitmodules
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Expand Up @@ -48,6 +48,7 @@
path = 3rdparty/cmocka
url = https://review.coreboot.org/cmocka.git
update = none
branch = stable-1.1
[submodule "3rdparty/qc_blobs"]
path = 3rdparty/qc_blobs
url = https://review.coreboot.org/qc_blobs.git
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2 changes: 1 addition & 1 deletion 3rdparty/cmocka
Submodule cmocka updated from 672c5c to 893184
9 changes: 7 additions & 2 deletions CHANGELOG.md
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Expand Up @@ -10,9 +10,13 @@ official [coreboot repository](https://review.coreboot.org/cgit/coreboot.git)
## Quick build instructions

Please use [pce-fw-builder](https://github.com/pcengines/pce-fw-builder)

****
## [Unreleased]

## [v4.16.0.3] - 2022-04-21
### Changed
- Rebased with official coreboot repository commit 2c4b426557

## [v4.16.0.2] - 2022-03-29
### Changed
- Rebased with official coreboot repository commit 66f99f7f
Expand Down Expand Up @@ -567,7 +571,8 @@ redundant code which was similar for APU2/3/5 boards.
- turn off D4 and D5 leds on boot
- enable power on after power failure

[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.16.0.2...develop
[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.16.0.3...develop
[v4.16.0.2]: https://github.com/pcengines/coreboot/compare/v4.16.0.2...v4.16.0.3
[v4.16.0.2]: https://github.com/pcengines/coreboot/compare/v4.16.0.1...v4.16.0.2
[v4.16.0.1]: https://github.com/pcengines/coreboot/compare/v4.15.0.3...v4.16.0.1
[v4.15.0.3]: https://github.com/pcengines/coreboot/compare/v4.15.0.2...v4.15.0.3
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81 changes: 55 additions & 26 deletions Documentation/getting_started/gpio.md
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Expand Up @@ -167,32 +167,61 @@ could cause catastrophic failures, up to and including your mainboard!
As per Intel Platform Controller Hub (PCH) EDS since Skylake, a GPIO PAD register
supports four different types of GPIO reset as:

| PAD Reset Config | Platform Reset | GPP | GPD |
|-------------------------------------------------|----------------|-----|-----|
| 00 - Power Good (GPP: RSMRST, GPD: DSW_PWROK) | Warm Reset | N | N |
| | Cold Reset | N | N |
| | S3/S4/S5 | N | N |
| | Global Reset | N | N |
| | Deep Sx | Y | N |
| | G3 | Y | N |
| 01 - Deep | Warm Reset | Y | Y |
| | Cold Reset | Y | Y |
| | S3/S4/S5 | N | N |
| | Global Reset | Y | Y |
| | Deep Sx | Y | Y |
| | G3 | Y | Y |
| 10 - Host Reset/PLTRST | Warm Reset | Y | Y |
| | Cold Reset | Y | Y |
| | S3/S4/S5 | Y | Y |
| | Global Reset | Y | Y |
| | Deep Sx | Y | Y |
| | G3 | Y | Y |
| 11 - Resume Reset (GPP: Reserved, GPD: RSMRST) | Warm Reset | - | N |
| | Cold Reset | - | N |
| | S3/S4/S5 | - | N |
| | Global Reset | - | N |
| | Deep Sx | - | Y |
| | G3 | - | Y |
```eval_rst
+------------------------+----------------+-------------+-------------+
| | | PAD Reset ? |
+ PAD Reset Config + Platform Reset +-------------+-------------+
| | | GPP | GPD |
+========================+================+=============+=============+
| | 00 - Power Good | Warm Reset | N | N |
| | (GPP: RSMRST, +----------------+-------------+-------------+
| | GPD: DSW_PWROK) | Cold Reset | N | N |
| +----------------+-------------+-------------+
| | S3/S4/S5 | N | N |
| +----------------+-------------+-------------+
| | Global Reset | N | N |
| +----------------+-------------+-------------+
| | Deep Sx | Y | N |
| +----------------+-------------+-------------+
| | G3 | Y | Y |
+------------------------+----------------+-------------+-------------+
| 01 - Deep | Warm Reset | Y | Y |
| +----------------+-------------+-------------+
| | Cold Reset | Y | Y |
| +----------------+-------------+-------------+
| | S3/S4/S5 | N | N |
| +----------------+-------------+-------------+
| | Global Reset | Y | Y |
| +----------------+-------------+-------------+
| | Deep Sx | Y | Y |
| +----------------+-------------+-------------+
| | G3 | Y | Y |
+------------------------+----------------+-------------+-------------+
| 10 - Host Reset/PLTRST | Warm Reset | Y | Y |
| +----------------+-------------+-------------+
| | Cold Reset | Y | Y |
| +----------------+-------------+-------------+
| | S3/S4/S5 | Y | Y |
| +----------------+-------------+-------------+
| | Global Reset | Y | Y |
| +----------------+-------------+-------------+
| | Deep Sx | Y | Y |
| +----------------+-------------+-------------+
| | G3 | Y | Y |
+------------------------+----------------+-------------+-------------+
| | 11 - Resume Reset | Warm Reset | n/a | N |
| | (GPP: Reserved, +----------------+-------------+-------------+
| | GPD: RSMRST) | Cold Reset | n/a | N |
| +----------------+-------------+-------------+
| | S3/S4/S5 | n/a | N |
| +----------------+-------------+-------------+
| | Global Reset | n/a | N |
| +----------------+-------------+-------------+
| | Deep Sx | n/a | Y |
| +----------------+-------------+-------------+
| | G3 | n/a | Y |
+------------------------+----------------+-------------+-------------+
```

Each GPIO Community has a Pad Configuration Lock register for a GPP allowing locking
specific register fields in the PAD configuration register.
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1 change: 1 addition & 0 deletions Documentation/mainboard/index.md
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Expand Up @@ -182,6 +182,7 @@ The boards in this section are not real mainboards, but emulators.

- [LabTop Mk IV](starlabs/labtop_cml.md)
- [StarLite Mk III](starlabs/lite_glk.md)
- [StarLite Mk IV](starlabs/lite_glkr.md)
- [StarBook Mk V](starlabs/starbook_tgl.md)

## Supermicro
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82 changes: 82 additions & 0 deletions Documentation/mainboard/starlabs/lite_glkr.md
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@@ -0,0 +1,82 @@
# StarLite Mk III

## Specs
- CPU (full processor specs available at https://ark.intel.com)
- Intel N5030 (Gemini Lake Refresh)
- EC
- Nuvoton NPCE985P/G
- Backlit Keyboard, with standard PS/2 keycodes and SCI hotkeys
- Battery
- Charger, using AC adapter or USB-C PD
- Suspend / resume
- GPU
- Intel UHD Graphics 605
- GOP driver is recommended, VBT is provided
- eDP 11.6-inch 1920x1080 LCD
- HDMI video
- USB-C DisplayPort video
- Memory
- 8GB on-board
- Networking
- 9461 CNVi WiFi / Bluetooth soldered to PCBA
- Sound
- Realtek ALC269
- Internal speakers
- Internal microphone
- Combined headphone / microphone 3.5-mm jack
- HDMI audio
- USB-C DisplayPort audio
- Storage
- M.2 SATA SSD
- RTS5129 MicroSD card reader
- USB
- 1200x1600 CCD camera
- USB 3.1 Gen 1 Type-C (left)
- USB 3.1 Gen 1 Type-A (left)
- USB 3.1 Gen 1 Type-A (right)

## Building coreboot

### Preliminaries

Prior to building coreboot the following files are required:
* Intel Flash Descriptor file (descriptor.bin)
* IFWI Image (ifwi.rom)

The files listed below are optional:
- Splash screen image in Windows 3.1 BMP format (Logo.bmp)

These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.

### Build

The following commands will build a working image:

```bash
make distclean
make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_lite_glkr
make
```

## Flashing coreboot

```eval_rst
+---------------------+------------+
| Type | Value |
+=====================+============+
| Socketed flash | no |
+---------------------+------------+
| Vendor | Gigadevice |
+---------------------+------------+
| Model | GD25LQ64(B)|
+---------------------+------------+
| Size | 8 MiB |
+---------------------+------------+
| Package | SOIC-8 |
+---------------------+------------+
| Internal flashing | yes |
+---------------------+------------+
| External flashing | yes |
+---------------------+------------+
Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.
2 changes: 1 addition & 1 deletion MAINTAINERS
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Expand Up @@ -880,7 +880,7 @@ F: src/security/tpm/

SUPERIOS & SUPERIOTOOL
M: Felix Held <felix-coreboot@felixheld.de>
S: Maintained
S: Odd Fixes
F: src/superio/
F: util/superiotool/

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4 changes: 2 additions & 2 deletions Makefile
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Expand Up @@ -470,10 +470,10 @@ doxyclean: doxygen-clean
doxygen-clean:
rm -rf $(DOXYGEN_OUTPUT_DIR)

clean-for-update: doxygen-clean clean-for-update-target
clean-for-update: doxygen-clean
rm -rf $(obj) .xcompile

clean: clean-for-update clean-target clean-utils
clean: clean-for-update clean-utils clean-payloads
rm -f .ccwrap

clean-cscope:
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29 changes: 9 additions & 20 deletions Makefile.inc
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Expand Up @@ -81,8 +81,9 @@ PHONY+= clean-abuild coreboot check-style build_complete
# root source directories of coreboot
subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi src/superio/common
subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*)
subdirs-y += $(wildcard src/soc/*) $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*)
subdirs-y += $(wildcard src/superio/*) $(wildcard src/superio/*/*)
subdirs-y += $(wildcard src/soc/*) $(wildcard src/soc/*/common) $(filter-out $(wildcard src/soc/*/common),$(wildcard src/soc/*/*))
subdirs-y += $(wildcard src/northbridge/*/*)
subdirs-y += $(filter-out src/superio/common,$(wildcard src/superio/*)) $(wildcard src/superio/*/*)
subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*) $(wildcard src/drivers/*/*/*)
subdirs-y += src/cpu src/vendorcode
subdirs-y += util/cbfstool util/sconfig util/nvramtool util/pgtblgen util/amdfwtool
Expand Down Expand Up @@ -260,9 +261,6 @@ endef
# ResourceTemplate is the correct code.
# As it's valid ASL, disable the warning.
EMPTY_RESOURCE_TEMPLATE_WARNING = 3150
# Redundant offset remarks are not useful in any way and are masking useful
# ones that might indicate an issue so it is better to hide them.
REDUNDANT_OFFSET_REMARK = 2158
# IASL compiler check for usage of _CRS, _DIS, _PRS, and _SRS objects:
# 1) If _PRS is present, must have _CRS and _SRS
# 2) If _SRS is present, must have _PRS (_PRS requires _CRS and _SRS)
Expand All @@ -279,8 +277,8 @@ ifeq ($(CONFIG_IGNORE_IASL_MISSING_DEPENDENCY),y)
build_complete::
printf "*** WARNING: The ASL code for this platform is incomplete. Please fix it. ***\n"
printf "*** If _PRS is present, must have _CRS and _SRS ***\n"
printf "*** If _SRS is present, must have _PRS, _CRS, and _SRS ***\n"
printf "*** If _DIS is present, must have _SRS, _PRS, _CRS, and _SRS ***\n"
printf "*** If _SRS is present, must have _PRS and _CRS ***\n"
printf "*** If _DIS is present, must have _SRS, _PRS and _CRS ***\n"
endif

IGNORED_IASL_WARNINGS = $(addprefix -vw , $(IASL_WARNINGS_LIST))
Expand Down Expand Up @@ -675,19 +673,6 @@ decompressor-y += $(CONFIG_MEMLAYOUT_LD_FILE)
clean-abuild:
rm -rf coreboot-builds

clean-for-update-target: clean-payloads
rm -f $(obj)/ramstage?* $(obj)/coreboot.romstage $(obj)/coreboot.pre* $(obj)/coreboot.bootblock $(obj)/coreboot.a
rm -rf $(obj)/bootblock?* $(obj)/romstage?* $(obj)/location.*
rm -f $(obj)/option_table.* $(obj)/crt0.S $(obj)/ldscript
rm -f $(obj)/mainboard/$(MAINBOARDDIR)/static.c $(obj)/mainboard/$(MAINBOARDDIR)/config.py $(obj)/mainboard/$(MAINBOARDDIR)/static.dot
rm -f $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s $(obj)/mainboard/$(MAINBOARDDIR)/crt0.disasm
rm -f $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
rm -f $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.* $(obj)/dsdt.*
rm -f $(obj)/cpu/x86/smm/smm_bin.c $(obj)/cpu/x86/smm/smm.* $(obj)/cpu/x86/smm/smm

clean-target:
rm -f $(obj)/coreboot*

#######################################################################
# Development utilities
printcrt0s:
Expand Down Expand Up @@ -1115,6 +1100,10 @@ ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y)
TS_OPTIONS := -j $(CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE)
endif

# coreboot.pre doesn't follow the standard Make conventions. It gets modified
# by multiple rules, and thus we can't compute the dependencies correctly.
$(shell rm -f $(obj)/coreboot.pre)

ifneq ($(CONFIG_UPDATE_IMAGE),y)
$(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $(obj)/fmap.fmap $(obj)/fmap.desc
$(CBFSTOOL) $@.tmp create -M $(obj)/fmap.fmap -r $(shell cat $(obj)/fmap.desc)
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2 changes: 1 addition & 1 deletion configs/config.pcengines_apu1
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@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.16.0.2"
CONFIG_LOCALVERSION="v4.16.0.3"
CONFIG_VENDOR_PCENGINES=y
CONFIG_CBFS_SIZE=0x00200000
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
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2 changes: 1 addition & 1 deletion configs/config.pcengines_apu2
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@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.16.0.2"
CONFIG_LOCALVERSION="v4.16.0.3"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,157b"
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2 changes: 1 addition & 1 deletion configs/config.pcengines_apu3
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@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.16.0.2"
CONFIG_LOCALVERSION="v4.16.0.3"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,1539"
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2 changes: 1 addition & 1 deletion configs/config.pcengines_apu4
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@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.16.0.2"
CONFIG_LOCALVERSION="v4.16.0.3"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,1539"
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2 changes: 1 addition & 1 deletion configs/config.pcengines_apu5
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@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.16.0.2"
CONFIG_LOCALVERSION="v4.16.0.3"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,1539"
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2 changes: 1 addition & 1 deletion configs/config.pcengines_apu6
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@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.16.0.2"
CONFIG_LOCALVERSION="v4.16.0.3"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,1539"
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6 changes: 2 additions & 4 deletions payloads/coreinfo/coreboot_module.c
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Expand Up @@ -94,10 +94,8 @@ static int coreboot_module_redraw(WINDOW *win)
mvwprintw(win, row++, 3, " Table: ");
}

wprintw(win, "%16.16llx - %16.16llx",
cb_unpack64(cb_info.range[i].start),
cb_unpack64(cb_info.range[i].start) +
cb_unpack64(cb_info.range[i].size) - 1);
wprintw(win, "%16.16llx - %16.16llx", cb_info.range[i].start,
cb_info.range[i].start + cb_info.range[i].size - 1);
}

return 0;
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8 changes: 4 additions & 4 deletions payloads/external/LinuxBoot/Kconfig
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Expand Up @@ -177,15 +177,15 @@ if LINUXBOOT_UROOT

choice
prompt "U-root version"
default LINUXBOOT_UROOT_MASTER
default LINUXBOOT_UROOT_MAIN

config LINUXBOOT_UROOT_CUSTOM
bool "custom"
help
choose a custom u-root branch

config LINUXBOOT_UROOT_MASTER
bool "master"
config LINUXBOOT_UROOT_MAIN
bool "main"
help
Latest u-root version

Expand All @@ -207,7 +207,7 @@ config LINUXBOOT_UROOT_CHECKOUT
config LINUXBOOT_UROOT_VERSION
string
default LINUXBOOT_UROOT_CHECKOUT if LINUXBOOT_UROOT_CUSTOM
default "master" if LINUXBOOT_UROOT_MASTER
default "main" if LINUXBOOT_UROOT_MAIN
default "v3.0.0" if LINUXBOOT_UROOT_V3_0_0
default "v2.0.0" if LINUXBOOT_UROOT_V2_0_0
default "v1.0.0" if LINUXBOOT_UROOT_V1_0_0
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2 changes: 1 addition & 1 deletion payloads/external/LinuxBoot/targets/u-root.mk
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Expand Up @@ -39,7 +39,7 @@ endif

get: version
if [ -d "$(go_path_dir)/src/$(uroot_package)" ]; then \
git -C $(go_path_dir)/src/$(uroot_package) checkout --quiet master; \
git -C $(go_path_dir)/src/$(uroot_package) checkout --quiet main; \
GOPATH=$(go_path_dir) go get -d -u -v $(uroot_package) || \
echo -e "\n<<u-root package update failed>>\n"; \
else \
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