Showing 880 changed files with 12,223 additions and 4,177 deletions.
diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs
diff --git a/3rdparty/fsp b/3rdparty/fsp
diff --git a/3rdparty/vboot b/3rdparty/vboot
diff --git a/AUTHORS b/AUTHORS
@@ -108,6 +108,7 @@ Jonas 'Sortie' Termansen
 Jonathan A. Kollasch
 Jonathan Neuschäfer
 Jordan Crouse
+Jörg Mische
 Joseph Smith
 Keith Hui
 Keith Packard

diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -13,6 +13,11 @@ Please use [pce-fw-builder](https://github.com/pcengines/pce-fw-builder)
 ****
 ## [Unreleased]
 
+## [v4.17.0.3] - 2022-08-22
+### Changed
+- Rebased with official coreboot repository commit e173f2b
+- Changed sign of life date format from YYYYDDMM to YYYYMMDD
+
 ## [v4.17.0.2] - 2022-07-27
 ### Changed
 - Rebased with official coreboot repository commit df721bd
@@ -589,7 +594,8 @@ redundant code which was similar for APU2/3/5 boards.
 - turn off D4 and D5 leds on boot
 - enable power on after power failure
 
-[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.17.0.2...develop
+[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.17.0.3...develop
+[v4.17.0.3]: https://github.com/pcengines/coreboot/compare/v4.17.0.2...v4.17.0.3
 [v4.17.0.2]: https://github.com/pcengines/coreboot/compare/v4.17.0.1...v4.17.0.2
 [v4.17.0.1]: https://github.com/pcengines/coreboot/compare/v4.16.0.4...v4.17.0.1
 [v4.16.0.4]: https://github.com/pcengines/coreboot/compare/v4.16.0.3...v4.16.0.4

diff --git a/Documentation/acronyms.md b/Documentation/acronyms.md
@@ -278,7 +278,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * ECC - [**Error Correction Code**](https://en.wikipedia.org/wiki/Error_correction_code) - Typically used to refer to a type of
   memory that can detect and correct memory errors.
 * EDID - [**Extended Display Identification Data**](https://en.wikipedia.org/wiki/Extended_Display_Identification_Data)
-* EDK2 - EFI Development Kit 2
+* edk2 - EFI Development Kit 2
 * EDO - Memory: [**Extended Data
   Out**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory#Extended_data_out_DRAM)
   - A DRAM standard introduced in 1994 that improved upon, but was

diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md
@@ -87,7 +87,7 @@ across architectures.
 ## Port payloads to ARM, AArch64 or RISC-V
 While we have a rather big set of payloads for x86 based platforms, all other
 architectures are rather limited. Improve the situation by porting a payload
-to one of the platforms, for example GRUB2, U-Boot (the UI part), Tianocore,
+to one of the platforms, for example GRUB2, U-Boot (the UI part), edk2,
 yabits, FILO, or Linux-as-Payload.
 
 Since this is a bit of a catch-all idea, an application to GSoC should pick a

diff --git a/Documentation/coreboot_logo.bmp b/Documentation/coreboot_logo.bmp
diff --git a/Documentation/distributions.md b/Documentation/distributions.md
@@ -37,15 +37,15 @@ firmware binaries on [GitHub](https://pcengines.github.io).
 
 [Star Labs](https://starlabs.systems/) offers a range of laptops designed and
 built specifically for Linux that are available with coreboot firmware. They
-use Tianocore as the payload and include an NVRAM option to disable the
-Intel Management Engine.
+use edk2 as the payload and include an NVRAM option to disable the Intel
+Management Engine.
 
 ### System76
 
 [System76](https://system76.com/) manufactures Linux laptops, desktops, and
 servers. Some models are sold with [System76 Open
 Firmware](https://github.com/system76/firmware-open), an open source
-distribution of coreboot, EDK2, and System76 firmware applications.
+distribution of coreboot, edk2, and System76 firmware applications.
 
 ### Purism
 
@@ -76,7 +76,7 @@ trustworthiness for all.
 
 [MrChromebox](https://mrchromebox.tech/) provides upstream coreboot firmware
 images for the vast majority of x86-based Chromebooks and Chromeboxes, using
-Tianocore as the payload to provide a modern UEFI bootloader. Why replace
+edk2 as the payload to provide a modern UEFI bootloader. Why replace
 coreboot with coreboot? Mr Chromebox's images are built using upstream
 coreboot (vs Google's older, static tree/branch), include many features and
 fixes not found in the stock firmware, and offer much broader OS compatibility

diff --git a/Documentation/drivers/smmstorev2.md b/Documentation/drivers/smmstorev2.md
@@ -21,7 +21,7 @@ operations is desired, as it reduces complexity and potential for bugs.
 
 This can be used by a FTW (FaultTolerantWrite) implementation that uses
 at least two regions in an A/B update scheme. The FTW implementation in
-EDK2 uses three different regions in the store:
+edk2 uses three different regions in the store:
 
 - The variable store
 - The FTW spare block
@@ -35,7 +35,7 @@ With 64 KiB as block size, the minimum size of the FTW-enabled store is:
 - The FTW spare block: 2 blocks = 2 * 64 KiB
 - The FTW working block: 1 block = 64 KiB
 
-Therefore, the minimum size for EDK2 FTW is 4 blocks, or 256 KiB.
+Therefore, the minimum size for edk2 FTW is 4 blocks, or 256 KiB.
 
 ## API
 

diff --git a/Documentation/index.md b/Documentation/index.md
@@ -26,7 +26,7 @@ initialization routines across many different use cases, no matter if
 they provide standard interfaces or entirely custom boot flows.
 
 Popular [payloads](payloads.md) in use with coreboot are SeaBIOS,
-which provides PCBIOS services, Tianocore, which provides UEFI services,
+which provides PCBIOS services, edk2, which provides UEFI services,
 GRUB2, the bootloader used by many Linux distributions, or depthcharge,
 a custom boot loader used on Chromebooks.
 

diff --git a/Documentation/mainboard/asus/p8z77-m_pro.md b/Documentation/mainboard/asus/p8z77-m_pro.md
@@ -37,7 +37,7 @@ easy to remove and reflash.
 
 ## Working
 
-- PS/2 keyboard with SeaBIOS & Tianocore (in Mint 18.3/19.1)
+- PS/2 keyboard with SeaBIOS & edk2 (in Mint 18.3/19.1)
 
 - Rear/front headphones connector audio & mic
 
@@ -57,7 +57,7 @@ easy to remove and reflash.
        port 3        port 5         port 1             port 8
        port 4        port 6         port 2             port 7
 
-- NVME SSD boot on PCIe-x16/x8/4x slot using Tianocore
+- NVME SSD boot on PCIe-x16/x8/4x slot using edk2
   (tested with M.2-to-PCIe adapter and a M.2 Samsung EVO 970 SSD)
 
 - CPU Temp sensors (tested PSensor on linux + HWINFO64 on Win10)
@@ -89,7 +89,7 @@ easy to remove and reflash.
 - If you use the MRC.bin, the NVRAM variable gfx_uma_size may be ignored
   as IGP's UMA could be reconfigured by the blob
 
-- Using TianoCore + a PCIe GPU under Windows crashes with an
+- Using edk2 + a PCIe GPU under Windows crashes with an
   ACPI_BIOS_ERROR fatal code, not sure why. Using just the IGP
   works perfectly
 
@@ -105,9 +105,9 @@ easy to remove and reflash.
 
 ## Not working
 
-- PS/2 keyboard in Win10 using Tianocore (please see [Known issues])
-- PS/2 mouse using Tianocore
-- PCIe graphics card on Windows and Tianocore (throws critical ACPI_BIOS_ERROR)
+- PS/2 keyboard in Win10 using edk2 (please see [Known issues])
+- PS/2 mouse using edk2
+- PCIe graphics card on Windows and edk2 (throws critical ACPI_BIOS_ERROR)
 
 ## Native raminit compatibility
 

diff --git a/Documentation/mainboard/facebook/monolith.md b/Documentation/mainboard/facebook/monolith.md
@@ -104,11 +104,11 @@ solution. Wires need to be connected to be able to flash using an external progr
 - SMBus
 - Initialization with FSP
 - SeaBIOS payload (commit a5cab58e9a3fb6e168aba919c5669bea406573b4)
-- TianoCore payload (commit 860a8d95c2ee89c9916d6e11230f246afa1cd629)
+- edk2 payload (commit 860a8d95c2ee89c9916d6e11230f246afa1cd629)
 - LinuxBoot (kernel kernel-4_19_97) (uroot commit 9c9db9dbd6b532f5f91a511a0de885c6562aadd7)
 - eMMC
 
-All of the above has been briefly tested by booting Linux from eMMC using the TianoCore payload
+All of the above has been briefly tested by booting Linux from eMMC using the edk2 payload
 and LinuxBoot.
 
 SeaBios has been checked to the extend that it runs to the boot selection and provides display

diff --git a/Documentation/mainboard/hp/folio_9480m.md b/Documentation/mainboard/hp/folio_9480m.md
@@ -130,7 +130,7 @@ The board can be debugged with EHCI debug. The EHCI debug port is the USB port o
 - Arch Linux with Linux 5.8.9
 - Memory initialization with mrc.bin version 1.6.1 Build 2
 - Graphics initialization with libgfxinit
-- Payload: SeaBIOS, Tianocore
+- Payload: SeaBIOS, edk2
 - EC firmware
   - KBC Revision 92.15 from OEM firmware version 01.33
   - KBC Revision 92.17 from OEM firmware version 01.50

diff --git a/Documentation/mainboard/hp/z220_sff.md b/Documentation/mainboard/hp/z220_sff.md
@@ -44,8 +44,17 @@ The SPI flash can be accessed using [flashrom].
 External programming with an SPI adapter and [flashrom] does work, but it powers the
 whole southbridge complex. You need to supply enough current through the programming adapter.
 
-If you want to use a SOIC pomona test clip, you have to cut the 2nd DRAM DIMM holder,
-as otherwise there's not enough space near the flash.
+If you want to use a SOIC pomona test clip, you have to cut the 2nd DRAM DIMM holder, as
+otherwise there's not enough space near the flash.
+
+In both case, if ME has not been completely disabled, ME/AMT Flash Override jumper had better
+be temporary closed for flashing to disable the locking of regions, and prevent ME to run and
+interfere.
+
+## Side note
+The mainboard of [HP Compaq Elite 8300 SFF] is very similar to the one of Z220 SFF, except
+that Compaq Elite 8300 uses Q77 instead of C216 for its PCH, and their boot firmwares are
+even interchangeable, so should do coreboot images built for them.
 
 ## Technology
 
@@ -66,5 +75,6 @@ as otherwise there's not enough space near the flash.
 ```
 
 [HP Z220 SFF Workstation]: https://support.hp.com/za-en/document/c03386950
+[HP Compaq Elite 8300 SFF]: https://support.hp.com/us-en/document/c03345460
 [HP]: https://www.hp.com/
 [flashrom]: https://flashrom.org/Flashrom
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
@@ -146,7 +146,6 @@ The boards in this section are not real mainboards, but emulators.
 ## Open Cellular
 
 - [Elgon](opencellular/elgon.md)
-- [Rotundu](opencellular/rotundu.md)
 
 ## PC Engines
 

diff --git a/Documentation/mainboard/kontron/mal10.md b/Documentation/mainboard/kontron/mal10.md
@@ -45,7 +45,7 @@ make
 ```
 ## Payloads
 - SeaBIOS
-- Tianocore
+- edk2
 - Linux as payload
 
 ## Flashing coreboot

diff --git a/Documentation/mainboard/opencellular/rotundu.md b/Documentation/mainboard/opencellular/rotundu.md
diff --git a/Documentation/mainboard/opencellular/rotundu_flash.jpg b/Documentation/mainboard/opencellular/rotundu_flash.jpg
diff --git a/Documentation/mainboard/opencellular/rotundu_header2.jpg b/Documentation/mainboard/opencellular/rotundu_header2.jpg
diff --git a/Documentation/mainboard/opencellular/rotundu_j16.png b/Documentation/mainboard/opencellular/rotundu_j16.png
diff --git a/Documentation/mainboard/purism/librem_14.md b/Documentation/mainboard/purism/librem_14.md
@@ -92,7 +92,7 @@ located underneath the Wi-Fi module, below the left cooling fan.
 
  * Internal display with libgfxinit, VGA option ROM, or FSP/GOP init
  * External displays via HDMI, USB-C Alt-Mode
- * SeaBIOS (1.14), Tianocore (CorebootPayloadPkg), and Heads payloads
+ * SeaBIOS (1.14), edk2 (CorebootPayloadPkg), and Heads payloads
  * Ethernet, m.2 2230 Wi-Fi
  * System firmware updates via flashrom
  * M.2 storage (NVMe, SATA III)

diff --git a/Documentation/mainboard/purism/librem_mini.md b/Documentation/mainboard/purism/librem_mini.md
@@ -107,7 +107,7 @@ desoldering it from the mainboard.
 
  * External displays via HDMI/DisplayPort with VGA option ROM or FSP/GOP init
    (no libgfxinit support yet)
- * SeaBIOS (1.14), Tianocore (CorebootPayloadPkg), Heads (Purism downstream) payloads
+ * SeaBIOS (1.14), edk2 (CorebootPayloadPkg), Heads (Purism downstream) payloads
  * Ethernet, m.2 2230 Wi-Fi
  * System firmware updates via flashrom
  * PCIe NVMe

diff --git a/Documentation/payloads.md b/Documentation/payloads.md
@@ -23,13 +23,11 @@ When chainloaded from GRUB2, the following menuentry could be used:
         module /vgaroms/seavgabios.bin
     }
 
-## Tianocore
+## edk2
 
-[Tianocore](https://www.tianocore.org) is the open source reference
-implementation of the UEFI Specifications that modern firmware for PCs is
-based on. There were various projects in the past to make it suitable as a
-coreboot payload, but these days this function is available directly in the
-UefiPayloadPkg part of its source tree.
+[edk2](https://github.com/tianocore/tianocore.github.io/wiki/Getting-Started-with-EDK-II) is an open-source modern, feature-rich,
+cross-platform firmware development environment for the UEFI and UEFI
+Platform Initialization (PI) specifications. 
 
 ## GRUB2
 

diff --git a/Documentation/releases/coreboot-4.15-relnotes.md b/Documentation/releases/coreboot-4.15-relnotes.md
@@ -52,9 +52,9 @@ Deprecations and incompatible changes
 
 Drop the deprecated COREBOOTPAYLOAD option, and replace it with MrChromebox's
 updated UefiPayloadPkg option. Simplify the Kconfig options to make it easier
-to build from upstream edk2 master. Drop the TIANOCORE_USE_8254_TIMER Kconfig
+to build from upstream edk2 master. Drop the EDK2_USE_8254_TIMER Kconfig
 option since it applies only to CorebootPayloadPkg. Clean up the Makefile now
-that we're only building from a single Tianocore package/target.
+that we're only building from a single edk2 package/target.
 
 ### Remove old lp4x and ddr4 versions of spd_tools
 

diff --git a/Documentation/releases/coreboot-4.6-relnotes.md b/Documentation/releases/coreboot-4.6-relnotes.md
@@ -55,15 +55,15 @@ is here: https://github.com/siro20/coreboot/tree/cbui/payloads/cbui
 
 ### UEFI support: A long road to go
 
-coreboot can be used with the Tianocore EDK2 UEFI implementation which
+coreboot can be used with the edk2 UEFI implementation which
 is open source and available at Github. Sadly it is not currently
 integrated into the coreboot build. This has several reasons:
 
-* EDK2 only supports GCC 4.8 profile. coreboot is now running on GCC 6.3.0.
-* Incompatibilities with code inside the EDK2 which has not been updated.
+* edk2 only supports GCC 4.8 profile. coreboot is now running on GCC 6.3.0.
+* Incompatibilities with code inside the edk2 which has not been updated.
 
 We started to make progress with the integration into our sources and
-the hope is that by the end of the summer, we finally support the EDK2
+the hope is that by the end of the summer, we finally support the edk2
 payload out-of-the- box. See the current patch state at
 http://review.coreboot.org/#/c/15057/
 

diff --git a/Documentation/releases/coreboot-4.7-relnotes.md b/Documentation/releases/coreboot-4.7-relnotes.md
@@ -84,7 +84,7 @@ General changes
 
 * Integrate me_cleaner
 * Add flashconsole implementation
-* Build Tianocore UEFI payload from upstream source
+* Build edk2 UEFI payload from upstream source
 * Remove CMOS NVRAM configurable baud rates
 * A common mrc_cache driver to store romstage settings in SPI flash
 

diff --git a/Documentation/releases/coreboot-4.8.1-relnotes.md b/Documentation/releases/coreboot-4.8.1-relnotes.md
@@ -71,7 +71,7 @@ detection
 Payloads
 --------
 * Bumped SeaBIOS to 1.11.1
-* Improved TianoCore integration
+* Improved edk2 integration
 
 Security
 --------

diff --git a/Documentation/security/vboot/list_vboot.md b/Documentation/security/vboot/list_vboot.md
@@ -211,6 +211,7 @@
 - Marzipan
 - Mrbland
 - Pazquel
+- Pazquel360
 - Pompom
 - Quackingstick
 - Wormdingler