CHANGELOG.md

@@ -2,7 +2,7 @@ Change log for PC Engines fork of coreboot
 ==========================================
 
 Releases 4.0.x are based on PC Engines 20160304 release.
-Releases 4.5.x are based on mainline support submitted in
+Releases 4.5.x and 4.6.x are based on mainline support submitted in
 [this gerrit ref](https://review.coreboot.org/#/c/14138/).
 
 ## Quick build instructions
@@ -14,6 +14,10 @@ Releases 4.5.x are based on mainline support submitted in
 
 ## [Unreleased]
 
+## [v4.6.1] - 2017-08-30
+### Added
+- APU5 target
+
 ## [v4.6.0] - 2017-07-21
 ### Added
 - Allow to force GPP3 PCIe CLK attached to mPCIe2 slot based on Konfig option
@@ -97,7 +101,8 @@ Releases 4.5.x are based on mainline support submitted in
 - turn off D4 and D5 leds on boot
 - enable power on after power failure
 
-[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.6.0...coreboot-4.6.x
+[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.6.1...coreboot-4.6.x
+[v4.6.1]: https://github.com/pcengines/coreboot/compare/v4.6.0...v4.6.1
 [v4.6.0]: https://github.com/pcengines/coreboot/compare/v4.5.8...v4.6.0
 [v4.5.8]: https://github.com/pcengines/coreboot/compare/v4.5.7...v4.5.8
 [v4.5.7]: https://github.com/pcengines/coreboot/compare/v4.5.6...v4.5.7

src/mainboard/pcengines/apu5/BiosCallOuts.c

@@ -0,0 +1,150 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "AGESA.h"
+#include "amdlib.h"
+#include <spd_bin.h>
+#include <northbridge/amd/pi/BiosCallOuts.h>
+#include "Ids.h"
+#include "OptionsIds.h"
+#include "heapManager.h"
+#include "FchPlatform.h"
+#include "cbfs.h"
+#include "gpio_ftns.h"
+#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM)
+#include "imc.h"
+#endif
+#include "hudson.h"
+#include <stdlib.h>
+
+static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr);
+static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr);
+
+const BIOS_CALLOUT_STRUCT BiosCallouts[] =
+{
+	{AGESA_ALLOCATE_BUFFER,          agesa_AllocateBuffer },
+	{AGESA_DEALLOCATE_BUFFER,        agesa_DeallocateBuffer },
+	{AGESA_LOCATE_BUFFER,            agesa_LocateBuffer },
+	{AGESA_READ_SPD,                 board_ReadSpd_from_cbfs },
+	{AGESA_DO_RESET,                 agesa_Reset },
+	{AGESA_READ_SPD_RECOVERY,        agesa_NoopUnsupported },
+	{AGESA_RUNFUNC_ONAP,             agesa_RunFuncOnAp },
+	{AGESA_GET_IDS_INIT_DATA,        agesa_EmptyIdsInitData },
+	{AGESA_HOOKBEFORE_DQS_TRAINING,  agesa_NoopSuccess },
+	{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
+	{AGESA_FCH_OEM_CALLOUT,          Fch_Oem_config }
+};
+const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
+
+//{AGESA_GNB_GFX_GET_VBIOS_IMAGE,  agesa_NoopUnsupported }
+
+
+/*
+ * Hardware Monitor Fan Control
+ * Hardware limitation:
+ *  HWM will fail to read the input temperature via I2C if other
+ *  software switches the I2C address.  AMD recommends using IMC
+ *  to control fans, instead of HWM.
+ */
+static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
+{
+	FchParams->Imc.ImcEnable = FALSE;
+	FchParams->Hwm.HwMonitorEnable = FALSE;
+	FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;                /* 1 enable, 0 disable TSI Auto Polling */
+}
+
+/**
+ * Fch Oem setting callback
+ *
+ *  Configure platform specific Hudson device,
+ *   such Azalia, SATA, IMC etc.
+ */
+static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr)
+{
+	AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr;
+	if (StdHeader->Func == AMD_INIT_RESET) {
+		FCH_RESET_DATA_BLOCK *FchParams =  (FCH_RESET_DATA_BLOCK *) FchData;
+		printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
+		//FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
+		FchParams->LegacyFree = CONFIG_HUDSON_LEGACY_FREE;
+		FchParams->FchReset.SataEnable = hudson_sata_enable();
+		FchParams->FchReset.IdeEnable = hudson_ide_enable();
+		FchParams->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+		FchParams->FchReset.Xhci1Enable = FALSE;
+	} else if (StdHeader->Func == AMD_INIT_ENV) {
+		FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData;
+		printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
+
+
+		FchParams->Azalia.AzaliaEnable = AzDisable;
+
+		/* Fan Control */
+		oem_fan_control(FchParams);
+
+		/* XHCI configuration */
+		FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+		FchParams->Usb.Xhci1Enable = FALSE;
+
+		/* EHCI configuration */
+		FchParams->Usb.Ehci3Enable = !IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+		FchParams->Usb.Ehci1Enable = TRUE;	// Enable EHCI 0 (port 0 to 3)
+		FchParams->Usb.Ehci2Enable = TRUE;	// Enable EHCI 1 ( port 4 to 7) port 4 and 5 to EHCI header port 6 and 7 to PCIe slot.
+
+		/* sata configuration */
+		FchParams->Sata.SataDevSlpPort0 = 0;	// Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP
+		FchParams->Sata.SataDevSlpPort1 = 0;
+
+		FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE;
+		switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) {
+		case SataRaid:
+		case SataAhci:
+		case SataAhci7804:
+		case SataLegacyIde:
+			FchParams->Sata.SataIdeMode = FALSE;
+			break;
+		case SataIde2Ahci:
+		case SataIde2Ahci7804:
+		default: /* SataNativeIde */
+			FchParams->Sata.SataIdeMode = TRUE;
+			break;
+		}
+	}
+	printk(BIOS_DEBUG, "Done\n");
+
+	return AGESA_SUCCESS;
+}
+
+static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr)
+{
+	AGESA_STATUS Status = AGESA_UNSUPPORTED;
+#ifdef __PRE_RAM__
+	AGESA_READ_SPD_PARAMS	*info = ConfigPtr;
+	u8 index = get_spd_offset();
+
+	if (info->MemChannelId > 0)
+		return AGESA_UNSUPPORTED;
+	if (info->SocketId != 0)
+		return AGESA_UNSUPPORTED;
+	if (info->DimmId != 0)
+		return AGESA_UNSUPPORTED;
+
+	/* Read index 0, first SPD_SIZE bytes of spd.bin file. */
+	if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, index) < 0)
+		die("No SPD data\n");
+
+	Status = AGESA_SUCCESS;
+#endif
+	return Status;
+}

src/mainboard/pcengines/apu5/Kconfig

@@ -0,0 +1,102 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+# Copyright (C) 2015 Kyösti Mälkki <kyosti.malkki@gmail.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+if BOARD_PCENGINES_APU5
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select CPU_AMD_PI_00730F01
+	select NORTHBRIDGE_AMD_PI_00730F01
+	select SOUTHBRIDGE_AMD_PI_AVALON
+	select SUPERIO_NUVOTON_NCT5104D
+	select HAVE_PIRQ_TABLE
+	select HAVE_MP_TABLE
+	select HAVE_ACPI_TABLES
+	select BOARD_ROMSIZE_KB_8192
+	select HUDSON_DISABLE_IMC
+	select USE_BLOBS
+	select GENERIC_SPD_BIN
+	select PXE
+
+config MAINBOARD_DIR
+	string
+	default pcengines/apu5
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "PC Engines apu5"
+
+config MAX_CPUS
+	int
+	default 4
+
+config IRQ_SLOT_COUNT
+	int
+	default 11
+
+config ONBOARD_VGA_IS_PRIMARY
+	bool
+	default y
+
+config HUDSON_LEGACY_FREE
+	bool
+	default y
+
+config AGESA_BINARY_PI_FILE
+	string
+	default "3rdparty/blobs/mainboard/pcengines/apu2/AGESA.bin"
+
+choice
+	prompt "J19 pins 1-10"
+	default APU5_PINMUX_UART_C
+
+config APU5_PINMUX_OFF_C
+	bool "disable"
+
+config APU5_PINMUX_GPIO0
+	bool "GPIO"
+
+config APU5_PINMUX_UART_C
+	bool "UART 0x3e8"
+
+endchoice
+
+choice
+	prompt "J19 pins 11-20"
+	default APU5_PINMUX_UART_D
+
+config APU5_PINMUX_OFF_D
+	bool "disable"
+
+config APU5_PINMUX_GPIO1
+	bool "GPIO"
+
+config APU5_PINMUX_UART_D
+	bool "UART 0x2e8"
+
+endchoice
+
+config DIMM_SPD_SIZE
+	int
+	default 128
+
+config FORCE_MPCIE2_CLK
+	bool "Force clock of mPCIe slot2 (GPP3 PCIe clock)  to be always on"
+	default n
+	help
+	  If no card is attached to mPCIe2 slot, say N.
+
+endif # BOARD_PCENGINES_APU5

src/mainboard/pcengines/apu5/Kconfig.name

@@ -0,0 +1,2 @@
+config BOARD_PCENGINES_APU5
+	bool "APU5"

src/mainboard/pcengines/apu5/Makefile.inc

@@ -0,0 +1,26 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+romstage-y += BiosCallOuts.c
+romstage-y += OemCustomize.c
+romstage-y += gpio_ftns.c
+
+ramstage-y += BiosCallOuts.c
+ramstage-y += OemCustomize.c
+ramstage-y += gpio_ftns.c
+
+# Order of names in SPD_SOURCES is important!
+SPD_SOURCES  = HYNIX-2G-1333
+SPD_SOURCES += HYNIX-4G-1333-ECC