.checkpatch.conf

@@ -16,6 +16,7 @@
 --ignore VOLATILE
 --ignore CONFIG_DESCRIPTION
 --ignore MISSING_SPACE
+--ignore CORRUPTED_PATCH
 
 # FILE_PATH_CHANGES seems to not be working correctly. It will
 # choke on added / deleted files even if the MAINTAINERS file
@@ -28,4 +29,3 @@
 
 # Exclude the vendorcode directory
 --exclude src/vendorcode
-

.clang-format

@@ -1,6 +1,10 @@
-BasedOnStyle: LLVM
-IndentWidth: 8
-UseTab: Always
-BreakBeforeBraces: Linux
-AllowShortIfStatementsOnASingleLine: false
-IndentCaseLabels: false
+BasedOnStyle:                              LLVM
+Language:                                  Cpp
+IndentWidth:                               8
+UseTab:                                    Always
+BreakBeforeBraces:                         Linux
+AllowShortIfStatementsOnASingleLine:       false
+IndentCaseLabels:                          false
+SortIncludes:                              false
+ContinuationIndentWidth:                   8
+ColumnLimit:                               80

.gitignore

@@ -17,6 +17,7 @@ payloads/external/depthcharge/depthcharge/
 payloads/external/FILO/filo/
 payloads/external/GRUB2/grub2/
 payloads/external/SeaBIOS/seabios/
+payloads/external/tianocore/tianocore/
 payloads/external/tint/tint/
 payloads/external/U-Boot/u-boot/
 payloads/external/Memtest86Plus/memtest86plus/
@@ -61,6 +62,7 @@ site-local
 *.pyc
 *.sw[po]
 /*.rom
+coreboot-builds*/
 
 # Development friendly files
 tags
@@ -85,7 +87,9 @@ util/*/.test
 util/amdfwtool/amdfwtool
 util/archive/archive
 util/bimgtool/bimgtool
+util/bincfg/bincfg
 util/board_status/board-status
+util/cbfstool/cbfs-compression-tool
 util/cbfstool/cbfstool
 util/cbfstool/fmaptool
 util/cbfstool/ifwitool
@@ -118,6 +122,8 @@ util/superiotool/superiotool
 util/vgabios/testbios
 util/viatool/viatool
 util/autoport/autoport
+util/kbc1126/kbc1126_ec_dump
+util/kbc1126/kbc1126_ec_insert
 
 documentation/*.aux
 documentation/*.idx
@@ -129,5 +135,6 @@ documentation/cpukconfig.tex
 documentation/mainboardkconfig.tex
 documentation/skconfig.tex
 documentation/socketfkconfig.tex
+Documentation/_build
 
 doxygen/*

CHANGELOG.md

@@ -13,6 +13,17 @@ Releases 4.5.x and 4.6.x are based on mainline support submitted in
 3. `make`
 
 ## [Unreleased]
+## [v4.8.0.1] - 2018-06-08
+### Changed
+- Rebased coreboot repository to official coreboot 4.8.0
+
+## [v4.6.10] - 2018-06-08
+### Changed
+- Updated SeaBIOS to 1.11.0.5
+- Updated sortbootorder to v4.6.9
+
+### Added
+- S1 button support for apu5b
 
 ## [v4.6.9] - 2018-05-11
 ### Added
@@ -177,7 +188,9 @@ redundant code which was similar for APU2/3/5 boards.
 - turn off D4 and D5 leds on boot
 - enable power on after power failure
 
-[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.6.9...coreboot-4.6.x
+[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.8.0.1...develop
+[v4.8.0.1]: https://github.com/pcengines/coreboot/compare/v4.6.9...v4.8.0.1
+[v4.6.10]: https://github.com/pcengines/coreboot/compare/v4.6.9...v4.6.10
 [v4.6.9]: https://github.com/pcengines/coreboot/compare/v4.6.8...v4.6.9
 [v4.6.8]: https://github.com/pcengines/coreboot/compare/v4.6.7...v4.6.8
 [v4.6.7]: https://github.com/pcengines/coreboot/compare/v4.6.6...v4.6.7

Documentation/AMD-S3.txt

@@ -13,7 +13,7 @@
  /_/    \_\_|  |_|_____/  |_____/  |____/
 
 
-               S3 in Coreboot (V 1.2)
+               S3 in coreboot (V 1.2)
 ----------------------------------------
                 Zheng Bao
             <zheng.bao@amd.com>
@@ -78,7 +78,7 @@ as reserved in e820, or BIOS saves the content into reserved space.
 Here is the address Map for S3 Resume. Assumingly the total memory is 1GB.
 00000000 --- 00100000      BIOS Reserved area.
 00100000 --- 00200000      Free
-00200000 --- 01000000      Coreboot ramstage area.
+00200000 --- 01000000      coreboot ramstage area.
 01000000 --- 2e160000      Free
 2e160000 --- 2e170000      ACPI table
 2e170000 --- 2ef70000      OSRAM
@@ -99,7 +99,7 @@ board.[2]
  Provided by Southbridge vendor code. Early is called before PCI
  enumeration, and Late is called after that.
 
-Lifecycle of booting, sleeping and waking Coreboot and Ubuntu
+Lifecycle of booting, sleeping and waking coreboot and Ubuntu
 =============================================================
 1. Cold boot.
 For a system with S3 feature, the BIOS needs to save some data to
@@ -130,7 +130,7 @@ when system wakeups.
 As we mentioned, Firmware detects the SLP_TYPx to find out if the board
 wakes up. In romstage.c, AmdInitReset and AmdInitEarly are called
 as they are during cold boot. AmdInitResume and AmdS3LateRestore are
-called only during resume. For whole ramstage, Coreboot goes through
+called only during resume. For whole ramstage, coreboot goes through
 almost the same way as cold boot, other than not calling the AmdInitMid,
 AmdInitLate and AmdS3Save, and restoring all the MTRRs.
 At last step of coreboot stage, coreboot finds out the wakeup vector in FADT,
@@ -141,13 +141,13 @@ When Linux resumes, all the sleeping scripts call their resume
 hooks. If we are more lucky, all the scripts can go through. More
 chances that the 99video hangs or fails to get the display
 back. Sometimes it can fixed if CONFIG_S3_VGA_ROM_RUN is unset in
-Coreboot/Kconfig. That needs more troubleshooting.
+coreboot/Kconfig. That needs more troubleshooting.
 
 
 Reference
 =========
 [1]   ACPI40a, http://www.acpi.info/spec40a.htm
-[2]   Coreboot Vendorcode, {top}/src/vendorcode/amd/agesa/{family}/Proc/Common/
-[3]   Coreboot AGESA wrapper, {top}/src/mainboard/amd/parmer/agesawrapper.c
-[4]   Coreboot AGESA wrapper, {top}/src/cpu/amd/agesa/s3_resume.c
-[5]   Coreboot Southbridge, {top}/src/southbridge/amd/agesa/hudson/spi.c
+[2]   coreboot Vendorcode, {top}/src/vendorcode/amd/agesa/{family}/Proc/Common/
+[3]   coreboot AGESA wrapper, {top}/src/mainboard/amd/parmer/agesawrapper.c
+[4]   coreboot AGESA wrapper, {top}/src/cpu/amd/agesa/s3_resume.c
+[5]   coreboot Southbridge, {top}/src/southbridge/amd/agesa/hudson/spi.c

Documentation/Binary Extraction.md

@@ -0,0 +1,68 @@
+# Intel IFD Binary Extraction Tutorial
+
+## Part 1: Extracting Binaries
+
+To begin extracting the binaries, first create a directory labeled "binaries"
+in the coreboot directory (i.e. /path/to/coreboot/binaries/).
+
+Now, execute the following commands to extract the binaries from a ROM image.
+**Note:** Make sure you are in the root coreboot directory.
+
+    cd /path/to/coreboot/util/ifdtool
+    ./ifdtool COREBOOT_IMAGE
+    ./ifdtool -d COREBOOT_IMAGE
+    ./ifdtool -x COREBOOT_IMAGE
+
+In the above steps, COREBOOT_IMAGE is the name of the ROM image to extract the
+binaries from, including the file path (ex. /build/coreboot.rom).
+
+Copy the extracted .bin files to the binaries directory you created previously.
+**Note:** You may want to rename your various .bin files to more clearly
+indicate what they are and their purpose.
+
+To extract the mrc.bin, move to the /coreboot/build directory and run the
+following command:
+
+    cd /path/to/coreboot/build/
+    ./cbfstool COREBOOT_IMAGE extract -n mrc.bin -f /path/to/destination/filename
+
+where COREBOOT_IMAGE is the filepath to the ROM image (same image as above),
+/path/to/destination is the filepath to the destination directory and filename
+is the output filename. An example command is given below:
+
+    ./cbfstool coreboot.rom extract -n mrc.bin -f /path/to/coreboot/binaries/mrc.bin
+
+## Part 2: Using extract_blobs.sh
+
+To simplify some of the steps above, there is a script in the
+/path/to/coreboot/util/chromeos/ directory called extract_blobs.sh what will
+extract the flashdescriptor.bin and intel_me.bin files.
+
+To run this script, switch to the /path/to/coreboot/util/chromeos/ directory
+and execute the script providing a coreboot image as an argument.
+
+    cd /path/to/coreboot/util/chromeos/
+    ./extract_blobs.sh COREBOOT_IMAGE
+
+Executing those commands will result in two binary blobs to appear in the
+/path/to/coreboot/util/chromeos/ directory under the names
+'flashdescriptor.bin' and 'me.bin'.
+
+## Part 3: Changing the coreboot configuration settings
+
+To begin using the binaries extracted above, enable the use of binary
+repositories in the menuconfig. From the main coreboot directory, run
+'make menuconfig'. Select "General Setup", then select "Allow use of
+binary-only repository", then exit to the main menu.
+
+To configure the ROM image for a specific board, select "Mainboard". Select
+"Mainboard vendor" and scroll to the correct vendor. Then select "Mainboard
+model" and select the name of the board model. Exit back to the main menu.
+
+To add the binaries you extracted, select "Chipset". Scroll and select "Add a
+System Agent Binary" and set the filepath to your mrc.bin file's filepath.
+Scroll and select "Add Intel descriptor.bin file" and type the filepath for
+your descriptor.bin file. Scroll down and select "Add Intel ME/TXE firmware
+file" and type the filepath for your ME file. Exit to the main menu.
+
+Select "Exit", and select "Yes" when prompted to save your configuration.