11 changes: 10 additions & 1 deletion CHANGELOG.md
View file
Expand Up @@ -14,6 +14,14 @@ Releases 4.5.x and 4.6.x are based on mainline support submitted in

## [Unreleased]

## [v4.6.7] - 2018-03-01
### Fixed
- SD cards performance drop
- SMBIOS part number format

### Changed
- xHCI has been enabled

## [v4.6.6] - 2018-01-31
### Changed
- Updated SeaBIOS to 1.11.0.3
Expand Down Expand Up @@ -150,7 +158,8 @@ redundant code which was similar for APU2/3/5 boards.
- turn off D4 and D5 leds on boot
- enable power on after power failure

[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.6.6...coreboot-4.6.x
[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.6.7...coreboot-4.6.x
[v4.6.7]: https://github.com/pcengines/coreboot/compare/v4.6.6...v4.6.7
[v4.6.6]: https://github.com/pcengines/coreboot/compare/v4.6.5...v4.6.6
[v4.6.5]: https://github.com/pcengines/coreboot/compare/v4.6.4...v4.6.5
[v4.6.4]: https://github.com/pcengines/coreboot/compare/v4.6.3...v4.6.4
Expand Down
4 changes: 2 additions & 2 deletions configs/pcengines_apu2.config
View file
Expand Up @@ -101,7 +101,7 @@ CONFIG_VENDOR_PCENGINES=y
# CONFIG_VENDOR_WYSE is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_DIR="pcengines/apu2"
CONFIG_MAINBOARD_PART_NUMBER="PC Engines apu2"
CONFIG_MAINBOARD_PART_NUMBER="apu2"
CONFIG_IRQ_SLOT_COUNT=11
CONFIG_MAINBOARD_VENDOR="PC Engines"
CONFIG_MAX_CPUS=4
Expand Down Expand Up @@ -587,7 +587,7 @@ CONFIG_HAVE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_SMBIOS_TABLES=y
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="PC Engines apu2"
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="apu2"

#
# Payload
Expand Down
4 changes: 2 additions & 2 deletions configs/pcengines_apu3.config
View file
Expand Up @@ -101,7 +101,7 @@ CONFIG_VENDOR_PCENGINES=y
# CONFIG_VENDOR_WYSE is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_DIR="pcengines/apu2"
CONFIG_MAINBOARD_PART_NUMBER="PC Engines apu3"
CONFIG_MAINBOARD_PART_NUMBER="apu3"
CONFIG_IRQ_SLOT_COUNT=11
CONFIG_MAINBOARD_VENDOR="PC Engines"
CONFIG_MAX_CPUS=4
Expand Down Expand Up @@ -587,7 +587,7 @@ CONFIG_HAVE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_SMBIOS_TABLES=y
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="PC Engines apu3"
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="apu3"

#
# Payload
Expand Down
4 changes: 2 additions & 2 deletions configs/pcengines_apu4.config
View file
Expand Up @@ -101,7 +101,7 @@ CONFIG_VENDOR_PCENGINES=y
# CONFIG_VENDOR_WYSE is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_DIR="pcengines/apu2"
CONFIG_MAINBOARD_PART_NUMBER="PC Engines apu4"
CONFIG_MAINBOARD_PART_NUMBER="apu4"
CONFIG_IRQ_SLOT_COUNT=11
CONFIG_MAINBOARD_VENDOR="PC Engines"
CONFIG_MAX_CPUS=4
Expand Down Expand Up @@ -587,7 +587,7 @@ CONFIG_HAVE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_SMBIOS_TABLES=y
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="PC Engines apu4"
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="apu4"

#
# Payload
Expand Down
4 changes: 2 additions & 2 deletions configs/pcengines_apu5.config
View file
Expand Up @@ -101,7 +101,7 @@ CONFIG_VENDOR_PCENGINES=y
# CONFIG_VENDOR_WYSE is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_DIR="pcengines/apu2"
CONFIG_MAINBOARD_PART_NUMBER="PC Engines apu5"
CONFIG_MAINBOARD_PART_NUMBER="apu5"
CONFIG_IRQ_SLOT_COUNT=11
CONFIG_MAINBOARD_VENDOR="PC Engines"
CONFIG_MAX_CPUS=4
Expand Down Expand Up @@ -585,7 +585,7 @@ CONFIG_HAVE_PIRQ_TABLE=y
CONFIG_GENERATE_MP_TABLE=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_SMBIOS_TABLES=y
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="PC Engines apu5"
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="apu5"

#
# Payload
Expand Down
1 change: 0 additions & 1 deletion payloads/external/SeaBIOS/Makefile
View file
Expand Up @@ -73,7 +73,6 @@ endif
echo "# CONFIG_PS2PORT is not set" >> seabios/.config
echo "# CONFIG_USB_UHCI is not set" >> seabios/.config
echo "# CONFIG_USB_OHCI is not set" >> seabios/.config
echo "# CONFIG_USB_XHCI is not set" >> seabios/.config
echo "# CONFIG_LPT is not set" >> seabios/.config
#
# Enable UDMA to speed up booting
Expand Down
8 changes: 4 additions & 4 deletions src/mainboard/pcengines/apu2/Kconfig
View file
Expand Up @@ -51,10 +51,10 @@ config DEVICETREE

config MAINBOARD_PART_NUMBER
string
default "PC Engines apu2" if BOARD_PCENGINES_APU2
default "PC Engines apu3" if BOARD_PCENGINES_APU3
default "PC Engines apu4" if BOARD_PCENGINES_APU4
default "PC Engines apu5" if BOARD_PCENGINES_APU5
default "apu2" if BOARD_PCENGINES_APU2
default "apu3" if BOARD_PCENGINES_APU3
default "apu4" if BOARD_PCENGINES_APU4
default "apu5" if BOARD_PCENGINES_APU5

config MAX_CPUS
int
Expand Down
12 changes: 0 additions & 12 deletions src/mainboard/pcengines/apu2/mainboard.c
View file
Expand Up @@ -40,7 +40,6 @@
#define PM_RTC_CONTROL 0x56
#define PM_RTC_SHADOW 0x5B
#define PM_S_STATE_CONTROL 0xBA
#define PM_USB_ENABLE 0xEF

#define SEC_REG_SERIAL_ADDR 0x1000
#define MAX_SERIAL_LEN 10
Expand Down Expand Up @@ -249,17 +248,6 @@ static void mainboard_enable(device_t dev)
//
pm_write8 ( PM_RTC_SHADOW, pm_read8( PM_RTC_SHADOW ) | (1 << 0));


//
// Set EHCI3 as controller for port 8 and 9 (front USB ports)
//
pm_write8 ( PM_USB_ENABLE, pm_read8( PM_USB_ENABLE ) & ~(1 << 7));

//
// Enable EHCI3
//
pm_write8 ( PM_USB_ENABLE, pm_read8( PM_USB_ENABLE ) | (1 << 5));

/* Initialize the PIRQ data structures for consumption */
pirq_setup();
}
Expand Down
3 changes: 2 additions & 1 deletion src/mainboard/pcengines/apu2/romstage.c
View file
Expand Up @@ -81,7 +81,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

if(scon) {
// sign of life strings
printk(BIOS_ALERT, CONFIG_MAINBOARD_PART_NUMBER "\n");
printk(BIOS_ALERT, CONFIG_MAINBOARD_SMBIOS_MANUFACTURER " "
CONFIG_MAINBOARD_PART_NUMBER "\n");
printk(BIOS_ALERT, "coreboot build %s\n", COREBOOT_DMI_DATE);
printk(BIOS_ALERT, "BIOS version %s\n", COREBOOT_ORIGIN_GIT_TAG);
}
Expand Down
37 changes: 19 additions & 18 deletions src/southbridge/amd/pi/hudson/sd.c
View file
Expand Up @@ -27,27 +27,28 @@ static void sd_init(struct device *dev)

stepping = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xFC);

struct southbridge_amd_pi_hudson_config *sd_chip =
(struct southbridge_amd_pi_hudson_config *)(dev->chip_info);
//struct southbridge_amd_pi_hudson_config *sd_chip =
// (struct southbridge_amd_pi_hudson_config *)(dev->chip_info);

if (sd_chip->sd_mode == 3) { /* SD 3.0 mode */
pci_write_config32(dev, 0xA4, 0x31FEC8B2);
pci_write_config32(dev, 0xA8, 0x00002503);
pci_write_config32(dev, 0xB0, 0x02180C19);
pci_write_config32(dev, 0xD0, 0x0000078B);
// if (sd_chip->sd_mode == 3) { /* SD 3.0 mode */
// pci_write_config32(dev, 0xA4, 0x31FEC8B2);
// pci_write_config32(dev, 0xA8, 0x00002503);
// pci_write_config32(dev, 0xB0, 0x02180C19);
// pci_write_config32(dev, 0xD0, 0x0000078B);
// }
// else { /* SD 2.0 mode */
if ((stepping & 0x0000000F) == 0) { /* Stepping A0 */
pci_write_config32(dev, 0xA4, 0x21DE32B2);
pci_write_config32(dev, 0xB0, 0x01180C19);
pci_write_config32(dev, 0xD0, 0x0000058B);
}
else { /* SD 2.0 mode */
if ((stepping & 0x0000000F) == 0) { /* Stepping A0 */
pci_write_config32(dev, 0xA4, 0x31DE32B2);
pci_write_config32(dev, 0xB0, 0x01180C19);
pci_write_config32(dev, 0xD0, 0x0000058B);
}
else { /* Stepping >= A1 */
pci_write_config32(dev, 0xA4, 0x31FE3FB2);
pci_write_config32(dev, 0xB0, 0x01180C19);
pci_write_config32(dev, 0xD0, 0x0000078B);
}
else { /* Stepping >= A1 */
pci_write_config32(dev, 0xA4, 0x21FE32B2);
pci_write_config32(dev, 0xA8, 0x00000070);
pci_write_config32(dev, 0xB0, 0x01180C19);
pci_write_config32(dev, 0xD0, 0x0000078B);
}
//}
}

static struct device_operations sd_ops = {
Expand Down