Showing 3,059 changed files with 245,490 additions and 241,470 deletions.
diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -4,6 +4,9 @@ Change log for PC Engines fork of coreboot
 Releases 4.0.x are based on PC Engines 20160304 release.
 Releases 4.5.x and 4.6.x are based on mainline support submitted in
 [this gerrit ref](https://review.coreboot.org/#/c/14138/).
+Releases 4.8.0.x are based on continuous synchronization with official
+[coreboot repository](https://review.coreboot.org/cgit/coreboot.git)
+
 
 ## Quick build instructions
 1. After cloning run `make crossgcc-i386` to build the toolchain.
@@ -13,6 +16,11 @@ Releases 4.5.x and 4.6.x are based on mainline support submitted in
 3. `make`
 
 ## [Unreleased]
+
+## [v4.8.0.2] - 2018-07-08
+### Changed
+- synced and rebased with coreboot official repo commit afc74ca
+
 ## [v4.8.0.1] - 2018-06-08
 ### Changed
 - Rebased coreboot repository to official coreboot 4.8.0
@@ -188,7 +196,8 @@ redundant code which was similar for APU2/3/5 boards.
 - turn off D4 and D5 leds on boot
 - enable power on after power failure
 
-[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.8.0.1...develop
+[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.8.0.2...develop
+[v4.8.0.2]: https://github.com/pcengines/coreboot/compare/v4.8.0.1...v4.8.0.2
 [v4.8.0.1]: https://github.com/pcengines/coreboot/compare/v4.6.9...v4.8.0.1
 [v4.6.10]: https://github.com/pcengines/coreboot/compare/v4.6.9...v4.6.10
 [v4.6.9]: https://github.com/pcengines/coreboot/compare/v4.6.8...v4.6.9

diff --git a/Documentation/Binary Extraction.md → Documentation/Binary_Extraction.md b/Documentation/Binary Extraction.md → Documentation/Binary_Extraction.md
diff --git a/Documentation/Intel/NativeRaminit/Sandybridge.md b/Documentation/Intel/NativeRaminit/Sandybridge.md
diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html
@@ -516,7 +516,7 @@ <h4><a name="SubsystemIds">Subsystem IDs</a></h4>
   a "struct pci_operations" that specifies a routine to set the subsystem
   IDs for the device.  The routine might look something like this:
 </p>
-<pre><code>static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+<pre><code>static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
 {
 	if (!vendor || !device) {
 		vendor = pci_read_config32(dev, PCI_VENDOR_ID);
@@ -538,7 +538,7 @@ <h3>Set up the <a name="MemoryMap">Memory Map</a></h3>
   The memory map is built by the various PCI device drivers during the
   BS_DEV_RESOURCES state of ramstage.  The northcluster driver will typically
   specify the DRAM resources while the other drivers will typically specify
-  the IO resources.  These resources are hung off the device_t data structure by
+  the IO resources.  These resources are hung off the struct device *data structure by
   src/device/device_util.c/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/device/device_util.c;hb=HEAD#l448">new_resource</a>.
 </p>
 <p>

diff --git a/Documentation/Lesson1.md b/Documentation/Lesson1.md
diff --git a/Documentation/RFC/config.tex b/Documentation/RFC/config.tex
@@ -119,8 +119,8 @@ \section{Language}
 statement ::=
 		  option
 		| default
-        	| cpu
-        	| arch
+		| cpu
+		| arch
 		| northbridge
 		| southbridge
 		| superio

diff --git a/Documentation/cbfs.txt b/Documentation/cbfs.txt
@@ -384,7 +384,7 @@ PAYLOAD_SEGMENT_BSS    0x20535342   The memory specified by the segment
 PAYLOAD_SEGMENT_PARAMS 0x41524150   The segment contains information for
                                      the payload
 PAYLOAD_SEGMENT_ENTRY  0x52544E45   The segment contains the entry point
-		       		    for the payload
+		  		    for the payload
 
 'compression' is the compression scheme for the segment.  Each segment can
 be independently compressed. There are three compression types defined by