.gitmodules

@@ -21,3 +21,8 @@
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
 	url = https://github.com/coreboot/libgfxinit.git
+[submodule "3rdparty/fsp"]
+	path = 3rdparty/fsp
+	url = https://github.com/coreboot/fsp.git
+	update = none
+	ignore = dirty

CHANGELOG.md

@@ -16,6 +16,16 @@ Releases 4.8.0.x are based on continuous synchronization with official
 3. `make`
 
 ## [Unreleased]
+## [v4.8.0.5] - 2018-10-04
+### Changed
+- Updated sortbootorder to v4.6.11
+- Removed custom libpayload modifications
+- Synced and rebased with coreboot official repo commit b7b085d
+
+### Fixed
+- ECC exclusion range, ECC now works properly
+- apu1 bootorder PCI paths and letter assignments
+
 ## [v4.8.0.4] - 2018-08-31
 ### Changed
 - Synced and rebased with coreboot official repo commit e27c096
@@ -215,7 +225,8 @@ redundant code which was similar for APU2/3/5 boards.
 - turn off D4 and D5 leds on boot
 - enable power on after power failure
 
-[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.8.0.4...develop
+[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.8.0.5...develop
+[v4.8.0.5]: https://github.com/pcengines/coreboot/compare/v4.8.0.4...v4.8.0.5
 [v4.8.0.4]: https://github.com/pcengines/coreboot/compare/v4.8.0.3...v4.8.0.4
 [v4.8.0.3]: https://github.com/pcengines/coreboot/compare/v4.8.0.2...v4.8.0.3
 [v4.8.0.2]: https://github.com/pcengines/coreboot/compare/v4.8.0.1...v4.8.0.2

Documentation/arch/riscv/index.md

@@ -0,0 +1,47 @@
+# RISCV architecture documentation
+
+This section contains documentation about coreboot on RISCV architecture.
+
+## Mode usage
+All stages run in M mode.
+
+Payloads have a choice of managing M mode activity: they can control
+everything or nothing.
+
+Payloads run from the romstage (i.e. rampayloads) are started in M mode.
+The payload must, for example, prepare and install its own SBI.
+
+Payloads run from the ramstage are started in S mode, and trap delegation
+will have been done. These payloads rely on the SBI and can not replace it.
+
+## Stage handoff protocol
+On entry to a stage or payload,
+* all harts are running.
+* A0 is the hart ID
+* A1 is the pointer to the Flattened Device Tree (FDT).
+
+## Additional payload handoff requirements
+The location of cbmem should be placed in a node in the FDT.
+
+## Trap delegation
+Traps are delegated in the ramstage.
+
+## SMP within a stage
+At the beginning of each stage, all harts save 0 are spinning in a loop on a semaphore.
+At the end of the stage harts 1..max are released by changing the
+semaphore.
+
+A possible way to do this is to have a pointer to a struct containing variables, e.g.
+
+```c
+struct blocker {
+	void (*fn)(); // never returns
+}
+```
+
+The hart blocks until fn is non-null, and then calls it.
+If fn returns we will panic if possible, but behavior
+is largely undefined.
+
+Only hart 0 runs through most of the code in each stage.
+

Documentation/mainboard/sifive/hifive-unleashed.md

@@ -11,14 +11,14 @@ For general setup instructions, please refer to the [Getting Started Guide].
 
 The following things are still missing from this coreboot port:
 
-- Trampoline in the MBR block to support boot mode 1
+- Support running romstage from flash (fix stack) to support boot mode 1
 - CBMEM support
 - FU540 clock configuration
 - FU540 RAM init
 - Placing the ramstage in DRAM
 - Starting the U54 cores
 - FU540 PIN configuration and GPIO access macros
-- FU540 OTP driver and serial number read-out
+- Provide serial number to payload (e.g. in device tree)
 - Support for booting Linux on RISC-V
 
 

Documentation/northbridge/intel/sandybridge/nri_features.md

@@ -16,7 +16,7 @@
 
 ```eval_rst
 +---------------------------+----------------------+-------------+---------+---------------------+
-| Option                    |            Supported | Implemented | Working | Description         |
+| Option                    |            Supported | Implemented | Working | Comments            |
 +===========================+======================+=============+=========+=====================+
 | **Supported channels**                                                                         |
 +---------------------------+----------------------+-------------+---------+---------------------+

Makefile.inc

@@ -195,6 +195,9 @@ ifeq ($(CONFIG_USE_BLOBS),y)
 # this is necessary because 3rdparty/blobs is update=none, and so is ignored
 # unless explicitly requested and enabled through --checkout
 forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs))
+ifeq ($(CONFIG_MAINBOARD_USES_FSP2_0),y)
+forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/fsp))
+endif
 endif
 UPDATED_SUBMODULES:=1
 COREBOOT_EXPORTS += UPDATED_SUBMODULES
@@ -958,7 +961,9 @@ endif # ifeq ($(CONFIG_FMDFILE),)
 
 # generated at the same time as fmap.fmap
 $(obj)/fmap_config.h: $(obj)/fmap.fmap
+	true
 $(obj)/fmap.desc: $(obj)/fmap.fmap
+	true
 
 $(obj)/fmap.fmap: $(obj)/fmap.fmd $(FMAPTOOL)
 	echo "    FMAP       $(FMAPTOOL) -h $(obj)/fmap_config.h $< $@"

README → README.md

@@ -1,6 +1,5 @@
--------------------------------------------------------------------------------
 coreboot README
--------------------------------------------------------------------------------
+===============
 
 coreboot is a Free Software project aimed at replacing the proprietary BIOS
 (firmware) found in most computers.  coreboot performs a little bit of
@@ -24,7 +23,7 @@ Payloads
 After the basic initialization of the hardware has been performed, any
 desired "payload" can be started by coreboot.
 
-See https://www.coreboot.org/Payloads for a list of supported payloads.
+See <https://www.coreboot.org/Payloads> for a list of supported payloads.
 
 
 Supported Hardware
@@ -34,8 +33,8 @@ coreboot supports a wide range of chipsets, devices, and mainboards.
 
 For details please consult:
 
- * https://www.coreboot.org/Supported_Motherboards
- * https://www.coreboot.org/Supported_Chipsets_and_Devices
+ * <https://www.coreboot.org/Supported_Motherboards>
+ * <https://www.coreboot.org/Supported_Chipsets_and_Devices>
 
 
 Build Requirements
@@ -48,7 +47,7 @@ Build Requirements
    to those patches, sometimes by gcc aborting, sometimes - and that's worse -
    by generating broken object code.
    Two options: use our toolchain (eg. make crosstools-i386) or enable the
-   ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this
+   `ANY_TOOLCHAIN` Kconfig option if you're feeling lucky (no support in this
    case).
  * iasl (for targets with ACPI support)
  * pkg-config
@@ -58,14 +57,14 @@ Optional:
 
  * doxygen (for generating/viewing documentation)
  * gdb (for better debugging facilities on some targets)
- * ncurses (for 'make menuconfig' and 'make nconfig')
+ * ncurses (for `make menuconfig` and `make nconfig`)
  * flex and bison (for regenerating parsers)
 
 
 Building coreboot
 -----------------
 
-Please consult https://www.coreboot.org/Build_HOWTO for details.
+Please consult <https://www.coreboot.org/Build_HOWTO> for details.
 
 
 Testing coreboot Without Modifying Your Hardware
@@ -75,7 +74,7 @@ If you want to test coreboot without any risks before you really decide
 to use it on your hardware, you can use the QEMU system emulator to run
 coreboot virtually in QEMU.
 
-Please see https://www.coreboot.org/QEMU for details.
+Please see <https://www.coreboot.org/QEMU> for details.
 
 
 Website and Mailing List
@@ -84,11 +83,11 @@ Website and Mailing List
 Further details on the project, a FAQ, many HOWTOs, news, development
 guidelines and more can be found on the coreboot website:
 
-  https://www.coreboot.org
+  <https://www.coreboot.org>
 
 You can contact us directly on the coreboot mailing list:
 
-  https://www.coreboot.org/Mailinglist
+  <https://www.coreboot.org/Mailinglist>
 
 
 Copyright and License

configs/config.pcengines_apu1

@@ -1,18 +1,16 @@
+CONFIG_LOCALVERSION="v4.8.0.5"
 CONFIG_VENDOR_PCENGINES=y
+CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU1=y
 CONFIG_NO_GFX_INIT=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
 CONFIG_SEABIOS_REVISION=y
 CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.5"
 CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder"
+CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
 CONFIG_SEABIOS_DEBUG_LEVEL=0
-CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
-CONFIG_PXE_ROM_ID="10ec,8168"
 # CONFIG_PXE_SERIAL_CONSOLE is not set
-CONFIG_CPU_MICROCODE_CBFS_NONE=y
 CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
-CONFIG_MEMTEST_MASTER=y
 CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
-CONFIG_LOCALVERSION="v4.8.0.3"

configs/config.pcengines_apu2

@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.8.0.4"
+CONFIG_LOCALVERSION="v4.8.0.5"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU2=y

configs/config.pcengines_apu3

@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.8.0.4"
+CONFIG_LOCALVERSION="v4.8.0.5"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU3=y

configs/config.pcengines_apu4

@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.8.0.4"
+CONFIG_LOCALVERSION="v4.8.0.5"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU4=y

configs/config.pcengines_apu5

@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.8.0.4"
+CONFIG_LOCALVERSION="v4.8.0.5"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU5=y

payloads/Makefile.inc

@@ -38,6 +38,7 @@ payloads/external/sgabios \
 payloads/external/tianocore \
 payloads/external/GRUB2 \
 payloads/external/LinuxBoot \
+payloads/external/Yabits \
 
 payloads/coreinfo/build/coreinfo.elf coreinfo:
 	$(MAKE) -C payloads/coreinfo defaultbuild

payloads/bayou/Doxyfile

@@ -800,7 +800,7 @@ HTML_HEADER            =
 
 HTML_FOOTER            =
 
-# If the HTML_FOOTER_DESCRIPTION tag is set to YES, Doxygen will 
+# If the HTML_FOOTER_DESCRIPTION tag is set to YES, Doxygen will
 # add generated date, project name and doxygen version to HTML footer.
 
 HTML_FOOTER_DESCRIPTION= YES

payloads/external/LinuxBoot/Kconfig

@@ -50,21 +50,21 @@ choice
 	default LINUXBOOT_KERNEL_STABLE
 
 config LINUXBOOT_KERNEL_STABLE
-	bool "4.15.3"
+	bool "4.14.67"
 	help
 	  Stable kernel version
 
 config LINUXBOOT_KERNEL_LATEST
-	bool "4.17.11"
+	bool "4.18.5"
 	help
 	  Latest kernel version
 
 endchoice
 
 config LINUXBOOT_KERNEL_VERSION
 	string
-	default "4.17.11" if LINUXBOOT_KERNEL_LATEST
-	default "4.15.3" if LINUXBOOT_KERNEL_STABLE
+	default "4.18.5" if LINUXBOOT_KERNEL_LATEST
+	default "4.14.67" if LINUXBOOT_KERNEL_STABLE
 
 config LINUXBOOT_KERNEL_CONFIGFILE
 	string "Kernel config file"

payloads/external/LinuxBoot/Makefile

@@ -77,26 +77,26 @@ else ifeq ($(CONFIG_LINUXBOOT_ARCH),arm64)
 $(project_dir)/vmlinux.bin: $(kernel_dir)/vmlinux
 	$(OBJCOPY) -O binary $< $@
 
-$(project_dir)/target.dtb: $(CONFIG_LINUXBOOT_DTB_FILE)
+$(project_dir)/target.dtb: $(PWD)/$(CONFIG_LINUXBOOT_DTB_FILE)
 	cp $< $@
 
 $(project_dir)/vmlinux.bin.lzma: $(project_dir)/vmlinux.bin
 	xz -c -k -f --format=lzma --lzma1=dict=1MiB,lc=3,lp=0,pb=3 $< > $@
 
-$(project_dir)/kernel-image: $(project_dir)/vmlinux.bin.lzma $(project_dir)/../arm64/kernel_fdt_lzma.its $(project_dir)/target.dtb $(project_dir)/initramfs.cpio.xz
+$(project_dir)/kernel-image: $(project_dir)/vmlinux.bin.lzma $(project_dir)/../arm64/kernel_fdt_lzma.its $(project_dir)/target.dtb $(PWD)/$(CONFIG_PAYLOAD_USERSPACE)
 	cp $(project_dir)/../arm64/kernel_fdt_lzma.its $(project_dir)
 	mkimage -f $(project_dir)/kernel_fdt_lzma.its $@
 endif
 
 ifeq ($(CONFIG_LINUXBOOT_UROOT),y)
-$(project_dir)/initramfs.cpio.xz:
+$(PWD)/$(CONFIG_PAYLOAD_USERSPACE):
 	$(MAKE) -f targets/u-root.mk
 else
-$(project_dir)/initramfs.cpio.xz:
+$(PWD)/$(CONFIG_PAYLOAD_USERSPACE):
 	echo "Building without u-root support"
 endif
 
-payload: $(project_dir)/kernel-image $(project_dir)/initramfs.cpio.xz
+payload: $(project_dir)/kernel-image $(PWD)/$(CONFIG_PAYLOAD_USERSPACE)
 
 clean:
 	if [ -d "$(kernel_dir)" ]; then rm -rf $(kernel_dir); fi

payloads/external/LinuxBoot/targets/u-root.mk

@@ -71,10 +71,10 @@ endif
 else
 ifneq ($(CONFIG_LINUXBOOT_UROOT_FILES),)
 	cd $(uroot_dir); GOARCH=$(CONFIG_LINUXBOOT_ARCH) GOPATH=$(go_path_dir) ./u-root \
-	-build=bb -files $(CONFIG_LINUXBOOT_UROOT_FILES) -o $(project_dir)/initramfs.cpio
+	-build=bb -files $(CONFIG_LINUXBOOT_UROOT_FILES) -o $(project_dir)/initramfs.cpio coreboot-app
 else
 	cd $(uroot_dir); GOARCH=$(CONFIG_LINUXBOOT_ARCH) GOPATH=$(go_path_dir) ./u-root \
-	-build=bb -o $(project_dir)/initramfs.cpio
+	-build=bb -o $(project_dir)/initramfs.cpio coreboot-app
 endif
 endif
 	xz -f --check=crc32 -9 --lzma2=dict=1MiB --threads=$(CPUS) $(project_dir)/initramfs.cpio

payloads/external/Makefile.inc

@@ -186,6 +186,7 @@ payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd tianocore: $(DOTCONFI
 		CONFIG_TIANOCORE_REVISION_ID=$(CONFIG_TIANOCORE_REVISION_ID) \
 		CONFIG_TIANOCORE_DEBUG=$(CONFIG_TIANOCORE_DEBUG) \
 		CONFIG_TIANOCORE_TARGET_IA32=$(CONFIG_TIANOCORE_TARGET_IA32) \
+		CONFIG_TIANOCORE_USE_8254_TIMER=$(CONFIG_TIANOCORE_USE_8254_TIMER) \
 		GCC_CC_x86_32=$(GCC_CC_x86_32) \
 		GCC_CC_x86_64=$(GCC_CC_x86_64) \
 		GCC_CC_arm=$(GCC_CC_arm) \
@@ -335,10 +336,23 @@ linuxboot:
 		CONFIG_LINUXBOOT_ARCH=$(CONFIG_LINUXBOOT_ARCH) \
 		CONFIG_LINUXBOOT_UROOT=$(CONFIG_LINUXBOOT_UROOT) \
 		CONFIG_LINUXBOOT_UROOT_FILES=$(CONFIG_LINUXBOOT_UROOT_FILES) \
-		CONFIG_LINUXBOOT_DTB_FILE=$(CONFIG_LINUXBOOT_DTB_FILE)
+		CONFIG_LINUXBOOT_DTB_FILE=$(CONFIG_LINUXBOOT_DTB_FILE) \
+		CONFIG_PAYLOAD_USERSPACE=$(CONFIG_PAYLOAD_USERSPACE)
 
 
 payloads/external/LinuxBoot/linuxboot/kernel-image: linuxboot
 payloads/external/LinuxBoot/linuxboot/initramfs.cpio.xz: linuxboot
 payloads/external/LinuxBoot/linuxboot/kernel/.config: linuxboot
 payloads/external/LinuxBoot/linuxboot/go/src/github.com/u-root/u-root/.git: linuxboot
+
+payloads/external/Yabits/uefi/build/uefi.elf yabits:
+	$(MAKE) -C payloads/external/Yabits all \
+		CC="$(CC_x86_32)" \
+		LD="$(LD_x86_32)" \
+		OBJCOPY="$(OBJCOPY_x86_32)" \
+		AS="$(AS_x86_32)" \
+		CONFIG_YABITS_REVISION=$(CONFIG_YABITS_REVISION) \
+		CONFIG_YABITS_REVISION_ID=$(CONFIG_YABITS_REVISION_ID) \
+		CONFIG_YABITS_MASTER=$(CONFIG_YABITS_MASTER) \
+		CONFIG_YABITS_STABLE=$(CONFIG_YABITS_STABLE) \
+		MFLAGS= MAKEFLAGS=