Showing 1,338 changed files with 7,620 additions and 33,591 deletions.
diff --git a/.gitignore b/.gitignore
@@ -90,6 +90,7 @@ util/archive/archive
 util/bimgtool/bimgtool
 util/bincfg/bincfg
 util/board_status/board-status
+util/bucts/bucts
 util/cbfstool/cbfs-compression-tool
 util/cbfstool/cbfstool
 util/cbfstool/fmaptool

diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -16,6 +16,19 @@ Releases 4.8.0.x are based on continuous synchronization with official
 3. `make`
 
 ## [Unreleased]
+## [v4.8.0.7] - 2018-12-03
+### Changed
+- updated SeaBIOS to rel-1.11.0.7
+- updated sortbootorder to v4.6.12
+
+### Added
+- [experimental option for adding microcode update](https://github.com/pcengines/apu2-documentation/blob/master/docs/microcode_patching.md)
+- enabled PCIe ACS and AER capabilities
+- [COM2 redirection runtime configuration](https://github.com/pcengines/apu2-documentation/blob/master/docs/serial_console.md)
+
+### Fixed
+- generating serial number from MAC address of first NIC
+
 ## [v4.8.0.6] - 2018-11-08
 ### Changed
 - Updated SeaBIOS to rel-1.11.0.6
@@ -233,7 +246,8 @@ redundant code which was similar for APU2/3/5 boards.
 - turn off D4 and D5 leds on boot
 - enable power on after power failure
 
-[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.8.0.6...develop
+[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.8.0.7...develop
+[v4.8.0.7]: https://github.com/pcengines/coreboot/compare/v4.8.0.6...v4.8.0.7
 [v4.8.0.6]: https://github.com/pcengines/coreboot/compare/v4.8.0.5...v4.8.0.6
 [v4.8.0.5]: https://github.com/pcengines/coreboot/compare/v4.8.0.4...v4.8.0.5
 [v4.8.0.4]: https://github.com/pcengines/coreboot/compare/v4.8.0.3...v4.8.0.4

diff --git a/Documentation/mainboard/asrock/h81m-hds.md b/Documentation/mainboard/asrock/h81m-hds.md
@@ -0,0 +1,146 @@
+# ASRock H81M-HDS
+
+This page describes how to run coreboot on the [ASRock H81M-HDS].
+
+## Required proprietary blobs
+
+This board currently requires a proprietary blob in order to initialise
+the RAM and a few other components. The blob largely consists of Intel's
+Memory Reference Code (shortened to mrc), and is just under 200 KiB
+in size. It is also known as a system agent binary. Unfortunately,
+it is not currently possible to distribute this as part of coreboot.
+However, the mrc can be obtained from a Haswell Chromebook firmware
+image, and you might find one online. The mrc from a ChromeOS image can
+be extracted with the following command. If extracting from a "standard"
+coreboot image, omit `-r RO_SECTION`.
+
+```bash
+cbfstool coreboot.rom extract -f mrc.bin -n mrc.bin -r RO_SECTION
+```
+
+Now, place mrc.bin in the root of the coreboot directory.
+Alternatively, place it anywhere you want, and set `MRC_FILE` to its
+location when building coreboot.
+
+## Building coreboot
+
+A fully working image should be possible just by setting your MAC
+address and obtaining the Haswell mrc. You can set the basic config
+with the following commands. However, it is strongly advised to use
+`make menuconfig` afterwards (or instead), so that you can see all of
+the settings.
+
+```bash
+make distclean # Note: this will remove your current config, if it exists.
+touch .config
+./util/scripts/config --enable VENDOR_ASROCK
+./util/scripts/config --enable BOARD_ASROCK_H81M_HDS
+./util/scripts/config --enable HAVE_MRC
+./util/scripts/config --set-str REALTEK_8168_MACADDRESS "xx:xx:xx:xx:xx:xx" # Fill this in!
+make olddefconfig
+```
+
+If you don't plan on using coreboot's serial console to collect logs,
+you might want to disable it at this point (`./util/scripts/config
+--disable CONSOLE_SERIAL`). It should reduce the boot time by several
+seconds. However, a more flexible method is to change the console log
+level from within an OS using `util/nvramtool`, or with the `nvramcui`
+payload.
+
+Now, run `make` to build the coreboot image.
+
+## Flashing coreboot
+
+### Internal programming
+
+The main SPI flash can be accessed using [flashrom]. By default, only
+the BIOS region of the flash is writable. If you wish to change any
+other region, such as the Management Engine or firmware descriptor, then
+an external programmer is required (unless you find a clever way around
+the flash protection).
+
+The following command may be used to flash coreboot:
+
+```bash
+sudo flashrom -p internal --ifd -i bios --noverify-all -w coreboot.rom
+```
+
+The use of `--noverify-all` is required since the Management Engine
+region is not readable even by the host.
+
+### External programming
+
+The flash chip is a 4 MiB socketed DIP-8 chip. Specifically, it's a
+Winbond W25Q32FV, whose datasheet can be found [here][W25Q32FV].
+The chip is located to the bottom right-hand side of the board. For
+a precise location, refer to section 1.4 (Motherboard Layout) of the
+[board manual], where the chip is labelled "32Mb BIOS". Take note of
+the chip's orientation, remove it from its socket, and flash it with
+an external programmer. For reference, the notch in the chip should be
+facing towards the bottom of the board.
+
+## Known issues
+
+- PCIe graphics is non-functional. The PCIe 16x slot doesn't work
+  with other devices, either.
+
+- The VGA port doesn't work until the OS reinitialises the display.
+
+- There is no automatic, OS-independent fan control. This is because
+  the super I/O hardware monitor can only obtain valid CPU temperature
+  readings from the PECI agent, but the required driver doesn't exist
+  in coreboot. The `coretemp` driver can still be used for accurate CPU
+  temperature readings from an OS.
+
+## Untested
+
+- parallel port
+- PS/2 keyboard
+- EHCI debug
+- TPM
+- infrared module
+- chassis intrusion header
+- chassis speaker header
+
+## Working
+
+- USB
+- S3 suspend/resume
+- Gigabit Ethernet
+- integrated graphics
+- PCIe (but not the 16x slot, see [Known issues](#known-issues))
+- SATA
+- PS/2 mouse
+- serial port
+- hardware monitor (see [Known issues](#known-issues))
+- onboard audio
+- front panel audio
+- initialisation with Haswell mrc version 1.6.1 build 2
+- graphics init with libgfxinit (see [Known issues](#known-issues))
+- flashrom under the vendor firmware
+- flashrom under coreboot
+- Wake-on-LAN
+- Using `me_cleaner`
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| Northbridge      | Intel Haswell                                    |
++------------------+--------------------------------------------------+
+| Southbridge      | Intel Lynx Point (H81)                           |
++------------------+--------------------------------------------------+
+| CPU              | Intel Haswell (LGA1150)                          |
++------------------+--------------------------------------------------+
+| Super I/O        | Nuvoton NCT6776                                  |
++------------------+--------------------------------------------------+
+| EC               | None                                             |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel Management Engine                          |
++------------------+--------------------------------------------------+
+```
+
+[ASRock H81M-HDS]: https://www.asrock.com/mb/Intel/H81M-HDS/
+[W25Q32FV]: https://www.winbond.com/resource-files/w25q32fv%20revi%2010202015.pdf
+[flashrom]: https://flashrom.org/Flashrom
+[Board manual]: http://asrock.pc.cdn.bitgravity.com/Manual/H81M-HDS.pdf
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
@@ -6,6 +6,10 @@ This section contains documentation about coreboot on specific mainboards.
 
 - [P8H61-M LX](asus/p8h61-m_lx.md)
 
+## ASRock
+
+- [H81M-HDS](asrock/h81m-hds.md)
+
 ## Cavium
 
 - [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)
@@ -16,6 +20,10 @@ The boards in this section are not real mainboards, but emulators.
 
 - [Spike RISC-V emulator](emulation/spike-riscv.md)
 
+## Intel
+
+- [DG43GT](intel/dg43gt.md)
+
 ## Foxconn
 
 - [D41S](foxconn/d41s.md)
@@ -44,6 +52,8 @@ The boards in this section are not real mainboards, but emulators.
 ### Ivy Bridge series
 
 - [T430](lenovo/t430.md)
+- [T530](lenovo/w530.md)
+- [W530](lenovo/w530.md)
 - [T430 / T530 / X230 / W530 common](lenovo/xx30_series.md)
 
 ## SiFive

diff --git a/Documentation/mainboard/intel/dg43gt.md b/Documentation/mainboard/intel/dg43gt.md
@@ -0,0 +1,99 @@
+# Intel DG43GT
+
+This page describes how to run coreboot on the [Intel DG43GT] desktop.
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | no         |
++---------------------+------------+
+| Model               | W25X32     |
++---------------------+------------+
+| Size                | 4 MiB      |
++---------------------+------------+
+| In circuit flashing | NO!        |
++---------------------+------------+
+| Package             | SOIC-8     |
++---------------------+------------+
+| Write protection    | No         |
++---------------------+------------+
+| Dual BIOS feature   | No         |
++---------------------+------------+
+| Internal flashing   | yes        |
++---------------------+------------+
+```
+
+### Internal programming
+
+The SPI flash can be accessed internally using [flashrom].
+Only the BIOS region can and needs to be written to.
+
+```bash
+     $ flashrom -p internal --ifd -i bios -w coreboot.rom --noverify-all
+```
+
+### External programming
+
+ISP (in circuit programming) seems to be impossible on this board, which
+is a property it shares with many boards featuring the ICH10 southbridge.
+**Recovering from a bad flash will require desoldering the flash!**
+Desoldering the SPI flash can easily be done with a hot air station.
+Apply some flux around the SPI flash, set the hot air station to 350-400°C
+and after heating the chip up for a minute it should be possible to remove it.
+
+Having removed the flash chip, you can reprogram it externally then resolder
+it using a soldering iron.
+Another option would be to hook up a SPI flash (socket) to the SPI header,
+for easier flash removing in the future (if you expect to be hacking on this
+board). To do this you first need to solder the SPI header to the board.
+
+**NOTE: This header cannot be used for ISP either.**
+
+**NOTE2: Don't forget to connect the WP# and HOLD# pin on the SPI flash to 3.3V.**
+
+The layout of the header is:
+
+```
+                  +---+---+
+           GND <- | x | x | -> SPI_CLK
+                  +---+---+
+          3VSB <- | x | x | -> SPI_MISO
+                  +---+---+
+                  |   | x | -> SPI_MOSI
+                  +---+---+
+        SPI_CS# <-| x | x | -> SPI_CS# (again)
+                  +---+---+
+```
+
+**Picture of the board with the flash hooked on externally**
+![][dg43gt_full]
+
+**Close up picture of the SPI flash pads and recovery header**
+![][dg43gt_closeup]
+
+[dg43gt_full]: dg43gt_full.jpg
+[dg43gt_closeup]: dg43gt_closeup.jpg
+
+## Technology
+
+```eval_rst
++------------------+---------------------------------------------------+
+| Northbridge      | Intel G43 (called x4x in coreboot code)           |
++------------------+---------------------------------------------------+
+| Southbridge      | Intel ICH10 (called i82801jx in coreboot code)    |
++------------------+---------------------------------------------------+
+| CPU (LGA775)     | model f4x, f6x, 6fx, 1067x (pentium 4, d, core 2) |
++------------------+---------------------------------------------------+
+| SuperIO          | Winbond W83627DHG                                 |
++------------------+---------------------------------------------------+
+| Coprocessor      | Intel ME (optionally enabled)                     |
++------------------+---------------------------------------------------+
+| Clockgen (CK505) | SLG8XP549T                                        |
++------------------+---------------------------------------------------+
+```
+
+[Intel DG43GT]: https://ark.intel.com/products/41036/Intel-Desktop-Board-DG43GT
+[flashrom]: https://flashrom.org/Flashrom
diff --git a/Documentation/mainboard/intel/dg43gt_closeup.jpg b/Documentation/mainboard/intel/dg43gt_closeup.jpg
diff --git a/Documentation/mainboard/intel/dg43gt_full.jpg b/Documentation/mainboard/intel/dg43gt_full.jpg
diff --git a/Documentation/mainboard/lenovo/t4xx_series.md b/Documentation/mainboard/lenovo/t4xx_series.md
@@ -18,3 +18,17 @@ the whole device.
 * Unplug the power cable
 * Remove the bottom enclosure
 * Flip the mainboard and remove the main frame
+
+## Docking stations
+The following docking stations are supported by coreboot:
+* Type 2505
+  * VGA, Ethernet, Modem, PS2, 4 USB Ports
+  * Dock ID on pc87382 reads as: 2
+* Type 2504
+  * Serial, LPT, LEDs, Audio, DVI, VGA, Ethernet, Modem, PS2, 4 USB Ports
+  * Dock ID on pc87382 reads as: 1
+  * PNP IO address of SuperIO pc87384: 0x2e
+
+There's no hotplug support for LPT and Serial on Type 2504.
+
+The Dock ID reads as 7 if no dock is connected.
diff --git a/Documentation/mainboard/lenovo/w530-1.jpg b/Documentation/mainboard/lenovo/w530-1.jpg
diff --git a/Documentation/mainboard/lenovo/w530-2.jpg b/Documentation/mainboard/lenovo/w530-2.jpg
diff --git a/Documentation/mainboard/lenovo/w530.md b/Documentation/mainboard/lenovo/w530.md
@@ -0,0 +1,27 @@
+# Lenovo W530 / T530
+
+## Flashing instructions
+You have to remove the keyboard and the palm rest to access one of the
+flash ICs. The second flash ICs is behind the case frame, but can be
+flashed by using a simple trick. Connect every pin of the first flash
+IC, but tie /CS to Vcc. Connect /CS of the second flash IC to the
+programmer.
+As all lines except /CS are shared between the flash ICs you can access
+both with an external programmer.
+
+For more details have a look at [T430 / T530 / X230 / T430s / W530 common] and
+```eval_rst
+:doc:`../../flash_tutorial/ext_power`
+```
+
+### After removing the keyboard and palm rest
+![][w530-1]
+
+[w530-1]: w530-1.jpg
+
+### Closeup view of the flash ICs
+![][w530-2]
+
+[w530-2]: w530-2.jpg
+
+[T430 / T530 / X230 / T430s / W530 common]: xx30_series.md