.gitlab-ci.yml

@@ -16,33 +16,34 @@ check_dependencies:
   script:
     - git ls-remote https://github.com/pcengines/coreboot.git | grep ${CI_COMMIT_REF_NAME}
   only:
-    - tags 
-      
+    - tags
+
 .build_rom_apu: &build_rom_apu
   image: coreboot/coreboot-sdk:1.50
   variables:
     PLATFORM: apux
   stage: build_rom
-  tags: 
+  tags:
     - docker
   script:
     - git clone https://github.com/pcengines/pce-fw-builder.git /home/coreboot/pce-fw-builder
     - cd /home/coreboot/pce-fw-builder
     - git checkout `git describe --tags --abbrev=0`
     - ./build.sh release-CI "${CI_COMMIT_REF_NAME}" "${PLATFORM}"
-    - cp -v /home/coreboot/release/${PLATFORM}_* ${RELEASE_DIR}
+    - cp -v /home/coreboot/release/${PLATFORM}_${CI_COMMIT_REF_NAME}.rom ${RELEASE_DIR}
     - ls -al ${RELEASE_DIR}
+    - sha256sum ${RELEASE_DIR}/${PLATFORM}_${CI_COMMIT_REF_NAME}.rom
   artifacts:
     name: ${PLATFORM}
     paths:
-      - ${RELEASE_DIR}/${PLATFORM}_*
+      - ${RELEASE_DIR}/${PLATFORM}_${CI_COMMIT_REF_NAME}.rom
   only:
     - tags
     - web
 
 .test_rom: &test_rom
   variables:
-    PLATFORM: 
+    PLATFORM:
   stage: test_rom
   tags:
     - docker
@@ -54,7 +55,7 @@ check_dependencies:
 
 .sign_rom: &sign_rom
   variables:
-    PLATFORM: 
+    PLATFORM:
   stage: sign_rom
   tags:
     - docker
@@ -79,8 +80,8 @@ check_dependencies:
     - ls -al ${RELEASE_DIR}
     - echo "curl -u ${UPLOADER_USERNAME}:${UPLOADER_PASSWORD} -X MKCOL ${UPLOADER_URL}/${PLATFORM}/; curl -u ${UPLOADER_USERNAME}:${UPLOADER_PASSWORD} -X MKCOL ${UPLOADER_URL}/${PLATFORM}/releases/"
     - curl -u ${UPLOADER_USERNAME}:${UPLOADER_PASSWORD} -X MKCOL "${UPLOADER_URL}/${PLATFORM}/"; curl -u ${UPLOADER_USERNAME}:${UPLOADER_PASSWORD} -X MKCOL "${UPLOADER_URL}/${PLATFORM}/releases/"
-    - echo "for file in ${RELEASE_DIR}/${PLATFORM}_*.tar.gz; do curl --fail -u ${UPLOADER_USERNAME}:${UPLOADER_PASSWORD} -T ${file} ${UPLOADER_URL}/${PLATFORM}/releases/; done"
-    - for file in ${RELEASE_DIR}/${PLATFORM}_*.tar.gz; do curl --fail -u ${UPLOADER_USERNAME}:${UPLOADER_PASSWORD} -T ${file} "${UPLOADER_URL}/${PLATFORM}/releases/"; done
+    - echo "for file in ${RELEASE_DIR}/${PLATFORM}_*.rom; do curl --fail -u ${UPLOADER_USERNAME}:${UPLOADER_PASSWORD} -T ${file} ${UPLOADER_URL}/${PLATFORM}/releases/; done"
+    - for file in ${RELEASE_DIR}/${PLATFORM}_*.rom; do curl --fail -u ${UPLOADER_USERNAME}:${UPLOADER_PASSWORD} -T ${file} "${UPLOADER_URL}/${PLATFORM}/releases/"; done
   only:
     - tags
 
@@ -115,18 +116,18 @@ build:apu2:
   <<: *test_rom
   variables:
     PLATFORM: apu2
-    
+
 .sign:apu2:
   <<: *sign_rom
   variables:
     PLATFORM: apu2
-    
+
 publish:apu2:
   <<: *publish_rom
   variables:
-    PLATFORM: apu2    
-    
-    
+    PLATFORM: apu2
+
+
 build:apu3:
   <<: *build_rom_apu
   variables:
@@ -136,18 +137,18 @@ build:apu3:
   <<: *test_rom
   variables:
     PLATFORM: apu3
-    
+
 .sign:apu3:
   <<: *sign_rom
   variables:
     PLATFORM: apu3
-    
+
 publish:apu3:
   <<: *publish_rom
   variables:
     PLATFORM: apu3
 
-   
+
 build:apu4:
   <<: *build_rom_apu
   variables:
@@ -157,18 +158,18 @@ build:apu4:
   <<: *test_rom
   variables:
     PLATFORM: apu4
-    
+
 .sign:apu4:
   <<: *sign_rom
   variables:
     PLATFORM: apu4
-    
+
 publish:apu4:
   <<: *publish_rom
   variables:
-    PLATFORM: apu4 
+    PLATFORM: apu4
+
 
-
 build:apu5:
   <<: *build_rom_apu
   variables:
@@ -178,13 +179,13 @@ build:apu5:
   <<: *test_rom
   variables:
     PLATFORM: apu5
-    
+
 .sign:apu5:
   <<: *sign_rom
   variables:
     PLATFORM: apu5
-    
+
 publish:apu5:
   <<: *publish_rom
   variables:
-    PLATFORM: apu5    
+    PLATFORM: apu5

CHANGELOG.md

@@ -4,18 +4,27 @@ Change log for PC Engines fork of coreboot
 Releases 4.0.x are based on PC Engines 20160304 release.
 Releases 4.5.x and 4.6.x are based on mainline support submitted in
 [this gerrit ref](https://review.coreboot.org/#/c/14138/).
-Releases 4.8.0.x are based on continuous synchronization with official
-[coreboot repository](https://review.coreboot.org/cgit/coreboot.git)
-
+Releases 4.8.0.x/4.9.0.x are based on continuous synchronization with
+official [coreboot repository](https://review.coreboot.org/cgit/coreboot.git)
 
 ## Quick build instructions
-1. After cloning run `make crossgcc-i386` to build the toolchain.
-2. `make menuconfig` and set:
-  * `Mainboard/Mainboard vendor` → `PCEngines`
-  * `Mainboard/Mainboard model` → `APU2`, `APU3` or `APU5`
-3. `make`
+
+Please use [pce-fw-builder](https://github.com/pcengines/pce-fw-builder)
 
 ## [Unreleased]
+
+## [v4.9.0.1] - 2019-01-09
+## Changed
+- rebased with official coreboot repository commit cd26f08
+- updated SeaBIOS to rel-1.12.0.1
+- prepare apu1 platform for TPM usage
+- enabled TPM2.0 module on apu1, apu2 and apu5 in default configuration
+
+## Fixed
+- disabled waiting for SVI2 command completion causing reboot hangs
+- introduced reproducible builds by passing build ID to iPXE
+- AGESA AmdInitLate error caused by AGESA bugs
+
 ## [v4.8.0.7] - 2018-12-03
 ### Changed
 - updated SeaBIOS to rel-1.11.0.7
@@ -246,7 +255,8 @@ redundant code which was similar for APU2/3/5 boards.
 - turn off D4 and D5 leds on boot
 - enable power on after power failure
 
-[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.8.0.7...develop
+[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.9.0.1...develop
+[v4.9.0.1]: https://github.com/pcengines/coreboot/compare/v4.8.0.7...v4.9.0.1
 [v4.8.0.7]: https://github.com/pcengines/coreboot/compare/v4.8.0.6...v4.8.0.7
 [v4.8.0.6]: https://github.com/pcengines/coreboot/compare/v4.8.0.5...v4.8.0.6
 [v4.8.0.5]: https://github.com/pcengines/coreboot/compare/v4.8.0.4...v4.8.0.5

Documentation/Intel/Board/Galileo_checklist.html

@@ -79,8 +79,6 @@ <h1>Galileo Implementation Status<br>2016/07/08 06:51:34 PDT</h1>
 <tr bgcolor=#ffc0c0><td>Required</td><td>smm_region_size</td></tr>
 <tr bgcolor=#c0ffc0><td>Required</td><td>soc_after_ram_init</td></tr>
 <tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_memory_init_params</td></tr>
-<tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_mtrrs</td></tr>
-<tr bgcolor=#c0ffc0><td>Required</td><td>soc_get_variable_mtrr_count</td></tr>
 <tr bgcolor=#c0ffc0><td>Required</td><td>soc_memory_init_params</td></tr>
 <tr bgcolor=#ffffc0><td>Optional</td><td>soc_pre_ram_init</td></tr>
 <tr bgcolor=#ffffc0><td>Optional</td><td>southbridge_smi_handler</td></tr>

Documentation/Intel/SoC/soc.html

@@ -234,8 +234,6 @@ <h3>Find FSP Binary</h3>
         <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc">src/drivers/intel/fsp1_1/cache_as_ram.inc</a>
       </li>
       <li>Add "select SOC_INTEL_COMMON" to enable the use of the files from src/soc/intel/common
-        specifically building
-        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/soc/intel/common/util.c">util.c</a>
       </li>
     </ol>
   </li>

Documentation/Intel/development.html

@@ -264,7 +264,7 @@ <h2>Add coreboot Features</h2>
       <ul>
         <li>MemoryInit UPD values are correct</li>
         <li>MemoryInit returns 0 (success) and</li>
-        <li>The the message "ERROR - coreboot's requirements not met by FSP binary!"
+        <li>The message "ERROR - coreboot's requirements not met by FSP binary!"
           is not displayed
         </li>
       </ul>
@@ -324,7 +324,7 @@ <h2>Add coreboot Features</h2>
       <ul>
         <li>MemoryInit UPD values are correct</li>
         <li>MemoryInit returns 0 (success) and</li>
-        <li>The the message "ERROR - coreboot's requirements not met by FSP binary!"
+        <li>The message "ERROR - coreboot's requirements not met by FSP binary!"
           is not displayed
         </li>
       </ul>
@@ -374,4 +374,4 @@ <h2>Add coreboot Features</h2>
 <hr>
 <p>Modified: 4 March 2016</p>
   </body>
-</html>
+</html>

Documentation/arch/index.md

@@ -6,3 +6,6 @@ architectures.
 ## RISC-V
 
 - [RISC-V documentation](riscv/index.md)
+
+## x86
+- [x86 documentation](x86/index.md)

Documentation/arch/x86/index.md

@@ -0,0 +1,42 @@
+# x86 architecture documentation
+
+This section contains documentation about coreboot on x86 architecture.
+
+## State of x86_64 support
+At the moment there's no single board that supports x86_64 or to be exact
+`ARCH_RAMSTAGE_X86_64` and `ARCH_ROMSTAGE_X86_64`.
+
+In order to add support for x86_64 the following assumptions are made:
+* The CPU supports long mode
+* All memory returned by malloc must be below 4GiB in physical memory
+* All code that is to be run must be below 4GiB in physical memory
+* The high dword of pointers is always zero
+* The reference implementation is qemu
+* The CPU supports 1GiB hugepages
+
+## Assuptions for ARCH_ROMSTAGE_X86_64 reference implementation
+* 0-4GiB are identity mapped using 1GiB huge-pages
+* Memory above 4GiB isn't accessible
+* pagetables reside in _pagetables
+* Romstage must install new pagetables in CBMEM after RAMINIT
+
+## Assuptions for ARCH_RAMSTAGE_X86_64 reference implementation
+* Romstage installed pagetables according to memory layout
+* Memory above 4GiB is accessible
+
+## Steps to add basic support for x86_64
+* Add x86_64 toolchain support - *DONE*
+* Fix compilation errors - *DONE*
+* Fix linker errors - *TODO*
+* Add x86_64 rmodule support - *ONGERRIT*
+* Add x86_64 exception handlers - *TODO*
+* Setup page tables for long mode - *TODO*
+* Add assembly code for long mode - *TODO*
+* Add assembly code to return to protected mode - *TODO*
+* Implement reference code for mainboard `emulation/qemu-q35` - *TODO*
+
+## Porting other boards
+* Fix compilation errors
+* Test how well CAR works with x86_64 and paging
+* Improve mode switches
+* Test libgfxinit / VGA Option ROMs / FSP

Documentation/cbfs.txt

@@ -174,7 +174,7 @@ with
 regards to the erase block sizes on the ROM - allowing one to replace a
 component at runtime without disturbing the others.
 
-'offset' is the offset of the the first CBFS component (from the start of
+'offset' is the offset of the first CBFS component (from the start of
 the ROM).  This is to allow for arbitrary space to be left at the beginning
 of the ROM for things like embedded controller firmware.