.gitmodules

@@ -26,3 +26,6 @@
 	url = https://github.com/coreboot/fsp.git
 	update = none
 	ignore = dirty
+[submodule "opensbi"]
+	path = 3rdparty/opensbi
+	url = https://github.com/coreboot/opensbi.git

CHANGELOG.md

@@ -12,6 +12,17 @@ official [coreboot repository](https://review.coreboot.org/cgit/coreboot.git)
 Please use [pce-fw-builder](https://github.com/pcengines/pce-fw-builder)
 
 ## [Unreleased]
+## [v4.9.0.5] - 2019-05-08
+### Changed
+- rebased with official coreboot repository commit fe80bf2
+
+### Fixed
+- MP table creation: fixed SDHCI, xHCI interrupt entries
+- redundant SVI2 information string in sign-of-life
+
+### Added
+- MP table entries for PCIe bridges, endpoints and IOMMU
+
 ## [v4.9.0.4] - 2019-04-03
 ### Changed
 - rebased with official coreboot repository commit 28def8b
@@ -292,7 +303,8 @@ redundant code which was similar for APU2/3/5 boards.
 - turn off D4 and D5 leds on boot
 - enable power on after power failure
 
-[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.9.0.4...develop
+[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.9.0.5...develop
+[v4.9.0.5]: https://github.com/pcengines/coreboot/compare/v4.9.0.4...v4.9.0.5
 [v4.9.0.4]: https://github.com/pcengines/coreboot/compare/v4.9.0.3...v4.9.0.4
 [v4.9.0.3]: https://github.com/pcengines/coreboot/compare/v4.9.0.2...v4.9.0.3
 [v4.9.0.2]: https://github.com/pcengines/coreboot/compare/v4.9.0.1...v4.9.0.2

Documentation/Intel/index.html

@@ -29,7 +29,6 @@ <h2>x86 coreboot Development</h2>
   </li>
   <li><a target="_blank" href="SoC/soc.html">SoC</a> support</li>
   <li><a target="_blank" href="Board/board.html">Board</a> support</li>
-  <li><a target="_blank" href="vboot.html">Verified Boot (vboot)</a> support</li>
 </ul>