Showing 1,222 changed files with 39,298 additions and 10,526 deletions.
diff --git a/.clang-format b/.clang-format
@@ -7,7 +7,7 @@ AllowShortIfStatementsOnASingleLine:		false
 IndentCaseLabels:				false
 SortIncludes:					false
 ContinuationIndentWidth:			8
-ColumnLimit:					0
+ColumnLimit:					96
 AlwaysBreakBeforeMultilineStrings:		true
 AllowShortLoopsOnASingleLine:			false
 AllowShortFunctionsOnASingleLine:		false

diff --git a/.gitmodules b/.gitmodules
@@ -29,3 +29,8 @@
 [submodule "opensbi"]
 	path = 3rdparty/opensbi
 	url = https://github.com/coreboot/opensbi.git
+[submodule "intel-microcode"]
+	path = 3rdparty/intel-microcode
+	url = https://github.com/coreboot/intel-microcode.git
+	update = none
+	ignore = dirty
diff --git a/3rdparty/blobs b/3rdparty/blobs
diff --git a/3rdparty/fsp b/3rdparty/fsp
diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -12,6 +12,17 @@ official [coreboot repository](https://review.coreboot.org/cgit/coreboot.git)
 Please use [pce-fw-builder](https://github.com/pcengines/pce-fw-builder)
 
 ## [Unreleased]
+## [v4.9.0.7] - 2019-07-09
+### Changed
+- [updated SeaBIOS to rel-1.12.1.3](https://github.com/pcengines/seabios/blob/apu_support/CHANGELOG.md#rel-11213---2019-07-05)
+- [updated sortbootorder to v4.6.15](https://github.com/pcengines/sortbootorder/blob/master/CHANGELOG.md#v4615---2019-07-05)
+- disabled IPv6 in iPXE that often caused the dhcp/autoboot command to time out
+- removed incorrectly assigned clock request mappings
+- rebased with official coreboot repository commit c32ccb7
+
+### Added
+- [prepared integration of tianocore payload allowing to boot UEFI aware systems](https://github.com/pcengines/apu2-documentation/blob/master/docs/tianocore_build.md)
+
 ## [v4.9.0.6] - 2019-06-08
 ### Changed
 - [updated SeaBIOS to rel-1.12.1.2](https://github.com/pcengines/seabios/blob/apu_support/CHANGELOG.md#rel-11212---2019-06-04)
@@ -315,7 +326,8 @@ redundant code which was similar for APU2/3/5 boards.
 - turn off D4 and D5 leds on boot
 - enable power on after power failure
 
-[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.9.0.6...develop
+[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.9.0.7...develop
+[v4.9.0.7]: https://github.com/pcengines/coreboot/compare/v4.9.0.6...v4.9.0.7
 [v4.9.0.6]: https://github.com/pcengines/coreboot/compare/v4.9.0.5...v4.9.0.6
 [v4.9.0.5]: https://github.com/pcengines/coreboot/compare/v4.9.0.4...v4.9.0.5
 [v4.9.0.4]: https://github.com/pcengines/coreboot/compare/v4.9.0.3...v4.9.0.4

diff --git a/Documentation/arch/riscv/index.md b/Documentation/arch/riscv/index.md
@@ -15,7 +15,7 @@ Payloads run from the ramstage are started in S mode, and trap delegation
 will have been done. These payloads rely on the SBI and can not replace it.
 
 ## Stage handoff protocol
-On entry to a stage or payload,
+On entry to a stage or payload (including SELF payloads),
 * all harts are running.
 * A0 is the hart ID.
 * A1 is the pointer to the Flattened Device Tree (FDT).

diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md
@@ -2,6 +2,8 @@
 
 This section contains documentation about coreboot on x86 architecture.
 
+* [x86 PAE support](pae.md)
+
 ## State of x86_64 support
 At the moment there's no single board that supports x86_64 or to be exact
 `ARCH_RAMSTAGE_X86_64` and `ARCH_ROMSTAGE_X86_64`.

diff --git a/Documentation/arch/x86/pae.md b/Documentation/arch/x86/pae.md
@@ -0,0 +1,15 @@
+# x86_32 PAE documentation
+
+Due to missing x86_64 support it's required to use PAE enabled x86_32 code.
+The corresponding functions can be found in ``src/cpu/x86/pae/``.
+
+## Memory clearing helper functions
+
+To clear all DRAM on request of the
+[Security API](../../security/memory_clearing.md), a helper function can be used
+called `memset_pae`.
+The function has additional requirements in contrast to `memset`, and has more
+overhead as it uses virtual memory to access memory above 4GiB.
+Memory is cleared in 2MiB chunks, which might take a while.
+
+Make sure to enable caches through MTRRs, otherwise `memset_pae` will be slow!
diff --git a/Documentation/drivers/index.md b/Documentation/drivers/index.md
@@ -0,0 +1,7 @@
+# Platform indenpendend drivers documentation
+
+The drivers can be found in `src/drivers`. They are intended for onboard
+and plugin devices, significantly reducing integration complexity and
+they allow to easily reuse existing code accross platforms.
+
+* [IPMI KCS](ipmi_kcs.md)
diff --git a/Documentation/drivers/ipmi_kcs.md b/Documentation/drivers/ipmi_kcs.md
@@ -0,0 +1,47 @@
+# IPMI KCS driver
+
+The driver can be found in `src/drivers/ipmi/`. It works with BMC that provide
+a KCS I/O interface as specified in the [IPMI] standard.
+
+The driver detects the IPMI version, reserves the I/O space in coreboot's
+resource allocator and writes the required ACPI and SMBIOS tables.
+
+## For developers
+
+To use the driver, select the `IPMI_KCS` Kconfig and add the following PNP
+device under the LPC bridge device (in example for the KCS at 0xca2):
+
+```
+ chip drivers/ipmi
+   device pnp ca2.0 on end         # IPMI KCS
+ end
+```
+
+**Note:** The I/O base address needs to be aligned to 2.
+
+The following registers can be set:
+
+* `have_nv_storage`
+  * Boolean
+  * If true `nv_storage_device_address` will be added to SMBIOS type 38.
+* `nv_storage_device_address`
+  * Integer
+  * The NV storage address as defined in SMBIOS spec for type 38.
+* `bmc_i2c_address`
+  * Integer
+  * The i2c address of the BMC. zero if not applicable.
+* `have_apic`
+  * Boolean
+  * If true the `apic_interrupt` will be added to SPMI table.
+* `apic_interrupt`
+  * Integer
+  * The APIC interrupt used to notify about a change on the KCS.
+* `have_gpe`
+  * Boolean
+  * If true the `gpe_interrupt` will be added to SPMI table.
+* `gpe_interrupt`
+  * Integer
+  * The bit in GPE (SCI) used to notify about a change on the KCS.
+
+
+[IPMI]: https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf
diff --git a/Documentation/getting_started/kconfig.md b/Documentation/getting_started/kconfig.md
@@ -1165,8 +1165,6 @@ saved .config file. As always, a 'select' statement overrides any specified
 - coreboot has added the glob operator '*' for the 'source' keyword.
 - coreboot’s Kconfig always defines variables except for strings. In other
   Kconfig implementations, bools set to false/0/no are not defined.
-- IS_ENABLED() is ‘false’ for undefined variables and ‘0’ variables. In Linux
-  (where the macro comes from) it’s ‘true’ as soon as the variable is defined.
 - coreboot’s version of Kconfig adds the KCONFIG_STRICT environment variable to
   error out if there are any issues in the Kconfig files.  In the Linux kernel,
   Kconfig will generate a warning, but will still output an updated .config or

diff --git a/Documentation/gfx/display-panel.md b/Documentation/gfx/display-panel.md
@@ -0,0 +1,64 @@
+Display Panel Specifics
+=======================
+
+Timing Parameters
+-----------------
+
+From the binary file `edid` in the sys filesystem on Linux, the panel can be
+identified. The exact path may differ slightly. Here is an example:
+
+```sh
+$ strings /sys/devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/edid
+@0 5
+LG Display
+LP140WF3-SPD1
+```
+
+To figure out the timing parameters, refer to the [Intel Programmer's Reference
+Manuals](https://01.org/linuxgraphics/documentation/hardware-specification-prms)
+and try to find the datasheet of the panel using the information from `edid`.
+In the example above, you would search for `LP140WF3-SPD1`. Find a table listing
+the power sequence timing parameters, which are usually named T[N] and also
+referenced in Intel's respective registers listing. You need the values for
+`PP_ON_DELAYS`, `PP_OFF_DELAYS` and `PP_DIVISOR` for your `devicetree.cb`:
+
+```eval_rst
++-----------------------------+---------------------------------------+-----+
+| Intel docs                  | devicetree.cb                         | eDP |
++-----------------------------+---------------------------------------+-----+
+| Power up delay              | `gpu_panel_power_up_delay`            | T3  |
++-----------------------------+---------------------------------------+-----+
+| Power on to backlight on    | `gpu_panel_power_backlight_on_delay`  | T7  |
++-----------------------------+---------------------------------------+-----+
+| Power Down delay            | `gpu_panel_power_down_delay`          | T10 |
++-----------------------------+---------------------------------------+-----+
+| Backlight off to power down | `gpu_panel_power_backlight_off_delay` | T9  |
++-----------------------------+---------------------------------------+-----+
+| Power Cycle Delay           | `gpu_panel_power_cycle_delay`         | T12 |
++-----------------------------+---------------------------------------+-----+
+```
+
+Intel GPU Tools and VBT
+-----------------------
+
+The Intel GPU tools are in a package called either `intel-gpu-tools` or
+`igt-gpu-tools` in most distributions of Linux-based operating systems.
+In the coreboot `util/` directory, you can find `intelvbttool`.
+
+From a running system, you can dump the register values directly:
+```sh
+$ intel_reg dump --all | grep PCH_PP
+                      PCH_PP_STATUS (0x000c7200): 0x80000008
+                     PCH_PP_CONTROL (0x000c7204): 0x00000007
+                   PCH_PP_ON_DELAYS (0x000c7208): 0x07d00001
+                  PCH_PP_OFF_DELAYS (0x000c720c): 0x01f40001
+                     PCH_PP_DIVISOR (0x000c7210): 0x0004af06
+```
+
+You can obtain the timing values from a VBT (Video BIOS Table), which you can
+dump from a vendor UEFI image:
+```sh
+$ intel_vbt_decode data.vbt | grep T3
+                Power Sequence: T3 2000 T7 10 T9 2000 T10 500 T12 5000
+                T3 optimization: no
+```
diff --git a/Documentation/gfx/libgfxinit.md b/Documentation/gfx/libgfxinit.md
@@ -55,6 +55,9 @@ follows:
 GMA: Per Board Configuration
 ----------------------------
 
+In order to set up the display panel, see the
+[display panel-specific documentation](/gfx/display-panel.md).
+
 There are a few Kconfig symbols to consider. To indicate that a
 board can initialize graphics through *libgfxinit*:
 

diff --git a/Documentation/index.md b/Documentation/index.md
@@ -173,7 +173,9 @@ Contents:
 * [Dealing with Untrusted Input in SMM](technotes/2017-02-dealing-with-untrusted-input-in-smm.md)
 * [GPIO toggling in ACPI AML](acpi/gpio.md)
 * [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md)
+* [Display panel-specific documentation](gfx/display-panel.md)
 * [Architecture-specific documentation](arch/index.md)
+* [Platform independend drivers documentation](drivers/index.md)
 * [Northbridge-specific documentation](northbridge/index.md)
 * [System on Chip-specific documentation](soc/index.md)
 * [Mainboard-specific documentation](mainboard/index.md)

diff --git a/Documentation/mainboard/asus/p8z77-m_pro.jpg b/Documentation/mainboard/asus/p8z77-m_pro.jpg