Showing 1,185 changed files with 15,400 additions and 10,399 deletions.
diff --git a/3rdparty/blobs b/3rdparty/blobs
diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit
diff --git a/3rdparty/libhwbase b/3rdparty/libhwbase
diff --git a/3rdparty/opensbi b/3rdparty/opensbi
diff --git a/3rdparty/vboot b/3rdparty/vboot
diff --git a/AUTHORS b/AUTHORS
@@ -0,0 +1,14 @@
+# This is the list of coreboot authors for copyright purposes.
+#
+# This does not necessarily list everyone who has contributed code, since in
+# some cases, their employer may be the copyright holder.  To see the full list
+# of contributors, see the revision history in source control.
+# git log --pretty=format:%an | sort | uniq
+#
+
+Alexander Couzens
+
+
+
+# Directories transferred
+src/acpi
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -12,6 +12,11 @@ official [coreboot repository](https://review.coreboot.org/cgit/coreboot.git)
 Please use [pce-fw-builder](https://github.com/pcengines/pce-fw-builder)
 
 ## [Unreleased]
+## [v4.10.0.0] - 2019-08-09
+### Changed
+- [ACPI support for GPIOs](https://github.com/pcengines/apu2-documentation/blob/master/docs/gpios.md)
+- rebased with official coreboot repository commit 2a20d13
+
 ## [v4.9.0.7] - 2019-07-09
 ### Changed
 - [updated SeaBIOS to rel-1.12.1.3](https://github.com/pcengines/seabios/blob/apu_support/CHANGELOG.md#rel-11213---2019-07-05)
@@ -326,7 +331,8 @@ redundant code which was similar for APU2/3/5 boards.
 - turn off D4 and D5 leds on boot
 - enable power on after power failure
 
-[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.9.0.7...develop
+[Unreleased]: https://github.com/pcengines/coreboot/compare/v4.10.0.0...develop
+[v4.10.0.0]: https://github.com/pcengines/coreboot/compare/v4.9.0.7...v4.10.0.0
 [v4.9.0.7]: https://github.com/pcengines/coreboot/compare/v4.9.0.6...v4.9.0.7
 [v4.9.0.6]: https://github.com/pcengines/coreboot/compare/v4.9.0.5...v4.9.0.6
 [v4.9.0.5]: https://github.com/pcengines/coreboot/compare/v4.9.0.4...v4.9.0.5

diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html
@@ -148,7 +148,6 @@ <h2><a name="Bootblock">Bootblock</a></h2>
   <li>Edit the src/soc/&lt;Vendor&gt;/&lt;Chip Family&gt;/memmap.c file
     <ol type="A">
       <li>Add the fsp/memmap.h include file</li>
-      <li>Add the mmap_region_granularity routine</li>
     </ol>
   </li>
   <li>Add the necessary .h files to define the necessary values and structures</li>

diff --git a/Documentation/arch/riscv/index.md b/Documentation/arch/riscv/index.md
@@ -23,8 +23,20 @@ On entry to a stage or payload (including SELF payloads),
 ## Additional payload handoff requirements
 The location of cbmem should be placed in a node in the FDT.
 
+## OpenSBI
+In case the payload doesn't install it's own SBI, like the [RISCV-PK] does,
+[OpenSBI] can be used instead.
+It's loaded into RAM after coreboot has finished loading the payload.
+coreboot then will jump to OpenSBI providing a pointer to the real payload,
+which OpenSBI will jump to once the SBI is installed.
+
+Besides providing SBI it also sets protected memory regions and provides
+a platform independent console.
+
+The OpenSBI code is always run in M mode.
+
 ## Trap delegation
-Traps are delegated in the ramstage.
+Traps are delegated to the payload.
 
 ## SMP within a stage
 At the beginning of each stage, all harts save 0 are spinning in a loop on
@@ -44,3 +56,6 @@ The hart blocks until fn is non-null, and then calls it.  If fn returns, we
 will panic if possible, but behavior is largely undefined.
 
 Only hart 0 runs through most of the code in each stage.
+
+[RISCV-PK]: https://github.com/riscv/riscv-pk
+[OpenSBI]: https://github.com/riscv/opensbi
diff --git a/Documentation/community/code_of_conduct.md b/Documentation/community/code_of_conduct.md
@@ -22,19 +22,30 @@ Refrain from insulting anyone or the group they belong to. Remember that
 people might be sensitive to other things than you are.
 
 Most of our community members are not native English speakers, thus
-misunderstandings can (and do) happen. Always assume that others are
-friendly and may have picked less-than-stellar wording by accident.
+misunderstandings can (and do) happen. Assume that others are friendly
+and may have picked less-than-stellar wording by accident as long as
+you possibly can.
 
-If you have a grievance due to conduct in this community, we want to hear
-about it so we can handle the situation. Please contact our arbitration
-team directly: They will listen to you and react in a timely fashion.
+## Reporting Issues
+
+If you have a grievance due to conduct in this community, we're sorry
+that you have had a bad experience, and we want to hear about it so
+we can resolve the situation.
+
+Please contact members of our arbitration team (listed below) promptly
+and directly, in person (if available) or by email: They will listen
+to you and react in a timely fashion.
+
+If you feel uncomfortable, please don't wait it out, ask for help,
+so we can work on setting things right.
 
 For transparency there is no alias or private mailing list address for
 you to reach out to, since we want to make sure that you know who will
-(and who won't) read your message.
+and who won't read your message.
 
-However since people might be on travel or otherwise be unavailable at
-times, consider reaching out to multiple persons.
+However since people might be on travel or otherwise be unavailable
+at times, please reach out to multiple persons at once, especially
+when using email.
 
 The team will treat your messages confidential as far as the law permits.
 For the purpose of knowing what law applies, the list provides the usual
@@ -73,15 +84,10 @@ immediately.
 If a community member engages in unacceptable behavior, the community
 organizers may take any action they deem appropriate, up to and including
 a temporary ban or permanent expulsion from the community without warning
-(and without refund in the case of a paid event). Community organizers
-can be part of the arbitration team, or organizers of events and online
-communities.
-
-## If You Witness or Are Subject to Unacceptable Behavior
-
-If you are subject to or witness unacceptable behavior, or have any other
-concerns, please notify someone from the arbitration team immediately.
+(and without refund in the case of a paid event).
 
+Community organizers can be members of the arbitration team, or organizers
+of events and online communities.
 
 ## Addressing Grievances
 
@@ -102,7 +108,7 @@ Our arbitration team consists of the following people
 * Stefan Reinauer <stefan.reinauer@coreboot.org> (USA)
 * Patrick Georgi <patrick@coreboot.org> (Germany)
 * Ronald Minnich <rminnich@coreboot.org> (USA)
-* Marc Jones <mjones@coreboot.org> (USA)
+* Martin Roth <martin@coreboot.org> (USA)
 
 ## License and attribution
 

diff --git a/Documentation/distributions.md b/Documentation/distributions.md
@@ -58,16 +58,6 @@ fixes not found in the stock firmware, and offer much broader OS compatibility
 microcode, as well as firmware updates for the device's embedded controller
 (EC). This firmware "takes the training wheels off" your ChromeOS device :)
 
-### John Lewis
-
-[John Lewis](https://johnlewis.ie/custom-chromebook-firmware) also provides
-replacement firmware for ChromeOS devices, for the express purpose of
-running Linux on Chromebooks. John Lewis' firmware supports a much smaller
-set of devices, and uses SeaBIOS as the payload to support Legacy BIOS booting.
-His firmware images are significantly older, and not actively maintained or
-supported, but worth a look if you need Legacy Boot support and is not
-available via Mr Chromebox's firmware.
-
 ### Heads
 
 [Heads](http://osresearch.net) is an open source custom firmware and OS

diff --git a/Documentation/drivers/index.md b/Documentation/drivers/index.md
@@ -1,4 +1,4 @@
-# Platform indenpendend drivers documentation
+# Platform independent drivers documentation
 
 The drivers can be found in `src/drivers`. They are intended for onboard
 and plugin devices, significantly reducing integration complexity and

diff --git a/Documentation/lessons/lesson1.md b/Documentation/lessons/lesson1.md
@@ -1,5 +1,5 @@
-coreboot lesson 1 - Starting from scratch
-=========================================
+coreboot Lesson 1: Starting from scratch
+========================================
 
 From a fresh Ubuntu 16.04 or 18.04 install, here are all the steps required for
 a very basic build:

diff --git a/Documentation/mainboard/emulation/qemu-aarch64.md b/Documentation/mainboard/emulation/qemu-aarch64.md
@@ -0,0 +1,47 @@
+# QEMU AArch64 emulator
+This page discribes how to build and run coreboot for QEMU/AArch64.
+You can use LinuxBoot via `make menuconfig` or an arbitrary FIT image
+as a payload for QEMU/AArch64.
+
+## Running coreboot in QEMU
+```bash
+qemu-system-aarch64 -bios ./build/coreboot.rom \
+    -M virt,secure=on,virtualization=on -cpu cortex-a53 \
+    -nographic -m 8912M
+```
+
+- The default CPU in QEMU for AArch64 is a cortex-a15 which is 32-bit
+ARM CPU. You need to specify 64-bit ARM CPU via `-cpu cortex-a53`.
+- The default privilege level in QEMU for AArch64 is EL1 that we can't
+have the right to access EL3/EL2 registers. You need to enable EL3/EL2
+via `-machine secure=on,virtualization=on`.
+- You need to specify the size of memory more than 544 MiB because 512
+MiB is reserved for the kernel.
+
+## Building coreboot with an arbitrary FIT payload
+There are 3 steps to make coreboot.rom for QEMU/AArch64. If you select
+LinuxBoot, step 2 and 3 have done by LinuxBoot.
+1. Get a DTB (Device Tree Blob)
+2. Build a FIT image with a DTB
+3. Add a FIT image to coreboot.rom
+
+### 1. Get a DTB
+You can get the DTB from QEMU with the following command.
+```
+$ qemu-system-aarch64 \
+    -M virt,dumpdtb=virt.dtb,secure=on,virtualization=on \
+    -cpu cortex-a53 -nographic -m 2048M
+```
+
+### 2. Build a FIT image with a DTB
+You need to write an image source file that has an `.its` extension to
+configure kernels, ramdisks, and DTBs.
+See [Flattened uImage Tree documentation](../../lib/payloads/fit.md) for more details.
+
+### 3. Add a FIT image to coreboot.rom
+You can use cbfstool to add the payload you created in step 2 to
+the coreboot.rom.
+```
+$ ./build/cbfstool ./build/coreboot.rom add -f <path-to-a-payload>/uImage \
+    -n fallback/payload -t fit -c lzma
+```
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
@@ -24,6 +24,7 @@ The boards in this section are not real mainboards, but emulators.
 
 - [Spike RISC-V emulator](emulation/spike-riscv.md)
 - [Qemu RISC-V emulator](emulation/qemu-riscv.md)
+- [Qemu AArch64 emulator](emulation/qemu-aarch64.md)
 
 ## Intel
 
@@ -69,6 +70,10 @@ The boards in this section are not real mainboards, but emulators.
 - [T4xx common](lenovo/t4xx_series.md)
 - [X2xx common](lenovo/x2xx_series.md)
 
+## Portwell
+
+- [PQ7-M107](portwell/pq7-m107.md)
+
 ### Sandy Bridge series
 
 - [T420](lenovo/t420.md)

diff --git a/Documentation/mainboard/portwell/pq7-m107.md b/Documentation/mainboard/portwell/pq7-m107.md
@@ -0,0 +1,79 @@
+# Portwell PQ7-M107
+
+This page describes how to run coreboot on the [Portwell PQ7-M107].
+
+PQ7-M107 are assembled with different onboard memory modules:
+	Rev 1.0	Onboard Samsung K4B8G1646D-MYKO memory
+	Rev 1.1	and 1.2 Onboard Micron MT41K512M16HA-125A memory
+
+Use 'make menuconfig' to configure `onboard memory manufacture` in Mainboard
+menu.
+
+## Required blobs
+
+This board currently requires:
+fsp blob	3rdparty/fsp/BraswellFspBinPkg/FspBin/BSWFSP.fd
+Microcode	Intel Braswell cpuid 1046C4 version 410
+		(Used pre-built binary retrieved from Intel site)
+
+## Flashing coreboot
+
+### Internal programming
+
+The main SPI flash can be accessed using [flashrom].
+
+### External programming
+
+The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip.
+This chip is located on the top middle side of the board. It's located
+between SoC and Q7 connector. Use clip (or solder wires) to program
+the chip.
+Specifically, it's a Winbond W25Q64FW (1.8V), whose datasheet can be found
+[here][W25Q64FW].
+
+## Known issues
+
+- The PQ7 module contains Q7 connector only. Depending on the carrier
+serial/video/pcie ports might be available.
+
+## Untested
+
+- hardware monitor
+- SDIO
+- Full Embedded Controller support
+
+## Working (using carrier)
+
+- USB
+- Gigabit Ethernet
+- integrated graphics
+- flashrom
+- external graphics
+- PCIe
+- eMMC
+- SATA
+- serial port
+- SMbus
+- HDA (codec on carrier)
+- initialization with FSP MR2
+- SeaBIOS payload (version rel-1.11.0-44-g7961917)
+- Embedded Linux (Ubuntu 4.15+)
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| SoC              | Intel Atom Processor N3710                       |
++------------------+--------------------------------------------------+
+| CPU              | Intel Braswell (N3710)                           |
++------------------+--------------------------------------------------+
+| Super I/O, EC    | ITE8256                                          |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel Management Engine                          |
++------------------+--------------------------------------------------+
+```
+
+[Portwell PQ7-M107]: http://portwell.com/products/detail.php?CUSTCHAR1=PQ7-M107
+[W25Q64FW]: https://www.winbond.com/resource-files/w25q64fw%20revn%2005182017%20sfdp.pdf
+[flashrom]: https://flashrom.org/Flashrom
+[Board manual]: www.portwell.com/pdf/embedded/PQ7-M107.pdf
diff --git a/Documentation/mainboard/sifive/hifive-unleashed.md b/Documentation/mainboard/sifive/hifive-unleashed.md
@@ -17,7 +17,6 @@ The following things are still missing from this coreboot port:
 - Provide serial number to payload (e.g. in device tree)
 - Implement instruction emulation
 - Support for booting Linux on RISC-V
-- Add support to run OpenSBI payload in m-mode
 - SMP support in trap handler
 
 ## Configuration

diff --git a/Documentation/releases/checklist.md b/Documentation/releases/checklist.md
@@ -68,6 +68,7 @@ be more frequent than was needed, so we scaled it back to twice a year.
 - [ ] Announce that the release tag is done on IRC
 - [ ] Update release notes with actual commit id, push to repo
 - [ ] Upload release files to web server
+- [ ] Upload crossgcc sources to web server
 - [ ] Update download page to point to files, push to repo
 - [ ] Write and publish blog post with release notes.
 - [ ] Update the topic in the irc channel that the release is done.
@@ -195,6 +196,22 @@ The downloads page is the official place to download the releases from, and it n
 
 Here is an example commit to change it: https://review.coreboot.org/#/c/19515/
 
+## Upload crossgcc sources
+Sometimes the source files for older revisions of
+crossgcc disappear. To deal with that we maintain a mirror at
+https://www.coreboot.org/releases/crossgcc-sources/ where we host the
+sources used by the crossgcc scripts that are part of coreboot releases.
+
+Run
+
+````
+% util/crossgcc/buildgcc -u
+````
+
+This will output the set of URLs that the script uses to download the
+sources. Download them yourself and copy them into the crossgcc-sources
+directory on the server.
+
 ## After the release is complete
 Post the release notes on https://blogs.coreboot.org