161 changes: 0 additions & 161 deletions src/drivers/intel/fsp1_1/stack.c
View file

This file was deleted.

44 changes: 44 additions & 0 deletions src/drivers/intel/fsp1_1/temp_ram_exit.c
View file
@@ -0,0 +1,44 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/

#include <console/console.h>
#include <fsp/util.h>

asmlinkage void chipset_teardown_car_main(void)
{
FSP_INFO_HEADER *fih;
uint32_t status;
FSP_TEMP_RAM_EXIT temp_ram_exit;
struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin");

if (prog_locate(&fsp)) {
die("Unable to locate fsp.bin\n");
} else {
/* This leaks a mapping which this code assumes is benign as
* the flash is memory mapped CPU's address space. */

/* FIXME: the implementation of find_fsp is utter garbage
as it casts error values to FSP_INFO_HEADER pointers.
Checking for return values can only be done sanely once
that is fixed. */
fih = find_fsp((uintptr_t)rdev_mmap_full(prog_rdev(&fsp)));
}

temp_ram_exit = (FSP_TEMP_RAM_EXIT)(fih->TempRamExitEntryOffset +
fih->ImageBase);
printk(BIOS_DEBUG, "Calling TempRamExit: %p\n", temp_ram_exit);
status = temp_ram_exit(NULL);

if (status != FSP_SUCCESS) {
printk(BIOS_CRIT, "TempRamExit returned 0x%08x\n", status);
die("TempRamExit returned an error!\n");
}
}
6 changes: 3 additions & 3 deletions src/drivers/intel/fsp2_0/hand_off_block.c
View file
Expand Up @@ -237,9 +237,9 @@ static void display_fsp_version_info_hob(const void *hob, size_t size)

/* Don't show ingredient name and version if its all 0xFF */
if (fvi[index].Version.MajorVersion == 0xFF &&
fvi[index].Version.MajorVersion == 0xFF &&
fvi[index].Version.MajorVersion == 0xFF &&
fvi[index].Version.MajorVersion == 0xFF &&
fvi[index].Version.MinorVersion == 0xFF &&
fvi[index].Version.Revision == 0xFF &&
fvi[index].Version.BuildNumber == 0xFF &&
fvi[index].VersionStringIndex == 0) {
str_ptr = (char *)((uintptr_t)str_ptr + cnt +
sizeof(uint8_t));
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/intel/fsp2_0/include/fsp/info_header.h
View file
Expand Up @@ -44,14 +44,12 @@ struct fsp_header {

enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob);

#if ENV_RAMSTAGE
/*
* This is a FSP_INFO_HEADER that came from fsps.bin blob. It contains
* both SiliconInit and Notify APIs. When SiliconInit is loaded the
* header is saved so that when Notify is called we do not have to start
* header parsing again.
*/
extern struct fsp_header fsps_hdr;
#endif

#endif /* _FSP2_0_INFO_HEADER_H_ */
9 changes: 6 additions & 3 deletions src/drivers/intel/fsp2_0/memory_init.c
View file
Expand Up @@ -277,7 +277,8 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake,
upd = (FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base);

if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE)
die("Invalid FSPM signature!\n");
die_with_post_code(POST_INVALID_VENDOR_BINARY,
"Invalid FSPM signature!\n");

/* Copy the default values from the UPD area */
memcpy(&fspm_upd, upd, sizeof(fspm_upd));
Expand All @@ -290,7 +291,8 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake,
/* Fill common settings on behalf of chipset. */
if (fsp_fill_common_arch_params(arch_upd, s3wake, fsp_version,
memmap) != CB_SUCCESS)
die("FSPM_ARCH_UPD not found!\n");
die_with_post_code(POST_INVALID_VENDOR_BINARY,
"FSPM_ARCH_UPD not found!\n");

/* Give SoC and mainboard a chance to update the UPD */
platform_fsp_memory_init_params_cb(&fspm_upd, fsp_version);
Expand All @@ -314,7 +316,8 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake,
fsp_handle_reset(status);
if (status != FSP_SUCCESS) {
printk(BIOS_CRIT, "FspMemoryInit returned 0x%08x\n", status);
die("FspMemoryInit returned an error!\n");
die_with_post_code(POST_RAM_FAILURE,
"FspMemoryInit returned an error!\n");
}

do_fsp_post_memory_init(s3wake, fsp_version);
Expand Down
9 changes: 9 additions & 0 deletions src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
View file
Expand Up @@ -45,6 +45,9 @@ static efi_return_status_t mp_get_processor_info(const
efi_uintn_t processor_number,
efi_processor_information *processor_info_buffer)
{
if (cpu_index() < 0)
return FSP_DEVICE_ERROR;

if (processor_info_buffer == NULL)
return FSP_INVALID_PARAMETER;

Expand All @@ -68,6 +71,9 @@ static efi_return_status_t mp_startup_all_aps(const
efi_ap_procedure procedure, efi_boolean_t ignored3,
efi_uintn_t timeout_usec, void *argument)
{
if (cpu_index() < 0)
return FSP_DEVICE_ERROR;

if (procedure == NULL)
return FSP_INVALID_PARAMETER;

Expand All @@ -85,6 +91,9 @@ static efi_return_status_t mp_startup_this_ap(const
efi_ap_procedure procedure, efi_uintn_t processor_number,
efi_uintn_t timeout_usec, void *argument)
{
if (cpu_index() < 0)
return FSP_DEVICE_ERROR;

if (processor_number > get_cpu_count())
return FSP_NOT_FOUND;

Expand Down
17 changes: 15 additions & 2 deletions src/drivers/intel/fsp2_0/silicon_init.c
View file
Expand Up @@ -18,6 +18,7 @@
#include <fsp/api.h>
#include <fsp/util.h>
#include <program_loading.h>
#include <soc/intel/common/vbt.h>
#include <stage_cache.h>
#include <string.h>
#include <timestamp.h>
Expand All @@ -29,11 +30,13 @@ static void do_silicon_init(struct fsp_header *hdr)
FSPS_UPD *upd, *supd;
fsp_silicon_init_fn silicon_init;
uint32_t status;
uint8_t postcode;

supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base);

if (supd->FspUpdHeader.Signature != FSPS_UPD_SIGNATURE)
die("Invalid FSPS signature\n");
die_with_post_code(POST_INVALID_VENDOR_BINARY,
"Invalid FSPS signature\n");

upd = xmalloc(sizeof(FSPS_UPD));

Expand All @@ -58,8 +61,18 @@ static void do_silicon_init(struct fsp_header *hdr)
/* Handle any errors returned by FspSiliconInit */
fsp_handle_reset(status);
if (status != FSP_SUCCESS) {
if (vbt_get()) {
/* Attempted to initialize graphics. Assume failure
* is related to a video failure.
*/
postcode = POST_VIDEO_FAILURE;
} else {
/* Other silicon initialization failed */
postcode = POST_HW_INIT_FAILURE;
}
printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status);
die("FspSiliconINit returned an error!\n");
die_with_post_code(postcode,
"FspSiliconINit returned an error!\n");
}
}

Expand Down
21 changes: 9 additions & 12 deletions src/drivers/intel/gma/Kconfig
View file
Expand Up @@ -67,7 +67,7 @@ config GFX_GMA
def_bool y
depends on NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X \
|| NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE \
|| NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_HASWELL \
|| NORTHBRIDGE_INTEL_HASWELL \
|| SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE
depends on MAINBOARD_USE_LIBGFXINIT
select RAMSTAGE_LIBHWBASE
Expand All @@ -86,22 +86,19 @@ config GFX_GMA_INTERNAL_IS_LVDS

if GFX_GMA

config GFX_GMA_CPU
config GFX_GMA_DYN_CPU
def_bool y
help
Activates runtime CPU detection in libgfxinit.

config GFX_GMA_GENERATION
string
default "Broxton" if SOC_INTEL_APOLLOLAKE
default "Skylake" if SOC_INTEL_SKYLAKE
default "Broadwell" if SOC_INTEL_BROADWELL
default "Haswell" if NORTHBRIDGE_INTEL_HASWELL
default "Ivybridge" if NORTHBRIDGE_INTEL_IVYBRIDGE
default "Sandybridge" if NORTHBRIDGE_INTEL_SANDYBRIDGE
default "Ironlake" if NORTHBRIDGE_INTEL_NEHALEM
default "Haswell" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL
default "Ironlake" if NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE
default "G45" if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X

config GFX_GMA_CPU_VARIANT
string
default "ULT" if (SOC_INTEL_SKYLAKE && !SKYLAKE_SOC_PCH_H) || SOC_INTEL_BROADWELL || NORTHBRIDGE_INTEL_HASWELL
default "Normal"

config GFX_GMA_INTERNAL_PORT
string
default "DP" if GFX_GMA_INTERNAL_IS_EDP
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/spi/boot_device_rw_nommap.c
View file
Expand Up @@ -109,7 +109,7 @@ const struct spi_flash *boot_device_spi_flash(void)
return car_get_var_ptr(&sfg);
}

int boot_device_wp_region(struct region_device *rd,
int boot_device_wp_region(const struct region_device *rd,
const enum bootdev_prot_type type)
{
uint32_t ctrlr_pr;
Expand Down
4 changes: 1 addition & 3 deletions src/drivers/uart/uart8250io.c
View file
Expand Up @@ -110,7 +110,7 @@ void uart_init(int idx)
div = uart_baudrate_divisor(get_uart_baudrate(),
uart_platform_refclk(), uart_input_clock_divider());
if ((check_com2() || idx == 1) &&
!IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5))
!CONFIG(BOARD_PCENGINES_APU5))
car_set_var(port_index, 1);
else
car_set_var(port_index, idx);
Expand All @@ -134,7 +134,6 @@ void uart_tx_flush(int idx)
uart8250_tx_flush(uart_platform_base(car_get_var(port_index)));
}

#if ENV_RAMSTAGE
void uart_fill_lb(void *data)
{
struct lb_serial serial;
Expand All @@ -148,4 +147,3 @@ void uart_fill_lb(void *data)

lb_add_console(LB_TAG_CONSOLE_SERIAL8250, data);
}
#endif
2 changes: 0 additions & 2 deletions src/drivers/uart/uart8250mem.c
View file
Expand Up @@ -147,7 +147,6 @@ void uart_tx_flush(int idx)
uart8250_mem_tx_flush(base);
}

#if ENV_RAMSTAGE
void uart_fill_lb(void *data)
{
struct lb_serial serial;
Expand All @@ -166,4 +165,3 @@ void uart_fill_lb(void *data)

lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
}
#endif
3 changes: 2 additions & 1 deletion src/ec/google/wilco/Makefile.inc
View file
@@ -1,6 +1,7 @@
ifeq ($(CONFIG_EC_GOOGLE_WILCO),y)

bootblock-y += bootblock.c
bootblock-y += bootblock.c commands.c mailbox.c
verstage-y += commands.c mailbox.c
romstage-y += commands.c mailbox.c romstage.c boardid.c
ramstage-y += chip.c commands.c mailbox.c boardid.c
smm-y += commands.c mailbox.c smihandler.c boardid.c
Expand Down
45 changes: 44 additions & 1 deletion src/ec/google/wilco/commands.c
View file
Expand Up @@ -159,7 +159,7 @@ void wilco_ec_power_off(enum ec_power_off_reason reason)

int wilco_ec_radio_control(enum ec_radio radio, uint8_t state)
{
uint8_t radio_control[3] = { 0, radio, state };
uint8_t radio_control[3] = { radio, RADIO_WRITE, state };

return wilco_ec_mailbox(WILCO_EC_MSG_DEFAULT, KB_RADIO_CONTROL,
radio_control, ARRAY_SIZE(radio_control),
Expand All @@ -181,3 +181,46 @@ int wilco_ec_signed_fw(void)
CONFIG_EC_BASE_ACPI_DATA);
return !!ec_read(EC_RAM_SIGNED_FW);
}

struct err_code_entry {
uint8_t post_code;
enum ec_err_code ec_err;
};

/*
* Any post codes not listed in the post_code_err_map[] use default.
*/
static const enum ec_err_code default_ec_err = DLED_ROM;
static const struct err_code_entry post_code_err_map[] = {
{ .post_code = POST_RAM_FAILURE, .ec_err = DLED_MEMORY, },
{ .post_code = POST_VIDEO_FAILURE, .ec_err = DLED_PANEL, },
};

/* Records the most recent post code during boot */
static uint8_t wilco_ec_saved_post_code;

void wilco_ec_save_post_code(uint8_t post_code)
{
wilco_ec_saved_post_code = post_code;
}

/* Send error code to the EC based on last saved post code */
void die_notify(void)
{
size_t i;
enum ec_err_code err_code = default_ec_err;

for (i = 0; i < ARRAY_SIZE(post_code_err_map); i++) {
if (post_code_err_map[i].post_code ==
wilco_ec_saved_post_code) {
err_code = post_code_err_map[i].ec_err;
break;
}
}

printk(BIOS_EMERG, "Fatal error: post_code 0x%02x, EC err 0x%02x\n",
wilco_ec_saved_post_code, err_code);

wilco_ec_mailbox(WILCO_EC_MSG_DEFAULT, KB_ERR_CODE,
&err_code, 1, NULL, 0);
}
29 changes: 28 additions & 1 deletion src/ec/google/wilco/commands.h
View file
Expand Up @@ -50,6 +50,8 @@ enum {
KB_SLP_EN = 0x64,
/* Inform the EC about BIOS boot progress */
KB_BIOS_PROGRESS = 0xc2,
/* Inform the EC that a fatal error occurred */
KB_ERR_CODE = 0x7b,
};

enum ec_ram_addr {
Expand Down Expand Up @@ -78,14 +80,28 @@ enum ec_audio_mute {
};

enum ec_radio {
RADIO_WIFI = 0x02,
RADIO_WIFI = 0,
RADIO_WWAN,
RADIO_BT,
};

enum ec_radio_action {
RADIO_READ = 1,
RADIO_WRITE,
RADIO_TOGGLE,
};

enum ec_camera {
CAMERA_ON = 0,
CAMERA_OFF
};

enum ec_err_code {
DLED_MEMORY = 0x03,
DLED_PANEL = 0x10,
DLED_ROM = 0x19,
};

/**
* wilco_ec_radio_control() - Control wireless radios.
* @ec_radio: Wireless radio type.
Expand Down Expand Up @@ -310,4 +326,15 @@ enum ec_acpi_wake_events {
*/
int wilco_ec_signed_fw(void);

/**
* wilco_ec_save_post_code
*
* Save this post code as the most recent progress step. If the boot fails
* and calls die_notify() this post code will be used to send an error code
* to the EC indicating the failure.
*
* @post_code: Post code to save
*/
void wilco_ec_save_post_code(uint8_t post_code);

#endif /* EC_GOOGLE_WILCO_COMMANDS_H */
2 changes: 1 addition & 1 deletion src/ec/lenovo/h8/acpi/battery.asl
View file
Expand Up @@ -160,7 +160,7 @@ Method(BSTA, 4, NotSerialized)
Return (Arg1)
}

Method(BINF, 2, NotSerialized)
Method(BINF, 2, Serialized)
{
Acquire(ECLK, 0xffff)
^BPAG(Or(1, Arg1)) /* Battery 0 static information */
Expand Down
9 changes: 8 additions & 1 deletion src/include/assert.h
View file
Expand Up @@ -19,6 +19,12 @@
#include <arch/hlt.h>
#include <console/console.h>

/* TODO: Fix vendorcode headers to not define macros coreboot uses or to be more
properly isolated. */
#ifdef ASSERT
#undef ASSERT
#endif

/* GCC and CAR versions */
#define ASSERT(x) { \
if (!(x)) { \
Expand Down Expand Up @@ -50,7 +56,8 @@
* bootmode.c:42: undefined reference to `dead_code_assertion_failed_at_line_42'
*/
#define __dead_code(line) do { \
extern void dead_code_assertion_failed_at_line_##line(void); \
extern void dead_code_assertion_failed_at_line_##line(void) \
__attribute__((noreturn)); \
dead_code_assertion_failed_at_line_##line(); \
} while (0)
#define _dead_code(line) __dead_code(line)
Expand Down
2 changes: 1 addition & 1 deletion src/include/boot_device.h
View file
Expand Up @@ -65,7 +65,7 @@ int boot_device_rw_subregion(const struct region *sub,
* by the region device.
* Returns 0 on success, < 0 on error.
*/
int boot_device_wp_region(struct region_device *rd,
int boot_device_wp_region(const struct region_device *rd,
const enum bootdev_prot_type type);

/*
Expand Down
1 change: 1 addition & 0 deletions src/include/console/console.h
View file
Expand Up @@ -43,6 +43,7 @@ void post_log_clear(void);
/* this function is weak and can be overridden by a mainboard function. */
void mainboard_post(u8 value);
void __noreturn die(const char *msg);
void __noreturn die_with_post_code(uint8_t value, const char *msg);

/*
* This function is weak and can be overridden to provide additional
Expand Down
44 changes: 44 additions & 0 deletions src/include/console/post_codes.h
View file
Expand Up @@ -318,6 +318,50 @@
*/
#define POST_JUMPING_TO_PAYLOAD 0xf3

/**
* \brief Invalid or corrupt ROM
*
* Set if firmware failed to find or validate a resource that is stored in ROM.
*/
#define POST_INVALID_ROM 0xe0

/**
* \brief Invalid or corrupt CBFS
*
* Set if firmware failed to find or validate a resource that is stored in CBFS.
*/
#define POST_INVALID_CBFS 0xe1

/**
* \brief Vendor binary error
*
* Set if firmware failed to find or validate a vendor binary, or the binary
* generated a fatal error.
*/
#define POST_INVALID_VENDOR_BINARY 0xe2

/**
* \brief RAM failure
*
* Set if RAM could not be initialized. This includes RAM is missing,
* unsupported RAM configuration, or RAM failure.
*/
#define POST_RAM_FAILURE 0xe3

/**
* \brief Hardware initialization failure
*
* Set when a required hardware component was not found or is unsupported.
*/
#define POST_HW_INIT_FAILURE 0xe4

/**
* \brief Video failure
*
* Video subsystem failed to initialize.
*/
#define POST_VIDEO_FAILURE 0xe5

/**
* \brief TPM failure
*
Expand Down
4 changes: 4 additions & 0 deletions src/include/cpu/cpu.h
View file
Expand Up @@ -5,6 +5,10 @@

#if !defined(__ROMCC__)
void cpu_initialize(unsigned int cpu_index);
/* Returns default APIC id based on logical_cpu number or < 0 on failure. */
int cpu_get_apic_id(int logical_cpu);
/* Function to keep track of cpu default apic_id */
void cpu_add_map_entry(unsigned int index);
struct bus;
void initialize_cpus(struct bus *cpu_bus);
asmlinkage void secondary_cpu_init(unsigned int cpu_index);
Expand Down
3 changes: 0 additions & 3 deletions src/include/cpu/x86/mp.h
View file
Expand Up @@ -145,9 +145,6 @@ int mp_run_on_all_cpus(void (*func)(void *), void *arg, long expire_us);
*/
int mp_park_aps(void);

/* Returns APIC id for coreboot CPU number or < 0 on failure. */
int mp_get_apic_id(int logical_cpu);

/*
* SMM helpers to use with initializing CPUs.
*/
Expand Down
2 changes: 2 additions & 0 deletions src/include/device/pci_ids.h
View file
Expand Up @@ -2694,6 +2694,7 @@
#define PCI_DEVICE_ID_INTEL_SPT_H_Q170 0xa146
#define PCI_DEVICE_ID_INTEL_SPT_H_Q150 0xa147
#define PCI_DEVICE_ID_INTEL_SPT_H_B150 0xa148
#define PCI_DEVICE_ID_INTEL_KBP_H_C236 0xa149
#define PCI_DEVICE_ID_INTEL_SPT_H_C236 0xa150
#define PCI_DEVICE_ID_INTEL_SPT_H_PREMIUM 0xa14e
#define PCI_DEVICE_ID_INTEL_SPT_H_H110 0xa143
Expand Down Expand Up @@ -3081,6 +3082,7 @@
#define PCI_DEVICE_ID_INTEL_KBL_ID_Y 0x590c
#define PCI_DEVICE_ID_INTEL_KBL_ID_H 0x5910
#define PCI_DEVICE_ID_INTEL_KBL_U_R 0x5914
#define PCI_DEVICE_ID_INTEL_KBL_ID_DT_2 0x5918
#define PCI_DEVICE_ID_INTEL_KBL_ID_DT 0x591f
#define PCI_DEVICE_ID_INTEL_CNL_ID_U 0x5A04
#define PCI_DEVICE_ID_INTEL_CNL_ID_Y 0x5A02
Expand Down
26 changes: 26 additions & 0 deletions src/include/endian.h
View file
Expand Up @@ -85,6 +85,32 @@
#define setbits_8(addr, set) setbits_8(addr, 0, set)

#ifndef __ROMCC__
/* be16dec/be32dec/be64dec/le16dec/le32dec/le64dec family of functions. */
#define DEFINE_ENDIAN_DEC(endian, width) \
static inline uint##width##_t endian##width##dec(const void *p) \
{ \
return endian##width##_to_cpu(*(uint##width##_t *)p); \
}
DEFINE_ENDIAN_DEC(be, 16)
DEFINE_ENDIAN_DEC(be, 32)
DEFINE_ENDIAN_DEC(be, 64)
DEFINE_ENDIAN_DEC(le, 16)
DEFINE_ENDIAN_DEC(le, 32)
DEFINE_ENDIAN_DEC(le, 64)

/* be16enc/be32enc/be64enc/le16enc/le32enc/le64enc family of functions. */
#define DEFINE_ENDIAN_ENC(endian, width) \
static inline void endian##width##enc(void *p, uint##width##_t u) \
{ \
*(uint##width##_t *)p = cpu_to_##endian##width(u); \
}
DEFINE_ENDIAN_ENC(be, 16)
DEFINE_ENDIAN_ENC(be, 32)
DEFINE_ENDIAN_ENC(be, 64)
DEFINE_ENDIAN_ENC(le, 16)
DEFINE_ENDIAN_ENC(le, 32)
DEFINE_ENDIAN_ENC(le, 64)

/*
* Portable (API) endian support that can be used in code that is shared
* with userspace (man 3 endian) tools.
Expand Down
4 changes: 4 additions & 0 deletions src/include/rules.h
View file
Expand Up @@ -257,6 +257,10 @@

#endif

/* ENV_PAYLOAD_LOADER is set when you are in a stage that loads the payload.
* For now, that is the ramstage. */
#define ENV_PAYLOAD_LOADER ENV_RAMSTAGE

/**
* For pre-DRAM stages and post-CAR always build with simple device model, ie.
* PCI, PNP and CPU functions operate without use of devicetree. The reason
Expand Down
2 changes: 1 addition & 1 deletion src/include/smbios.h
View file
Expand Up @@ -44,7 +44,7 @@ int smbios_write_type38(unsigned long *current, int *handle,
const u8 irq);
int smbios_write_type41(unsigned long *current, int *handle,
const char *name, u8 instance, u16 segment,
u8 bus, u8 device, u8 function);
u8 bus, u8 device, u8 function, u8 device_type);

const char *smbios_system_manufacturer(void);
const char *smbios_system_product_name(void);
Expand Down
15 changes: 15 additions & 0 deletions src/include/string.h
View file
Expand Up @@ -178,4 +178,19 @@ static inline int tolower(int c)
c -= 'A'-'a';
return c;
}

/*
* Parses an unsigned integer and moves the input pointer forward to the first
* character that's not a valid digit. s and *s must not be NULL. Result
* undefined if it overruns the return type size.
*/
static inline unsigned int skip_atoi(char **s)
{
unsigned int i = 0;

while (isdigit(**s))
i = i*10 + *((*s)++) - '0';
return i;
}

#endif /* STRING_H */
3 changes: 3 additions & 0 deletions src/include/superio/conf_mode.h
View file
Expand Up @@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Nico Huber <nico.h@gmx.de>
* Copyright (C) 2017-2018 Eltan B.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
Expand All @@ -25,6 +26,7 @@ void pnp_enter_conf_mode_6767(struct device *dev);
void pnp_enter_conf_mode_7777(struct device *dev);
void pnp_enter_conf_mode_8787(struct device *dev);
void pnp_enter_conf_mode_a0a0(struct device *dev);
void pnp_enter_conf_mode_a5a5(struct device *dev);
void pnp_exit_conf_mode_aa(struct device *dev);
void pnp_enter_conf_mode_870155aa(struct device *dev);
void pnp_exit_conf_mode_0202(struct device *dev);
Expand All @@ -34,6 +36,7 @@ extern const struct pnp_mode_ops pnp_conf_mode_6767_aa;
extern const struct pnp_mode_ops pnp_conf_mode_7777_aa;
extern const struct pnp_mode_ops pnp_conf_mode_8787_aa;
extern const struct pnp_mode_ops pnp_conf_mode_a0a0_aa;
extern const struct pnp_mode_ops pnp_conf_mode_a5a5_aa;
extern const struct pnp_mode_ops pnp_conf_mode_870155_aa;

#endif /* DEVICE_PNP_CONF_MODE_H */
25 changes: 25 additions & 0 deletions src/lib/Kconfig
View file
Expand Up @@ -30,6 +30,31 @@ config FLATTENED_DEVICE_TREE
Selected by features that require to parse and manipulate a flattened
devicetree in ramstage.

config GENERIC_SPD_BIN
bool
help
If enabled, add support for adding spd.hex files in cbfs as spd.bin
and locating it runtime to load SPD. Additionally provide provision to
fetch SPD over SMBus.

config DIMM_MAX
int
default 4
help
Total number of memory DIMM slots available on motherboard.
It is multiplication of number of channel to number of DIMMs per
channel

config DIMM_SPD_SIZE
int
default 256
help
Total SPD size that will be used for DIMM.
Ex: DDR3 256, DDR4 512.

config SPD_READ_BY_WORD
bool

if RAMSTAGE_LIBHWBASE

config HWBASE_DYNAMIC_MMIO
Expand Down
2 changes: 1 addition & 1 deletion src/lib/boot_device.c
View file
Expand Up @@ -20,7 +20,7 @@ void __weak boot_device_init(void)
/* Provide weak do-nothing init. */
}

int __weak boot_device_wp_region(struct region_device *rd,
int __weak boot_device_wp_region(const struct region_device *rd,
const enum bootdev_prot_type type)
{
/* return a failure, make aware WP is not implemented */
Expand Down
6 changes: 3 additions & 3 deletions src/lib/bootblock.c
View file
Expand Up @@ -42,12 +42,12 @@ asmlinkage void bootblock_main_with_timestamp(uint64_t base_timestamp,
timestamps[i].entry_stamp);
}

sanitize_cmos();
cmos_post_init();

bootblock_soc_early_init();
bootblock_mainboard_early_init();

sanitize_cmos();
cmos_post_init();

if (CONFIG(BOOTBLOCK_CONSOLE)) {
console_init();
exception_init();
Expand Down
2 changes: 0 additions & 2 deletions src/lib/bootmode.c
View file
Expand Up @@ -17,7 +17,6 @@
#include <bootmode.h>
#include <vendorcode/google/chromeos/chromeos.h>

#if ENV_RAMSTAGE
static int gfx_init_done = -1;

int gfx_get_init_done(void)
Expand All @@ -31,7 +30,6 @@ void gfx_set_init_done(int done)
{
gfx_init_done = done;
}
#endif

int display_init_required(void)
{
Expand Down
7 changes: 6 additions & 1 deletion src/lib/cbfs.c
View file
Expand Up @@ -96,7 +96,12 @@ int cbfs_locate_file_in_region(struct cbfsf *fh, const char *region_name,
return -1;
}

return cbfs_locate(fh, &rdev, name, type);
int ret = cbfs_locate(fh, &rdev, name, type);
if (!ret)
if (vboot_measure_cbfs_hook(fh, name))
return -1;

return ret;
}

size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset,
Expand Down
19 changes: 19 additions & 0 deletions src/lib/coreboot_table.c
View file
Expand Up @@ -321,6 +321,22 @@ static void lb_sku_id(struct lb_header *header)
printk(BIOS_INFO, "SKU ID: %d\n", sid);
}

static void lb_mmc_info(struct lb_header *header)
{
struct lb_mmc_info *rec;
int32_t *ms_cbmem;

ms_cbmem = cbmem_find(CBMEM_ID_MMC_STATUS);
if (!ms_cbmem)
return;

rec = (struct lb_mmc_info *)lb_new_record(header);

rec->tag = LB_TAG_MMC_INFO;
rec->size = sizeof(*rec);
rec->early_cmd1_status = *ms_cbmem;
}

static void add_cbmem_pointers(struct lb_header *header)
{
/*
Expand Down Expand Up @@ -559,6 +575,9 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end)
lb_ram_code(head);
lb_sku_id(head);

/* Pass mmc early init status */
lb_mmc_info(head);

/* Add SPI flash description if available */
if (CONFIG(BOOT_DEVICE_SPI_FLASH))
lb_spi_flash(head);
Expand Down
16 changes: 8 additions & 8 deletions src/lib/device_tree.c
View file
Expand Up @@ -56,7 +56,7 @@ int fdt_next_property(const void *blob, uint32_t offset,
int fdt_node_name(const void *blob, uint32_t offset, const char **name)
{
uint8_t *ptr = ((uint8_t *)blob) + offset;
if (be32toh(*(uint32_t *)ptr) != FDT_TOKEN_BEGIN_NODE)
if (be32dec(ptr) != FDT_TOKEN_BEGIN_NODE)
return 0;

ptr += 4;
Expand Down Expand Up @@ -358,14 +358,14 @@ static void dt_flatten_prop(struct device_tree_property *prop,
uint8_t *dstruct = (uint8_t *)*struct_start;
uint8_t *dstrings = (uint8_t *)*strings_start;

*((uint32_t *)dstruct) = htobe32(FDT_TOKEN_PROPERTY);
be32enc(dstruct, FDT_TOKEN_PROPERTY);
dstruct += sizeof(uint32_t);

*((uint32_t *)dstruct) = htobe32(prop->prop.size);
be32enc(dstruct, prop->prop.size);
dstruct += sizeof(uint32_t);

uint32_t name_offset = (uintptr_t)dstrings - (uintptr_t)strings_base;
*((uint32_t *)dstruct) = htobe32(name_offset);
be32enc(dstruct, name_offset);
dstruct += sizeof(uint32_t);

strcpy((char *)dstrings, prop->prop.name);
Expand All @@ -385,7 +385,7 @@ static void dt_flatten_node(const struct device_tree_node *node,
uint8_t *dstruct = (uint8_t *)*struct_start;
uint8_t *dstrings = (uint8_t *)*strings_start;

*((uint32_t *)dstruct) = htobe32(FDT_TOKEN_BEGIN_NODE);
be32enc(dstruct, FDT_TOKEN_BEGIN_NODE);
dstruct += sizeof(uint32_t);

strcpy((char *)dstruct, node->name);
Expand All @@ -401,7 +401,7 @@ static void dt_flatten_node(const struct device_tree_node *node,
dt_flatten_node(child, (void **)&dstruct, strings_base,
(void **)&dstrings);

*((uint32_t *)dstruct) = htobe32(FDT_TOKEN_END_NODE);
be32enc(dstruct, FDT_TOKEN_END_NODE);
dstruct += sizeof(uint32_t);

*struct_start = dstruct;
Expand Down Expand Up @@ -489,9 +489,9 @@ void dt_read_cell_props(const struct device_tree_node *node, u32 *addrcp,
struct device_tree_property *prop;
list_for_each(prop, node->properties, list_node) {
if (addrcp && !strcmp("#address-cells", prop->prop.name))
*addrcp = be32toh(*(u32 *)prop->prop.data);
*addrcp = be32dec(prop->prop.data);
if (sizecp && !strcmp("#size-cells", prop->prop.name))
*sizecp = be32toh(*(u32 *)prop->prop.data);
*sizecp = be32dec(prop->prop.data);
}
}

Expand Down
8 changes: 8 additions & 0 deletions src/lib/fit.c
View file
Expand Up @@ -63,6 +63,14 @@ static void fit_add_default_compat_strings(void)
fit_add_compat_string(compat_string);
}

if (sku_id() != UNDEFINED_STRAPPING_ID) {
snprintf(compat_string, sizeof(compat_string), "%s,%s-sku%u",
CONFIG_MAINBOARD_VENDOR, CONFIG_MAINBOARD_PART_NUMBER,
sku_id());

fit_add_compat_string(compat_string);
}

if (board_id() != UNDEFINED_STRAPPING_ID) {
snprintf(compat_string, sizeof(compat_string), "%s,%s-rev%u",
CONFIG_MAINBOARD_VENDOR, CONFIG_MAINBOARD_PART_NUMBER,
Expand Down
6 changes: 1 addition & 5 deletions src/lib/hexdump.c
View file
Expand Up @@ -14,11 +14,7 @@

#include <console/console.h>
#include <lib.h>

static int isprint(int c)
{
return (c >= 32 && c <= 126);
}
#include <string.h>

void hexdump(const void *memory, size_t length)
{
Expand Down
10 changes: 6 additions & 4 deletions src/lib/prog_loaders.c
View file
Expand Up @@ -69,7 +69,8 @@ void run_romstage(void)

fail:
if (CONFIG(BOOTBLOCK_CONSOLE))
die("Couldn't load romstage.\n");
die_with_post_code(POST_INVALID_ROM,
"Couldn't load romstage.\n");
halt();
}

Expand Down Expand Up @@ -162,7 +163,7 @@ void run_ramstage(void)
prog_run(&ramstage);

fail:
die("Ramstage was not loaded!\n");
die_with_post_code(POST_INVALID_ROM, "Ramstage was not loaded!\n");
}

#ifdef __RAMSTAGE__ // gc-sections should take care of this
Expand Down Expand Up @@ -195,13 +196,14 @@ void payload_load(void)
break;
} /* else fall-through */
default:
die("Unsupported payload type.\n");
die_with_post_code(POST_INVALID_ROM,
"Unsupported payload type.\n");
break;
}

out:
if (prog_entry(payload) == NULL)
die("Payload not loaded.\n");
die_with_post_code(POST_INVALID_ROM, "Payload not loaded.\n");
}

void payload_run(void)
Expand Down
12 changes: 8 additions & 4 deletions src/lib/timestamp.c
View file
Expand Up @@ -47,12 +47,15 @@ DECLARE_OPTIONAL_REGION(timestamp);
#define USE_TIMESTAMP_REGION 0
#endif

/* The cache location will sit in BSS when in ramstage. */
#define TIMESTAMP_CACHE_IN_BSS ENV_RAMSTAGE
/* The cache location will sit in BSS when in ramstage/postcar. */
#define TIMESTAMP_CACHE_IN_BSS (ENV_RAMSTAGE || ENV_POSTCAR)

#define HAS_CBMEM (ENV_ROMSTAGE || ENV_RAMSTAGE || ENV_POSTCAR)

/* Storage of cache entries during ramstage prior to cbmem coming online. */
/*
* Storage of cache entries during ramstage/postcar prior to cbmem coming
* online.
*/
static struct timestamp_cache timestamp_cache;

enum {
Expand Down Expand Up @@ -220,7 +223,7 @@ void timestamp_init(uint64_t base)
/* Timestamps could have already been recovered.
* In those circumstances honor the cache which sits in BSS
* as it has already been initialized. */
if (ENV_RAMSTAGE &&
if (TIMESTAMP_CACHE_IN_BSS &&
ts_cache->cache_state != TIMESTAMP_CACHE_UNINITIALIZED)
return;

Expand Down Expand Up @@ -350,6 +353,7 @@ uint32_t get_us_since_boot(void)
}

ROMSTAGE_CBMEM_INIT_HOOK(timestamp_sync_cache_to_cbmem)
POSTCAR_CBMEM_INIT_HOOK(timestamp_sync_cache_to_cbmem)
RAMSTAGE_CBMEM_INIT_HOOK(timestamp_sync_cache_to_cbmem)

/* Provide default timestamp implementation using monotonic timer. */
Expand Down
9 changes: 0 additions & 9 deletions src/mainboard/amd/inagua/acpi/gpe.asl
View file
Expand Up @@ -15,12 +15,6 @@

Scope(\_GPE) { /* Start Scope GPE */

/* General event 3 */
Method(_L03) {
/* DBGO("\\_GPE\\_L00\n") */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}

/* Legacy PM event */
Method(_L08) {
/* DBGO("\\_GPE\\_L08\n") */
Expand All @@ -42,7 +36,6 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}

/* ExtEvent0 SCI event */
Expand All @@ -63,14 +56,12 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}

/* Azalia SCI event */
Method(_L1B) {
/* DBGO("\\_GPE\\_L1B\n") */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
} /* End Scope GPE */

Expand Down
9 changes: 0 additions & 9 deletions src/mainboard/amd/persimmon/acpi/gpe.asl
View file
Expand Up @@ -15,12 +15,6 @@

Scope(\_GPE) { /* Start Scope GPE */

/* General event 3 */
Method(_L03) {
/* DBGO("\\_GPE\\_L00\n") */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}

/* Legacy PM event */
Method(_L08) {
/* DBGO("\\_GPE\\_L08\n") */
Expand All @@ -42,7 +36,6 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}

/* ExtEvent0 SCI event */
Expand All @@ -63,14 +56,12 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}

/* Azalia SCI event */
Method(_L1B) {
/* DBGO("\\_GPE\\_L1B\n") */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
} /* End Scope GPE */

Expand Down
9 changes: 0 additions & 9 deletions src/mainboard/amd/south_station/acpi/gpe.asl
View file
Expand Up @@ -15,12 +15,6 @@

Scope(\_GPE) { /* Start Scope GPE */

/* General event 3 */
Method(_L03) {
/* DBGO("\\_GPE\\_L00\n") */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}

/* Legacy PM event */
Method(_L08) {
/* DBGO("\\_GPE\\_L08\n") */
Expand All @@ -42,7 +36,6 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}

/* ExtEvent0 SCI event */
Expand All @@ -63,14 +56,12 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}

/* Azalia SCI event */
Method(_L1B) {
/* DBGO("\\_GPE\\_L1B\n") */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
} /* End Scope GPE */

Expand Down
9 changes: 0 additions & 9 deletions src/mainboard/amd/union_station/acpi/gpe.asl
View file
Expand Up @@ -15,12 +15,6 @@

Scope(\_GPE) { /* Start Scope GPE */

/* General event 3 */
Method(_L03) {
/* DBGO("\\_GPE\\_L00\n") */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}

/* Legacy PM event */
Method(_L08) {
/* DBGO("\\_GPE\\_L08\n") */
Expand All @@ -42,7 +36,6 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}

/* ExtEvent0 SCI event */
Expand All @@ -63,14 +56,12 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}

/* Azalia SCI event */
Method(_L1B) {
/* DBGO("\\_GPE\\_L1B\n") */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
} /* End Scope GPE */

Expand Down
1 change: 0 additions & 1 deletion src/mainboard/apple/macbook21/romstage.c
View file
Expand Up @@ -18,7 +18,6 @@
/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */

#include <stdint.h>
#include <arch/io.h>
#include <cf9_reset.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/asrock/b75pro3-m/Kconfig
View file
Expand Up @@ -22,7 +22,7 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_INT15
select NORTHBRIDGE_INTEL_IVYBRIDGE
select NORTHBRIDGE_INTEL_SANDYBRIDGE
select SERIRQ_CONTINUOUS_MODE
select SOUTHBRIDGE_INTEL_C216
select USE_NATIVE_RAMINIT
Expand Down
9 changes: 0 additions & 9 deletions src/mainboard/asrock/e350m1/acpi/gpe.asl
View file
Expand Up @@ -15,12 +15,6 @@

Scope(\_GPE) { /* Start Scope GPE */

/* General event 3 */
Method(_L03) {
/* DBGO("\\_GPE\\_L00\n") */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}

/* Legacy PM event */
Method(_L08) {
/* DBGO("\\_GPE\\_L08\n") */
Expand All @@ -42,7 +36,6 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}

/* ExtEvent0 SCI event */
Expand All @@ -63,14 +56,12 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}

/* Azalia SCI event */
Method(_L1B) {
/* DBGO("\\_GPE\\_L1B\n") */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}

} /* End Scope GPE */
Expand Down
8 changes: 0 additions & 8 deletions src/mainboard/asrock/h81m-hds/Kconfig
View file
Expand Up @@ -40,14 +40,6 @@ config CBFS_SIZE
hex
default 0x200000

#
# The override of GFX_GMA_CPU_VARIANT should be removed once the patches
# for dynamic CPU detection are merged in libgfxinit.
#
config GFX_GMA_CPU_VARIANT
string
default "Normal"

config MAINBOARD_DIR
string
default asrock/h81m-hds
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/asus/h61m-cs/Kconfig
View file
Expand Up @@ -6,7 +6,7 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_INT15
select NORTHBRIDGE_INTEL_IVYBRIDGE
select NORTHBRIDGE_INTEL_SANDYBRIDGE
select SERIRQ_CONTINUOUS_MODE
select SOUTHBRIDGE_INTEL_BD82X6X
select USE_NATIVE_RAMINIT
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/asus/p5gc-mx/romstage.c
View file
Expand Up @@ -18,7 +18,6 @@
// __PRE_RAM__ means: use "unsigned" for device, not a struct.

#include <stdint.h>
#include <arch/io.h>
#include <cf9_reset.h>
#include <device/pnp_ops.h>
#include <device/pci_ops.h>
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/asus/p5qpl-am/romstage.c
View file
Expand Up @@ -15,7 +15,6 @@
* GNU General Public License for more details.
*/

#include <arch/io.h>
#include <cf9_reset.h>
#include <device/pnp_ops.h>
#include <device/pci_ops.h>
Expand Down
5 changes: 4 additions & 1 deletion src/mainboard/asus/p8h61-m_pro/Kconfig
View file
Expand Up @@ -21,7 +21,7 @@ config BOARD_SPECIFIC_OPTIONS
select BOARD_ROMSIZE_KB_4096
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select NORTHBRIDGE_INTEL_IVYBRIDGE
select NORTHBRIDGE_INTEL_SANDYBRIDGE
select SERIRQ_CONTINUOUS_MODE
select SOUTHBRIDGE_INTEL_BD82X6X
select USE_NATIVE_RAMINIT
Expand All @@ -31,6 +31,9 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_CMOS_DEFAULT
select DRIVERS_ASMEDIA_ASPM_BLACKLIST
select MAINBOARD_HAS_LPC_TPM
select REALTEK_8168_RESET
select RT8168_SET_LED_MODE
select INTEL_GMA_HAVE_VBT

config MAINBOARD_DIR
string
Expand Down
Binary file added src/mainboard/asus/p8h61-m_pro/data.vbt
View file
Binary file not shown.
8 changes: 7 additions & 1 deletion src/mainboard/asus/p8h61-m_pro/devicetree.cb
View file
Expand Up @@ -49,7 +49,13 @@ chip northbridge/intel/sandybridge
device pci 1b.0 on end # High Definition Audio Audio controller
device pci 1c.0 on end # PCIe x1 Port (PCIEX1_1)
device pci 1c.1 on end # PCIe x1 Port (PCIEX1_2)
device pci 1c.2 on end # Realtek RTL8111E Ethernet Controller
device pci 1c.2 on # Realtek RTL8111E Ethernet Controller
chip drivers/net
register "customized_leds" = "0x00f6"
register "wake" = "9"
device pci 00.0 on end
end
end
device pci 1c.3 on end # ASMedia ASM1042 USB3 Controller
device pci 1c.4 on end # PCIe x1 Port, x16 size (PCIEX16_2)
device pci 1c.5 on end # ASMedia ASM1062 SATA Controller
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/compulab/intense_pc/Kconfig
View file
Expand Up @@ -7,7 +7,7 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_INT15
select NORTHBRIDGE_INTEL_IVYBRIDGE
select NORTHBRIDGE_INTEL_SANDYBRIDGE
select SERIRQ_CONTINUOUS_MODE
select SOUTHBRIDGE_INTEL_C216
select SYSTEM_TYPE_LAPTOP
Expand Down
9 changes: 0 additions & 9 deletions src/mainboard/elmex/pcm205400/acpi/gpe.asl
View file
Expand Up @@ -15,12 +15,6 @@

Scope(\_GPE) { /* Start Scope GPE */

/* General event 3 */
Method(_L03) {
/* DBGO("\\_GPE\\_L00\n") */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}

/* Legacy PM event */
Method(_L08) {
/* DBGO("\\_GPE\\_L08\n") */
Expand All @@ -42,7 +36,6 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}

/* ExtEvent0 SCI event */
Expand All @@ -63,14 +56,12 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}

/* Azalia SCI event */
Method(_L1B) {
/* DBGO("\\_GPE\\_L1B\n") */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
} /* End Scope GPE */

Expand Down
2 changes: 2 additions & 0 deletions src/mainboard/foxconn/d41s/Makefile.inc
View file
@@ -1,2 +1,4 @@
romstage-y += early_init.c
bootblock-y += early_init.c
ramstage-y += cstates.c
romstage-y += gpio.c
3 changes: 2 additions & 1 deletion src/mainboard/foxconn/d41s/romstage.c → src/mainboard/foxconn/d41s/early_init.c
View file
Expand Up @@ -15,6 +15,7 @@
* GNU General Public License for more details.
*/

#include <bootblock_common.h>
#include <device/pci_ops.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
#include <northbridge/intel/pineview/pineview.h>
Expand All @@ -23,7 +24,7 @@

#define SERIAL_DEV PNP_DEV(0x2e, IT8721F_SP1)

void mb_enable_lpc(void)
void bootblock_mainboard_early_init(void)
{
/* Disable Serial IRQ */
pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
Expand Down
11 changes: 2 additions & 9 deletions src/mainboard/gigabyte/ga-b75m-d3h/Kconfig
View file
Expand Up @@ -3,7 +3,7 @@ if BOARD_GIGABYTE_GA_B75M_D3H
config BOARD_SPECIFIC_OPTIONS
def_bool y
select ARCH_X86
select NORTHBRIDGE_INTEL_IVYBRIDGE
select NORTHBRIDGE_INTEL_SANDYBRIDGE
select USE_NATIVE_RAMINIT
select SOUTHBRIDGE_INTEL_C216
select SUPERIO_ITE_IT8728F
Expand All @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select HAVE_ACPI_RESUME
select INTEL_GMA_HAVE_VBT
select INTEL_INT15
select SERIRQ_CONTINUOUS_MODE
select MAINBOARD_HAS_LIBGFXINIT
Expand All @@ -37,12 +38,4 @@ config MAX_CPUS
int
default 8

config VGA_BIOS_ID
string
default "8086,0162"

config VGA_BIOS_FILE
string
default "pci8086,0162.rom"

endif # BOARD_GIGABYTE_GA_B75M_D3H
2 changes: 1 addition & 1 deletion src/mainboard/gigabyte/ga-b75m-d3h/acpi/mainboard.asl
View file
Expand Up @@ -18,6 +18,6 @@ Scope (\_SB)
{
Device (PWRB)
{
Name (_HID, EisaId("PNP0C0C"))
Name (_HID, EisaId ("PNP0C0C"))
}
}
5 changes: 2 additions & 3 deletions src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl
View file
Expand Up @@ -17,14 +17,13 @@
* entering a sleep state. The sleep state number is passed in Arg0
*/

Method(_PTS,1)
Method (_PTS, 1)
{

}

/* The _WAK method is called on system wakeup */

Method(_WAK,1)
{
Return(Package(){0,0})
Return (Package () {0, 0})
}
19 changes: 0 additions & 19 deletions src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl
View file
@@ -1,19 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

/* mainboard configuration */

#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
#define SIO_ENABLE_PS2M // Enable PS/2 Mouse
2 changes: 1 addition & 1 deletion src/mainboard/gigabyte/ga-b75m-d3h/board_info.txt
View file
@@ -1,5 +1,5 @@
Category: desktop
Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=4150#sp
Board URL: https://www.gigabyte.com/products/product-page.aspx?pid=4150#ov
ROM package: SOIC-8
ROM protocol: SPI
ROM socketed: n
Expand Down
Binary file added src/mainboard/gigabyte/ga-b75m-d3h/data.vbt
View file
Binary file not shown.
7 changes: 3 additions & 4 deletions src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb
View file
Expand Up @@ -21,16 +21,15 @@ chip northbridge/intel/sandybridge

device domain 0 on
subsystemid 0x1458 0x5000 inherit
device pci 00.0 on # host bridge
device pci 00.0 on # Host bridge
subsystemid 0x1458 0x5000
end
device pci 01.0 on end # PCIe Bridge for discrete graphics
device pci 02.0 on # vga controller
device pci 02.0 on # Integrated VGA controller
subsystemid 0x1458 0xd000
end

chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH

# GPI routing
register "alt_gp_smi_en" = "0x0000"
register "gen1_dec" = "0x003c0a01"
Expand Down Expand Up @@ -109,7 +108,7 @@ chip northbridge/intel/sandybridge
end

chip drivers/pc80/tpm
device pnp 0c31.0 on end
device pnp 0c31.0 on end
end
end
device pci 1f.2 on # SATA Controller 1
Expand Down
2 changes: 2 additions & 0 deletions src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl
View file
Expand Up @@ -24,7 +24,9 @@ DefinitionBlock(
#include <southbridge/intel/bd82x6x/acpi/platform.asl>

// Some generic macros
#include "acpi/mainboard.asl"
#include "acpi/platform.asl"
#include "acpi/thermal.asl"
#include <cpu/intel/common/acpi/cpu.asl>
/* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
Expand Down
42 changes: 2 additions & 40 deletions src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c
View file
Expand Up @@ -19,54 +19,16 @@
#include <drivers/intel/gma/int15.h>
#include <southbridge/intel/bd82x6x/pch.h>

static void mainboard_init(struct device *dev)
{
RCBA32(0x38c8) = 0x00002005;
RCBA32(0x38c4) = 0x00802005;
RCBA32(0x2240) = 0x00330e71;
RCBA32(0x2244) = 0x003f0eb1;
RCBA32(0x2248) = 0x002102cd;
RCBA32(0x224c) = 0x00f60000;
RCBA32(0x2250) = 0x00020000;
RCBA32(0x2254) = 0x00e3004c;
RCBA32(0x2258) = 0x00e20bef;
RCBA32(0x2260) = 0x003304ed;
RCBA32(0x2278) = 0x001107c1;
RCBA32(0x227c) = 0x001d07e9;
RCBA32(0x2280) = 0x00e20000;
RCBA32(0x2284) = 0x00ee0000;
RCBA32(0x2288) = 0x005b05d3;
RCBA32(0x2318) = 0x04b8ff2e;
RCBA32(0x231c) = 0x03930f2e;
RCBA32(0x3808) = 0x005044a3;
RCBA32(0x3810) = 0x52410000;
RCBA32(0x3814) = 0x0000008a;
RCBA32(0x3818) = 0x00000006;
RCBA32(0x381c) = 0x0000072e;
RCBA32(0x3820) = 0x0000000a;
RCBA32(0x3824) = 0x00000123;
RCBA32(0x3828) = 0x00000009;
RCBA32(0x382c) = 0x00000001;
RCBA32(0x3834) = 0x0000061a;
RCBA32(0x3838) = 0x00000003;
RCBA32(0x383c) = 0x00000a76;
RCBA32(0x3840) = 0x00000004;
RCBA32(0x3844) = 0x0000e5e4;
RCBA32(0x3848) = 0x0000000e;
}

// mainboard_enable is executed as first thing after
// enumerate_buses().

static void mainboard_enable(struct device *dev)
{
dev->ops->init = mainboard_init;

install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
GMA_INT15_PANEL_FIT_DEFAULT,
GMA_INT15_BOOT_DISPLAY_CRT, 0);
GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}

struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
.enable_dev = mainboard_enable
};
25 changes: 12 additions & 13 deletions src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
View file
Expand Up @@ -25,12 +25,6 @@
#define SIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO)
#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01)

void mainboard_rcba_config(void)
{
/* Enable HECI */
RCBA32(FD2) &= ~0x2;
}

void pch_enable_lpc(void)
{
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN |
Expand All @@ -40,7 +34,10 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);

pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}

void mainboard_config_superio(void)
{
/* Initialize SuperIO */
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

Expand Down Expand Up @@ -87,18 +84,20 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 5, 6 },
};

void mainboard_get_spd(spd_raw_data *spd, bool id_only)
void mainboard_early_init(int s3resume)
{
read_spd (&spd[0], 0x50, id_only);
read_spd (&spd[1], 0x51, id_only);
read_spd (&spd[2], 0x52, id_only);
read_spd (&spd[3], 0x53, id_only);
}

void mainboard_early_init(int s3resume)
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
{
read_spd(&spd[0], 0x50, id_only);
read_spd(&spd[1], 0x51, id_only);
read_spd(&spd[2], 0x52, id_only);
read_spd(&spd[3], 0x53, id_only);
}

void mainboard_config_superio(void)
void mainboard_rcba_config(void)
{
/* Enable HECI */
RCBA32(FD2) &= ~0x2;
}
12 changes: 3 additions & 9 deletions src/mainboard/gigabyte/ga-b75m-d3v/Kconfig
View file
Expand Up @@ -3,7 +3,7 @@ if BOARD_GIGABYTE_GA_B75M_D3V
config BOARD_SPECIFIC_OPTIONS
def_bool y
select ARCH_X86
select NORTHBRIDGE_INTEL_IVYBRIDGE
select NORTHBRIDGE_INTEL_SANDYBRIDGE
select USE_NATIVE_RAMINIT
select SOUTHBRIDGE_INTEL_C216
select SUPERIO_ITE_IT8728F
Expand All @@ -12,9 +12,11 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select HAVE_ACPI_RESUME
select INTEL_GMA_HAVE_VBT
select INTEL_INT15
select SERIRQ_CONTINUOUS_MODE
select MAINBOARD_HAS_LIBGFXINIT
select MAINBOARD_HAS_LPC_TPM

config DRAM_RESET_GATE_GPIO
int
Expand All @@ -36,12 +38,4 @@ config MAX_CPUS
int
default 8

config VGA_BIOS_ID
string
default "8086,0102"

config VGA_BIOS_FILE
string
default "pci8086,0102.rom"

endif # BOARD_GIGABYTE_GA_B75M_D3V
23 changes: 23 additions & 0 deletions src/mainboard/gigabyte/ga-b75m-d3v/acpi/mainboard.asl
View file
@@ -0,0 +1,23 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

Scope (\_SB)
{
Device (PWRB)
{
Name (_HID, EisaId ("PNP0C0C"))
}
}
4 changes: 2 additions & 2 deletions src/mainboard/gigabyte/ga-b75m-d3v/acpi/platform.asl
View file
Expand Up @@ -17,13 +17,13 @@
* entering a sleep state. The sleep state number is passed in Arg0
*/

Method(_PTS,1)
Method (_PTS, 1)
{
}

/* The _WAK method is called on system wakeup */

Method(_WAK,1)
{
Return(Package(){0,0})
Return (Package () {0, 0})
}
4 changes: 0 additions & 4 deletions src/mainboard/gigabyte/ga-b75m-d3v/acpi/superio.asl
View file
@@ -1,4 +0,0 @@
/* mainboard configuration */

#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
#define SIO_ENABLE_PS2M // Enable PS/2 Mouse
4 changes: 2 additions & 2 deletions src/mainboard/gigabyte/ga-b75m-d3v/board_info.txt
View file
@@ -1,7 +1,7 @@
Category: desktop
Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=4151#ov
Board URL: https://www.gigabyte.com/products/product-page.aspx?pid=4151#ov
ROM package: SOIC-8
ROM protocol: SPI
ROM socketed: n
Flashrom support: y
Release date: 2012
Release year: 2012
Binary file added src/mainboard/gigabyte/ga-b75m-d3v/data.vbt
View file
Binary file not shown.
10 changes: 7 additions & 3 deletions src/mainboard/gigabyte/ga-b75m-d3v/devicetree.cb
View file
@@ -1,4 +1,5 @@
chip northbridge/intel/sandybridge
# IGD Displays
register "gfx.ndid" = "3"
register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"

Expand All @@ -20,16 +21,15 @@ chip northbridge/intel/sandybridge

device domain 0 on
subsystemid 0x1458 0x5000 inherit
device pci 00.0 on # host bridge
device pci 00.0 on # Host bridge
subsystemid 0x1458 0x5000
end
device pci 01.0 on end # PCIe Bridge for discrete graphics
device pci 02.0 on # vga controller
device pci 02.0 on # Integrated VGA controller
subsystemid 0x1458 0xd000
end

chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH

# GPI routing
register "alt_gp_smi_en" = "0x0000"
register "gen1_dec" = "0x003c0a01"
Expand Down Expand Up @@ -106,6 +106,10 @@ chip northbridge/intel/sandybridge
device pnp 2e.7 off end # GPIO
device pnp 2e.a off end # IR
end

chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
end
device pci 1f.2 on # SATA Controller 1
subsystemid 0x1458 0xb005
Expand Down
2 changes: 2 additions & 0 deletions src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl
View file
Expand Up @@ -24,7 +24,9 @@ DefinitionBlock(
#include <southbridge/intel/bd82x6x/acpi/platform.asl>

// Some generic macros
#include "acpi/mainboard.asl"
#include "acpi/platform.asl"
#include "acpi/thermal.asl"
#include <cpu/intel/common/acpi/cpu.asl>
/* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
Expand Down
42 changes: 2 additions & 40 deletions src/mainboard/gigabyte/ga-b75m-d3v/mainboard.c
View file
Expand Up @@ -19,54 +19,16 @@
#include <drivers/intel/gma/int15.h>
#include <southbridge/intel/bd82x6x/pch.h>

static void mainboard_init(struct device *dev)
{
RCBA32(0x38c8) = 0x00002005;
RCBA32(0x38c4) = 0x00802005;
RCBA32(0x2240) = 0x00330e71;
RCBA32(0x2244) = 0x003f0eb1;
RCBA32(0x2248) = 0x002102cd;
RCBA32(0x224c) = 0x00f60000;
RCBA32(0x2250) = 0x00020000;
RCBA32(0x2254) = 0x00e3004c;
RCBA32(0x2258) = 0x00e20bef;
RCBA32(0x2260) = 0x003304ed;
RCBA32(0x2278) = 0x001107c1;
RCBA32(0x227c) = 0x001d07e9;
RCBA32(0x2280) = 0x00e20000;
RCBA32(0x2284) = 0x00ee0000;
RCBA32(0x2288) = 0x005b05d3;
RCBA32(0x2318) = 0x04b8ff2e;
RCBA32(0x231c) = 0x03930f2e;
RCBA32(0x3808) = 0x005044a3;
RCBA32(0x3810) = 0x52410000;
RCBA32(0x3814) = 0x0000008a;
RCBA32(0x3818) = 0x00000006;
RCBA32(0x381c) = 0x0000072e;
RCBA32(0x3820) = 0x0000000a;
RCBA32(0x3824) = 0x00000123;
RCBA32(0x3828) = 0x00000009;
RCBA32(0x382c) = 0x00000001;
RCBA32(0x3834) = 0x0000061a;
RCBA32(0x3838) = 0x00000003;
RCBA32(0x383c) = 0x00000a76;
RCBA32(0x3840) = 0x00000004;
RCBA32(0x3844) = 0x0000e5e4;
RCBA32(0x3848) = 0x0000000e;
}

// mainboard_enable is executed as first thing after
// enumerate_buses().

static void mainboard_enable(struct device *dev)
{
dev->ops->init = mainboard_init;

install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
GMA_INT15_PANEL_FIT_DEFAULT,
GMA_INT15_BOOT_DISPLAY_CRT, 0);
GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
}

struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
.enable_dev = mainboard_enable
};
27 changes: 13 additions & 14 deletions src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
View file
Expand Up @@ -25,12 +25,6 @@
#define SIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO)
#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01)

void mainboard_rcba_config(void)
{
/* Enable HECI */
RCBA32(FD2) &= ~0x2;
}

void pch_enable_lpc(void)
{
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN |
Expand All @@ -40,7 +34,10 @@ void pch_enable_lpc(void)
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);

pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
}

void mainboard_config_superio(void)
{
/* Initialize SuperIO */
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);

Expand Down Expand Up @@ -87,19 +84,21 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 5, 6 },
};

/* FIXME: This board only has two DIMM slots! */
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
void mainboard_early_init(int s3resume)
{
read_spd (&spd[0], 0x50, id_only);
read_spd (&spd[1], 0x51, id_only);
read_spd (&spd[2], 0x52, id_only);
read_spd (&spd[3], 0x53, id_only);
}

void mainboard_early_init(int s3resume)
/* FIXME: This board only has two DIMM slots! */
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
{
read_spd(&spd[0], 0x50, id_only);
read_spd(&spd[1], 0x51, id_only);
read_spd(&spd[2], 0x52, id_only);
read_spd(&spd[3], 0x53, id_only);
}

void mainboard_config_superio(void)
void mainboard_rcba_config(void)
{
/* Enable HECI */
RCBA32(FD2) &= ~0x2;
}
9 changes: 0 additions & 9 deletions src/mainboard/gizmosphere/gizmo/acpi/gpe.asl
View file
Expand Up @@ -16,12 +16,6 @@

Scope(\_GPE) { /* Start Scope GPE */

/* General event 3 */
Method(_L03) {
/* DBGO("\\_GPE\\_L00\n") */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}

/* Legacy PM event */
Method(_L08) {
/* DBGO("\\_GPE\\_L08\n") */
Expand All @@ -43,7 +37,6 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}

/* ExtEvent0 SCI event */
Expand All @@ -64,14 +57,12 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}

/* Azalia SCI event */
Method(_L1B) {
/* DBGO("\\_GPE\\_L1B\n") */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
} /* End Scope GPE */

Expand Down
3 changes: 3 additions & 0 deletions src/mainboard/google/auron/Makefile.inc
View file
Expand Up @@ -17,6 +17,7 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c

romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
bootblock-$(CONFIG_CHROMEOS) += chromeos.c

smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c

Expand All @@ -32,3 +33,5 @@ subdirs-y += variants/$(VARIANT_DIR)
subdirs-y += variants/$(VARIANT_DIR)/spd

CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include

romstage-y += variants/$(VARIANT_DIR)/gpio.c
1 change: 0 additions & 1 deletion src/mainboard/google/auron/chromeos.c
View file
Expand Up @@ -27,7 +27,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
struct lb_gpio chromeos_gpios[] = {
{CROS_WP_GPIO, ACTIVE_HIGH, get_write_protect_state(),
"write protect"},
{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
{-1, ACTIVE_HIGH, 0, "power"},
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
Expand Down
22 changes: 6 additions & 16 deletions src/mainboard/google/auron/romstage.c
View file
Expand Up @@ -17,36 +17,26 @@
#include <console/console.h>
#include <string.h>
#include <ec/google/chromeec/ec.h>
#include <soc/gpio.h>
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
#include <soc/romstage.h>
#include <variant/gpio.h>
#include <variant/spd.h>
#include "variant.h"

__weak void variant_romstage_entry(struct romstage_params *rp)
{
}

void mainboard_romstage_entry(struct romstage_params *rp)
void mainboard_pre_raminit(struct romstage_params *rp)
{
struct pei_data pei_data;

post_code(0x32);

/* Initialize GPIOs */
init_gpios(mainboard_gpio_config);

/* Fill out PEI DATA */
memset(&pei_data, 0, sizeof(pei_data));
mainboard_fill_pei_data(&pei_data);
mainboard_fill_spd_data(&pei_data);
rp->pei_data = &pei_data;
mainboard_fill_pei_data(&rp->pei_data);
mainboard_fill_spd_data(&rp->pei_data);

/* Call into the real romstage main with this board's attributes. */
romstage_common(rp);
}

void mainboard_post_raminit(struct romstage_params *rp)
{
/* Do variant-specific init */
variant_romstage_entry(rp);
}
7 changes: 1 addition & 6 deletions ...ariants/auron_yuna/include/variant/gpio.h → .../google/auron/variants/auron_paine/gpio.c
View file
Expand Up @@ -13,12 +13,9 @@
* GNU General Public License for more details.
*/

#ifndef AURON_YUNA_GPIO_H
#define AURON_YUNA_GPIO_H

#include <soc/gpio.h>

static const struct gpio_config mainboard_gpio_config[] = {
const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 0: UNUSED */
PCH_GPIO_UNUSED, /* 1: UNUSED */
PCH_GPIO_UNUSED, /* 2: UNUSED */
Expand Down Expand Up @@ -116,5 +113,3 @@ static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 94: UNUSED */
PCH_GPIO_END
};

#endif
1 change: 0 additions & 1 deletion src/mainboard/google/auron/variants/auron_paine/spd/spd.c
View file
Expand Up @@ -22,7 +22,6 @@
#include <soc/romstage.h>
#include <ec/google/chromeec/ec.h>
#include <mainboard/google/auron/ec.h>
#include <variant/gpio.h>
#include <variant/spd.h>

static void mainboard_print_spd_info(uint8_t spd[])
Expand Down
3 changes: 2 additions & 1 deletion src/mainboard/google/auron/variants/auron_paine/variant.c
View file
Expand Up @@ -26,7 +26,8 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current)
BOARD_TRACKPAD_I2C_BUS, /* segment */
BOARD_TRACKPAD_I2C_ADDR, /* bus */
0, /* device */
0); /* function */
0, /* function */
SMBIOS_DEVICE_TYPE_OTHER); /* device type */

return len;
}
7 changes: 1 addition & 6 deletions ...riants/auron_paine/include/variant/gpio.h → ...d/google/auron/variants/auron_yuna/gpio.c
View file
Expand Up @@ -13,12 +13,9 @@
* GNU General Public License for more details.
*/

#ifndef AURON_PAINE_GPIO_H
#define AURON_PAINE_GPIO_H

#include <soc/gpio.h>

static const struct gpio_config mainboard_gpio_config[] = {
const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 0: UNUSED */
PCH_GPIO_UNUSED, /* 1: UNUSED */
PCH_GPIO_UNUSED, /* 2: UNUSED */
Expand Down Expand Up @@ -116,5 +113,3 @@ static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 94: UNUSED */
PCH_GPIO_END
};

#endif
1 change: 0 additions & 1 deletion src/mainboard/google/auron/variants/auron_yuna/spd/spd.c
View file
Expand Up @@ -22,7 +22,6 @@
#include <soc/romstage.h>
#include <ec/google/chromeec/ec.h>
#include <mainboard/google/auron/ec.h>
#include <variant/gpio.h>
#include <variant/spd.h>

static void mainboard_print_spd_info(uint8_t spd[])
Expand Down
3 changes: 2 additions & 1 deletion src/mainboard/google/auron/variants/auron_yuna/variant.c
View file
Expand Up @@ -26,7 +26,8 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current)
BOARD_TRACKPAD_I2C_BUS, /* segment */
BOARD_TRACKPAD_I2C_ADDR, /* bus */
0, /* device */
0); /* function */
0, /* function */
SMBIOS_DEVICE_TYPE_OTHER); /* device type */

return len;
}
7 changes: 1 addition & 6 deletions ...ron/variants/buddy/include/variant/gpio.h → ...nboard/google/auron/variants/buddy/gpio.c
View file
Expand Up @@ -14,12 +14,9 @@
* GNU General Public License for more details.
*/

#ifndef BUDDY_GPIO_H
#define BUDDY_GPIO_H

#include <soc/gpio.h>

static const struct gpio_config mainboard_gpio_config[] = {
const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 0: UNUSED */
PCH_GPIO_UNUSED, /* 1: UNUSED */
PCH_GPIO_UNUSED, /* 2: UNUSED */
Expand Down Expand Up @@ -117,5 +114,3 @@ static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 94: UNUSED */
PCH_GPIO_END
};

#endif
3 changes: 2 additions & 1 deletion src/mainboard/google/auron/variants/buddy/variant.c
View file
Expand Up @@ -35,7 +35,8 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current)
BOARD_TOUCHSCREEN_I2C_BUS, /* segment */
BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */
0, /* device */
0); /* function */
0, /* function */
SMBIOS_DEVICE_TYPE_OTHER); /* device type */

return len;
}
Expand Down
7 changes: 1 addition & 6 deletions ...on/variants/gandof/include/variant/gpio.h → ...board/google/auron/variants/gandof/gpio.c
View file
Expand Up @@ -13,12 +13,9 @@
* GNU General Public License for more details.
*/

#ifndef GANDOF_GPIO_H
#define GANDOF_GPIO_H

#include <soc/gpio.h>

static const struct gpio_config mainboard_gpio_config[] = {
const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 0: UNUSED */
PCH_GPIO_UNUSED, /* 1: UNUSED */
PCH_GPIO_UNUSED, /* 2: UNUSED */
Expand Down Expand Up @@ -116,5 +113,3 @@ static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 94: UNUSED */
PCH_GPIO_END
};

#endif
1 change: 0 additions & 1 deletion src/mainboard/google/auron/variants/gandof/spd/spd.c
View file
Expand Up @@ -22,7 +22,6 @@
#include <soc/romstage.h>
#include <ec/google/chromeec/ec.h>
#include <mainboard/google/auron/ec.h>
#include <variant/gpio.h>
#include <variant/spd.h>

static void mainboard_print_spd_info(uint8_t spd[])
Expand Down
3 changes: 2 additions & 1 deletion src/mainboard/google/auron/variants/gandof/variant.c
View file
Expand Up @@ -29,7 +29,8 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current)
BOARD_TRACKPAD_I2C_BUS, /* segment */
BOARD_TRACKPAD_I2C_ADDR, /* bus */
0, /* device */
0); /* function */
0, /* function */
SMBIOS_DEVICE_TYPE_OTHER); /* device type */

return len;
}
Expand Down
7 changes: 1 addition & 6 deletions ...uron/variants/lulu/include/variant/gpio.h → ...inboard/google/auron/variants/lulu/gpio.c
View file
Expand Up @@ -14,12 +14,9 @@
* GNU General Public License for more details.
*/

#ifndef LULU_GPIO_H
#define LULU_GPIO_H

#include <soc/gpio.h>

static const struct gpio_config mainboard_gpio_config[] = {
const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 0: UNUSED */
PCH_GPIO_UNUSED, /* 1: UNUSED */
PCH_GPIO_UNUSED, /* 2: UNUSED */
Expand Down Expand Up @@ -117,5 +114,3 @@ static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 94: UNUSED */
PCH_GPIO_END
};

#endif
1 change: 0 additions & 1 deletion src/mainboard/google/auron/variants/lulu/spd/spd.c
View file
Expand Up @@ -23,7 +23,6 @@
#include <soc/romstage.h>
#include <ec/google/chromeec/ec.h>
#include <mainboard/google/auron/ec.h>
#include <variant/gpio.h>
#include <variant/spd.h>

static void mainboard_print_spd_info(uint8_t spd[])
Expand Down
6 changes: 4 additions & 2 deletions src/mainboard/google/auron/variants/lulu/variant.c
View file
Expand Up @@ -29,7 +29,8 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current)
BOARD_TRACKPAD_I2C_BUS, /* segment */
BOARD_TRACKPAD_I2C_ADDR, /* bus */
0, /* device */
0); /* function */
0, /* function */
SMBIOS_DEVICE_TYPE_OTHER); /* device type */

len += smbios_write_type41(
current, handle,
Expand All @@ -38,7 +39,8 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current)
BOARD_TOUCHSCREEN_I2C_BUS, /* segment */
BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */
0, /* device */
0); /* function */
0, /* function */
SMBIOS_DEVICE_TYPE_OTHER); /* device type */

return len;
}
Expand Down
7 changes: 1 addition & 6 deletions ...ron/variants/samus/include/variant/gpio.h → ...nboard/google/auron/variants/samus/gpio.c
View file
Expand Up @@ -13,12 +13,9 @@
* GNU General Public License for more details.
*/

#ifndef SAMUS_GPIO_H
#define SAMUS_GPIO_H

#include <soc/gpio.h>

static const struct gpio_config mainboard_gpio_config[] = {
const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 0: UNUSED */
PCH_GPIO_UNUSED, /* 1: UNUSED */
PCH_GPIO_UNUSED, /* 2: UNUSED */
Expand Down Expand Up @@ -116,5 +113,3 @@ static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 94: UNUSED */
PCH_GPIO_END
};

#endif
1 change: 0 additions & 1 deletion src/mainboard/google/auron/variants/samus/spd/spd.c
View file
Expand Up @@ -22,7 +22,6 @@
#include <soc/romstage.h>
#include <ec/google/chromeec/ec.h>
#include <mainboard/google/auron/ec.h>
#include <variant/gpio.h>
#include <variant/spd.h>

static void mainboard_print_spd_info(uint8_t spd[])
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/google/beltino/chromeos.c
View file
Expand Up @@ -36,7 +36,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
{GPIO_SPI_WP, ACTIVE_HIGH,
get_write_protect_state(), "write protect"},
{GPIO_REC_MODE, ACTIVE_LOW,
!get_recovery_mode_switch(), "recovery"},
!get_recovery_mode_switch(), "presence"},
{-1, ACTIVE_HIGH, 1, "lid"},
{-1, ACTIVE_HIGH, 0, "power"},
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
Expand Down
3 changes: 0 additions & 3 deletions src/mainboard/google/butterfly/chromeos.c
View file
Expand Up @@ -40,9 +40,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
{WP_GPIO, ACTIVE_LOW, !get_write_protect_state(),
"write protect"},

/* Recovery: virtual GPIO active high */
{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},

/* lid switch value from EC */
{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},

Expand Down
3 changes: 2 additions & 1 deletion src/mainboard/google/butterfly/mainboard.c
View file
Expand Up @@ -264,7 +264,8 @@ static int butterfly_onboard_smbios_data(struct device *dev, int *handle,
0, /* segment */
BOARD_TRACKPAD_I2C_ADDR, /* bus */
0, /* device */
0); /* function */
0, /* function */
SMBIOS_DEVICE_TYPE_OTHER); /* device type */

return len;
}
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/google/cheza/mainboard.c
View file
Expand Up @@ -16,7 +16,6 @@
#include <device/device.h>
#include <bootblock_common.h>
#include <gpio.h>
#include <timestamp.h>
#include <soc/usb.h>

static struct usb_board_data usb1_board_data = {
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/google/cyan/chromeos.c
View file
Expand Up @@ -35,7 +35,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio chromeos_gpios[] = {
{-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
{-1, ACTIVE_HIGH, vboot_recovery_mode_enabled(), "recovery"},
{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
{-1, ACTIVE_HIGH, 0, "power"},
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
Expand Down
3 changes: 0 additions & 3 deletions src/mainboard/google/daisy/chromeos.c
View file
Expand Up @@ -29,9 +29,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
{EXYNOS5_GPD1, ACTIVE_LOW, !get_write_protect_state(),
"write protect"},

/* Recovery: active low */
{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},

/* Lid: active high (LID_GPIO) */
{EXYNOS5_GPX3, ACTIVE_HIGH, gpio_get_value(GPIO_X35), "lid"},

Expand Down
1 change: 0 additions & 1 deletion src/mainboard/google/dragonegg/chromeos.c
View file
Expand Up @@ -28,7 +28,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio chromeos_gpios[] = {
{-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
{-1, ACTIVE_HIGH, 0, "power"},
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
Expand Down
10 changes: 10 additions & 0 deletions src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb
View file
Expand Up @@ -167,6 +167,16 @@ chip soc/intel/icelake
},
}"

# GPIO PM programming
register "gpio_override_pm" = "1"

# GPIO community PM configuration
register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN"
register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"

device domain 0 on
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/google/eve/chromeos.c
View file
Expand Up @@ -27,7 +27,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio chromeos_gpios[] = {
{-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
{-1, ACTIVE_HIGH, 0, "power"},
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/google/fizz/chromeos.c
View file
Expand Up @@ -27,7 +27,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio chromeos_gpios[] = {
{-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
{-1, ACTIVE_HIGH, 1, "lid"}, /* Lid switch always open */
{-1, ACTIVE_HIGH, 0, "power"},
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
Expand Down
3 changes: 0 additions & 3 deletions src/mainboard/google/foster/chromeos.c
View file
Expand Up @@ -28,9 +28,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
/* Write Protect: active low */
{-1, ACTIVE_LOW, !get_write_protect_state(), "write protect"},

/* Recovery: active high */
{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},

/* TODO: Power: active low / high depending on board id */
{GPIO(X5), ACTIVE_LOW, -1, "power"},

Expand Down
2 changes: 0 additions & 2 deletions src/mainboard/google/gale/chromeos.c
View file
Expand Up @@ -68,8 +68,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio chromeos_gpios[] = {
{PP_SW, ACTIVE_LOW, read_gpio(PP_SW), "presence"},
{get_rec_sw_gpio_pin(), ACTIVE_LOW,
read_gpio(get_rec_sw_gpio_pin()), "recovery"},
{get_wp_status_gpio_pin(), ACTIVE_LOW,
!get_write_protect_state(), "write protect"},
{-1, ACTIVE_LOW, 1, "power"},
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/google/glados/chromeos.c
View file
Expand Up @@ -26,7 +26,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio chromeos_gpios[] = {
{-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
{-1, ACTIVE_HIGH, 0, "power"},
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/google/gru/chromeos.c
View file
Expand Up @@ -34,7 +34,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
struct lb_gpio chromeos_gpios[] = {
{GPIO_WP.raw, wp_polarity,
get_write_protect_state() ^ !wp_polarity, "write protect"},
{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
#if CONFIG(GRU_BASEBOARD_SCARLET)
{GPIO_BACKLIGHT.raw, ACTIVE_HIGH, -1, "backlight"},
#endif
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/google/hatch/Kconfig
View file
Expand Up @@ -64,7 +64,7 @@ config GBB_HWID
depends on CHROMEOS
default "HATCH TEST 1823" if BOARD_GOOGLE_HATCH
default "HATCH_WHL TEST 2374" if BOARD_GOOGLE_HATCH_WHL
default "KOHAKU TEST 1953" if BOARD_GOOGLE_HATCH_WHL
default "KOHAKU TEST 1953" if BOARD_GOOGLE_KOHAKU

config MAINBOARD_DIR
string
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/google/hatch/chromeos.c
View file
Expand Up @@ -25,7 +25,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio chromeos_gpios[] = {
{-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
{-1, ACTIVE_HIGH, 0, "power"},
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
Expand Down
54 changes: 47 additions & 7 deletions src/mainboard/google/hatch/romstage.c
View file
Expand Up @@ -16,23 +16,63 @@
#include <baseboard/variants.h>
#include <console/console.h>
#include <ec/google/chromeec/ec.h>
#include <gpio.h>
#include <memory_info.h>
#include <soc/cnl_memcfg_init.h>
#include <soc/romstage.h>
#include <string.h>

/* Memory configuration board straps */
#define GPIO_MEM_CONFIG_0 GPP_F20
#define GPIO_MEM_CONFIG_1 GPP_F21
#define GPIO_MEM_CONFIG_2 GPP_F11
#define GPIO_MEM_CONFIG_3 GPP_F22

/*
* GPIO_MEM_CH_SEL is set to 1 for single channel skus
* and 0 for dual channel skus.
*/
#define GPIO_MEM_CH_SEL GPP_F2

static int memory_sku(void)
{
const gpio_t spd_gpios[] = {
GPIO_MEM_CONFIG_0,
GPIO_MEM_CONFIG_1,
GPIO_MEM_CONFIG_2,
GPIO_MEM_CONFIG_3,
};

return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
}

void mainboard_memory_init_params(FSPM_UPD *memupd)
{
struct cnl_mb_cfg memcfg;

const struct spd_info spd = {
.spd_by_index = true,
.spd_spec.spd_index = variant_memory_sku(),
};
int mem_sku;
int is_single_ch_mem;

variant_memory_params(&memcfg);
cannonlake_memcfg_init(&memupd->FspmConfig,
&memcfg, &spd);
mem_sku = memory_sku();
/*
* GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single
* channel skus and 0 for dual channel skus.
*/
is_single_ch_mem = gpio_get(GPIO_MEM_CH_SEL);

/*
* spd[0]-spd[3] map to CH0D0, CH0D1, CH1D0, CH1D1 respectively.
* Dual-DIMM memory is not used in hatch family, so we only
* fill in spd_info for CH0D0 and CH1D0 here.
*/
memcfg.spd[0].read_type = READ_SPD_CBFS;
memcfg.spd[0].spd_spec.spd_index = mem_sku;
if (!is_single_ch_mem) {
memcfg.spd[2].read_type = READ_SPD_CBFS;
memcfg.spd[2].spd_spec.spd_index = mem_sku;
}

cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
}

void mainboard_get_dram_part_num(const char **part_num, size_t *len)
Expand Down
10 changes: 10 additions & 0 deletions src/mainboard/google/hatch/variants/baseboard/devicetree.cb
View file
Expand Up @@ -89,6 +89,16 @@ chip soc/intel/cannonlake
register "PchHdaAudioLinkSsp1" = "1"
register "PchHdaAudioLinkDmic0" = "1"

# GPIO PM programming
register "gpio_override_pm" = "1"

# GPIO community PM configuration
register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
register "gpio_pm[COMM_1]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
register "gpio_pm[COMM_4]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN"

device cpu_cluster 0 on
device lapic 0 on end
end
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/google/hatch/variants/baseboard/gpio.c
View file
Expand Up @@ -339,7 +339,7 @@ static const struct pad_config gpio_table[] = {
/* G4 : SD_DATA3 */
PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
/* G5 : SD_CD# */
PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
PAD_CFG_NF(GPP_G5, NONE, PLTRST, NF1),
/* G6 : SD_CLK */
PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
/* G7 : SD_WP => NC */
Expand Down
4 changes: 2 additions & 2 deletions src/mainboard/google/hatch/variants/baseboard/include/baseboard/acpi/dptf.asl
View file
Expand Up @@ -21,7 +21,7 @@
#define DPTF_CPU_ACTIVE_AC3 80
#define DPTF_CPU_ACTIVE_AC4 75

#define DPTF_TSR0_SENSOR_ID 1
#define DPTF_TSR0_SENSOR_ID 0
#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1"
#define DPTF_TSR0_PASSIVE 65
#define DPTF_TSR0_CRITICAL 75
Expand All @@ -31,7 +31,7 @@
#define DPTF_TSR0_ACTIVE_AC3 42
#define DPTF_TSR0_ACTIVE_AC4 39

#define DPTF_TSR1_SENSOR_ID 2
#define DPTF_TSR1_SENSOR_ID 1
#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2"
#define DPTF_TSR1_PASSIVE 65
#define DPTF_TSR1_CRITICAL 75
Expand Down
7 changes: 0 additions & 7 deletions src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h
View file
Expand Up @@ -22,13 +22,6 @@

#define GPIO_PCH_WP GPP_C20

/* Memory configuration board straps */
#define GPIO_MEM_CONFIG_0 GPP_F20
#define GPIO_MEM_CONFIG_1 GPP_F21
#define GPIO_MEM_CONFIG_2 GPP_F11
#define GPIO_MEM_CONFIG_3 GPP_F22


/* EC wake pin is LAN_WAKE# */
#define GPE_EC_WAKE GPE0_LAN_WAK

Expand Down
3 changes: 0 additions & 3 deletions src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h
View file
Expand Up @@ -31,9 +31,6 @@ const struct pad_config *base_early_gpio_table(size_t *num);
const struct pad_config *override_gpio_table(size_t *num);
const struct pad_config *override_early_gpio_table(size_t *num);

/* Return memory SKU for the board. */
int variant_memory_sku(void);

/* Return board specific memory configuration */
void variant_memory_params(struct cnl_mb_cfg *bcfg);

Expand Down
33 changes: 2 additions & 31 deletions src/mainboard/google/hatch/variants/baseboard/memory.c
View file
Expand Up @@ -15,16 +15,15 @@

#include <baseboard/variants.h>
#include <baseboard/gpio.h>
#include <gpio.h>
#include <soc/cnl_memcfg_init.h>
#include <string.h>

static const struct cnl_mb_cfg baseboard_memcfg = {
/* Baseboard uses 121, 81 and 100 rcomp resistors */
.rcomp_resistor = { 121, 81, 100 },
.rcomp_resistor = {121, 81, 100},

/* Baseboard Rcomp target values */
.rcomp_targets = { 100, 40, 20, 20, 26 },
.rcomp_targets = {100, 40, 20, 20, 26},

/* Set CaVref config to 2 */
.vref_ca_config = 2,
Expand All @@ -36,32 +35,4 @@ static const struct cnl_mb_cfg baseboard_memcfg = {
void __weak variant_memory_params(struct cnl_mb_cfg *bcfg)
{
memcpy(bcfg, &baseboard_memcfg, sizeof(baseboard_memcfg));
/*
* GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single
* channel skus and 0 for dual channel skus.
*/
if (gpio_get(GPP_F2) == 1) {
/*
* Single channel config: for Hatch, Channel 0 is
* always populated.
*/
bcfg->channel_empty[0] = 0;
bcfg->channel_empty[1] = 1;
} else {
/* Dual channel config: both channels populated. */
bcfg->channel_empty[0] = 0;
bcfg->channel_empty[1] = 0;
}
}

int __weak variant_memory_sku(void)
{
const gpio_t spd_gpios[] = {
GPIO_MEM_CONFIG_0,
GPIO_MEM_CONFIG_1,
GPIO_MEM_CONFIG_2,
GPIO_MEM_CONFIG_3,
};

return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
}
4 changes: 2 additions & 2 deletions src/mainboard/google/hatch/variants/hatch/overridetree.cb
View file
Expand Up @@ -78,8 +78,8 @@ chip soc/intel/cannonlake
register "generic.probed" = "1"
register "generic.reset_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
register "generic.reset_delay_ms" = "30"
register "generic.reset_off_delay_ms" = "3"
register "generic.reset_delay_ms" = "10"
register "generic.reset_off_delay_ms" = "1"
register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 5d on end
Expand Down
4 changes: 2 additions & 2 deletions src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb
View file
Expand Up @@ -63,8 +63,8 @@ chip soc/intel/cannonlake
register "generic.probed" = "1"
register "generic.reset_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
register "generic.reset_delay_ms" = "30"
register "generic.reset_off_delay_ms" = "3"
register "generic.reset_delay_ms" = "10"
register "generic.reset_off_delay_ms" = "1"
register "generic.has_power_resource" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 5d on end
Expand Down
29 changes: 6 additions & 23 deletions src/mainboard/google/hatch/variants/kohaku/memory.c
View file
Expand Up @@ -15,7 +15,6 @@

#include <baseboard/variants.h>
#include <baseboard/gpio.h>
#include <gpio.h>
#include <soc/cnl_memcfg_init.h>
#include <string.h>

Expand All @@ -30,8 +29,8 @@ static const struct cnl_mb_cfg baseboard_memcfg = {
* the index = pin number on SoC
* the value = pin number on lpddr3 part
*/
.dqs_map[DDR_CH0] = { 0, 1, 3, 2, 5, 7, 6, 4 },
.dqs_map[DDR_CH1] = { 1, 3, 2, 0, 5, 7, 6, 4 },
.dqs_map[DDR_CH0] = {0, 1, 3, 2, 5, 7, 6, 4},
.dqs_map[DDR_CH1] = {1, 3, 2, 0, 5, 7, 6, 4},

.dq_map[DDR_CH0] = {
{0xf, 0xf0},
Expand All @@ -40,21 +39,21 @@ static const struct cnl_mb_cfg baseboard_memcfg = {
{0xf, 0x0},
{0xff, 0x0},
{0xff, 0x0}
},
},
.dq_map[DDR_CH1] = {
{0xf, 0xf0},
{0x0, 0xf0},
{0xf, 0xf0},
{0xf, 0x0},
{0xff, 0x0},
{0xff, 0x0}
},
},

/* Kohaku uses 200, 80.6 and 162 rcomp resistors */
.rcomp_resistor = { 200, 81, 162 },
.rcomp_resistor = {200, 81, 162},

/* Kohaku Rcomp target values */
.rcomp_targets = { 100, 40, 40, 23, 40 },
.rcomp_targets = {100, 40, 40, 23, 40},

/* Set CaVref config to 0 for LPDDR3 */
.vref_ca_config = 0,
Expand All @@ -66,20 +65,4 @@ static const struct cnl_mb_cfg baseboard_memcfg = {
void variant_memory_params(struct cnl_mb_cfg *bcfg)
{
memcpy(bcfg, &baseboard_memcfg, sizeof(baseboard_memcfg));
/*
* GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single
* channel skus and 0 for dual channel skus.
*/
if (gpio_get(GPP_F2) == 1) {
/*
* Single channel config: for kohaku, Channel 0 is
* always populated.
*/
bcfg->channel_empty[0] = 0;
bcfg->channel_empty[1] = 1;
} else {
/* Dual channel config: both channels populated. */
bcfg->channel_empty[0] = 0;
bcfg->channel_empty[1] = 0;
}
}
2 changes: 1 addition & 1 deletion src/mainboard/google/hatch/variants/kohaku/overridetree.cb
View file
Expand Up @@ -90,7 +90,7 @@ chip soc/intel/cannonlake
chip drivers/i2c/da7219
# TODO: these settings were copied from another board
# with the same chip. verify the settings
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H0_IRQ)"
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
register "btn_cfg" = "50"
register "mic_det_thr" = "500"
register "jack_ins_deb" = "20"
Expand Down
7 changes: 6 additions & 1 deletion src/mainboard/google/jecht/Makefile.inc
View file
Expand Up @@ -16,14 +16,19 @@
subdirs-y += spd
romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
verstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-y += lan.c

smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c led.c

romstage-y += variants/$(VARIANT_DIR)/pei_data.c
ramstage-y += variants/$(VARIANT_DIR)/pei_data.c

romstage-y += led.c
bootblock-y += led.c

bootblock-y += bootblock.c

subdirs-y += variants/$(VARIANT_DIR)
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include

romstage-y += variants/$(VARIANT_DIR)/gpio.c
31 changes: 31 additions & 0 deletions src/mainboard/google/jecht/bootblock.c
View file
@@ -0,0 +1,31 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2010 coresystems GmbH
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include <bootblock_common.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8772f/it8772f.h>
#include "onboard.h"

void bootblock_mainboard_early_init(void)
{
/* Early SuperIO setup */
it8772f_ac_resume_southbridge(IT8772F_SUPERIO_DEV);
ite_kill_watchdog(IT8772F_GPIO_DEV);
ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE);

/* Turn On Power LED */
set_power_led(LED_ON);
}
2 changes: 1 addition & 1 deletion src/mainboard/google/jecht/chromeos.c
View file
Expand Up @@ -37,7 +37,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
{GPIO_SPI_WP, ACTIVE_HIGH,
get_write_protect_state(), "write protect"},
{GPIO_REC_MODE, ACTIVE_LOW,
!get_recovery_mode_switch(), "recovery"},
!get_recovery_mode_switch(), "presence"},
{-1, ACTIVE_HIGH, 1, "lid"},
{-1, ACTIVE_HIGH, 0, "power"},
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
Expand Down
35 changes: 6 additions & 29 deletions src/mainboard/google/jecht/romstage.c
View file
Expand Up @@ -18,47 +18,24 @@
#include <console/console.h>
#include <string.h>
#include <ec/google/chromeec/ec.h>
#include <soc/gpio.h>
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
#include <soc/romstage.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8772f/it8772f.h>
#include <mainboard/google/jecht/spd/spd.h>
#include <variant/gpio.h>
#include "onboard.h"


void mainboard_romstage_entry(struct romstage_params *rp)
void mainboard_pre_raminit(struct romstage_params *rp)
{
struct pei_data pei_data;

post_code(0x32);

/* Initialize GPIOs */
init_gpios(mainboard_gpio_config);

/* Fill out PEI DATA */
memset(&pei_data, 0, sizeof(pei_data));
mainboard_fill_pei_data(&pei_data);
mainboard_fill_spd_data(&pei_data);
rp->pei_data = &pei_data;

/* Call into the real romstage main with this board's attributes. */
romstage_common(rp);

if (CONFIG(CHROMEOS))
init_bootmode_straps();
mainboard_fill_pei_data(&rp->pei_data);
mainboard_fill_spd_data(&rp->pei_data);
}

void mainboard_pre_console_init(void)
void mainboard_post_raminit(struct romstage_params *rp)
{
/* Early SuperIO setup */
it8772f_ac_resume_southbridge(IT8772F_SUPERIO_DEV);
ite_kill_watchdog(IT8772F_GPIO_DEV);
ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE);

/* Turn On Power LED */
set_power_led(LED_ON);

if (CONFIG(CHROMEOS))
init_bootmode_straps();
}
7 changes: 1 addition & 6 deletions ...cht/variants/guado/include/variant/gpio.h → ...nboard/google/jecht/variants/guado/gpio.c
View file
Expand Up @@ -13,12 +13,9 @@
* GNU General Public License for more details.
*/

#ifndef GUADO_GPIO_H
#define GUADO_GPIO_H

#include <soc/gpio.h>

static const struct gpio_config mainboard_gpio_config[] = {
const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 0: UNUSED */
PCH_GPIO_UNUSED, /* 1: UNUSED */
PCH_GPIO_UNUSED, /* 2: UNUSED */
Expand Down Expand Up @@ -116,5 +113,3 @@ static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 94: UNUSED */
PCH_GPIO_END
};

#endif
7 changes: 1 addition & 6 deletions ...cht/variants/jecht/include/variant/gpio.h → ...nboard/google/jecht/variants/jecht/gpio.c
View file
Expand Up @@ -13,12 +13,9 @@
* GNU General Public License for more details.
*/

#ifndef JECHT_GPIO_H
#define JECHT_GPIO_H

#include <soc/gpio.h>

static const struct gpio_config mainboard_gpio_config[] = {
const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 0: UNUSED */
PCH_GPIO_UNUSED, /* 1: UNUSED */
PCH_GPIO_UNUSED, /* 2: UNUSED */
Expand Down Expand Up @@ -116,5 +113,3 @@ static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 94: UNUSED */
PCH_GPIO_END
};

#endif
7 changes: 1 addition & 6 deletions ...cht/variants/rikku/include/variant/gpio.h → ...nboard/google/jecht/variants/rikku/gpio.c
View file
Expand Up @@ -13,12 +13,9 @@
* GNU General Public License for more details.
*/

#ifndef RIKKU_GPIO_H
#define RIKKU_GPIO_H

#include <soc/gpio.h>

static const struct gpio_config mainboard_gpio_config[] = {
const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 0: UNUSED */
PCH_GPIO_UNUSED, /* 1: UNUSED */
PCH_GPIO_UNUSED, /* 2: UNUSED */
Expand Down Expand Up @@ -116,5 +113,3 @@ static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 94: UNUSED */
PCH_GPIO_END
};

#endif
7 changes: 1 addition & 6 deletions ...cht/variants/tidus/include/variant/gpio.h → ...nboard/google/jecht/variants/tidus/gpio.c
View file
Expand Up @@ -13,12 +13,9 @@
* GNU General Public License for more details.
*/

#ifndef TIDUS_GPIO_H
#define TIDUS_GPIO_H

#include <soc/gpio.h>

static const struct gpio_config mainboard_gpio_config[] = {
const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 0: UNUSED */
PCH_GPIO_UNUSED, /* 1: UNUSED */
PCH_GPIO_UNUSED, /* 2: UNUSED */
Expand Down Expand Up @@ -116,5 +113,3 @@ static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_UNUSED, /* 94: UNUSED */
PCH_GPIO_END
};

#endif
1 change: 0 additions & 1 deletion src/mainboard/google/kahlee/chromeos.c
View file
Expand Up @@ -24,7 +24,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio chromeos_gpios[] = {
{-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
{-1, ACTIVE_HIGH, 0, "power"},
{GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW),
Expand Down
5 changes: 3 additions & 2 deletions src/mainboard/google/kahlee/mainboard.c
View file
Expand Up @@ -27,6 +27,7 @@
#include <soc/nvs.h>
#include <soc/pci_devs.h>
#include <soc/southbridge.h>
#include <amdblocks/acpimmio.h>
#include <variant/ec.h>
#include <variant/thermal.h>
#include <vendorcode/google/chromeos/chromeos.h>
Expand Down Expand Up @@ -145,13 +146,13 @@ static void mainboard_init(void *chip_info)
pm_write8(PM_PCIB_CFG, pm_read8(PM_PCIB_CFG) | PM_GENINT_DISABLE);

/* Set low-power mode for BayHub eMMC bridge's PCIe clock. */
clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL),
clrsetbits_le32((uint32_t *)(ACPIMMIO_MISC_BASE + GPP_CLK_CNTRL),
GPP_CLK2_REQ_MAP_MASK,
GPP_CLK2_REQ_MAP_CLK_REQ2 <<
GPP_CLK2_REQ_MAP_SHIFT);

/* Same for the WiFi */
clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL),
clrsetbits_le32((uint32_t *)(ACPIMMIO_MISC_BASE + GPP_CLK_CNTRL),
GPP_CLK0_REQ_MAP_MASK,
GPP_CLK0_REQ_MAP_CLK_REQ0 <<
GPP_CLK0_REQ_MAP_SHIFT);
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/audio.asl
View file
Expand Up @@ -35,7 +35,7 @@ Device (I2S)
Name (RBUF, ResourceTemplate () {
// Memory resource is for MISC FCH register set.
// It is needed for enabling the clock.
Memory32Fixed(ReadWrite, MISC_MMIO_BASE, 0x100)
Memory32Fixed(ReadWrite, ACPIMMIO_MISC_BASE, 0x100)
})

Return (RBUF)
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/google/kahlee/variants/baseboard/spd/micron-MT40A512M16TB-062E-J.spd.hex
View file
Expand Up @@ -6,7 +6,7 @@
16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 60 5B
00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 30 53
0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/google/kukui/chromeos.c
View file
Expand Up @@ -35,7 +35,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
struct lb_gpio chromeos_gpios[] = {
{GPIO_WP.id, ACTIVE_LOW,
!get_write_protect_state(), "write protect"},
{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
{EC_IN_RW.id, ACTIVE_HIGH, -1, "EC in RW"},
{EC_IRQ.id, ACTIVE_LOW, -1, "EC interrupt"},
{CR50_IRQ.id, ACTIVE_HIGH, -1, "TPM interrupt"},
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/google/link/Kconfig
View file
Expand Up @@ -3,7 +3,7 @@ if BOARD_GOOGLE_LINK
config BOARD_SPECIFIC_OPTIONS
def_bool y
select SYSTEM_TYPE_LAPTOP
select NORTHBRIDGE_INTEL_IVYBRIDGE
select NORTHBRIDGE_INTEL_SANDYBRIDGE
select SOUTHBRIDGE_INTEL_C216
select BOARD_ROMSIZE_KB_8192
select EC_GOOGLE_CHROMEEC
Expand Down
4 changes: 0 additions & 4 deletions src/mainboard/google/link/chromeos.c
View file
Expand Up @@ -28,10 +28,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
/* Write Protect: GPIO57 = PCH_SPI_WP_D */
{57, ACTIVE_HIGH, get_write_protect_state(), "write protect"},

/* Recovery: the "switch" comes from the EC */
/* -1 indicates that this is a pseudo GPIO */
{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},

/* Lid: the "switch" comes from the EC */
{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},

Expand Down
9 changes: 6 additions & 3 deletions src/mainboard/google/link/mainboard.c
View file
Expand Up @@ -170,7 +170,8 @@ static int link_onboard_smbios_data(struct device *dev, int *handle,
0, /* segment */
BOARD_LIGHTSENSOR_I2C_ADDR, /* bus */
0, /* device */
0); /* function */
0, /* function */
SMBIOS_DEVICE_TYPE_OTHER); /* device type */

len += smbios_write_type41(
current, handle,
Expand All @@ -179,7 +180,8 @@ static int link_onboard_smbios_data(struct device *dev, int *handle,
0, /* segment */
BOARD_TRACKPAD_I2C_ADDR, /* bus */
0, /* device */
0); /* function */
0, /* function */
SMBIOS_DEVICE_TYPE_OTHER); /* device type */

len += smbios_write_type41(
current, handle,
Expand All @@ -188,7 +190,8 @@ static int link_onboard_smbios_data(struct device *dev, int *handle,
0, /* segment */
BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */
0, /* device */
0); /* function */
0, /* function */
SMBIOS_DEVICE_TYPE_OTHER); /* device type */

return len;
}
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/google/mistral/bootblock.c
View file
Expand Up @@ -14,7 +14,6 @@
*/

#include <bootblock_common.h>
#include <timestamp.h>

void bootblock_mainboard_init(void)
{
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/google/mistral/mainboard.c
View file
Expand Up @@ -15,7 +15,6 @@

#include <device/device.h>
#include <bootblock_common.h>
#include <timestamp.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <soc/usb.h>

Expand Down
1 change: 0 additions & 1 deletion src/mainboard/google/nyan/chromeos.c
View file
Expand Up @@ -22,7 +22,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
struct lb_gpio chromeos_gpios[] = {
{GPIO(R1), ACTIVE_LOW, !get_write_protect_state(),
"write protect"},
{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
{GPIO(R4), ACTIVE_HIGH, -1, "lid"},
{GPIO(Q0), ACTIVE_LOW, -1, "power"},
{GPIO(U4), ACTIVE_HIGH, -1, "EC in RW"},
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/google/nyan_big/chromeos.c
View file
Expand Up @@ -22,7 +22,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
struct lb_gpio chromeos_gpios[] = {
{GPIO(R1), ACTIVE_LOW,
!get_write_protect_state(), "write protect"},
{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
{GPIO(R4), ACTIVE_HIGH, -1, "lid"},
{GPIO(Q0), ACTIVE_LOW, -1, "power"},
{GPIO(U4), ACTIVE_HIGH, -1, "EC in RW"},
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/google/nyan_blaze/chromeos.c
View file
Expand Up @@ -22,7 +22,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
struct lb_gpio chromeos_gpios[] = {
{GPIO(R1), ACTIVE_LOW, !get_write_protect_state(),
"write protect"},
{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
{GPIO(R4), ACTIVE_HIGH, -1, "lid"},
{GPIO(Q0), ACTIVE_LOW, -1, "power"},
{GPIO(U4), ACTIVE_HIGH, -1, "EC in RW"},
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/google/oak/chromeos.c
View file
Expand Up @@ -36,7 +36,6 @@ void fill_lb_gpios(struct lb_gpios *gpios)
struct lb_gpio chromeos_gpios[] = {
{WRITE_PROTECT.id, ACTIVE_LOW,
!get_write_protect_state(), "write protect"},
{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
{LID.id, ACTIVE_HIGH, -1, "lid"},
{POWER_BUTTON.id, ACTIVE_HIGH, -1, "power"},
{EC_IN_RW.id, ACTIVE_HIGH, -1, "EC in RW"},
Expand Down
3 changes: 3 additions & 0 deletions src/mainboard/google/octopus/Kconfig
View file
Expand Up @@ -59,6 +59,7 @@ config VARIANT_DIR
default "casta" if BOARD_GOOGLE_CASTA
default "bloog" if BOARD_GOOGLE_BLOOG
default "octopus" if BOARD_GOOGLE_OCTOPUS
default "garg" if BOARD_GOOGLE_GARG

config DEVICETREE
string
Expand All @@ -79,6 +80,7 @@ config MAINBOARD_PART_NUMBER
default "Casta" if BOARD_GOOGLE_CASTA
default "Bloog" if BOARD_GOOGLE_BLOOG
default "Octopus" if BOARD_GOOGLE_OCTOPUS
default "Garg" if BOARD_GOOGLE_GARG

config MAINBOARD_FAMILY
string
Expand All @@ -96,6 +98,7 @@ config GBB_HWID
default "CASTA TEST 8105" if BOARD_GOOGLE_CASTA
default "BLOOG TEST 2509" if BOARD_GOOGLE_BLOOG
default "OCTOPUS TEST 6859" if BOARD_GOOGLE_OCTOPUS
default "GARG TEST 1337" if BOARD_GOOGLE_GARG

config MAX_CPUS
int
Expand Down