4 changes: 2 additions & 2 deletions src/lib/coreboot_table.c
View file
Expand Up @@ -314,7 +314,7 @@ static struct lb_board_config *lb_board_config(struct lb_header *header)
config->board_id = board_id();
config->ram_code = ram_code();
config->sku_id = sku_id();
config->fw_config = pack_lb64(fw_config);
config->fw_config = fw_config;

if (config->board_id != UNDEFINED_STRAPPING_ID)
printk(BIOS_INFO, "Board ID: %d\n", config->board_id);
Expand Down Expand Up @@ -429,7 +429,7 @@ static void lb_add_acpi_rsdp(struct lb_header *head)
acpi_rsdp = (struct lb_acpi_rsdp *)rec;
acpi_rsdp->tag = LB_TAG_ACPI_RSDP;
acpi_rsdp->size = sizeof(*acpi_rsdp);
acpi_rsdp->rsdp_pointer = pack_lb64(get_coreboot_rsdp());
acpi_rsdp->rsdp_pointer = get_coreboot_rsdp();
}

size_t write_coreboot_forwarding_table(uintptr_t entry, uintptr_t target)
Expand Down
9 changes: 1 addition & 8 deletions src/mainboard/amd/chausie/chromeos.c
View file
Expand Up @@ -18,11 +18,4 @@ int get_write_protect_state(void)
return 0;
}

static const struct cros_gpio cros_gpios[] = {
/* No ChromeOS GPIOs */
};

void mainboard_chromeos_acpi_generate(void)
{
chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
}
DECLARE_NO_CROS_GPIOS();
9 changes: 3 additions & 6 deletions src/mainboard/amd/chausie/devicetree.cb
View file
Expand Up @@ -28,12 +28,9 @@ chip soc/amd/sabrina

device domain 0 on
device ref iommu on end
device ref gpp_bridge_0 on end # NVMe
device ref gpp_bridge_1 on end
device ref gpp_bridge_2 on end # WWAN
device ref gpp_bridge_3 on end # LAN
device ref gpp_bridge_4 on end # WLAN
device ref gpp_bridge_5 on end
device ref gpp_bridge_0 on end # GBE
device ref gpp_bridge_1 on end # WIFI
device ref gpp_bridge_2 on end # NVMe SSD
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
device ref gfx on end # Internal GPU (GFX)
device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)
Expand Down
119 changes: 37 additions & 82 deletions src/mainboard/amd/chausie/port_descriptors.c
View file
Expand Up @@ -4,128 +4,83 @@
#include <soc/platform_descriptors.h>
#include <types.h>

static const fsp_dxio_descriptor chausie_czn_dxio_descriptors[] = {
{ /* MXM */
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 16,
.end_logical_lane = 23,
.device_number = 1,
.function_number = 1,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ0,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
},
{ /* SSD */
static const fsp_dxio_descriptor chausie_dxio_descriptors[] = {
{ /* GBE*/
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 0,
.end_logical_lane = 1,
.end_logical_lane = 0,
.device_number = 2,
.function_number = 1,
.link_speed_capability = GEN3,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ5,
.gpio_group_id = GPIO_40,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
.link_aspm = 2,
.link_hotplug = 3,
.clk_req = CLK_REQ3,
},
{ /* DT */
{ /* WIFI */
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 4,
.end_logical_lane = 4,
.start_logical_lane = 1,
.end_logical_lane = 1,
.device_number = 2,
.function_number = 2,
.link_speed_capability = GEN3,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ4_GFX,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
},
{ /* WWAN */
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 5,
.end_logical_lane = 5,
.device_number = 2,
.function_number = 3,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ2,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
},
{ /* LAN */
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 6,
.end_logical_lane = 6,
.device_number = 2,
.function_number = 4,
.turn_off_unused_lanes = true,
.link_aspm = 2,
.link_hotplug = 3,
.clk_req = CLK_REQ1,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
},
{ /* WLAN */
{ /* NVMe SSD */
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 7,
.end_logical_lane = 7,
.device_number = 2,
.function_number = 5,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ6,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
},
{ /* TB */
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 8,
.end_logical_lane = 11,
.start_logical_lane = 2,
.end_logical_lane = 3,
.device_number = 2,
.function_number = 6,
.function_number = 3,
.link_speed_capability = GEN3,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ3,
.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
.link_aspm = 2,
.link_hotplug = 3,
.gpio_group_id = GPIO_27,
.clk_req = CLK_REQ0,
},
{ /* SATA */
.engine_type = SATA_ENGINE,
.port_present = true,
.start_logical_lane = 2,
.end_logical_lane = 3,
.channel_type = SATA_CHANNEL_LONG,
}
};

static const fsp_ddi_descriptor chausie_czn_ddi_descriptors[] = {
{ /* DDI0 - DP */
.connector_type = DDI_DP,
static const fsp_ddi_descriptor chausie_ddi_descriptors[] = {
{ /* DDI0 - eDP */
.connector_type = DDI_EDP,
.aux_index = DDI_AUX1,
.hdp_index = DDI_HDP1
},
{ /* DDI1 - HDMI */
{ /* DDI1 - HDMI - TODO: add runtime HDMI/DP connector card detection */
.connector_type = DDI_HDMI,
.aux_index = DDI_AUX2,
.hdp_index = DDI_HDP2
},
{ /* DDI2 */
.connector_type = DDI_UNUSED_TYPE,
.aux_index = DDI_AUX3,
.hdp_index = DDI_HDP3,
},
{ /* DDI3 - DP (type C) */
{ /* DDI2 - DP (type C) */
.connector_type = DDI_DP,
.aux_index = DDI_AUX3,
.hdp_index = DDI_HDP3,
},
{ /* DDI4 - DP (type C) */
{ /* DDI3 - DP (type C) */
.connector_type = DDI_DP,
.aux_index = DDI_AUX4,
.hdp_index = DDI_HDP4,
},
{ /* DDI4 - unused */
.connector_type = DDI_UNUSED_TYPE,
.aux_index = DDI_AUX5,
.hdp_index = DDI_HDP5,
}
};

void mainboard_get_dxio_ddi_descriptors(
const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
{
*dxio_descs = chausie_czn_dxio_descriptors;
*dxio_num = ARRAY_SIZE(chausie_czn_dxio_descriptors);
*ddi_descs = chausie_czn_ddi_descriptors;
*ddi_num = ARRAY_SIZE(chausie_czn_ddi_descriptors);
*dxio_descs = chausie_dxio_descriptors;
*dxio_num = ARRAY_SIZE(chausie_dxio_descriptors);
*ddi_descs = chausie_ddi_descriptors;
*ddi_num = ARRAY_SIZE(chausie_ddi_descriptors);
}
4 changes: 0 additions & 4 deletions src/mainboard/amd/inagua/BiosCallOuts.c
View file
Expand Up @@ -28,13 +28,11 @@ const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
UINTN FcnData;
MEM_DATA_STRUCT *MemData;
UINT32 GpioMmioAddr;
UINT8 Data8;
UINT8 TempData8;

FcnData = Data;
MemData = ConfigPtr;

Status = AGESA_SUCCESS;
Expand Down Expand Up @@ -101,13 +99,11 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
UINTN FcnData;
PCIe_SLOT_RESET_INFO *ResetInfo;

UINT32 GpioMmioAddr;
UINT8 Data8;

FcnData = Data;
ResetInfo = ConfigPtr;
GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
Status = AGESA_UNSUPPORTED;
Expand Down
9 changes: 1 addition & 8 deletions src/mainboard/amd/majolica/chromeos.c
View file
Expand Up @@ -18,11 +18,4 @@ int get_write_protect_state(void)
return 0;
}

static const struct cros_gpio cros_gpios[] = {
/* No ChromeOS GPIOs */
};

void mainboard_chromeos_acpi_generate(void)
{
chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
}
DECLARE_NO_CROS_GPIOS();
14 changes: 7 additions & 7 deletions src/mainboard/amd/majolica/port_descriptors.c
View file
Expand Up @@ -5,7 +5,7 @@
#include <types.h>
#include <amdblocks/cpu.h>

static const fsp_dxio_descriptor majolica_czn_dxio_descriptors[] = {
static const fsp_dxio_descriptor majolica_dxio_descriptors[] = {
{ /* MXM */
.engine_type = PCIE_ENGINE,
.port_present = true,
Expand Down Expand Up @@ -93,7 +93,7 @@ static const fsp_dxio_descriptor majolica_czn_dxio_descriptors[] = {
}
};

static fsp_ddi_descriptor majolica_czn_ddi_descriptors[] = {
static fsp_ddi_descriptor majolica_ddi_descriptors[] = {
{ /* DDI0 - DP */
.connector_type = DDI_DP,
.aux_index = DDI_AUX1,
Expand Down Expand Up @@ -126,10 +126,10 @@ void mainboard_get_dxio_ddi_descriptors(
const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
{
if ((get_cpu_count() == 4 && get_threads_per_core() == 2) || get_cpu_count() == 2)
majolica_czn_ddi_descriptors[1].connector_type = DDI_UNUSED_TYPE;
majolica_ddi_descriptors[1].connector_type = DDI_UNUSED_TYPE;

*dxio_descs = majolica_czn_dxio_descriptors;
*dxio_num = ARRAY_SIZE(majolica_czn_dxio_descriptors);
*ddi_descs = majolica_czn_ddi_descriptors;
*ddi_num = ARRAY_SIZE(majolica_czn_ddi_descriptors);
*dxio_descs = majolica_dxio_descriptors;
*dxio_num = ARRAY_SIZE(majolica_dxio_descriptors);
*ddi_descs = majolica_ddi_descriptors;
*ddi_num = ARRAY_SIZE(majolica_ddi_descriptors);
}
2 changes: 0 additions & 2 deletions src/mainboard/amd/persimmon/BiosCallOuts.c
View file
Expand Up @@ -36,13 +36,11 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
UINTN FcnData;
PCIe_SLOT_RESET_INFO *ResetInfo;

UINT32 GpioMmioAddr;
UINT8 Data8;

FcnData = Data;
ResetInfo = ConfigPtr;
Status = AGESA_UNSUPPORTED;
GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
Expand Down
4 changes: 0 additions & 4 deletions src/mainboard/amd/south_station/BiosCallOuts.c
View file
Expand Up @@ -28,13 +28,11 @@ const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
UINTN FcnData;
MEM_DATA_STRUCT *MemData;
UINT32 GpioMmioAddr;
UINT8 Data8;
UINT8 TempData8;

FcnData = Data;
MemData = ConfigPtr;

Status = AGESA_SUCCESS;
Expand Down Expand Up @@ -101,14 +99,12 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
UINTN FcnData;
PCIe_SLOT_RESET_INFO *ResetInfo;
UINT32 GpioMmioAddr;
UINT8 Data8;

GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;

FcnData = Data;
ResetInfo = ConfigPtr;
Status = AGESA_UNSUPPORTED;
switch (ResetInfo->ResetId) {
Expand Down
4 changes: 0 additions & 4 deletions src/mainboard/amd/union_station/BiosCallOuts.c
View file
Expand Up @@ -28,13 +28,11 @@ const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
UINTN FcnData;
MEM_DATA_STRUCT *MemData;
UINT32 GpioMmioAddr;
UINT8 Data8;
UINT8 TempData8;

FcnData = Data;
MemData = ConfigPtr;

Status = AGESA_SUCCESS;
Expand Down Expand Up @@ -101,14 +99,12 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
UINTN FcnData;
PCIe_SLOT_RESET_INFO *ResetInfo;
UINT32 GpioMmioAddr;
UINT8 Data8;

GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;

FcnData = Data;
ResetInfo = ConfigPtr;
Status = AGESA_UNSUPPORTED;
switch (ResetInfo->ResetId) {
Expand Down
2 changes: 0 additions & 2 deletions src/mainboard/asrock/e350m1/BiosCallOuts.c
View file
Expand Up @@ -25,13 +25,11 @@ const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
UINTN FcnData;
MEM_DATA_STRUCT *MemData;
UINT32 GpioMmioAddr;
UINT8 Data8;
UINT8 TempData8;

FcnData = Data;
MemData = ConfigPtr;

Status = AGESA_SUCCESS;
Expand Down
63 changes: 63 additions & 0 deletions src/mainboard/clevo/tgl-u/Kconfig
View file
@@ -0,0 +1,63 @@
config BOARD_CLEVO_TGLU_COMMON
def_bool n
select BOARD_ROMSIZE_KB_16384
select DRIVERS_I2C_HID
select DRIVERS_INTEL_PMC
select DRIVERS_INTEL_USB4_RETIMER
select HAVE_ACPI_TABLES
select HAVE_CMOS_DEFAULT
select HAVE_OPTION_TABLE
select INTEL_GMA_HAVE_VBT
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_LPC_TPM
select MAINBOARD_HAS_TPM2
select NO_UART_ON_SUPERIO
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
select SOC_INTEL_TIGERLAKE
select SPD_READ_BY_WORD
select SYSTEM_TYPE_LAPTOP

config BOARD_CLEVO_L140MU
select BOARD_CLEVO_TGLU_COMMON
select HAVE_SPD_IN_CBFS

if BOARD_CLEVO_TGLU_COMMON

config MAINBOARD_DIR
default "clevo/tgl-u"

config VARIANT_DIR
default "l140mu" if BOARD_CLEVO_L140MU

config MAINBOARD_PART_NUMBER
default "L140MU" if BOARD_CLEVO_L140MU

config MAINBOARD_VERSION
default "2.2A" if BOARD_CLEVO_L140MU

config DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"

config CBFS_SIZE
default 0xb00000 if BOARD_CLEVO_L140MU

config CONSOLE_POST
default y

config UART_FOR_CONSOLE
default 2

config TPM_PIRQ
default 0x77 if BOARD_CLEVO_L140MU # GPP_C9_IRQ

config POST_DEVICE
default n

config SEABIOS_PS2_TIMEOUT
default 500

config USE_PM_ACPI_TIMER
default n

endif
4 changes: 4 additions & 0 deletions src/mainboard/clevo/tgl-u/Kconfig.name
View file
@@ -0,0 +1,4 @@
comment "Tiger Lake U"

config BOARD_CLEVO_L140MU
bool "L140MU / L141MU / L142MU"
14 changes: 14 additions & 0 deletions src/mainboard/clevo/tgl-u/Makefile.inc
View file
@@ -0,0 +1,14 @@
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include

bootblock-y += bootblock.c
bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c

romstage-y += romstage.c
romstage-y += variants/$(VARIANT_DIR)/romstage.c

ramstage-y += ramstage.c
ramstage-y += variants/$(VARIANT_DIR)/ramstage.c
ramstage-y += variants/$(VARIANT_DIR)/gpio.c
ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c

subdirs-y += variants/$(VARIANT_DIR)
6 changes: 6 additions & 0 deletions src/mainboard/clevo/tgl-u/board_info.txt
View file
@@ -0,0 +1,6 @@
Vendor name: Clevo
Category: laptop
ROM package: SOIC-8
ROM protocol: SPI
ROM socketed: n
Flashrom support: y
9 changes: 9 additions & 0 deletions src/mainboard/clevo/tgl-u/bootblock.c
View file
@@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <bootblock_common.h>
#include <variant/gpio.h>

void bootblock_mainboard_early_init(void)
{
variant_configure_early_gpios();
}
3 changes: 3 additions & 0 deletions src/mainboard/clevo/tgl-u/cmos.default
View file
@@ -0,0 +1,3 @@
boot_option=Fallback
debug_level=Debug
power_on_after_fail=Disable
57 changes: 57 additions & 0 deletions src/mainboard/clevo/tgl-u/cmos.layout
View file
@@ -0,0 +1,57 @@
# SPDX-License-Identifier: GPL-2.0-only

# -----------------------------------------------------------------
entries

# start-bit length config config-ID name
0 120 r 0 reserved_memory

# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter

# -----------------------------------------------------------------
# coreboot config options: console
395 4 e 6 debug_level

# -----------------------------------------------------------------
# coreboot config options: southbridge
410 2 e 7 power_on_after_fail

# -----------------------------------------------------------------
# vboot nv area
800 128 r 0 vbnv

# -----------------------------------------------------------------
# coreboot config options: check sums
984 16 h 0 check_sum

# -----------------------------------------------------------------

enumerations

#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep

# -----------------------------------------------------------------
checksums

checksum 392 799 984
32 changes: 32 additions & 0 deletions src/mainboard/clevo/tgl-u/dsdt.asl
View file
@@ -0,0 +1,32 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <acpi/acpi.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20110725
)
{
#include <acpi/dsdt_top.asl>
#include <soc/intel/common/block/acpi/acpi/platform.asl>
#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
#include <cpu/intel/common/acpi/cpu.asl>

Device (\_SB.PCI0)
{
#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
#include <soc/intel/tigerlake/acpi/southbridge.asl>
#include <soc/intel/tigerlake/acpi/tcss.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
}

Scope (\_SB.PCI0.LPCB)
{
#include <drivers/pc80/pc/ps2_controller.asl>
}

#include <southbridge/intel/common/acpi/sleepstates.asl>
}
9 changes: 9 additions & 0 deletions src/mainboard/clevo/tgl-u/include/variant/gpio.h
View file
@@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H

void variant_configure_early_gpios(void);
void variant_configure_gpios(void);

#endif
8 changes: 8 additions & 0 deletions src/mainboard/clevo/tgl-u/include/variant/ramstage.h
View file
@@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#ifndef VARIANT_RAMSTAGE_H
#define VARIANT_RAMSTAGE_H

void variant_configure_fsps(FSP_S_CONFIG *params);

#endif
8 changes: 8 additions & 0 deletions src/mainboard/clevo/tgl-u/include/variant/romstage.h
View file
@@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#ifndef VARIANT_ROMSTAGE_H
#define VARIANT_ROMSTAGE_H

void variant_configure_fspm(FSPM_UPD *memupd);

#endif
20 changes: 20 additions & 0 deletions src/mainboard/clevo/tgl-u/ramstage.c
View file
@@ -0,0 +1,20 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <device/device.h>
#include <soc/ramstage.h>
#include <variant/gpio.h>
#include <variant/ramstage.h>

void mainboard_silicon_init_params(FSP_S_CONFIG *params)
{
variant_configure_fsps(params);
}

static void init_mainboard(void *chip_info)
{
variant_configure_gpios();
}

struct chip_operations mainboard_ops = {
.init = init_mainboard,
};
9 changes: 9 additions & 0 deletions src/mainboard/clevo/tgl-u/romstage.c
View file
@@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <soc/romstage.h>
#include <variant/romstage.h>

void mainboard_memory_init_params(FSPM_UPD *memupd)
{
variant_configure_fspm(memupd);
}
32 changes: 32 additions & 0 deletions src/mainboard/clevo/tgl-u/spd/samsung-M471A1G44AB0-CWE.spd.hex
View file
@@ -0,0 +1,32 @@
23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00
00 00 05 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A
20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 E8 F5
0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80 CE 00 00 00 00 00 00 00 4D 34 37 31 41 31 47
34 34 41 42 30 2D 43 57 45 20 20 20 20 00 80 CE
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
1 change: 1 addition & 0 deletions src/mainboard/clevo/tgl-u/variants/l140mu/Makefile.inc
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SPD_SOURCES = samsung-M471A1G44AB0-CWE
2 changes: 2 additions & 0 deletions src/mainboard/clevo/tgl-u/variants/l140mu/board_info.txt
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Board name: L140MU
Release year: 2021
Binary file added src/mainboard/clevo/tgl-u/variants/l140mu/data.vbt
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Binary file not shown.
249 changes: 249 additions & 0 deletions src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb
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chip soc/intel/tigerlake
device cpu_cluster 0 on
register "tcc_offset" = "12"
register "eist_enable" = "true"
device lapic 0 on end
end
device domain 0 on
subsystemid 0x1558 0x14a1 inherit
device ref system_agent on
register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{
.tdp_pl1_override = 20,
.tdp_pl2_override = 30,
.psys_pmax = 65,
}"
register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{
.tdp_pl1_override = 20,
.tdp_pl2_override = 30,
.psys_pmax = 65,
}"
register "SaGv" = "SaGv_Enabled"
register "enable_c6dram" = "true"
end
device ref igpu on
register "gfx" = "GMA_DEFAULT_PANEL(0)"
# eDP
register "DdiPortAConfig" = "1"
register "DdiPortAHpd" = "1"
register "DdiPortADdc" = "0"
# HDMI
register "DdiPortBConfig" = "0"
register "DdiPortBHpd" = "1"
register "DdiPortBDdc" = "1"
end
device ref dptf on end
device ref tbt_pcie_rp0 on end
device ref tbt_dma0 on
chip drivers/intel/usb4/retimer
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)"
use tcss_usb3_port1 as dfp[0].typec_port
device generic 0 on end
end
end
device ref north_xhci on
register "UsbTcPortEn" = "true"
register "TcssXhciEn" = "true"
chip drivers/usb/acpi
device ref tcss_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB3 J_TYPEC1""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(1, 1)"
device ref tcss_usb3_port1 on end
end
end
end
end
device ref south_xhci on
# USB2
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A, left (J_USB3_1)
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A, right (J_USB3_2)
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C (J_TYPEC1)
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # 3G/LTE
register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
# USB3
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, left (J_USB3_1)
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, right (J_USB3_2)
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 3G/LTE
# ACPI
chip drivers/usb/acpi
device ref xhci_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB2 J_USB3_1""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(1, 2)"
device ref usb2_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 J_USB3_2""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(2, 1)"
device ref usb2_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 J_TYPEC1""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "group" = "ACPI_PLD_GROUP(1, 1)"
device ref usb2_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 3G/LTE""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb2_port4 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Camera""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb2_port7 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb2_port10 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 J_USB3_1""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(1, 1)"
device ref usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 J_USB3_2""
register "type" = "UPC_TYPE_A"
register "group" = "ACPI_PLD_GROUP(2, 1)"
device ref usb3_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 3G/LTE""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb3_port4 on end
end
end
end
end
device ref i2c0 on
register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
register "common_soc_config.i2c[0]" = "{
.speed = I2C_SPEED_FAST,
.rise_time_ns = 80,
.fall_time_ns = 110,
.speed_config[0] = {
.speed = I2C_SPEED_FAST,
.scl_lcnt = 0x13b,
.scl_hcnt = 0xc8,
.sda_hold = 0x5a,
}
}"
chip drivers/i2c/hid
register "generic.hid" = ""ELAN040D""
register "generic.desc" = ""ELAN Touchpad""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)"
register "generic.probed" = "true"
register "hid_desc_reg_offset" = "0x01"
device i2c 15 on end
end
end
device ref i2c1 on # Retimer ROM
register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
end
device ref cnvi_wifi on
register "CnviBtCore" = "true"
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
device generic 0 on end
end
end
device ref pcie_rp3 on
register "PcieRpEnable[2]" = "true"
register "PcieRpLtrEnable[2]" = "true"
register "PcieClkSrcUsage[1]" = "2"
register "PcieClkSrcClkReq[1]" = "1"
register "PcieRpSlotImplemented[2]" = "true"
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
chip drivers/wifi/generic
device pci 00.0 on end
end
end
device ref pcie_rp6 on
# Card reader
device pci 00.0 on end
register "PcieRpEnable[5]" = "true"
register "PcieRpLtrEnable[5]" = "true"
register "PcieClkSrcUsage[2]" = "5"
register "PcieClkSrcClkReq[2]" = "2"
end
device ref pcie_rp9 on
# SSD2 - PCIe mode
register "PcieRpEnable[8]" = "true"
register "PcieRpLtrEnable[8]" = "true"
register "PcieClkSrcUsage[0]" = "8"
register "PcieClkSrcClkReq[0]" = "0"
register "PcieRpSlotImplemented[8]" = "true"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
chip soc/intel/common/block/pcie/rtd3
device generic 0 on end
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D9)"
register "srcclk_pin" = "0"
end
end
device ref peg on
# SSD1 - PCIe4
register "PcieClkSrcUsage[3]" = "0x40"
register "PcieClkSrcClkReq[3]" = "3"
#register "CpuPcieRpLtrEnable[0]" = "true" # currently set in ramstage.c
#register "CpuPcieRpSlotImplemented[0]" = "true" # currently set in ramstage.c
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
chip soc/intel/common/block/pcie/rtd3
device generic 0 on end
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C13)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C22)"
register "srcclk_pin" = "3"
end
end
device ref pch_espi on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
end
device ref sata on
# SSD2 - SATA mode
register "SataPortsEnable[1]" = "true"
register "SataPortsDevSlp[1]" = "true"
register "SataPortsEnableDitoConfig[1]" = "true"
register "SataSalpSupport" = "true"
end
device ref pmc hidden
register "AcousticNoiseMitigation" = "true"
register "SlowSlewRate" = "SLEW_FAST_4"
register "FastPkgCRampDisable" = "true"
register "PchPmSlpS3MinAssert" = "3" # 50ms
register "PchPmSlpS4MinAssert" = "1" # 1s
register "PchPmSlpAMinAssert" = "4" # 2s
register "PchPmSlpSusMinAssert" = "4" # 4s
register "PchPmPwrCycDur" = "0" # 4-5s
register "s0ix_enable" = "true"
chip drivers/intel/pmc_mux
device generic 0 on
chip drivers/intel/pmc_mux/conn
use usb2_port3 as usb2_port
use tcss_usb3_port1 as usb3_port
device generic 0 alias conn0 on end
end
end
end
end
device ref hda on
register "PchHdaAudioLinkHdaEnable" = "true"
end
device ref uart2 on
register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
end
device ref heci1 on end
device ref smbus on end
device ref shared_ram on end
device ref p2sb hidden end
device ref fast_spi on end
end
end
235 changes: 235 additions & 0 deletions src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c
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/* SPDX-License-Identifier: GPL-2.0-only */

#include <soc/gpe.h>
#include <soc/gpio.h>
#include <variant/gpio.h>

/* Name format: <pad name> / <net/pin name in schematics> */
static const struct pad_config gpio_table[] = {
/* ------- GPIO Group GPD ------- */
PAD_NC(GPD0, NONE),
PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), /* ACPRESENT / AC_PRESENT */
PAD_NC(GPD2, NONE),
PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* PWRBTN# / PWR_BTN# */
PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SLP_S3# / SUSB#_PCH */
PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SLP_S4# / SUSC#_PCH */
PAD_NC(GPD6, NONE),
PAD_NC(GPD7, NONE),
PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUSCLK / SUS_CLK */
PAD_NC(GPD9, NONE),
PAD_NC(GPD10, NONE),
PAD_NC(GPD11, NONE),

/* ------- GPIO Group GPP_A ------- */
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), /* ESPI_IO0 / ESPI_IO_0 */
PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), /* ESPI_IO1 / ESPI_IO_1 */
PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), /* ESPI_IO2 / ESPI_IO_2 */
PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), /* ESPI_IO3 / ESPI_IO_3 */
PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), /* ESPI_CS# / ESPI_CS_N */
PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), /* ESPI_CLK */
PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* ESPI_RESET# / ESPI_RESET_N */
PAD_NC(GPP_A7, NONE),
PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2), /* CNV_RF_RESET# / CNVI_RST# */
PAD_CFG_NF(GPP_A9, UP_20K, DEEP, NF2), /* MODEM_CLKREQ / CNVI_CLKREQ */
PAD_NC(GPP_A10, NONE),
PAD_NC(GPP_A11, NONE),
PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), /* SATAXPCIE1 / SATAGP1 (wrong name!) */
PAD_CFG_GPO(GPP_A13, 1, DEEP), /* GPP_A13 / PCH_BT_EN */
PAD_NC(GPP_A14, NONE),
PAD_NC(GPP_A15, NONE),
PAD_NC(GPP_A16, NONE),
PAD_NC(GPP_A17, NONE),
PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* DDSP_HPDB / HDMI_HPD */
PAD_NC(GPP_A19, NONE),
PAD_NC(GPP_A20, NONE),
PAD_NC(GPP_A21, NONE),
PAD_NC(GPP_A22, NONE),
PAD_CFG_GPO(GPP_A23, 0, PLTRST), /* GPP_A23 / TC_RETIMER_FORCE_PWR */

/* ------- GPIO Group GPP_B ------- */
PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID0 / VCCIN_AUX_VID0 */
PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* CORE_VID1 / VCCIN_AUX_VID1 */
PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), /* VRALERT# */
PAD_CFG_GPI_APIC_LOW(GPP_B3, NONE, DEEP), /* GPP_B3 (touchpad interrupt) */
PAD_NC(GPP_B4, NONE),
PAD_NC(GPP_B5, NONE),
PAD_NC(GPP_B6, NONE),
PAD_NC(GPP_B7, NONE),
PAD_NC(GPP_B8, NONE),
PAD_NC(GPP_B9, NONE),
PAD_NC(GPP_B10, NONE),
PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* GPP_B11 / TBTA_I2C_INT */
PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_S0# */
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLT_RST# */
PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR / PCH_SPKR */
PAD_NC(GPP_B15, NONE),
PAD_NC(GPP_B16, NONE),
PAD_NC(GPP_B17, NONE),
PAD_NC(GPP_B18, NONE),
PAD_NC(GPP_B19, NONE),
PAD_NC(GPP_B20, NONE),
PAD_NC(GPP_B21, NONE),
PAD_NC(GPP_B22, NONE),
PAD_NC(GPP_B23, NONE),

/* ------- GPIO Group GPP_C ------- */
PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK / SMB_CLK_DDR */
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA / SMB_DAT_DDR */
PAD_NC(GPP_C2, NONE),
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0CLK */
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_DATA */
PAD_NC(GPP_C5, NONE),
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1CLK / TBT_I2C_SCL */
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1_DATA / TBT_I2C_SDA */
PAD_NC(GPP_C8, NONE),
PAD_CFG_GPI_APIC_LOW(GPP_C9, NONE, DEEP), /* GPP_C9 / TPM_PIRQ# */
PAD_NC(GPP_C10, NONE),
PAD_NC(GPP_C11, NONE),
PAD_NC(GPP_C12, NONE),
PAD_CFG_GPO(GPP_C13, 1, DEEP), /* GPP_C13 / SSD1_PWR_DN# */
PAD_NC(GPP_C14, NONE),
PAD_NC(GPP_C15, NONE),
PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_SDA / T_SDA (touchpad) */
PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_SCL / T_SCL (touchpad) */
PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SDA / PCH_I2C_SDA (retimer rom) */
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* I2C1_SCL / PCH_I2C_SCL (retimer rom) */
PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), /* UART2_RXD */
PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1), /* UART2_TXD */
PAD_CFG_GPO(GPP_C22, 1, DEEP), /* GPP_C22 / GPP_C12_RTD3 (SSD1) */
PAD_NC(GPP_C23, UP_20K), /* GPP_C23 / PCH_GPP_C23 (WLAN_WAKEUP#) */

/* ------- GPIO Group GPP_D ------- */
PAD_CFG_GPO(GPP_D0, 1, DEEP), /* GPP_D0 / SB_BLON */
PAD_NC(GPP_D1, NONE),
PAD_NC(GPP_D2, NONE), /* LEDKB_DET# (unused; not sold w/o KBLED) */
PAD_NC(GPP_D3, NONE), /* BOARD_ID (unused; always high) */
PAD_NC(GPP_D4, NONE),
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* SRCCLKREQ0# / SSD1_CLKREQ# (for SSD2!) */
PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* SRCCLKREQ1# / WLAN_CLKREQ# */
PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* SRCCLKREQ2# / CARD_CLKREQ# */
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* SRCCLKREQ3# / SSD2_CLKREQ# (for SSD1!) */
PAD_CFG_GPO(GPP_D9, 1, DEEP), /* GPP_D9 / GPP_D13_RTD3 (SSD2) */
PAD_NC(GPP_D10, NONE),
PAD_NC(GPP_D11, NONE),
PAD_NC(GPP_D12, NONE),
PAD_NC(GPP_D13, NONE),
PAD_CFG_GPO(GPP_D14, 1, DEEP), /* GPP_D14 / SSD2_PWR_DN# */
PAD_NC(GPP_D15, NONE),
PAD_NC(GPP_D16, NONE),
PAD_NC(GPP_D17, NONE),
PAD_NC(GPP_D18, NONE),
PAD_NC(GPP_D19, NONE),

/* ------- GPIO Group GPP_E ------- */
PAD_NC(GPP_E0, NONE),
PAD_CFG_GPO(GPP_E1, 0, DEEP), /* GPP_E1 / ROM_I2C_EN */
PAD_NC(GPP_E2, NONE),
PAD_NC(GPP_E3, NONE), /* SB_KBCRST# (eSPI Virtual Wire) */
PAD_NC(GPP_E4, NONE),
PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1 */
PAD_NC(GPP_E6, NONE),
PAD_NC(GPP_E7, NONE),
PAD_NC(GPP_E8, NONE),
PAD_NC(GPP_E9, NONE),
PAD_NC(GPP_E10, NONE),
PAD_NC(GPP_E11, NONE),
PAD_NC(GPP_E12, NONE),
PAD_NC(GPP_E13, NONE),
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDSP_HPDA / EDP_HPD */
PAD_NC(GPP_E15, NONE), /* SCI# (eSPI Virtual Wire) */
PAD_NC(GPP_E16, NONE), /* SMI# (eSPI Virtual Wire) */
PAD_NC(GPP_E17, NONE),
PAD_CFG_NF(GPP_E18, NONE, DEEP, NF2), /* TBT_LSX0_TXD */
PAD_CFG_NF(GPP_E19, NONE, DEEP, NF2), /* TBT_LSX0_RXD */
PAD_NC(GPP_E20, NONE), /* SWI# (eSPI Virtual Wire) */
PAD_NC(GPP_E21, NONE),
PAD_NC(GPP_E22, NONE),
PAD_NC(GPP_E23, NONE),

/* ------- GPIO Group GPP_F ------- */
PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_BRI_DT / CNVI_BRI_DT */
PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), /* CNV_BRI_RSP / CNVI_BRI_RSP */
PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* CNV_RGI_DT / CNVI_RGI_DT */
PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), /* CNV_RGI_RSP / CNVI_RGI_RSP */
PAD_NC(GPP_F4, NONE),
PAD_NC(GPP_F5, NONE),
PAD_NC(GPP_F6, NONE),
PAD_NC(GPP_F7, NONE),
PAD_NC(GPP_F8, NONE),
PAD_NC(GPP_F9, NONE),
PAD_NC(GPP_F10, NONE),
PAD_NC(GPP_F11, NONE),
PAD_NC(GPP_F12, NONE),
PAD_NC(GPP_F13, NONE),
PAD_NC(GPP_F14, NONE),
PAD_NC(GPP_F15, NONE),
PAD_NC(GPP_F16, NONE),
PAD_CFG_GPI(GPP_F17, UP_20K, DEEP), /* GPP_F17 / TPM_DET# */
PAD_NC(GPP_F18, NONE),
PAD_NC(GPP_F19, NONE),
PAD_NC(GPP_F20, NONE),
PAD_NC(GPP_F21, NONE),
PAD_NC(GPP_F22, NONE),
PAD_NC(GPP_F23, NONE),

/* ------- GPIO Group GPP_H ------- */
PAD_NC(GPP_H0, NONE),
PAD_NC(GPP_H1, NONE),
PAD_NC(GPP_H2, NONE),
PAD_NC(GPP_H3, NONE),
PAD_NC(GPP_H4, NONE),
PAD_NC(GPP_H5, NONE),
PAD_NC(GPP_H6, NONE),
PAD_NC(GPP_H7, NONE),
PAD_NC(GPP_H8, NONE),
PAD_NC(GPP_H9, NONE),
PAD_NC(GPP_H10, NONE),
PAD_NC(GPP_H11, NONE),
PAD_NC(GPP_H12, NONE),
PAD_NC(GPP_H13, NONE),
PAD_NC(GPP_H14, NONE),
PAD_NC(GPP_H15, NONE),
PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), /* DDPB_CTRLCLK / HDMI_CTRLCLK */
PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), /* DDPB_CTRLDATA / HDMI_CTRLDATA */
PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* CPU_C10_GATE# */
PAD_NC(GPP_H19, NONE), /* GPP_H19 / CNVI_WAKE#
(UART_WAKE# in M.2 spec; unused)
*/
PAD_NC(GPP_H20, NONE),
PAD_NC(GPP_H21, NONE),
PAD_NC(GPP_H22, NONE),
PAD_NC(GPP_H23, NONE),

/* ------- GPIO Group GPP_R ------- */
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), /* HDA_BCLK / HDA_BITCLK */
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), /* HDA_SYNC */
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), /* HDA_SDO / HDA_SDOUT */
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), /* HDA_SDI0 / HDA_SDIN0 */
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), /* HDA_RST# / AZ_RST#_R */
PAD_NC(GPP_R5, NONE),
PAD_NC(GPP_R6, NONE),
PAD_NC(GPP_R7, NONE),

/* ------- GPIO Group GPP_S ------- */
PAD_NC(GPP_S0, NONE),
PAD_NC(GPP_S1, NONE),
PAD_NC(GPP_S2, NONE),
PAD_NC(GPP_S3, NONE),
PAD_NC(GPP_S4, NONE),
PAD_NC(GPP_S5, NONE),
PAD_NC(GPP_S6, NONE),
PAD_NC(GPP_S7, NONE),

/* ------- GPIO Group GPP_T ------- */
PAD_NC(GPP_T2, NONE),
PAD_NC(GPP_T3, NONE),

/* ------- GPIO Group GPP_U ------- */
PAD_NC(GPP_U4, NONE),
PAD_NC(GPP_U5, NONE),
};

void variant_configure_gpios(void)
{
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}
15 changes: 15 additions & 0 deletions src/mainboard/clevo/tgl-u/variants/l140mu/gpio_early.c
View file
@@ -0,0 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <soc/gpio.h>
#include <variant/gpio.h>

/* Name format: <pad name> / <net/pin name in schematics> */
static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */
};

void variant_configure_early_gpios(void)
{
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}
82 changes: 82 additions & 0 deletions src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c
View file
@@ -0,0 +1,82 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <device/azalia_device.h>

const u32 cim_verb_data[] = {
/* Realtek ALC293 */
0x10ec0293, /* Vendor ID */
0x155814a1, /* Subsystem ID */
12, /* Number of entries */
AZALIA_SUBVENDOR(0, 0x155814a1),

/* Microphone (display lid), vendor value: 0x90a60130 */
AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC(
INTEGRATED,
LOCATION_OTHER, /* vendor: SEPARATE_CHASSIS */
SPECIAL7, /* lid, vendor: NA */
MIC_IN,
OTHER_DIGITAL,
COLOR_UNKNOWN,
1, /* no presence detect */
3, 0)
),

/* Integrated speakers, vendor value: 0x90170110 */
AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC(
INTEGRATED,
LOCATION_OTHER, /* vendor: SEPARATE_CHASSIS */
BOTTOM, /* vendor: NA */
SPEAKER,
OTHER_ANALOG,
COLOR_UNKNOWN,
1, /* no presence detect */
1, 0)
),

/* Headphones, vendor value: 0x02211020 */
AZALIA_PIN_CFG(0, 0x15, AZALIA_PIN_DESC(
JACK,
EXTERNAL_PRIMARY_CHASSIS,
RIGHT, /* vendor: FRONT */
HP_OUT,
STEREO_MONO_1_8,
BLACK,
0, /* has presence detect */
2, 0)
),

/* ext. Microphone, vendor value: 0x411111f0, linux override: 0x01a1913c */
AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_DESC(
JACK,
EXTERNAL_PRIMARY_CHASSIS,
RIGHT, /* vendor: REAR */
MIC_IN,
STEREO_MONO_1_8,
BLACK, /* vendor: PINK */
1, /* no separate presence detect */
3, 12)
),

/* PCBEEP, vendor value: 0x41748245 */
AZALIA_PIN_CFG(0, 0x1d, AZALIA_PIN_DESC(
INTEGRATED, /* vendor: NC */
INTERNAL, /* vendor: EXTERNAL_PRIMARY_CHASSIS */
NA, /* vendor: REAR */
DEVICE_OTHER, /* vendor: MODEM_HANDSET_SIDE */
OTHER_ANALOG, /* vendor: RCA */
COLOR_UNKNOWN, /* vendor: PURPLE */
1, /* no presence detect, vendor: 2 */
4, 5)
),

AZALIA_PIN_CFG(0, 0x13, 0x40000000), /* NC, but different from 0x411111f0 */
AZALIA_PIN_CFG(0, 0x16, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
};

const u32 pc_beep_verbs[] = {};

AZALIA_ARRAY_SIZES;
11 changes: 11 additions & 0 deletions src/mainboard/clevo/tgl-u/variants/l140mu/ramstage.c
View file
@@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <soc/ramstage.h>
#include <variant/ramstage.h>

void variant_configure_fsps(FSP_S_CONFIG *params)
{
/* SSD1 - PCIe4 */
params->CpuPcieRpLtrEnable[0] = 1;
params->CpuPcieRpSlotImplemented[0] = 1;
}
19 changes: 19 additions & 0 deletions src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c
View file
@@ -0,0 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <soc/meminit.h>
#include <variant/romstage.h>

void variant_configure_fspm(FSPM_UPD *memupd)
{
const struct mb_cfg board_cfg = {
.type = MEM_TYPE_DDR4,
};
const struct mem_spd spd_info = {
.topo = MEM_TOPO_MIXED,
.cbfs_index = 0,
.smbus[1] = { .addr_dimm[0] = 0x52, },
};
const bool half_populated = false;

memcfg_init(memupd, &board_cfg, &spd_info, half_populated);
}
2 changes: 1 addition & 1 deletion src/mainboard/dell/snb_ivb_workstations/Kconfig.name
View file
@@ -1,7 +1,7 @@
config BOARD_DELL_OPTIPLEX_9010
bool "OptiPlex 9010 SFF"
select BOARD_DELL_SNB_IVB_WORKSTATIONS
select SOUTHBRIDGE_INTEL_BD82X6X
select SOUTHBRIDGE_INTEL_C216

config BOARD_DELL_PRECISION_T1650
bool "Dell Precision T1650"
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb
View file
Expand Up @@ -4,7 +4,7 @@ chip northbridge/intel/sandybridge
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
register "sata_port_map" = "0x7"
device pci 1c.4 on # PCIe Port #5
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "SLOT2" "SlotDataBusWidth4X"
smbios_slot_desc "SlotTypePciExpressGen2X16" "SlotLengthLong" "SLOT2" "SlotDataBusWidth4X"
end
device pci 1c.5 on end # PCIe Port #6
device pci 1c.6 on end # PCIe Port #7
Expand Down
4 changes: 2 additions & 2 deletions src/mainboard/dell/snb_ivb_workstations/variants/precision_t1650/overridetree.cb
View file
Expand Up @@ -5,10 +5,10 @@ chip northbridge/intel/sandybridge
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
register "sata_port_map" = "0xf"
device pci 1c.2 on # PCIe Port #3
smbios_slot_desc "SlotTypePciExpressGen3X1" "SlotLengthShort" "SLOT2" "SlotDataBusWidth1X"
smbios_slot_desc "SlotTypePciExpressGen2X1" "SlotLengthShort" "SLOT2" "SlotDataBusWidth1X"
end
device pci 1c.4 on # PCIe Port #5
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "SLOT4" "SlotDataBusWidth4X"
smbios_slot_desc "SlotTypePciExpressGen2X16" "SlotLengthLong" "SLOT4" "SlotDataBusWidth4X"
end
device pci 1c.5 on end # PCIe Port #6
device pci 1c.6 on end # PCIe Port #7
Expand Down
2 changes: 0 additions & 2 deletions src/mainboard/elmex/pcm205400/BiosCallOuts.c
View file
Expand Up @@ -36,13 +36,11 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
{
AGESA_STATUS Status;
UINTN FcnData;
PCIe_SLOT_RESET_INFO *ResetInfo;

UINT32 GpioMmioAddr;
UINT8 Data8;

FcnData = Data;
ResetInfo = ConfigPtr;
Status = AGESA_UNSUPPORTED;
GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
Expand Down
5 changes: 1 addition & 4 deletions src/mainboard/emulation/qemu-q35/chromeos.c
View file
Expand Up @@ -19,11 +19,8 @@ void fill_lb_gpios(struct lb_gpios *gpios)
static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, "QEMU"),
};
DECLARE_CROS_GPIOS(cros_gpios);

void mainboard_chromeos_acpi_generate(void)
{
chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
}

int get_ec_is_trusted(void)
{
Expand Down
3 changes: 0 additions & 3 deletions src/mainboard/facebook/fbg1701/Kconfig
View file
Expand Up @@ -2,9 +2,6 @@

if BOARD_FACEBOOK_FBG1701

config IGNORE_IASL_MISSING_DEPENDENCY
def_bool y

config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_8192
Expand Down
10 changes: 0 additions & 10 deletions src/mainboard/facebook/fbg1701/acpi/superio.asl
View file
Expand Up @@ -15,14 +15,4 @@ Device (COM1) {
FixedIO (0x6E, 0x02)
IRQNoFlags () {4}
})

Name (_PRS, ResourceTemplate ()
{
StartDependentFn (0, 0) {
FixedIO (0x03F8, 0x08)
FixedIO (0x6E, 0x02)
IRQNoFlags () {4}
}
EndDependentFn ()
})
}
9 changes: 7 additions & 2 deletions src/mainboard/facebook/fbg1701/board_verified_boot.c
View file
Expand Up @@ -2,14 +2,19 @@

#include "board_verified_boot.h"

/* The items verified by the bootblock, the bootblock will not measure the
/*
* The items verified by the bootblock, the bootblock will not measure the
* items to the TPM
*/
const verify_item_t bootblock_verify_list[] = {
{ VERIFY_FILE, ROMSTAGE, { { NULL, CBFS_TYPE_STAGE } },
HASH_IDX_ROM_STAGE, MBOOT_PCR_INDEX_0 },
{ VERIFY_FILE, BOOTBLOCK, { { NULL, CBFS_TYPE_BOOTBLOCK } },
HASH_IDX_BOOTBLOCK, MBOOT_PCR_INDEX_0 },
{ VERIFY_FILE, FSP, { { NULL, CBFS_TYPE_FSP } }, HASH_IDX_FSP,
MBOOT_PCR_INDEX_1 },
{ VERIFY_FILE, "spd.bin", { { NULL, CBFS_TYPE_SPD } },
HASH_IDX_SPD0, MBOOT_PCR_INDEX_1 },
#if CONFIG(VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST)
{ VERIFY_BLOCK, "PublicKey",
{ { (void *)CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_LOCATION,
Expand All @@ -20,7 +25,7 @@ const verify_item_t bootblock_verify_list[] = {
};

/*
* The items used by the romstage. Bootblock and PublicKey are added here to make sure they
* The items used by the romstage. Items verified by bootblock are added here to make sure they
* are measured
*/
const verify_item_t romstage_verify_list[] = {
Expand Down
3 changes: 0 additions & 3 deletions src/mainboard/facebook/monolith/Kconfig
View file
@@ -1,8 +1,5 @@
if BOARD_FACEBOOK_MONOLITH

config IGNORE_IASL_MISSING_DEPENDENCY
def_bool y

config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_16384
Expand Down
19 changes: 0 additions & 19 deletions src/mainboard/facebook/monolith/acpi/superio.asl
View file
Expand Up @@ -17,16 +17,6 @@ Device (COM1) {
FixedIO (0x6E, 0x02)
IRQNoFlags () {4}
})

Name (_PRS, ResourceTemplate ()
{
StartDependentFn (0, 0) {
FixedIO (0x03F8, 0x08)
FixedIO (0x6E, 0x02)
IRQNoFlags () {4}
}
EndDependentFn ()
})
}

Device (COM2) {
Expand All @@ -43,13 +33,4 @@ Device (COM2) {
FixedIO (0x03E8, 0x08)
IRQNoFlags () {3}
})

Name (_PRS, ResourceTemplate ()
{
StartDependentFn (0, 0) {
FixedIO (0x03E8, 0x08)
IRQNoFlags () {3}
}
EndDependentFn ()
})
}
6 changes: 1 addition & 5 deletions src/mainboard/google/auron/chromeos.c
View file
Expand Up @@ -35,11 +35,7 @@ static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_DEVICE_NAME),
};

void mainboard_chromeos_acpi_generate(void)
{
chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
}
DECLARE_CROS_GPIOS(cros_gpios);

int get_ec_is_trusted(void)
{
Expand Down
44 changes: 3 additions & 41 deletions src/mainboard/google/beltino/chromeos.c
View file
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <device/pci_ops.h>
#include <bootmode.h>
#include <boot/coreboot_tables.h>
#include <device/device.h>
Expand All @@ -10,9 +9,6 @@
#include <vendorcode/google/chromeos/chromeos.h>
#include "onboard.h"

#define FLAG_SPI_WP 0
#define FLAG_REC_MODE 1

void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio chromeos_gpios[] = {
Expand All @@ -25,55 +21,21 @@ void fill_lb_gpios(struct lb_gpios *gpios)
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}

static bool raw_write_protect_state(void)
{
return get_gpio(GPIO_SPI_WP);
}

static bool raw_recovery_mode_switch(void)
{
return !get_gpio(GPIO_REC_MODE);
}

int get_write_protect_state(void)
{
const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1;
return get_gpio(GPIO_SPI_WP);
}

int get_recovery_mode_switch(void)
{
const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);
return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
}

void init_bootmode_straps(void)
{
u32 flags = 0;
const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2);

/* Write Protect: GPIO58 = GPIO_SPI_WP, active high */
if (raw_write_protect_state())
flags |= (1 << FLAG_SPI_WP);

/* Recovery: GPIO12 = RECOVERY_L, active low */
if (raw_recovery_mode_switch())
flags |= (1 << FLAG_REC_MODE);

/* Developer: Virtual */

pci_s_write_config32(dev, SATA_SP, flags);
return !get_gpio(GPIO_REC_MODE);
}

static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
};

void mainboard_chromeos_acpi_generate(void)
{
chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
}
DECLARE_CROS_GPIOS(cros_gpios);

int get_ec_is_trusted(void)
{
Expand Down
11 changes: 9 additions & 2 deletions src/mainboard/google/brya/Kconfig
View file
Expand Up @@ -36,6 +36,7 @@ config BOARD_GOOGLE_BRYA_COMMON
select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3
select SOC_INTEL_CSE_LITE_SKU
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES if SOC_INTEL_ALDERLAKE_PCH_P
select SOC_INTEL_COMMON_BASECODE_DEBUG_FEATURE

config BOARD_GOOGLE_BASEBOARD_BRYA
def_bool n
Expand All @@ -60,6 +61,7 @@ config BOARD_GOOGLE_BASEBOARD_NISSA
def_bool n
select BOARD_GOOGLE_BRYA_COMMON
select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS
select MAINBOARD_NEEDS_I2C_TI50_WORKAROUND
select MEMORY_SOLDERDOWN
select SOC_INTEL_ALDERLAKE_PCH_N
select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW
Expand Down Expand Up @@ -116,13 +118,16 @@ config DRIVER_TPM_I2C_BUS
default 0x1 if BOARD_GOOGLE_VOLMAR
default 0x1 if BOARD_GOOGLE_BANSHEE
default 0x1 if BOARD_GOOGLE_KINOX
default 0x0 if BOARD_GOOGLE_CRAASK
default 0x1 if BOARD_GOOGLE_CROTA
default 0x1 if BOARD_GOOGLE_MOLI

config DRIVER_TPM_I2C_ADDR
hex
default 0x50

config FMDFILE
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-serger.fmd" if BOARD_GOOGLE_KANO || BOARD_GOOGLE_BRASK
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-serger.fmd" if BOARD_GOOGLE_BRASK
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-nissa.fmd" if BOARD_GOOGLE_BASEBOARD_NISSA
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd"

Expand Down Expand Up @@ -168,6 +173,7 @@ config MAINBOARD_PART_NUMBER
default "Crota" if BOARD_GOOGLE_CROTA
default "Moli" if BOARD_GOOGLE_MOLI
default "Kinox" if BOARD_GOOGLE_KINOX
default "Craask" if BOARD_GOOGLE_CRAASK

config VARIANT_DIR
default "brya0" if BOARD_GOOGLE_BRYA0
Expand Down Expand Up @@ -195,6 +201,7 @@ config VARIANT_DIR
default "crota" if BOARD_GOOGLE_CROTA
default "moli" if BOARD_GOOGLE_MOLI
default "kinox" if BOARD_GOOGLE_KINOX
default "craask" if BOARD_GOOGLE_CRAASK

config VBOOT
select VBOOT_EARLY_EC_SYNC
Expand Down Expand Up @@ -225,7 +232,7 @@ config USE_PM_ACPI_TIMER

choice
prompt "Cache as RAM (CAR) setup configuration to use"
default USE_ADL_NEM if BOARD_GOOGLE_BRYA4ES || BOARD_GOOGLE_PRIMUS4ES || BOARD_GOOGLE_GIMBLE4ES || BOARD_GOOGLE_REDRIX4ES || BOARD_GOOGLE_TAEKO4ES || BOARD_GOOGLE_ANAHERA4ES || BOARD_GOOGLE_TANIKS || BOARD_GOOGLE_NIVVIKS || BOARD_GOOGLE_NEREID
default USE_ADL_NEM if BOARD_GOOGLE_BRYA4ES || BOARD_GOOGLE_PRIMUS4ES || BOARD_GOOGLE_GIMBLE4ES || BOARD_GOOGLE_REDRIX4ES || BOARD_GOOGLE_TAEKO4ES || BOARD_GOOGLE_ANAHERA4ES || BOARD_GOOGLE_TANIKS || BOARD_GOOGLE_NIVVIKS || BOARD_GOOGLE_NEREID || BOARD_GOOGLE_CRAASK
default USE_ADL_ENEM

config USE_ADL_ENEM
Expand Down
14 changes: 13 additions & 1 deletion src/mainboard/google/brya/Kconfig.name
View file
Expand Up @@ -3,7 +3,7 @@ comment "Brya"
config BOARD_GOOGLE_AGAH
bool "-> Agah"
select BOARD_GOOGLE_BASEBOARD_BRYA
select DRIVERS_I2C_MAX98390
select DRIVERS_GENESYSLOGIC_GL9750
select PCIEXP_SUPPORT_RESIZABLE_BARS
select RT8168_GEN_ACPI_POWER_RESOURCE
select RT8168_GET_MAC_FROM_VPD
Expand All @@ -13,6 +13,7 @@ config BOARD_GOOGLE_ANAHERA
bool "-> Anahera"
select BOARD_GOOGLE_BASEBOARD_BRYA
select DRIVERS_GENESYSLOGIC_GL9763E
select DRIVERS_GENESYSLOGIC_GL9750
select DRIVERS_GFX_GENERIC
select HAVE_PCIE_WWAN
select HAVE_WWAN_POWER_SEQUENCE
Expand All @@ -21,6 +22,7 @@ config BOARD_GOOGLE_ANAHERA4ES
bool "-> Anahera4ES"
select BOARD_GOOGLE_BASEBOARD_BRYA
select DRIVERS_GENESYSLOGIC_GL9763E
select DRIVERS_GENESYSLOGIC_GL9750
select DRIVERS_GFX_GENERIC
select HAVE_PCIE_WWAN
select HAVE_WWAN_POWER_SEQUENCE
Expand Down Expand Up @@ -90,7 +92,10 @@ config BOARD_GOOGLE_NIVVIKS

config BOARD_GOOGLE_NEREID
bool "-> Nereid"
select ALDERLAKE_CONFIGURE_DESCRIPTOR
select BOARD_GOOGLE_BASEBOARD_NISSA
select DRIVERS_GENERIC_BAYHUB_LV2
select DRIVERS_GENERIC_GPIO_KEYS

config BOARD_GOOGLE_PRIMUS
bool "-> Primus"
Expand Down Expand Up @@ -153,6 +158,7 @@ config BOARD_GOOGLE_TANIKS
select DRIVERS_GENERIC_BAYHUB_LV2
select DRIVERS_GENESYSLOGIC_GL9750
select DRIVERS_GENESYSLOGIC_GL9763E
select DRIVERS_GENESYSLOGIC_GL9763E_L1_MAX

config BOARD_GOOGLE_VELL
bool "-> Vell"
Expand All @@ -174,10 +180,12 @@ config BOARD_GOOGLE_BANSHEE
select BOARD_GOOGLE_BASEBOARD_BRYA
select MEMORY_SODIMM
select CHROMEOS_WIFI_SAR if CHROMEOS
select DRIVERS_GENERIC_GPIO_KEYS

config BOARD_GOOGLE_CROTA
bool "-> Crota"
select BOARD_GOOGLE_BASEBOARD_BRYA
select DRIVERS_I2C_CS42L42

config BOARD_GOOGLE_MOLI
bool "-> Moli"
Expand All @@ -186,3 +194,7 @@ config BOARD_GOOGLE_MOLI
config BOARD_GOOGLE_KINOX
bool "-> Kinox"
select BOARD_GOOGLE_BASEBOARD_BRASK

config BOARD_GOOGLE_CRAASK
bool "-> Craask"
select BOARD_GOOGLE_BASEBOARD_NISSA
7 changes: 7 additions & 0 deletions src/mainboard/google/brya/bootblock.c
View file
Expand Up @@ -10,3 +10,10 @@ void bootblock_mainboard_early_init(void)
pads = variant_early_gpio_table(&num);
gpio_configure_pads(pads, num);
}

void bootblock_mainboard_init(void)
{
variant_update_descriptor();
}

void __weak variant_update_descriptor(void) {}
10 changes: 0 additions & 10 deletions src/mainboard/google/brya/chromeos.c
View file
@@ -1,12 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */

#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <bootmode.h>
#include <boot/coreboot_tables.h>
#include <gpio.h>
#include <types.h>
#include <vendorcode/google/chromeos/chromeos.h>

void fill_lb_gpios(struct lb_gpios *gpios)
{
Expand All @@ -24,14 +22,6 @@ int get_write_protect_state(void)
return gpio_get(GPIO_PCH_WP);
}

void mainboard_chromeos_acpi_generate(void)
{
const struct cros_gpio *gpios;
size_t num;
gpios = variant_cros_gpios(&num);
chromeos_acpi_gpio_generate(gpios, num);
}

int get_ec_is_trusted(void)
{
/* EC is trusted if not in RW. */
Expand Down
21 changes: 19 additions & 2 deletions src/mainboard/google/brya/mainboard.c
View file
Expand Up @@ -7,11 +7,11 @@
#include <drivers/tpm/cr50.h>
#include <drivers/wwan/fm/chip.h>
#include <ec/ec.h>
#include <soc/ramstage.h>
#include <fw_config.h>
#include <security/tpm/tss.h>
#include <soc/gpio.h>
#include <soc/ramstage.h>
#include <stdio.h>

WEAK_DEV_PTR(rp6_wwan);

Expand Down Expand Up @@ -64,6 +64,11 @@ __weak void variant_update_soc_chip_config(struct soc_intel_alderlake_config *co
/* default implementation does nothing */
}

__weak void variant_init(void)
{
/* default implementation does nothing */
}

static void mainboard_init(void *chip_info)
{
const struct pad_config *base_pads;
Expand All @@ -74,6 +79,7 @@ static void mainboard_init(void *chip_info)
override_pads = variant_gpio_override_table(&override_num);
gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num);

variant_init();
variant_devtree_update();
}

Expand Down Expand Up @@ -154,7 +160,7 @@ void __weak variant_fill_ssdt(const struct device *dev)
/* Add board-specific SSDT entries */
}

void __weak variant_generate_s0ix_hook(enum s0ix_entry)
void __weak variant_generate_s0ix_hook(enum s0ix_entry entry)
{
/* Add board-specific MS0X entries */
/*
Expand All @@ -174,7 +180,18 @@ static void mainboard_enable(struct device *dev)
dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt;
}


void __weak variant_finalize(void)
{
}

static void mainboard_final(void *chip_info)
{
variant_finalize();
}

struct chip_operations mainboard_ops = {
.init = mainboard_init,
.enable_dev = mainboard_enable,
.final = mainboard_final,
};
14 changes: 7 additions & 7 deletions src/mainboard/google/brya/variants/agah/gpio.c
View file
Expand Up @@ -18,7 +18,7 @@ static const struct pad_config override_gpio_table[] = {
/* A15 : USB_OC2# ==> USB_C2_OC_ODL */
PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
/* A17 : DISP_MISCC ==> EN_GPU_PPVAR_GPU_NVVDD_X_PCH */
PAD_CFG_GPO(GPP_A17, 1, DEEP),
PAD_CFG_GPI(GPP_A17, NONE, DEEP),
/* A19 : DDSP_HPD1 ==> EN_PCH_PPVAR_GPU_FBVDDQ_X_L */
PAD_CFG_GPO(GPP_A19, 0, DEEP),
/* A20 : DDSP_HPD2 ==> NC */
Expand All @@ -29,7 +29,7 @@ static const struct pad_config override_gpio_table[] = {
PAD_CFG_GPI(GPP_A22, NONE, DEEP),

/* B3 : PROC_GP2 ==> GPU_PERST_L */
PAD_CFG_GPO_LOCK(GPP_B3, 1, LOCK_CONFIG),
PAD_CFG_GPO(GPP_B3, 1, DEEP),
/* B5 : ISH_I2C0_SDA ==> PCH_I2C_NVDD_GPU_SDA */
PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG),
/* B6 : ISH_I2C0_SDA ==> PCH_I2C_NVDD_GPU_SCL */
Expand Down Expand Up @@ -65,7 +65,7 @@ static const struct pad_config override_gpio_table[] = {
/* D5 : SRCCLKREQ0# ==> GPU_CLKREQ_ODL */
PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
/* D9 : ISH_SPI_CS# ==> GPU_THERM_INT_ODL */
PAD_CFG_GPI_LOCK(GPP_D9, NONE, LOCK_CONFIG),
PAD_CFG_GPI(GPP_D9, NONE, DEEP),
/* D10 : ISH_SPI_CLK ==> GPP_D10_STRAP */
PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG),
/* D13 : ISH_UART0_RXD ==> NC */
Expand All @@ -80,19 +80,19 @@ static const struct pad_config override_gpio_table[] = {
/* E3 : PROC_GP0 ==> NC */
PAD_NC(GPP_E3, NONE),
/* E4 : SATA_DEVSLP0 ==> PG_PPVAR_GPU_FBVDDQ_X_OD */
PAD_CFG_GPO(GPP_E4, 0, DEEP),
PAD_CFG_GPI(GPP_E4, NONE, DEEP),
/* E5 : SATA_DEVSLP1 ==> PG_GPU_ALLRAILS */
PAD_CFG_GPI(GPP_E5, NONE, DEEP),
PAD_CFG_GPO(GPP_E5, 0, DEEP),
/* E7 : PROC_GP1 ==> NC */
PAD_NC(GPP_E7, NONE),
/* E9 : USB_OC0# ==> USB_A2_OC_ODL */
PAD_CFG_NF_LOCK(GPP_E9, NONE, NF1, LOCK_CONFIG),
/* E10 : THC0_SPI1_CS# ==> EN_PP0950_GPU_X */
PAD_CFG_GPO_LOCK(GPP_E10, 0, LOCK_CONFIG),
/* E16 : RSVD_TP ==> PG_PPVAR_GPU_NVVDD_X_OD */
PAD_CFG_GPO(GPP_E16, 0, DEEP),
PAD_CFG_GPI(GPP_E16, NONE, DEEP),
/* E17 : RSVD_TP ==> PG_PP0950_GPU_X_OD */
PAD_CFG_GPI_LOCK(GPP_E17, NONE, LOCK_CONFIG),
PAD_CFG_GPI(GPP_E17, NONE, DEEP),
/* E18 : DDP1_CTRLCLK ==> EN_PP1800_GPU_X */
PAD_CFG_GPO(GPP_E18, 0, DEEP),
/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
Expand Down
31 changes: 9 additions & 22 deletions src/mainboard/google/brya/variants/agah/overridetree.cb
View file
Expand Up @@ -127,28 +127,6 @@ chip soc/intel/alderlake
register "property_list[0].integer" = "1"
device i2c 1a on end
end
chip drivers/i2c/max98390
register "desc" = ""MAX98390 Speaker Amp 0""
register "uid" = "0"
register "name" = ""MXW0""
register "r0_calib_key" = ""dsm_calib_r0_0""
register "temperature_calib_key" = ""dsm_calib_temp_0""
register "dsm_param_file_name" = ""dsm_param_R""
register "vmon_slot_no" = "0"
register "imon_slot_no" = "1"
device i2c 0x3a on end
end
chip drivers/i2c/max98390
register "desc" = ""MAX98390 Speaker Amp 1""
register "uid" = "1"
register "name" = ""MXW1""
register "r0_calib_key" = ""dsm_calib_r0_1""
register "temperature_calib_key" = ""dsm_calib_temp_1""
register "dsm_param_file_name" = ""dsm_param_L""
register "vmon_slot_no" = "1"
register "imon_slot_no" = "0"
device i2c 0x3b on end
end
end #I2C0
device ref i2c1 on end # GPU
device ref i2c2 on end # External GPU
Expand Down Expand Up @@ -191,6 +169,15 @@ chip soc/intel/alderlake
device generic 0 on end
end
end #PCIE8 SD card
device ref hda on
chip drivers/generic/max98357a
register "hid" = ""MX98360A""
register "sdmode_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
register "sdmode_delay" = "5"
device generic 0 on end
end
end
device ref pch_espi on
chip ec/google/chromeec
use conn0 as mux_conn[0]
Expand Down
6 changes: 4 additions & 2 deletions src/mainboard/google/brya/variants/banshee/gpio.c
View file
Expand Up @@ -101,7 +101,8 @@ static const struct pad_config override_gpio_table[] = {
/* D10 : ISH_SPI_CLK ==> USB_C2_LSX_RX_STRAP */
/* D11 : ISH_SPI_MISO ==> USB_C3_LSX_TX */
PAD_CFG_NF_LOCK(GPP_D11, NONE, NF4, LOCK_CONFIG),
/* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */
/* D12 : ISH_SPI_MOSI ==> USB_C3_LSX_RX */
PAD_CFG_NF_LOCK(GPP_D12, NONE, NF4, LOCK_CONFIG),
/* D13 : ISH_UART0_RXD ==> NC */
PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG),
/* D14 : ISH_UART0_TXD ==> NC */
Expand Down Expand Up @@ -186,7 +187,8 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC(GPP_F20, NONE),
/* F21 : EXT_PWR_GATE2# ==> NC */
PAD_NC(GPP_F21, NONE),
/* F22 : NC */
/* F22 : NC ==> MIC_SW */
PAD_CFG_GPI_GPIO_DRIVER(GPP_F22, NONE, DEEP),
/* F23 : NC */

/* H0 : GPPH0_BOOT_STRAP1 */
Expand Down
11 changes: 11 additions & 0 deletions src/mainboard/google/brya/variants/banshee/overridetree.cb
View file
Expand Up @@ -196,6 +196,17 @@ chip soc/intel/alderlake
register "property_list[0].integer" = "1"
device i2c 1a on end
end
chip drivers/generic/gpio_keys
register "name" = ""MUTE""
register "label" = ""mic_mute_switch""
register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_F22)"
register "key.wakeup_route" = "WAKEUP_ROUTE_DISABLED"
register "key.dev_name" = ""MMSW""
register "key.linux_code" = "SW_MUTE_DEVICE"
register "key.linux_input_type" = "EV_SW"
register "key.label" = ""mic_mute_switch_key""
device generic 0 on end
end
end #I2C0
device ref i2c1 on
chip drivers/i2c/tpm
Expand Down
10 changes: 3 additions & 7 deletions src/mainboard/google/brya/variants/baseboard/brask/gpio.c
View file
Expand Up @@ -80,7 +80,7 @@ static const struct pad_config gpio_table[] = {
/* B13 : PLTRST# ==> PLT_RST_L */
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
/* B14 : SPKR ==> PWM_PP3300_BUZZER */
PAD_CFG_NF_LOCK(GPP_B14, NONE, NF1, LOCK_CONFIG),
PAD_CFG_GPO_LOCK(GPP_B14, 0, LOCK_CONFIG),
/* B15 : TIME_SYNC0 ==> TP159 */
PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
/* B16 : I2C5_SDA ==> NC */
Expand Down Expand Up @@ -118,7 +118,7 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_C7, NONE),

/* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */
PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG),
PAD_CFG_GPO_LOCK(GPP_D0, 0, LOCK_CONFIG),
/* D1 : ISH_GP1 ==> FP_RST_ODL */
PAD_CFG_GPO_LOCK(GPP_D1, 1, LOCK_CONFIG),
/* D2 : ISH_GP2 ==> EN_FP_PWR */
Expand Down Expand Up @@ -426,11 +426,7 @@ static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
};

const struct cros_gpio *__weak variant_cros_gpios(size_t *num)
{
*num = ARRAY_SIZE(cros_gpios);
return cros_gpios;
}
DECLARE_WEAK_CROS_GPIOS(cros_gpios);

const struct pad_config *__weak variant_romstage_gpio_table(size_t *num)
{
Expand Down
6 changes: 1 addition & 5 deletions src/mainboard/google/brya/variants/baseboard/brya/gpio.c
View file
Expand Up @@ -445,11 +445,7 @@ static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
};

const struct cros_gpio *__weak variant_cros_gpios(size_t *num)
{
*num = ARRAY_SIZE(cros_gpios);
return cros_gpios;
}
DECLARE_WEAK_CROS_GPIOS(cros_gpios);

const struct pad_config *__weak variant_romstage_gpio_table(size_t *num)
{
Expand Down
8 changes: 6 additions & 2 deletions src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
View file
Expand Up @@ -15,7 +15,6 @@
const struct pad_config *variant_gpio_table(size_t *num);
const struct pad_config *variant_gpio_override_table(size_t *num);
const struct pad_config *variant_early_gpio_table(size_t *num);
const struct cros_gpio *variant_cros_gpios(size_t *num);
const struct pad_config *variant_romstage_gpio_table(size_t *num);

const struct mb_cfg *variant_memory_params(void);
Expand All @@ -30,11 +29,13 @@ enum s0ix_entry {
S0IX_ENTRY,
};

void variant_generate_s0ix_hook(enum s0ix_entry);
void variant_generate_s0ix_hook(enum s0ix_entry entry);

/* Modify devictree settings during ramstage */
void variant_devtree_update(void);

void variant_update_descriptor(void);

struct cpu_power_limits {
uint16_t mchid;
u8 cpu_tdp;
Expand Down Expand Up @@ -81,4 +82,7 @@ void variant_update_psys_power_limits(const struct cpu_power_limits *limits,
size_t num_entries,
const struct psys_config *config);

void variant_init(void);
void variant_finalize(void);

#endif /*__BASEBOARD_VARIANTS_H__ */
30 changes: 20 additions & 10 deletions src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
View file
Expand Up @@ -74,33 +74,43 @@ chip soc/intel/alderlake
.i2c[0] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 650,
.fall_time_ns = 400,
.data_hold_time_ns = 50,
.speed_config[0] = {
.scl_lcnt = 157,
.scl_hcnt = 78,
}
},
.i2c[1] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 650,
.fall_time_ns = 400,
.data_hold_time_ns = 50,
.speed_config[0] = {
.scl_lcnt = 157,
.scl_hcnt = 78,
}
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 650,
.fall_time_ns = 400,
.data_hold_time_ns = 50,
.speed_config[0] = {
.scl_lcnt = 157,
.scl_hcnt = 78,
}
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 650,
.fall_time_ns = 400,
.data_hold_time_ns = 50,
.speed_config[0] = {
.scl_lcnt = 157,
.scl_hcnt = 78,
}
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 650,
.fall_time_ns = 400,
.data_hold_time_ns = 50,
.speed_config[0] = {
.scl_lcnt = 157,
.scl_hcnt = 78,
}
},
}"

Expand Down
103 changes: 49 additions & 54 deletions src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
View file
Expand Up @@ -29,13 +29,13 @@ static const struct pad_config gpio_table[] = {
/* A12 : NC */
PAD_NC(GPP_A12, NONE),
/* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG),
/* A14 : USB_OC1# ==> NC */
PAD_NC(GPP_A14, NONE),
/* A15 : USB_OC2# ==> NC */
PAD_NC(GPP_A15, NONE),
/* A16 : USB_OC3# ==> NC */
PAD_NC(GPP_A16, NONE),
PAD_NC_LOCK(GPP_A16, NONE, LOCK_CONFIG),
/* A17 : NC */
PAD_NC(GPP_A17, NONE),
/* A18 : NC */
Expand All @@ -58,17 +58,17 @@ static const struct pad_config gpio_table[] = {
/* B2 : NC */
PAD_NC(GPP_B2, NONE),
/* B3 : NC */
PAD_NC(GPP_B3, NONE),
PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG),
/* B4 : NC */
PAD_NC(GPP_B4, NONE),
PAD_NC_LOCK(GPP_B4, NONE, LOCK_CONFIG),
/* B5 : I2C2_SDA ==> SOC_I2C_SUB_SDA */
PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG),
/* B6 : I2C2_SCL ==> SOC_I2C_SUB_SCL */
PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG),
/* B7 : I2C3_SDA ==> SOC_I2C_AUDIO_SDA */
PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
/* B8 : I2C3_SCL ==> SOC_I2C_AUDIO_SCL */
PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
/* B9 : Not available */
PAD_NC(GPP_B9, NONE),
/* B10 : Not available */
Expand All @@ -80,13 +80,13 @@ static const struct pad_config gpio_table[] = {
/* B13 : PLTRST# ==> PLT_RST_L */
PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
/* B14 : SPKR ==> GPP_B14_STRAP */
PAD_NC(GPP_B14, NONE),
PAD_NC_LOCK(GPP_B14, NONE, LOCK_CONFIG),
/* B15 : NC */
PAD_NC(GPP_B15, NONE),
PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
/* B16 : I2C5_SDA ==> SOC_I2C_TCHPAD_SDA */
PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
PAD_CFG_NF_LOCK(GPP_B16, NONE, NF2, LOCK_CONFIG),
/* B17 : I2C5_SCL ==> SOC_I2C_TCHPAD_SCL */
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
PAD_CFG_NF_LOCK(GPP_B17, NONE, NF2, LOCK_CONFIG),
/* B18 : GPP_B18 ==> GPP_B18_STRAP */
PAD_NC(GPP_B18, NONE),
/* B19 : Not available */
Expand Down Expand Up @@ -118,13 +118,13 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, INVERT),

/* D0 : NC */
PAD_NC(GPP_D0, NONE),
PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG),
/* D1 : NC */
PAD_NC(GPP_D1, NONE),
PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG),
/* D2 : NC */
PAD_NC(GPP_D2, NONE),
PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
/* D3 : ISH_GP3 ==> WCAM_RST_L */
PAD_CFG_GPO(GPP_D3, 0, DEEP),
PAD_CFG_GPO_LOCK(GPP_D3, 0, LOCK_CONFIG),
/* D4 : IMGCLKOUT0 ==> BT_DISABLE_L */
PAD_CFG_GPO(GPP_D4, 1, DEEP),
/* D5 : NC */
Expand All @@ -136,64 +136,64 @@ static const struct pad_config gpio_table[] = {
/* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
/* D9 : NC */
PAD_NC(GPP_D9, NONE),
PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
/* D10 : ISH_SPI_CLK ==> GPP_D10_STRAP */
PAD_NC(GPP_D10, NONE),
PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG),
/* D11 : NC */
PAD_NC(GPP_D11, NONE),
PAD_NC_LOCK(GPP_D11, NONE, LOCK_CONFIG),
/* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */
PAD_NC(GPP_D12, NONE),
PAD_NC_LOCK(GPP_D12, NONE, LOCK_CONFIG),
/* D13 : NC */
PAD_NC(GPP_D13, NONE),
PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG),
/* D14 : NC */
PAD_NC(GPP_D14, NONE),
PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG),
/* D15 : ISH_UART0_RTS# ==> EN_PP2800_WCAM_X */
PAD_CFG_GPO(GPP_D15, 0, DEEP),
PAD_CFG_GPO_LOCK(GPP_D15, 0, LOCK_CONFIG),
/* D16 : ISH_UART0_CTS# ==> EN_PP1800_PP1200_WCAM_X */
PAD_CFG_GPO(GPP_D16, 0, DEEP),
PAD_CFG_GPO_LOCK(GPP_D16, 0, LOCK_CONFIG),
/* D17 : NC */
PAD_NC(GPP_D17, NONE),
PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG),
/* D18 : NC */
PAD_NC(GPP_D18, NONE),
PAD_NC_LOCK(GPP_D18, NONE, LOCK_CONFIG),
/* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */
PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),

/* E0 : NC */
PAD_NC(GPP_E0, NONE),
/* E1 : THC0_SPI1_IO2 ==> MEM_STRAP_0 */
PAD_CFG_GPI(GPP_E1, NONE, DEEP),
PAD_CFG_GPI_LOCK(GPP_E1, NONE, LOCK_CONFIG),
/* E2 : THC0_SPI1_IO3 ==> MEM_STRAP_1 */
PAD_CFG_GPI(GPP_E2, NONE, DEEP),
PAD_CFG_GPI_LOCK(GPP_E2, NONE, LOCK_CONFIG),
/* E3 : PROC_GP0 ==> MEM_STRAP_2 */
PAD_CFG_GPI(GPP_E3, NONE, DEEP),
/* E4 : NC */
PAD_NC(GPP_E4, NONE),
/* E5 : NC */
PAD_NC(GPP_E5, NONE),
/* E6 : THC0_SPI1_RST# ==> GPP_E6_STRAP */
PAD_NC(GPP_E6, NONE),
PAD_NC_LOCK(GPP_E6, NONE, LOCK_CONFIG),
/* E7 : NC */
PAD_NC(GPP_E7, NONE),
/* E8 : GPP_E8 ==> WLAN_DISABLE_L */
PAD_CFG_GPO(GPP_E8, 1, DEEP),
/* E9 : NC */
PAD_NC(GPP_E9, NONE),
PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG),
/* E10 : NC */
PAD_NC(GPP_E10, NONE),
PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG),
/* E11 : NC */
PAD_NC(GPP_E11, NONE),
PAD_NC_LOCK(GPP_E11, NONE, LOCK_CONFIG),
/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E12, NONE, LOCK_CONFIG),
/* E13 : NC */
PAD_NC(GPP_E13, NONE),
PAD_NC_LOCK(GPP_E13, NONE, LOCK_CONFIG),
/* E14 : DDSP_HPDA ==> EDP_HPD */
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
/* E15 : NC */
PAD_NC(GPP_E15, NONE),
/* E16 : NC */
PAD_NC(GPP_E16, NONE),
/* E17 : NC */
PAD_NC(GPP_E17, NONE),
PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG),
/* E18 : NC */
PAD_NC(GPP_E18, NONE),
/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
Expand Down Expand Up @@ -230,21 +230,21 @@ static const struct pad_config gpio_table[] = {
/* F10 : GPP_F10 ==> GPP_F10_STRAP */
PAD_NC(GPP_F10, NONE),
/* F11 : NC */
PAD_NC(GPP_F11, NONE),
PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
/* F12 : GSXDOUT ==> WWAN_RST_L */
PAD_CFG_GPO(GPP_F12, 0, DEEP),
PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
/* F13 : GSXSLOAD ==> SOC_PEN_DETECT_R_ODL */
PAD_CFG_GPI_GPIO_DRIVER(GPP_F13, NONE, DEEP),
PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_F13, NONE, LOCK_CONFIG),
/* F14 : GSXDIN ==> TCHPAD_INT_ODL */
PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, PLTRST, LEVEL, INVERT),
PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F14, NONE, LEVEL, INVERT, LOCK_CONFIG),
/* F15 : GSXSRESET# ==> SOC_PEN_DETECT_ODL */
PAD_CFG_GPI_SCI_HIGH(GPP_F15, NONE, DEEP, EDGE_SINGLE),
PAD_CFG_GPI_SCI_HIGH_LOCK(GPP_F15, NONE, EDGE_SINGLE, LOCK_CONFIG),
/* F16 : NC */
PAD_NC(GPP_F16, NONE),
PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
/* F17 : THC1_SPI2_RST# ==> EC_SOC_WAKE_ODL */
PAD_CFG_GPI_SCI(GPP_F17, NONE, DEEP, LEVEL, INVERT),
PAD_CFG_GPI_SCI_LOCK(GPP_F17, NONE, LEVEL, INVERT, LOCK_CONFIG),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG),
/* F19 : Not available */
PAD_NC(GPP_F19, NONE),
/* F20 : Not available */
Expand All @@ -263,11 +263,11 @@ static const struct pad_config gpio_table[] = {
/* H2 : GPP_H2_STRAP */
PAD_NC(GPP_H2, NONE),
/* H3 : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */
PAD_CFG_GPI_SCI_LOW(GPP_H3, NONE, DEEP, EDGE_SINGLE),
PAD_CFG_GPI_SCI_LOW_LOCK(GPP_H3, NONE, EDGE_SINGLE, LOCK_CONFIG),
/* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */
PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
PAD_CFG_NF_LOCK(GPP_H4, NONE, NF1, LOCK_CONFIG),
/* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */
PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
PAD_CFG_NF_LOCK(GPP_H5, NONE, NF1, LOCK_CONFIG),
/* H6 : I2C1_SDA ==> SOC_I2C_TCHSCR_SDA */
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
/* H7 : I2C1_SCL ==> SOC_I2C_TCHSCR_SCL */
Expand All @@ -281,9 +281,9 @@ static const struct pad_config gpio_table[] = {
/* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
/* H12 : UART0_RTS# ==> SD_PERST_L */
PAD_CFG_GPO(GPP_H12, 1, DEEP),
PAD_CFG_GPO_LOCK(GPP_H12, 1, LOCK_CONFIG),
/* H13 : UART0_CTS# ==> EN_PP3300_SD_X */
PAD_CFG_GPO(GPP_H13, 1, DEEP),
PAD_CFG_GPO_LOCK(GPP_H13, 1, LOCK_CONFIG),
/* H14 : Not available */
PAD_NC(GPP_H14, NONE),
/* H15 : NC */
Expand Down Expand Up @@ -432,12 +432,7 @@ static const struct cros_gpio cros_gpios[] = {
CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
};

const struct cros_gpio *__weak variant_cros_gpios(size_t *num)
{
*num = ARRAY_SIZE(cros_gpios);
return cros_gpios;
}
DECLARE_CROS_GPIOS(cros_gpios);

const struct pad_config *__weak variant_romstage_gpio_table(size_t *num)
{
Expand Down
2 changes: 2 additions & 0 deletions src/mainboard/google/brya/variants/brask/include/variant/gpio.h
View file
Expand Up @@ -5,4 +5,6 @@

#include <baseboard/gpio.h>

#define NFC_POWER GPP_D3

#endif /* __MAINBOARD_GPIO_H__ */
10 changes: 10 additions & 0 deletions src/mainboard/google/brya/variants/brask/variant.c
View file
Expand Up @@ -3,9 +3,19 @@
#include <chip.h>
#include <fw_config.h>
#include <baseboard/variants.h>
#include <variant/gpio.h>
#include <acpi/acpigen.h>

void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
{
config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO,
NAU88L25B_I2S));
}

void variant_generate_s0ix_hook(enum s0ix_entry entry)
{
if (entry == S0IX_ENTRY)
acpigen_soc_clear_tx_gpio(NFC_POWER);
else if (entry == S0IX_EXIT)
acpigen_soc_set_tx_gpio(NFC_POWER);
}
23 changes: 22 additions & 1 deletion src/mainboard/google/brya/variants/brya0/fw_config.c
View file
Expand Up @@ -26,6 +26,19 @@ static const struct pad_config sndw_enable_pads[] = {
PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1), /* SDW_SPKR_DATA */
};

static const struct pad_config max98360_enable_pads[] = {
PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), /* I2S_SPKR_SCLK_R */
PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), /* I2S_SPKR_SFRM_R */
PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), /* I2S_PCH_TX_SPKR_RX_R */
PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), /* I2S_PCH_RX_SPKR_TX */
PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC_CLK0_R */
PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC_DATA0_R */
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), /* DMIC_CLK1_R */
PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* DMIC_DATA1_R */
PAD_NC(GPP_R6, NONE),
PAD_NC(GPP_R7, NONE),
};

static const struct pad_config sndw_disable_pads[] = {
PAD_NC(GPP_S0, NONE),
PAD_NC(GPP_S1, NONE),
Expand Down Expand Up @@ -110,7 +123,7 @@ static void fw_config_handle(void *unused)
gpio_configure_pads(i2s0_enable_pads, ARRAY_SIZE(i2s0_enable_pads));
gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads));
gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
} else {
} else if (!fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))) {
printk(BIOS_INFO, "BT offload disabled\n");
gpio_configure_pads(i2s0_disable_pads, ARRAY_SIZE(i2s0_disable_pads));
gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads));
Expand All @@ -126,5 +139,13 @@ static void fw_config_handle(void *unused)
printk(BIOS_INFO, "Configure audio over I2S with ALC1019 NAU88L25B.\n");
enable_i2s();
}

if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))) {
printk(BIOS_INFO, "Configure audio over I2S with MAX98360 ALC5682I.\n");
gpio_configure_pads(max98360_enable_pads, ARRAY_SIZE(max98360_enable_pads));
printk(BIOS_INFO, "BT offload enabled\n");
gpio_configure_pads(i2s0_disable_pads, ARRAY_SIZE(i2s0_disable_pads));
gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
}
}
BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
22 changes: 17 additions & 5 deletions src/mainboard/google/brya/variants/brya0/overridetree.cb
View file
Expand Up @@ -12,11 +12,12 @@ fw_config
option KB_BL_PRESENT 1
end
field AUDIO 8 10
option AUDIO_UNKNOWN 0
option MAX98357_ALC5682I_I2S 1
option MAX98373_ALC5682_SNDW 2
option MAX98373_NAU88L25B_I2S 3
option ALC1019_NAU88L25B_I2S 4
option AUDIO_UNKNOWN 0
option MAX98357_ALC5682I_I2S 1
option MAX98373_ALC5682_SNDW 2
option MAX98373_NAU88L25B_I2S 3
option ALC1019_NAU88L25B_I2S 4
option MAX98360_ALC5682I_I2S 5
end
field DB_LTE 11 12
option LTE_ABSENT 0
Expand Down Expand Up @@ -254,6 +255,7 @@ chip soc/intel/alderlake
register "property_list[0].integer" = "1"
device i2c 1a on
probe AUDIO MAX98357_ALC5682I_I2S
probe AUDIO MAX98360_ALC5682I_I2S
end
end
chip drivers/i2c/nau8825
Expand Down Expand Up @@ -611,6 +613,16 @@ chip soc/intel/alderlake
end
end

chip drivers/generic/max98357a
register "hid" = ""MX98360A""
register "sdmode_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
register "sdmode_delay" = "5"
device generic 0 on
probe AUDIO MAX98360_ALC5682I_I2S
end
end

chip drivers/intel/soundwire
device generic 0 on
probe AUDIO MAX98373_ALC5682_SNDW
Expand Down
8 changes: 8 additions & 0 deletions src/mainboard/google/brya/variants/craask/include/variant/ec.h
View file
@@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */

#ifndef __VARIANT_EC_H__
#define __VARIANT_EC_H__

#include <baseboard/ec.h>

#endif
8 changes: 8 additions & 0 deletions src/mainboard/google/brya/variants/craask/include/variant/gpio.h
View file
@@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */

#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H

#include <baseboard/gpio.h>

#endif
5 changes: 5 additions & 0 deletions src/mainboard/google/brya/variants/craask/memory/Makefile.inc
View file
@@ -0,0 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# This is an auto-generated file. Do not edit!!
# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate.

SPD_SOURCES = placeholder
1 change: 1 addition & 0 deletions src/mainboard/google/brya/variants/craask/memory/dram_id.generated.txt
View file
@@ -0,0 +1 @@
DRAM Part Name ID to assign
11 changes: 11 additions & 0 deletions src/mainboard/google/brya/variants/craask/memory/mem_parts_used.txt
View file
@@ -0,0 +1,11 @@
# This is a CSV file containing a list of memory parts used by this variant.
# One part per line with an optional fixed ID in column 2.
# Only include a fixed ID if it is required for legacy reasons!
# Generated IDs are dependent on the order of parts in this file,
# so new parts must always be added at the end of the file!
#
# Generate an updated Makefile.inc and dram_id.generated.txt by running the
# part_id_gen tool from util/spd_tools.
# See util/spd_tools/README.md for more details and instructions.

# Part Name
6 changes: 6 additions & 0 deletions src/mainboard/google/brya/variants/craask/overridetree.cb
View file
@@ -0,0 +1,6 @@
chip soc/intel/alderlake

device domain 0 on
end

end
1 change: 1 addition & 0 deletions src/mainboard/google/brya/variants/crota/Makefile.inc
View file
@@ -1,5 +1,6 @@
bootblock-y += gpio.c

romstage-y += gpio.c
romstage-y += memory.c

ramstage-y += gpio.c
102 changes: 102 additions & 0 deletions src/mainboard/google/brya/variants/crota/memory.c
View file
@@ -0,0 +1,102 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */

#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <gpio.h>

static const struct mb_cfg baseboard_memcfg = {
.type = MEM_TYPE_LP5X,

.rcomp = {
/* Baseboard uses only 100ohm Rcomp resistors */
.resistor = 100,

/* Baseboard Rcomp target values */
.targets = { 40, 36, 35, 35, 35 },
},

/* DQ byte map */
.lpx_dq_map = {
.ddr0 = {
.dq0 = { 3, 2, 1, 0, 5, 4, 6, 7, },
.dq1 = { 15, 14, 12, 13, 8, 9, 10, 11, },
},
.ddr1 = {
.dq0 = { 0, 2, 3, 1, 5, 7, 4, 6, },
.dq1 = { 14, 13, 15, 12, 8, 9, 11, 10, },
},
.ddr2 = {
.dq0 = { 1, 2, 0, 3, 4, 6, 5, 7, },
.dq1 = { 15, 13, 12, 14, 9, 10, 8, 11, },
},
.ddr3 = {
.dq0 = { 2, 1, 3, 0, 7, 4, 5, 6, },
.dq1 = { 13, 12, 15, 14, 9, 11, 8, 10, },
},
.ddr4 = {
.dq0 = { 1, 2, 3, 0, 6, 4, 5, 7, },
.dq1 = { 15, 13, 14, 12, 10, 9, 8, 11, },
},
.ddr5 = {
.dq0 = { 1, 0, 3, 2, 6, 7, 4, 5, },
.dq1 = { 14, 12, 15, 13, 8, 9, 10, 11, },
},
.ddr6 = {
.dq0 = { 0, 2, 1, 3, 4, 7, 5, 6, },
.dq1 = { 12, 13, 15, 14, 9, 11, 10, 8, },
},
.ddr7 = {
.dq0 = { 3, 2, 1, 0, 5, 4, 6, 7, },
.dq1 = { 13, 15, 11, 12, 10, 9, 14, 8, },
},
},

/* DQS CPU<>DRAM map */
.lpx_dqs_map = {
.ddr0 = { .dqs0 = 0, .dqs1 = 1 },
.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
.ddr7 = { .dqs0 = 0, .dqs1 = 1 }
},

.lp5x_config = {
.ccc_config = 0xff,
},

.ect = 1, /* Early Command Training */

};

const struct mb_cfg *variant_memory_params(void)
{
return &baseboard_memcfg;
}

int variant_memory_sku(void)
{
/*
* Memory configuration board straps
* GPIO_MEM_CONFIG_0 GPP_E11
* GPIO_MEM_CONFIG_1 GPP_E2
* GPIO_MEM_CONFIG_2 GPP_E1
* GPIO_MEM_CONFIG_3 GPP_E12
*/
gpio_t spd_gpios[] = {
GPP_E11,
GPP_E2,
GPP_E1,
GPP_E12,
};

return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
}

bool variant_is_half_populated(void)
{
/* GPIO_MEM_CH_SEL GPP_E13 */
return gpio_get(GPP_E13);
}
312 changes: 310 additions & 2 deletions src/mainboard/google/brya/variants/crota/overridetree.cb
View file
@@ -1,6 +1,314 @@
fw_config
field MB_SD 0 1
option SD_ABSENT 0
option SD_GL9750 1
end
field KB_BL 2 2
option KB_BL_ABSENT 0
option KB_BL_PRESENT 1
end
field AUDIO 3 5
option AUDIO_UNKNOWN 0
option MAX98360_CS42L42 1
end
field DB_LTE 6 7
option LTE_ABSENT 0
option LTE_USB 1
end
end

chip soc/intel/alderlake

device domain 0 on
end
# Acoustic settings
register "acoustic_noise_mitigation" = "1"
register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_4"
register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_4"
register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1"
register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"

# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| GSPI1 | Fingerprint MCU |
#| I2C0 | Audio |
#| I2C1 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| I2C2 | |
#| I2C3 | Touchscreen |
#| I2C5 | Trackpad |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.i2c[0] = {
.speed = I2C_SPEED_FAST,
},
.i2c[1] = {
.early_init = 1,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 600,
.fall_time_ns = 400,
.data_hold_time_ns = 50,
},
.i2c[2] = {
.speed = I2C_SPEED_FAST,
},
.i2c[3] = {
.speed = I2C_SPEED_FAST,
.rise_time_ns = 650,
.fall_time_ns = 400,
.data_hold_time_ns = 50,
},
.i2c[5] = {
.speed = I2C_SPEED_FAST,
},
}"

register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1
register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2_C4
register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2_C6
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2_C8
register "usb3_ports[0]" = "USB3_PORT_EMPTY"
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port
register "tcss_ports[1]" = "TCSS_PORT_EMPTY"

device domain 0 on
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
device generic 0 on end
end
end
device ref pcie_rp3 on
chip soc/intel/common/block/pcie/rtd3
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)"
register "srcclk_pin" = "1"
device generic 0 alias emmc_rtd3 on end
end
# Enable PCIe-to-eMMC bridge PCIE 3 using clk 1
register "pch_pcie_rp[PCH_RP(3)]" = "{
.clk_src = 1,
.clk_req = 1,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end #PCIE3 BH799BB
device ref tcss_dma0 on
chip drivers/intel/usb4/retimer
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
use tcss_usb3_port1 as dfp[0].typec_port
device generic 0 on end
end
end
device ref tcss_dma1 on
chip drivers/intel/usb4/retimer
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
use tcss_usb3_port3 as dfp[0].typec_port
device generic 0 on end
end
end
device ref pcie_rp6 off end #PCIE6 WWAN
device ref pcie_rp8 on
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
register "srcclk_pin" = "3"
device generic 0 on end
end
end #PCIE8 SD card
device ref pcie4_0 on
# Enable CPU PCIE RP 1 using CLK 1
register "cpu_pcie_rp[CPU_RP(1)]" = "{
.clk_req = 1,
.clk_src = 1,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end
device ref i2c0 on
chip drivers/i2c/cs42l42
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B13)"
register "ts_inv" = "true"
register "ts_dbnc_rise" = "RISE_DEB_1000_MS"
register "ts_dbnc_fall" = "FALL_DEB_0_MS"
register "btn_det_init_dbnce" = "100"
register "btn_det_event_dbnce" = "10"
register "bias_lvls[0]" = "15"
register "bias_lvls[1]" = "8"
register "bias_lvls[2]" = "4"
register "bias_lvls[3]" = "1"
register "hs_bias_ramp_rate" = "HSBIAS_RAMP_SLOW"
register "hs_bias_sense_disable" = "true"
device i2c 48 on end
end
end #I2C0
device ref i2c1 on
chip drivers/i2c/tpm
register "hid" = ""GOOG0005""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
device i2c 50 on end
end
end
device ref i2c3 on
chip drivers/i2c/hid
register "generic.hid" = ""ELAN9050""
register "generic.desc" = ""ELAN Touchscreen""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
register "generic.probed" = "1"
register "generic.reset_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
register "generic.reset_delay_ms" = "300"
register "generic.reset_off_delay_ms" = "1"
register "generic.enable_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
register "generic.enable_delay_ms" = "6"
register "generic.stop_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
register "generic.stop_off_delay_ms" = "1"
register "generic.has_power_resource" = "1"
register "generic.disable_gpio_export_in_crs" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 0x10 on end
end
end
device ref i2c5 on
chip drivers/i2c/generic
register "hid" = ""ELAN0000""
register "desc" = ""ELAN Touchpad""
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
register "wake" = "GPE0_DW2_14"
register "probed" = "1"
device i2c 15 on end
end
chip drivers/i2c/hid
register "generic.hid" = ""GXTP7288""
register "generic.desc" = ""Goodix Touchpad""
register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)"
register "generic.wake" = "GPE0_DW2_14"
register "generic.probed" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 2c on end
end
end
device ref hda on
chip drivers/generic/max98357a
register "hid" = ""MX98360A""
register "sdmode_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
register "sdmode_delay" = "5"
device generic 0 on end
end
end
device ref gspi1 on
chip drivers/spi/acpi
register "name" = ""CRFP""
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "uid" = "1"
register "compat_string" = ""google,cros-ec-spi""
register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
register "wake" = "GPE0_DW2_15"
device spi 0 on end
end # FPMCU
end
device ref pch_espi on
chip ec/google/chromeec
use conn0 as mux_conn[0]
use conn1 as mux_conn[1]
device pnp 0c09.0 on end
end
end
device ref pmc hidden
chip drivers/intel/pmc_mux
device generic 0 on
chip drivers/intel/pmc_mux/conn
use usb2_port1 as usb2_port
use tcss_usb3_port1 as usb3_port
device generic 0 alias conn0 on end
end
chip drivers/intel/pmc_mux/conn
use usb2_port3 as usb2_port
use tcss_usb3_port3 as usb3_port
device generic 1 alias conn1 on end
end
end
end
end
device ref tcss_xhci on
chip drivers/usb/acpi
device ref tcss_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C0 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
device ref tcss_usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C2 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
device ref tcss_usb3_port3 on end
end
end
end
end
device ref xhci on
chip drivers/usb/acpi
device ref xhci_root_hub on
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C0 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
device ref usb2_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C2 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
device ref usb2_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 WWAN""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb2_port4 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Camera""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb2_port6 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port (MLB)""
register "type" = "UPC_TYPE_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))"
device ref usb2_port8 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Bluetooth""
register "type" = "UPC_TYPE_INTERNAL"
register "reset_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
device ref usb2_port10 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port (MLB)""
register "type" = "UPC_TYPE_USB3_A"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))"
device ref usb3_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 WWAN""
register "type" = "UPC_TYPE_INTERNAL"
device ref usb3_port4 on end
end
end
end
end
end
end
2 changes: 2 additions & 0 deletions src/mainboard/google/brya/variants/felwinter/gpio.c
View file
Expand Up @@ -53,6 +53,8 @@ static const struct pad_config override_gpio_table[] = {
PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG),
/* E18 : DDP1_CTRLCLK ==> NC */
PAD_NC(GPP_E18, NONE),
/* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */
PAD_NC(GPP_E19, NONE),
/* E22 : DDPA_CTRLCLK ==> NC */
PAD_NC(GPP_E22, NONE),
/* E23 : DDPA_CTRLDATA ==> NC */
Expand Down
4 changes: 4 additions & 0 deletions src/mainboard/google/brya/variants/felwinter/overridetree.cb
View file
Expand Up @@ -44,6 +44,10 @@ chip soc/intel/alderlake
[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
}"

# As per Intel Advisory doc#723158, the change is required to prevent possible
# display flickering issue.
register "usb2_phy_sus_pg_disable" = "1"

# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
Expand Down
105 changes: 8 additions & 97 deletions src/mainboard/google/brya/variants/kano/overridetree.cb
View file
Expand Up @@ -22,6 +22,13 @@ chip soc/intel/alderlake
# GPE configuration
register "pmc_gpe0_dw1" = "GPP_D"

# Acoustic settings
register "acoustic_noise_mitigation" = "1"
register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1"
register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1"

register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1
register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable M.2 WWAN

Expand Down Expand Up @@ -56,7 +63,7 @@ chip soc/intel/alderlake
.data_hold_time_ns = 50,
},
.i2c[3] = {
.speed = 390000,
.speed = I2C_SPEED_FAST,
.rise_time_ns = 650,
.fall_time_ns = 400,
.data_hold_time_ns = 50,
Expand Down Expand Up @@ -271,102 +278,6 @@ chip soc/intel/alderlake
end
end
device ref i2c2 on
chip drivers/i2c/sx9324
register "desc" = ""SAR1 Proximity Sensor""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)"
register "speed" = "I2C_SPEED_FAST"
register "uid" = "1"
register "reg_gnrl_ctrl0" = "0x16"
register "reg_gnrl_ctrl1" = "0x21"
register "reg_afe_ctrl0" = "0x00"
register "reg_afe_ctrl1" = "0x10"
register "reg_afe_ctrl2" = "0x00"
register "reg_afe_ctrl3" = "0x00"
register "reg_afe_ctrl4" = "0x07"
register "reg_afe_ctrl5" = "0x00"
register "reg_afe_ctrl6" = "0x00"
register "reg_afe_ctrl7" = "0x07"
register "reg_afe_ctrl8" = "0x12"
register "reg_afe_ctrl9" = "0x0f"
register "reg_prox_ctrl0" = "0x12"
register "reg_prox_ctrl1" = "0x12"
register "reg_prox_ctrl2" = "0x90"
register "reg_prox_ctrl3" = "0x60"
register "reg_prox_ctrl4" = "0x0c"
register "reg_prox_ctrl5" = "0x12"
register "reg_prox_ctrl6" = "0x3c"
register "reg_prox_ctrl7" = "0x58"
register "reg_adv_ctrl0" = "0x00"
register "reg_adv_ctrl1" = "0x00"
register "reg_adv_ctrl2" = "0x00"
register "reg_adv_ctrl3" = "0x00"
register "reg_adv_ctrl4" = "0x00"
register "reg_adv_ctrl5" = "0x05"
register "reg_adv_ctrl6" = "0x00"
register "reg_adv_ctrl7" = "0x00"
register "reg_adv_ctrl8" = "0x00"
register "reg_adv_ctrl9" = "0x00"
register "reg_adv_ctrl10" = "0x5c"
register "reg_adv_ctrl11" = "0x52"
register "reg_adv_ctrl12" = "0xb5"
register "reg_adv_ctrl13" = "0x00"
register "reg_adv_ctrl14" = "0x80"
register "reg_adv_ctrl15" = "0x0c"
register "reg_adv_ctrl16" = "0x38"
register "reg_adv_ctrl17" = "0x56"
register "reg_adv_ctrl18" = "0x33"
register "reg_adv_ctrl19" = "0xf0"
register "reg_adv_ctrl20" = "0xf0"
device i2c 28 on end
end
chip drivers/i2c/sx9324
register "desc" = ""SAR2 Proximity Sensor""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)"
register "speed" = "I2C_SPEED_FAST"
register "uid" = "2"
register "reg_gnrl_ctrl0" = "0x16"
register "reg_gnrl_ctrl1" = "0x21"
register "reg_afe_ctrl0" = "0x00"
register "reg_afe_ctrl1" = "0x10"
register "reg_afe_ctrl2" = "0x00"
register "reg_afe_ctrl3" = "0x00"
register "reg_afe_ctrl4" = "0x07"
register "reg_afe_ctrl5" = "0x00"
register "reg_afe_ctrl6" = "0x00"
register "reg_afe_ctrl7" = "0x07"
register "reg_afe_ctrl8" = "0x12"
register "reg_afe_ctrl9" = "0x0f"
register "reg_prox_ctrl0" = "0x12"
register "reg_prox_ctrl1" = "0x12"
register "reg_prox_ctrl2" = "0x90"
register "reg_prox_ctrl3" = "0x60"
register "reg_prox_ctrl4" = "0x0c"
register "reg_prox_ctrl5" = "0x12"
register "reg_prox_ctrl6" = "0x3c"
register "reg_prox_ctrl7" = "0x58"
register "reg_adv_ctrl0" = "0x00"
register "reg_adv_ctrl1" = "0x00"
register "reg_adv_ctrl2" = "0x00"
register "reg_adv_ctrl3" = "0x00"
register "reg_adv_ctrl4" = "0x00"
register "reg_adv_ctrl5" = "0x05"
register "reg_adv_ctrl6" = "0x00"
register "reg_adv_ctrl7" = "0x00"
register "reg_adv_ctrl8" = "0x00"
register "reg_adv_ctrl9" = "0x00"
register "reg_adv_ctrl10" = "0x5c"
register "reg_adv_ctrl11" = "0x52"
register "reg_adv_ctrl12" = "0xb5"
register "reg_adv_ctrl13" = "0x00"
register "reg_adv_ctrl14" = "0x80"
register "reg_adv_ctrl15" = "0x0c"
register "reg_adv_ctrl16" = "0x38"
register "reg_adv_ctrl17" = "0x56"
register "reg_adv_ctrl18" = "0x33"
register "reg_adv_ctrl19" = "0xf0"
register "reg_adv_ctrl20" = "0xf0"
device i2c 2C on end
end
chip drivers/intel/mipi_camera
register "acpi_hid" = ""INT3474""
register "acpi_uid" = "0"
Expand Down
2 changes: 2 additions & 0 deletions src/mainboard/google/brya/variants/kinox/gpio.c
View file
Expand Up @@ -24,6 +24,8 @@ static const struct pad_config override_gpio_table[] = {
/* B2 : VRALERT# ==> TP153 */
PAD_NC(GPP_B2, NONE),

/* D0 : ISH_GP0 ==> NC */
PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG),
/* D1 : ISH_GP1 ==> NC */
PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG),
/* D2 : ISH_GP2 ==> NC */
Expand Down