diff --git a/Documentation/mainboard/asus/p8h61-m_lx.md b/Documentation/mainboard/asus/p8h61-m_lx.md
@@ -0,0 +1,111 @@
+# ASUS P8H61-M LX
+
+This page describes how to run coreboot on the [ASUS P8H61-M LX].
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | yes        |
++---------------------+------------+
+| Model               | W25Q32BV   |
++---------------------+------------+
+| Size                | 4 MiB      |
++---------------------+------------+
+| Package             | DIP-8      |
++---------------------+------------+
+| Write protection    | no         |
++---------------------+------------+
+| Dual BIOS feature   | no         |
++---------------------+------------+
+| Internal flashing   | yes        |
++---------------------+------------+
+```
+
+### Internal programming
+
+The main SPI flash can be accessed using [flashrom]. By default, only
+the BIOS region of the flash is writable. If you wish to change any
+other region (Management Engine or flash descriptor), then an external
+programmer is required.
+
+The following command may be used to flash coreboot:
+
+```
+$ sudo flashrom --noverify-all --ifd -i bios -p internal -w coreboot.rom
+```
+
+The use of `--noverify-all` is required since the Management Engine
+region is not readable even by the host.
+
+## Known issues
+
+- S3 suspend/resume does not work. This is the case for both coreboot
+  and the vendor firmware, tested with Linux 4.9, Linux 4.17, and
+  OpenBSD 6.3. Interestingly, it is possible to resume from S3 with
+  Linux, but _only_ if the resume is started immediately after the
+  suspend.
+
+- There is no automatic, OS-independent fan control. This is because
+  the super I/O hardware monitor can only obtain valid CPU temperature
+  readings from the PECI agent, whose complete initialisation is not
+  publicly documented. The `coretemp` driver can still be used for
+  accurate CPU temperature readings.
+
+## Untested
+
+- PCIe graphics
+- parallel port
+- PS/2 keyboard
+- EHCI debug
+- S/PDIF audio
+
+## Working
+
+- USB
+- Gigabit Ethernet
+- integrated graphics
+- PCIe
+- SATA
+- PS/2 mouse
+- serial port
+- hardware monitor (see [Known issues](#known-issues) for caveats)
+- onboard audio
+- front panel audio
+- native raminit (2 x 2GB, DDR3-1333)
+- native graphics init (libgfxinit)
+- flashrom under the vendor firmware
+- flashrom under coreboot
+- Wake-on-LAN
+- Using `me_cleaner` (add `-S --whitelist EFFS,FCRS` if not using
+  `me_cleaner` as part of the coreboot build process).
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
++------------------+--------------------------------------------------+
+| Southbridge      | bd82x6x                                          |
++------------------+--------------------------------------------------+
+| CPU              | model_206ax                                      |
++------------------+--------------------------------------------------+
+| Super I/O        | Nuvoton NCT6776                                  |
++------------------+--------------------------------------------------+
+| EC               | None                                             |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel Management Engine                          |
++------------------+--------------------------------------------------+
+```
+
+## Extra resources
+
+- [Board manual]
+- [Flash chip datasheet][W25Q32BV]
+
+[ASUS P8H61-M LX]: https://www.asus.com/Motherboards/P8H61M_LX/
+[W25Q32BV]: https://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.pdf
+[flashrom]: https://flashrom.org/Flashrom
+[Board manual]: http://dlcdnet.asus.com/pub/ASUS/mb/LGA1155/P8H61_M_LX/E6803_P8H61-M_LX.zip
diff --git a/Documentation/mainboard/foxconn/d41s.md b/Documentation/mainboard/foxconn/d41s.md
@@ -0,0 +1,75 @@
+# Foxconn D41S
+
+This page describes how to run coreboot on the [FOXCONN D41S] desktop from [FOXCONN].
+The D42S, D51S, D52S are compatible boards with the difference being the CPU.
+
+## Building coreboot
+
+The default options for this board should result in a fully working image:
+
+	# echo "CONFIG_VENDOR_FOXCONN=y" > .config
+	# echo "CONFIG_BOARD_FOXCONN_D41S=y" >> .config
+	# make olddefconfig && make
+
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+--------+
+| Type                | Value  |
++=====================+========+
+| Socketed flash      | yes    |
++---------------------+--------+
+| Model               | W25X80 |
++---------------------+--------+
+| Size                | 1 MiB  |
++---------------------+--------+
+| In circuit flashing | yes    |
++---------------------+--------+
+| Package             | DIP-8  |
++---------------------+--------+
+| Write protection    | No     |
++---------------------+--------+
+| Dual BIOS feature   | No     |
++---------------------+--------+
+| Internal flashing   | yes    |
++---------------------+--------+
+```
+
+### Internal programming
+
+The SPI flash can be accessed using [flashrom].
+
+### External programming
+
+The easiest to flash externally is to simply extract the SPI flash from its socket.
+To do this gently take the SPI flash out of its socket and flash with your programmer.
+
+**NOTE: Don't forget to set the WP# AND HOLD# to 3V.**
+
+**NOTE2: Make sure to reinsert it in the right direction afterward**
+
+**Location and orientation of the SPI flash socket**
+![][d41s_flash]
+
+[d41s_flash]: d41s_flash.jpg
+
+## Technology
+
+```eval_rst
++------------------+------------------+
+| Northbridge      | Intel Pinevew    |
++------------------+------------------+
+| Southbridge      | Intel NM10       |
++------------------+------------------+
+| CPU              | model_106cx      |
++------------------+------------------+
+| SuperIO          | ITE IT8721F      |
++------------------+------------------+
+| clockgen (CK505) | ICS 9LPRS525AGLF |
++------------------+------------------+
+```
+
+[FOXCONN D41S]: http://www.foxconnchannel.com/ProductDetail.aspx?T=motherboard&U=en-us0000481
+[FOXCONN]: http://www.foxconnchannel.com
+[Flashrom]: https://flashrom.org/Flashrom
diff --git a/Documentation/mainboard/foxconn/d41s_flash.jpg b/Documentation/mainboard/foxconn/d41s_flash.jpg
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
@@ -2,10 +2,18 @@
 
 This section contains documentation about coreboot on specific mainboards.
 
+## ASUS
+
+- [P8H61-M LX](asus/p8h61-m_lx.md)
+
 ## Cavium
 
 - [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)
 
+## Foxconn
+
+- [D41S](foxconn/d41s.md)
+
 ## Gigabyte
 
 - [GA-H61M-S2PV](gigabyte/ga-h61m-s2pv.md)

diff --git a/Documentation/northbridge/intel/sandybridge/nri.md b/Documentation/northbridge/intel/sandybridge/nri.md
@@ -3,7 +3,7 @@
 ## Introduction
 
 This documentation is intended to document the closed source memory controller
-hardware for Intel 2nd Gen (Sandy Bride) and 3rd Gen (Ivy Bridge) core-i CPUs.
+hardware for Intel 2nd Gen (Sandy Bridge) and 3rd Gen (Ivy Bridge) core-i CPUs.
 
 The memory initialization code has to take care of lots of duties:
 1. Selection of operating frequency
@@ -41,13 +41,13 @@ The memory initialization code has to take care of lots of duties:
 ```
 
 ## (Inoffical) register documentation
-- [Sandy Bride - Register documentation](nri_registers.md)
+- [Sandy Bridge - Register documentation](nri_registers.md)
 
 ## Frequency selection
-- [Sandy Bride - Frequency selection](nri_freq.md)
+- [Sandy Bridge - Frequency selection](nri_freq.md)
 
 ## Read training
-- [Sandy Bride - Read training](nri_read.md)
+- [Sandy Bridge - Read training](nri_read.md)
 
 ### SMBIOS type 17
 The SMBIOS specification allows to report the memory configuration in use.
@@ -113,7 +113,7 @@ than a board that doesn't boot at all.
 > **Note:** This feature is available since coreboot 4.5
 
 Try to swap memory modules and or try to use a different vendor. If nothing
-helps you could have a look at capter [Debuggin] or report a ticket
+helps you could have a look at chapter [Debugging] or report a ticket
 at [ticket.coreboot.org]. Please provide a full RAM init log,
 that has been captured using EHCI debug.
 

diff --git a/Documentation/northbridge/intel/sandybridge/nri_freq.md b/Documentation/northbridge/intel/sandybridge/nri_freq.md
@@ -1,7 +1,8 @@
 # Frequency selection
 
 ## Introduction
-This chapter explains the frequency selection done on Sandybride and Ivybridge.
+This chapter explains the frequency selection done on Sandy Bridge and Ivy
+Bridge memory initialization.
 
 ## Definitions
 ```eval_rst
@@ -58,7 +59,7 @@ and thus are called "soft" fuses, as it is possible to ignore them.
 
 > **Note:** Ignoring the fuses might cause system instability !
 
-On Sandy Bride *CAPID0_A* is being read, and on Ivybridge *CAPID0_B* is being
+On Sandy Bridge *CAPID0_A* is being read, and on Ivy Bridge *CAPID0_B* is being
 read. coreboot reads those registers and honors the limit in case the Kconfig
 option `CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES` wasn't set.
 Power users that want to let their RAM run at DRAM's "stock" frequency need to
@@ -84,15 +85,15 @@ by the board manufacturer.
 By using this register it's possible to force a minimum operating frequency.
 
 ## Reference clock
-While Sandybride supports 133 MHz reference clock (REFCK), Ivy Bridge also
+While Sandy Bridge supports 133 MHz reference clock (REFCK), Ivy Bridge also
 supports 100 MHz reference clock. The reference clock is multiplied by the DRAM
 multiplier to select the DRAM frequency (SCK) by the following formula:
 
  REFCK * MULT = 1 / DCK
 
 > **Note:** Since coreboot 4.6 Ivy Bridge supports 100MHz REFCK.
 
-## Sandy Bride's supported frequencies
+## Sandy Bridge's supported frequencies
 ```eval_rst
 +------------+-----------+------------------+-------------------------+---------------+
 | SCK [Mhz]  | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment       |
@@ -111,7 +112,7 @@ multiplier to select the DRAM frequency (SCK) by the following formula:
 +------------+-----------+------------------+-------------------------+---------------+
 ```
 
-## Ivybridge's supported frequencies
+## Ivy Bridge's supported frequencies
 ```eval_rst
 +------------+-----------+------------------+-------------------------+---------------+
 | SCK [Mhz]  | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment       |
@@ -144,7 +145,7 @@ multiplier to select the DRAM frequency (SCK) by the following formula:
 > '1: since coreboot 4.6
 
 ## Multiplier selection
-coreboot select the maximum frequency to operate at by the following formula:
+coreboot selects the maximum frequency to operate at by the following formula:
 ```
 if devicetree's max_mem_clock_mhz > 0:
      freq_max := max_mem_clock_mhz

diff --git a/Documentation/northbridge/intel/sandybridge/nri_read.md b/Documentation/northbridge/intel/sandybridge/nri_read.md
@@ -2,7 +2,7 @@
 
 ## Introduction
 
-This chapter explains the read training sequence done on Sandy Bride and
+This chapter explains the read training sequence done on Sandy Bridge and
 Ivy Bridge memory initialization.
 
 Read training is done to compensate the skew between DQS and SCK and to find

diff --git a/Documentation/northbridge/intel/sandybridge/nri_registers.md b/Documentation/northbridge/intel/sandybridge/nri_registers.md
@@ -1556,7 +1556,7 @@ Please handle with care !
 
 *Width:* 16 Bit
 
-*Desc:*  OTHP Workaround (SandyBridge only) Register,  Channel 0
+*Desc:*  OTHP Workaround (Sandy Bridge only) Register,  Channel 0
 
 ```eval_rst
 +-----------+------------------------------------------------------------------+
@@ -2137,8 +2137,8 @@ Please handle with care !
 +===========+==================================================================+
 |        0:7|                Selected multiplier: 100Mhz [7,12], 133Mhz [3,19] |
 +-----------+------------------------------------------------------------------+
-|         8 | - 1: 100Mhz reference clock                                      |
-|           | - 0: 133Mhz reference clock (IvyBridge only)                     |
+|         8 | - 1: 100Mhz reference clock (Ivy Bridge only)                    |
+|           | - 0: 133Mhz reference clock                                      |
 +-----------+------------------------------------------------------------------+
 |        31 |                                                         PLL busy |
 +-----------+------------------------------------------------------------------+
@@ -2172,3 +2172,4 @@ Please handle with care !
 +===========+==================================================================+
 |         8 |                                                      Force RCOMP |
 +-----------+------------------------------------------------------------------+
+```
diff --git a/Documentation/releases/coreboot-4.1-relnotes.md b/Documentation/releases/coreboot-4.1-relnotes.md
@@ -1,5 +1,5 @@
-Announcing coreboot 4.1
-=======================
+coreboot 4.1 release notes
+==========================
 
 Dear coreboot community,
 

diff --git a/Documentation/releases/coreboot-4.2-relnotes.md b/Documentation/releases/coreboot-4.2-relnotes.md
@@ -1,5 +1,5 @@
-Announcing coreboot 4.2
-=======================
+coreboot 4.2 release notes
+==========================
 
 Halloween 2015 release - just as scary as that sounds
 

diff --git a/Documentation/releases/coreboot-4.3-relnotes.md b/Documentation/releases/coreboot-4.3-relnotes.md
@@ -1,5 +1,5 @@
-Announcing coreboot 4.3
-=======================
+coreboot 4.3 release notes
+==========================
 
 The "Oh, has FOSDEM started?" release
 

diff --git a/Documentation/releases/coreboot-4.4-relnotes.md b/Documentation/releases/coreboot-4.4-relnotes.md
@@ -1,5 +1,5 @@
-Announcing coreboot 4.4
-=======================
+coreboot 4.4 release notes
+==========================
 
 We are happy to announce the release of coreboot 4.4.  This is our
 fourth quarterly release.  Since the last release, we've had 850 commits

diff --git a/Documentation/releases/coreboot-4.5-relnotes.md b/Documentation/releases/coreboot-4.5-relnotes.md
@@ -1,5 +1,5 @@
-Announcing coreboot 4.5
-=======================
+coreboot 4.5 release notes
+==========================
 
 We are happy to announce the release of coreboot 4.5
 

diff --git a/Documentation/releases/coreboot-4.6-relnotes.md b/Documentation/releases/coreboot-4.6-relnotes.md
@@ -1,5 +1,5 @@
-Announcing coreboot 4.6
-=======================
+coreboot 4.6 release notes
+==========================
 
 We are happy to announce the April 2017 release of coreboot, version
 4.6.

diff --git a/Documentation/releases/coreboot-4.9-relnotes.md b/Documentation/releases/coreboot-4.9-relnotes.md
@@ -1,4 +1,4 @@
-coreboot 4.9 release notes
+Upcoming release - coreboot 4.9
 ==========================
 
 The 4.9 release is planned for November 2018

diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md
@@ -1,16 +1,17 @@
 Release notes for previous releases
 ===================================
 
-### * [4.1 - July 2015](coreboot-4.1-relnotes.md)
-### * [4.2 - October 2015](coreboot-4.2-relnotes.md)
-### * [4.3 - January 2016](coreboot-4.3-relnotes.md)
-### * [4.4 - May 2016](coreboot-4.4-relnotes.md)
-### * [4.5 - October 2016](coreboot-4.5-relnotes.md)
-### * [4.6 - April 2017](coreboot-4.6-relnotes.md)
-### * [4.7 - January 2018](coreboot-4.7-relnotes.md)
-### * [4.8 - May 2018](coreboot-4.8.1-relnotes.md)
+* [4.1 - July 2015](coreboot-4.1-relnotes.md)
+* [4.2 - October 2015](coreboot-4.2-relnotes.md)
+* [4.3 - January 2016](coreboot-4.3-relnotes.md)
+* [4.4 - May 2016](coreboot-4.4-relnotes.md)
+* [4.5 - October 2016](coreboot-4.5-relnotes.md)
+* [4.6 - April 2017](coreboot-4.6-relnotes.md)
+* [4.7 - January 2018](coreboot-4.7-relnotes.md)
+* [4.8 - May 2018](coreboot-4.8.1-relnotes.md)
 
 Upcoming release
 ----------------
-### * [4.9 - November 2018](coreboot-4.9-relnotes.md)
+* [4.9 - November 2018](coreboot-4.9-relnotes.md)
+
 Please add to the release notes as changes are added:
diff --git a/Documentation/soc/intel/index.md b/Documentation/soc/intel/index.md
@@ -4,4 +4,5 @@ This section contains documentation about coreboot on specific Intel SOCs.
 
 ## Platforms
 
+- [Common code development strategy](code_development_model/code_development_model.md)
 - [Ice Lake/9th Gen Core-i series](icelake/index.md)
diff --git a/Documentation/util.md b/Documentation/util.md
@@ -0,0 +1,129 @@
+# Utilities
+_Scripts and programs found in the `./util` directory_
+* __abuild__ - coreboot autobuild script builds coreboot images for all
+available targets. `bash`
+* __acpi__ - Walk through all ACPI tables with their addresses. `bash`
+* __amdfwtool__ - Create AMD Firmware combination `C`
+* __amdtools__ - A set of tools to compare extended) K8 memory
+settings. `Perl`
+* __archive__ - Concatenate files and create an archive `C`
+* __mksunxiboot__ - A simple tool to generate bootable image for sunxi
+platform. `C`
+* __autoport__ - Automated porting coreboot to Sandy Bridge/Ivy Bridge
+platforms `Go`
+* __bimgtool__ - A simple tool which generates and verifies boot images
+in the BIMG format, used in systems designed by Imagination
+Technologies, for example the Pistachio SoC. `C`
+* __bincfg__ - Compiler/Decompiler for data blobs with specs `Lex`
+`Yacc`
+* __board_status__ - Tools to collect logs and upload them to the board
+status repository `Bash` `Go`
+* __broadcom__ - Generate Broadcom secure boot image. `C`
+* __cavium__ - Devicetree_convert Tool to convert a DTB to a static C
+file `Python`
+* __cbfstool__
+	* _cbfstool_ - For manipulating CBFS file `C`
+	* _fmaptool_ - Converts plaintext fmd files into fmap blobs `C`
+	* _rmodtool_ - Creates rmodules `C`
+	* _ifwitool_ - For manipulating IFWI `C`
+* __cbmem__ - Cbmem console log reader `C`
+* __checklist__ - Board implementation checklist generator `Make`
+* __chromeos__ - These scripts can be used to extract System Agent
+reference code and other blobs (e.g. mrc.bin, refcode, VGA option roms)
+from a Chrome OS recovery image. `C`
+* __crossgcc__ - A cross toolchain builder for -elf toolchains (ie. no
+libc support)
+* __docker__ - Dockerfiles for _coreboot-sdk_, _coreboot-jenkins-node_,
+_coreboot.org-status_ and _docs.coreboot.org_
+* __dtd_parser__ - DTD structure parser `Python2`
+* __ectool__ - Dumps the RAM of a laptop's Embedded/Environmental
+Controller (EC). `C`
+* __exynos__ - Computes and fills Exynos ROM checksum (for BL1 or BL2).
+`Python2`
+* __futility__ - Firmware utility for signing ChromeOS images `Make`
+* __fuzz-tests__ - Create test cases that crash the jpeg code. `C`
+* __genbuild_h__ - Generate build system definitions `Shell`
+* __genprof__ - Format function tracing logs `Bash` `C`
+* __gitconfig__ - Initialize git repository submodules install git
+hooks `Bash`
+* __ifdtool__ - Extract and dump Intel Firmware Descriptor information
+`C`
+* __intelmetool__ - Dump interesting things about Management Engine
+even if hidden `C`
+* __inteltool__ - Provides information about the Intel CPU/chipset
+hardware configuration (register contents, MSRs, etc). `C`
+* __intelvbttool__ - Parse VBT from VGA BIOS `C`
+* __ipqheader__
+	* _createxbl.py_ - Concatentates XBL segments into one ELF
+image `Python`
+	* _ipqheader.py_ - Returns a packed MBN header image with the
+specified base and size `Python`
+	* _mbncat.py_ - Generate ipq8064 uber SBL `Python`
+	* *mbn_tools.py* - Contains all MBN Utilities for image
+generation `Python`
+* __k8resdump__ - This program will dump the IO/memory/PCI resources
+from the K8 memory controller `C`
+* __kbc1126__ - Tools used to dump the two blobs from the factory
+firmware of many HP laptops with 8051-based SMSC KBC1098/KBC1126
+embedded controller and insert them to the firmware image. `C`
+* __kconfig__ - Build system `Make`
+* __lint__ - Source linter and linting rules `Shell`
+* __marvell__ - Add U-Boot boot loader for Marvell ARMADA38X `C`
+* __[me_cleaner](https://github.com/corna/me_cleaner)__ - Tool for
+partial deblobbing of Intel ME/TXE firmware images `Python`
+* __mma__ - Memory Margin Analysis automation tests `Bash`
+* __msrtool__ - Dumps chipset-specific MSR registers. `C`
+* __mtkheader__ - Generate MediaTek bootload header. `Python2`
+* __nvidia__ - nvidia blob parsers
+* __nvramtool__ - Reads and writes coreboot parameters and displaying
+information from the coreboot table in CMOS/NVRAM. `C`
+* __post__ - Userspace utility that can be used to test POST cards. `C`
+* __qualcomm__ - CMM script to debug Qualcomm coreboot environments.
+`CMM`
+* __release__ - Generate coreboot release `Bash`
+* __riscv__
+	* _make-spike-elf.sh_ - Converts a flat file into an ELF, that
+can be passed to SPIKE, the RISC-V reference emulator.`Bash`
+	* _sifive-gpt.py_ - Wraps the bootblock in a GPT partition for
+SiFive's bootrom. `Python3`
+* __rockchip__ - Generate Rockchip idblock bootloader. `Python2`
+* __romcc__ - Compile a C source file generating a binary that does not
+implicitly use RAM. `C`
+* __sconfig__ - coreboot device tree compiler `Lex` `Yacc`
+* __scripts__
+	* _config_ - Manipulate options in a .config file from the
+command line `Bash`
+	* _cross-repo-cherrypick_ - Pull in patches from another tree
+from a gerrit repository. `Shell`
+	* _dts-to-fmd.sh_ -Converts a depthcharge fmap.dts into an
+fmaptool compatible .fmd format `Bash`
+	* _find-unused-kconfig-symbols.sh_ - Points out Kconfig
+variables that may be unused. There are some false positives, but it
+serves as a starting point `Shell`
+	* _gerrit-rebase_ - Applies all commits that from-branch has
+over to-branch, based on a common ancestor and gerrit meta-data `Bash`
+	* _get_maintainer.pl_ - Print selected MAINTAINERS information
+for the files modified in a patch or for a file `Perl`
+	* _maintainers.go_ - Build subsystem Maintainers `Go`
+	* _no-fsf-addresses.sh_ - Removes various FSF addresses from
+license headers `Shell`
+	* _parse-maintainers.pl_ - Script to alphabetize MAINTAINERS
+file `Perl`
+	* _ucode_h_to_bin.sh_ - Microcode conversion tool `Bash`
+	* _update_submodules_ - Check all submodules for updates `Bash`
+* __showdevicetree__ - Compile and dump the device tree `C`
+* __spkmodem_recv__ - Decode spkmodem signals `C`
+* __superiotool__ - A user-space utility to detect Super I/O of a
+mainboard and provide detailed information about the register contents
+of the Super I/O. `C`
+* __testing__ - coreboot test targets `Make`
+* __uio_usbdebug__ - Debug coreboot's usbdebug driver inside a running
+operating system (only Linux at this time). `C`
+* __util_readme__ - Creates README.md of description files in `./util`
+subdirectories `Bash`
+* __vgabios__ - emulated vga driver for qemu `C`
+* __viatool__ - Extract certain configuration bits on VIA chipsets and
+CPUs. `C`
+* __x86__ - Generates 32-bit PAE page tables based on a CSV input file.
+`Go`
+* __xcompile__ - Cross compile setup `Bash`
diff --git a/MAINTAINERS b/MAINTAINERS
@@ -414,7 +414,6 @@ F:	util/me_cleaner/
 IFDTOOL
 M:	Stefan Reinauer <stefan.reinauer@coreboot.org>
 F:	util/ifdtool/
-F:	util/ifdfake/
 
 BUILD SYSTEM
 M:	Patrick Georgi <patrick@georgi-clan.de>

diff --git a/Makefile b/Makefile
@@ -174,6 +174,7 @@ real-all: real-target
 
 # must come rather early
 .SECONDEXPANSION:
+.DELETE_ON_ERROR:
 
 $(KCONFIG_AUTOHEADER): $(KCONFIG_CONFIG)
 	+$(MAKE) oldconfig

diff --git a/Makefile.inc b/Makefile.inc
@@ -385,11 +385,13 @@ CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time
 CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
 CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie
 ifeq ($(CONFIG_COMPILER_GCC),y)
-CFLAGS_common += -Wno-packed-not-aligned
 CFLAGS_common += -fno-delete-null-pointer-checks
 # Don't add these GCC specific flags when running scan-build
 ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
+CFLAGS_common += -Wno-packed-not-aligned
 CFLAGS_common += -fconserve-stack
+# cf. commit f69a99db (coreboot: x86: enable gc-sections)
+CFLAGS_common += -Wno-unused-but-set-variable
 endif
 endif
 
@@ -439,11 +441,6 @@ ADAFLAGS_common += -gnatyN
 
 LDFLAGS_common := --gc-sections -nostdlib -nostartfiles -static --emit-relocs
 
-ifeq ($(CONFIG_COMPILER_GCC),y)
-# cf. commit f69a99db (coreboot: x86: enable gc-sections)
-CFLAGS_common += -Wno-unused-but-set-variable
-endif
-
 ifeq ($(CONFIG_WARNINGS_ARE_ERRORS),y)
 CFLAGS_common += -Werror
 endif
@@ -460,18 +457,31 @@ ADAFLAGS_common += -gnata
 endif
 
 additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/ifdtool \
-		   $(objutil)/ifdfake $(objutil)/options $(objutil)/amdfwtool \
+		   $(objutil)/options $(objutil)/amdfwtool \
 		   $(objutil)/cbootimage $(objutil)/bimgtool
 
 export $(COREBOOT_EXPORTS)
 
 #######################################################################
 # generate build support files
-$(obj)/build.h: .xcompile
+
+build_h := $(obj)/build.h
+
+# We have to manually export variables that `genbuild_h.sh` uses
+# when we call it through the `$(shell)` function. This is fragile
+# but as variables newly added to `genbuild_h.sh` would just not
+# work, we'd notice that instantly at least.
+build_h_exports := BUILD_TIMELESS KERNELVERSION COREBOOT_EXTRA_VERSION
+
+# Report new `build.ht` as dependency if `build.h` differs.
+build_h_check := \
+	export $(foreach exp,$(build_h_exports),$(exp)="$($(exp))"); \
+	util/genbuild_h/genbuild_h.sh >$(build_h)t 2>/dev/null; \
+	cmp -s $(build_h)t $(build_h) >/dev/null 2>&1 || echo $(build_h)t
+
+$(build_h): $$(shell $$(build_h_check))
 	@printf "    GEN        build.h\n"
-	rm -f $(obj)/build.h
-	util/genbuild_h/genbuild_h.sh > $(obj)/build.ht
-	mv $(obj)/build.ht $(obj)/build.h
+	mv $< $@
 
 build-dirs:
 	mkdir -p $(objcbfs) $(objgenerated)
@@ -522,11 +532,6 @@ $(IFDTOOL):
 	+$(MAKE) -C $(top)/util/ifdtool
 	cp -a $(top)/util/ifdtool/ifdtool $@
 
-IFDFAKE:=$(objutil)/ifdfake/ifdfake
-$(IFDFAKE): $(top)/util/ifdfake/ifdfake.c
-	@printf "    HOSTCC     $(subst $(obj)/,,$(@))\n"
-	$(HOSTCC) $(HOSTCFLAGS) -o $@ $<
-
 AMDFWTOOL:=$(objutil)/amdfwtool/amdfwtool
 $(AMDFWTOOL): $(top)/util/amdfwtool/amdfwtool.c
 	@printf "    HOSTCC     $(subst $(obj)/,,$(@))\n"
@@ -600,10 +605,13 @@ update:
 gitconfig:
 	util/gitconfig/gitconfig.sh "$(MAKE)"
 
+install-git-commit-clangfmt:
+	cp util/scripts/prepare-commit-msg.clang-format .git/hooks/prepare-commit-msg
+
 include util/crossgcc/Makefile.inc
 
 .PHONY: tools
-tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(IFDFAKE) $(CBOOTIMAGE) $(AMDFWTOOL) $(FUTILITY) $(BINCFG)
+tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(FUTILITY) $(BINCFG)
 
 ###########################################################################
 # Common recipes for all stages
@@ -1023,6 +1031,10 @@ ifneq ($(CONFIG_UPDATE_IMAGE),y)
 endif
 endif
 endif
+ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y)
+	@printf "    SeaBIOS    Add sercon-port file\n"
+	$(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port
+endif
 ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
 ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
 	@printf "    UPDATE-FIT\n"

diff --git a/configs/config.cavium_cn8100_sff_evb_bdk_verbose_fit_payload_support b/configs/config.cavium_cn8100_sff_evb_bdk_verbose_fit_payload_support
@@ -0,0 +1,9 @@
+CONFIG_VENDOR_CAVIUM=y
+CONFIG_CAVIUM_BDK_VERBOSE_INIT=y
+CONFIG_CAVIUM_BDK_VERBOSE_DRAM=y
+CONFIG_CAVIUM_BDK_VERBOSE_DRAM_TEST=y
+CONFIG_CAVIUM_BDK_VERBOSE_QLM=y
+CONFIG_CAVIUM_BDK_VERBOSE_PCIE_CONFIG=y
+CONFIG_CAVIUM_BDK_VERBOSE_PCIE=y
+CONFIG_CAVIUM_BDK_VERBOSE_PHY=y
+CONFIG_PAYLOAD_FIT_SUPPORT=y
diff --git a/configs/config.lenovo_t400_all_debug_and_option_table b/configs/config.lenovo_t400_all_debug_and_option_table
@@ -0,0 +1,14 @@
+CONFIG_USE_OPTION_TABLE=y
+CONFIG_VENDOR_LENOVO=y
+CONFIG_BOARD_LENOVO_T400=y
+CONFIG_NO_POST=y
+CONFIG_FATAL_ASSERTS=y
+CONFIG_DEBUG_CBFS=y
+CONFIG_DEBUG_RAM_SETUP=y
+CONFIG_DEBUG_SMBUS=y
+CONFIG_DEBUG_SMI=y
+CONFIG_DEBUG_SMM_RELOCATION=y
+CONFIG_DEBUG_MALLOC=y
+CONFIG_DEBUG_ACPI=y
+CONFIG_DEBUG_BOOT_STATE=y
+CONFIG_DEBUG_ADA_CODE=y
diff --git a/configs/config.lenovo_t420_static_option_table_no_mem_fuses b/configs/config.lenovo_t420_static_option_table_no_mem_fuses
@@ -0,0 +1,7 @@
+CONFIG_USE_OPTION_TABLE=y
+CONFIG_STATIC_OPTION_TABLE=y
+CONFIG_VENDOR_LENOVO=y
+CONFIG_BOARD_LENOVO_T420=y
+CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES=y
+CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS=y
+# CONFIG_INTEL_CHIPSET_LOCKDOWN is not set
diff --git a/configs/config.lenovo_thinkpad_t430_all_debug_and_option_table b/configs/config.lenovo_thinkpad_t430_all_debug_and_option_table
@@ -0,0 +1,15 @@
+CONFIG_USE_OPTION_TABLE=y
+CONFIG_VENDOR_LENOVO=y
+# CONFIG_POST_IO is not set
+# CONFIG_POST_DEVICE is not set
+CONFIG_BOARD_LENOVO_THINKPAD_T430=y
+CONFIG_BOOTBLOCK_NORMAL=y
+CONFIG_MAINBOARD_USE_LIBGFXINIT=y
+CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
+CONFIG_DEBUG_RAM_SETUP=y
+CONFIG_DEBUG_SMBUS=y
+CONFIG_DEBUG_SMI=y
+CONFIG_DEBUG_SMM_RELOCATION=y
+CONFIG_DEBUG_SPI_FLASH=y
+CONFIG_DEBUG_BOOT_STATE=y
+CONFIG_DEBUG_ADA_CODE=y
diff --git a/configs/config.lenovo_x201_all_debug_option_table_bt_on_wifi b/configs/config.lenovo_x201_all_debug_option_table_bt_on_wifi
@@ -0,0 +1,14 @@
+CONFIG_USE_OPTION_TABLE=y
+CONFIG_VENDOR_LENOVO=y
+CONFIG_BOARD_LENOVO_X201=y
+CONFIG_H8_SUPPORT_BT_ON_WIFI=y
+CONFIG_FATAL_ASSERTS=y
+CONFIG_DEBUG_CBFS=y
+CONFIG_DEBUG_SMBUS=y
+CONFIG_DEBUG_SMI=y
+CONFIG_DEBUG_SMM_RELOCATION=y
+CONFIG_DEBUG_MALLOC=y
+CONFIG_DEBUG_ACPI=y
+CONFIG_DEBUG_SPI_FLASH=y
+CONFIG_DEBUG_BOOT_STATE=y
+CONFIG_DEBUG_ADA_CODE=y
diff --git a/configs/config.lenovo_x220_option_table_debug_tpm_extended_cbfs b/configs/config.lenovo_x220_option_table_debug_tpm_extended_cbfs
@@ -0,0 +1,5 @@
+CONFIG_USE_OPTION_TABLE=y
+CONFIG_VENDOR_LENOVO=y
+CONFIG_CBFS_SIZE=0x200000
+CONFIG_BOARD_LENOVO_X220=y
+CONFIG_DEBUG_TPM=y
diff --git a/configs/config.pcengines_apu2 b/configs/config.pcengines_apu2
@@ -1,20 +1,20 @@
+CONFIG_LOCALVERSION="v4.8.0.4"
 CONFIG_VENDOR_PCENGINES=y
+CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU2=y
-CONFIG_APU2_PINMUX_UART_C=y
-CONFIG_APU2_PINMUX_UART_D=y
+CONFIG_CPU_MICROCODE_CBFS_NONE=y
 CONFIG_NO_GFX_INIT=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
+CONFIG_SEABIOS_REVISION=y
+CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.5"
+CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
+CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
+CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
+CONFIG_IPXE_MASTER=y
 CONFIG_PXE_ROM_ID="8086,157b"
 # CONFIG_PXE_SERIAL_CONSOLE is not set
-CONFIG_CPU_MICROCODE_CBFS_NONE=y
 CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
-CONFIG_MEMTEST_MASTER=y
 CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
-CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
-CONFIG_SEABIOS_DEBUG_LEVEL=0
-CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
-CONFIG_SEABIOS_REVISION=y
-CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.5"
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
-CONFIG_LOCALVERSION="v4.8.0.3"
+CONFIG_MEMTEST_MASTER=y
diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu3
@@ -1,18 +1,20 @@
+CONFIG_LOCALVERSION="v4.8.0.4"
 CONFIG_VENDOR_PCENGINES=y
+CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU3=y
+CONFIG_CPU_MICROCODE_CBFS_NONE=y
 CONFIG_NO_GFX_INIT=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
+CONFIG_SEABIOS_REVISION=y
+CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.5"
+CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
+CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
+CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
+CONFIG_IPXE_MASTER=y
 CONFIG_PXE_ROM_ID="8086,1539"
 # CONFIG_PXE_SERIAL_CONSOLE is not set
-CONFIG_CPU_MICROCODE_CBFS_NONE=y
 CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
-CONFIG_MEMTEST_MASTER=y
 CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
-CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
-CONFIG_SEABIOS_DEBUG_LEVEL=0
-CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
-CONFIG_SEABIOS_REVISION=y
-CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.5"
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
-CONFIG_LOCALVERSION="v4.8.0.3"
+CONFIG_MEMTEST_MASTER=y
diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_apu4
@@ -1,18 +1,20 @@
+CONFIG_LOCALVERSION="v4.8.0.4"
 CONFIG_VENDOR_PCENGINES=y
+CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU4=y
+CONFIG_CPU_MICROCODE_CBFS_NONE=y
 CONFIG_NO_GFX_INIT=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
+CONFIG_SEABIOS_REVISION=y
+CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.5"
+CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
+CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
+CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
+CONFIG_IPXE_MASTER=y
 CONFIG_PXE_ROM_ID="8086,1539"
 # CONFIG_PXE_SERIAL_CONSOLE is not set
-CONFIG_CPU_MICROCODE_CBFS_NONE=y
 CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
-CONFIG_MEMTEST_MASTER=y
 CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
-CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
-CONFIG_SEABIOS_DEBUG_LEVEL=0
-CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
-CONFIG_SEABIOS_REVISION=y
-CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.5"
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
-CONFIG_LOCALVERSION="v4.8.0.3"
+CONFIG_MEMTEST_MASTER=y
diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu5
@@ -1,18 +1,20 @@
+CONFIG_LOCALVERSION="v4.8.0.4"
 CONFIG_VENDOR_PCENGINES=y
+CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU5=y
+CONFIG_CPU_MICROCODE_CBFS_NONE=y
 CONFIG_NO_GFX_INIT=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
+CONFIG_SEABIOS_REVISION=y
+CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.5"
+CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
+CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y
+CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
+CONFIG_IPXE_MASTER=y
 CONFIG_PXE_ROM_ID="8086,1539"
 # CONFIG_PXE_SERIAL_CONSOLE is not set
-CONFIG_CPU_MICROCODE_CBFS_NONE=y
 CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
-CONFIG_MEMTEST_MASTER=y
 CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
-CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
-CONFIG_SEABIOS_DEBUG_LEVEL=0
-CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
-CONFIG_SEABIOS_REVISION=y
-CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.5"
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
-CONFIG_LOCALVERSION="v4.8.0.3"
+CONFIG_MEMTEST_MASTER=y
diff --git a/payloads/Kconfig b/payloads/Kconfig
@@ -129,27 +129,6 @@ config MEMTEST_SECONDARY_PAYLOAD
 	  Memtest86+ can be loaded as a secondary payload under SeaBIOS, GRUB,
 	  or any other payload that can load additional payloads.
 
-choice
-	prompt "Memtest86+ version"
-	default MEMTEST_STABLE
-	depends on MEMTEST_SECONDARY_PAYLOAD
-
-config MEMTEST_STABLE
-	bool "Stable"
-	help
-	  Stable Memtest86+ version.
-
-	  For reproducible builds, this option must be selected.
-config MEMTEST_MASTER
-	bool "Master"
-	help
-	  Newest Memtest86+ version.
-
-	  This option will fetch the newest version of the Memtest86+ code,
-	  updating as new changes are committed.  This makes the build
-	  non-reproducible, as it can fetch different code each time.
-endchoice
-
 config NVRAMCUI_SECONDARY_PAYLOAD
 	bool "Load nvramcui as a secondary payload"
 	default n
@@ -166,6 +145,7 @@ config TINT_SECONDARY_PAYLOAD
 	  tint can be loaded as a secondary payload under SeaBIOS, GRUB,
 	  or any other payload that can load additional payloads.
 
+
 config SORTBOOTORDER_SECONDARY_PAYLOAD
 	bool "Load sortbootorder as a secondary payload"
 	default n
@@ -174,5 +154,7 @@ config SORTBOOTORDER_SECONDARY_PAYLOAD
 	  sortbootorder can be loaded as a secondary payload under SeaBIOS
 	  or any other payload that can load additional payloads.
 
+source "payloads/external/*/Kconfig.secondary"
+
 endmenu # "Secondary Payloads"
 endmenu
diff --git a/payloads/external/LinuxBoot/Kconfig b/payloads/external/LinuxBoot/Kconfig
@@ -53,10 +53,17 @@ config LINUXBOOT_KERNEL_STABLE
 	bool "4.15.3"
 	help
 	  Stable kernel version
+
+config LINUXBOOT_KERNEL_LATEST
+	bool "4.17.11"
+	help
+	  Latest kernel version
+
 endchoice
 
 config LINUXBOOT_KERNEL_VERSION
 	string
+	default "4.17.11" if LINUXBOOT_KERNEL_LATEST
 	default "4.15.3" if LINUXBOOT_KERNEL_STABLE
 
 config LINUXBOOT_KERNEL_CONFIGFILE
@@ -111,8 +118,8 @@ config LINUXBOOT_UROOT_COMMANDS
 	string "Select u-root commands"
 	default ""
 	help
-	  Comma separated list of additional modules to include. Otherwise all modules
-	  of u-root are included.
+	  List of additional modules to include, separated by space. Otherwise
+	  all modules of u-root are included.
 
 config LINUXBOOT_UROOT_FILES
 	string "Add files to u-root base"

diff --git a/payloads/external/LinuxBoot/Makefile b/payloads/external/LinuxBoot/Makefile
@@ -21,23 +21,23 @@ unexport MAKEFLAGS
 
 XGCCPATH?=$(PWD)/util/crossgcc/xgcc/bin
 ifeq ($(CONFIG_LINUXBOOT_ARCH),386)
-CROSS_COMPILE?=$(XGCCPATH)/i386-linux-
+LINUXBOOT_COMPILE?=$(XGCCPATH)/i386-linux-
 ARCH?=x86
 else ifeq ($(CONFIG_LINUXBOOT_ARCH),amd64)
-CROSS_COMPILE?=$(XGCCPATH)/x86_64-linux-
+LINUXBOOT_COMPILE?=$(XGCCPATH)/x86_64-linux-
 ARCH?=x86_64
 else ifeq ($(CONFIG_LINUXBOOT_ARCH),arm64)
-CROSS_COMPILE?=$(XGCCPATH)/aarch64-linux-
+LINUXBOOT_COMPILE?=$(XGCCPATH)/aarch64-linux-
 ARCH?=arm64
 endif
 
-OBJCOPY:=$(CROSS_COMPILE)objcopy
+OBJCOPY:=$(LINUXBOOT_COMPILE)objcopy
 
 all: payload
 
 toolchain:
-	if [[ ! -x "$(CROSS_COMPILE)gcc" ]]; then \
-	echo "Toolchain '$(CROSS_COMPILE)*' is missing."; \
+	if [[ ! -x "$(LINUXBOOT_COMPILE)gcc" ]]; then \
+	echo "Toolchain '$(LINUXBOOT_COMPILE)*' is missing."; \
 	exit 1; \
 	fi
 
@@ -67,8 +67,8 @@ else ifeq ($(CONFIG_LINUXBOOT_ARCH),arm64)
 $(kernel_dir)/vmlinux: config toolchain
 endif
 	echo "    MAKE       Kernel $(CONFIG_LINUXBOOT_KERNEL_VERSION)"
-	$(MAKE) -C $(kernel_dir) olddefconfig CROSS_COMPILE=$(CROSS_COMPILE) ARCH=$(ARCH)
-	$(MAKE) -C $(kernel_dir) -j $(CPUS) CROSS_COMPILE=$(CROSS_COMPILE) ARCH=$(ARCH)
+	$(MAKE) -C $(kernel_dir) olddefconfig CROSS_COMPILE=$(LINUXBOOT_COMPILE) ARCH=$(ARCH)
+	$(MAKE) -C $(kernel_dir) -j $(CPUS) CROSS_COMPILE=$(LINUXBOOT_COMPILE) ARCH=$(ARCH)
 
 ifneq (,$(filter $(CONFIG_LINUXBOOT_ARCH),386 amd64))
 $(project_dir)/kernel-image: $(kernel_dir)/arch/x86/boot/bzImage
@@ -99,7 +99,7 @@ endif
 payload: $(project_dir)/kernel-image $(project_dir)/initramfs.cpio.xz
 
 clean:
-	if [ -d "$(kernel_dir)" ]; then make -C $(kernel_dir) clean; fi
+	if [ -d "$(kernel_dir)" ]; then rm -rf $(kernel_dir); fi
 	rm -f $(project_dir)/initramfs.cpio.xz
 
 distclean:

diff --git a/payloads/external/LinuxBoot/targets/u-root.mk b/payloads/external/LinuxBoot/targets/u-root.mk
@@ -62,10 +62,11 @@ ifneq ($(CONFIG_LINUXBOOT_UROOT_COMMANDS),)
 ifneq ($(CONFIG_LINUXBOOT_UROOT_FILES),)
 	cd $(uroot_dir); GOARCH=$(CONFIG_LINUXBOOT_ARCH) GOPATH=$(go_path_dir) ./u-root \
 	-build=bb -files $(CONFIG_LINUXBOOT_UROOT_FILES) -o $(project_dir)/initramfs.cpio \
-	./cmds/{$(CONFIG_LINUXBOOT_UROOT_COMMANDS)}
+	$(patsubst %,cmds/%,$(CONFIG_LINUXBOOT_UROOT_COMMANDS))
 else
 	cd $(uroot_dir); GOARCH=$(CONFIG_LINUXBOOT_ARCH) GOPATH=$(go_path_dir) ./u-root \
-	-build=bb -o $(project_dir)/initramfs.cpio ./cmds/{$(CONFIG_LINUXBOOT_UROOT_COMMANDS)}
+	-build=bb -o $(project_dir)/initramfs.cpio \
+	$(patsubst %,cmds/%,$(CONFIG_LINUXBOOT_UROOT_COMMANDS))
 endif
 else
 ifneq ($(CONFIG_LINUXBOOT_UROOT_FILES),)

diff --git a/payloads/external/LinuxBoot/x86/defconfig b/payloads/external/LinuxBoot/x86/defconfig
@@ -0,0 +1,147 @@
+# CONFIG_64BIT is not set
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_KERNEL_XZ=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+# CONFIG_USELIB is not set
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+# CONFIG_MULTIUSER is not set
+# CONFIG_SYSFS_SYSCALL is not set
+# CONFIG_BUG is not set
+# CONFIG_PCSPKR_PLATFORM is not set
+# CONFIG_BASE_FULL is not set
+# CONFIG_AIO is not set
+# CONFIG_KALLSYMS is not set
+CONFIG_BPF_SYSCALL=y
+CONFIG_USERFAULTFD=y
+CONFIG_EMBEDDED=y
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLOB=y
+# CONFIG_SLAB_MERGE_DEFAULT is not set
+CONFIG_GCC_PLUGINS=y
+CONFIG_GCC_PLUGIN_LATENT_ENTROPY=y
+CONFIG_GCC_PLUGIN_STRUCTLEAK=y
+CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL=y
+CONFIG_GCC_PLUGIN_RANDSTRUCT=y
+CONFIG_CC_STACKPROTECTOR_STRONG=y
+CONFIG_ARCH_MMAP_RND_BITS=16
+CONFIG_REFCOUNT_FULL=y
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_MQ_IOSCHED_DEADLINE is not set
+# CONFIG_MQ_IOSCHED_KYBER is not set
+# CONFIG_ZONE_DMA is not set
+# CONFIG_X86_FAST_FEATURE_TESTS is not set
+# CONFIG_X86_MPPARSE is not set
+# CONFIG_X86_EXTENDED_PLATFORM is not set
+# CONFIG_SCHED_OMIT_FRAME_POINTER is not set
+# CONFIG_DMI is not set
+CONFIG_PREEMPT=y
+# CONFIG_X86_MCE is not set
+# CONFIG_MICROCODE is not set
+CONFIG_SPARSEMEM_MANUAL=y
+# CONFIG_COMPACTION is not set
+# CONFIG_MTRR is not set
+# CONFIG_X86_INTEL_UMIP is not set
+CONFIG_KEXEC=y
+# CONFIG_RELOCATABLE is not set
+# CONFIG_MODIFY_LDT_SYSCALL is not set
+# CONFIG_SUSPEND is not set
+CONFIG_PM=y
+CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
+# CONFIG_ACPI_REV_OVERRIDE_POSSIBLE is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_BATTERY is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_FAN is not set
+# CONFIG_ACPI_PROCESSOR is not set
+# CONFIG_ACPI_TABLE_UPGRADE is not set
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y
+# CONFIG_CPU_IDLE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIEASPM_POWER_SUPERSAVE=y
+CONFIG_PCI_MSI=y
+# CONFIG_BINFMT_SCRIPT is not set
+# CONFIG_COREDUMP is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_UEVENT_HELPER is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+# CONFIG_FW_LOADER is not set
+# CONFIG_ALLOW_DEV_COREDUMP is not set
+# CONFIG_PNP_DEBUG_MESSAGES is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_SD=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_CRYPT=y
+CONFIG_HW_RANDOM_TIMERIOMEM=y
+# CONFIG_HW_RANDOM_AMD is not set
+# CONFIG_HW_RANDOM_VIA is not set
+# CONFIG_DEVPORT is not set
+CONFIG_I2C=y
+CONFIG_POWER_SUPPLY=y
+# CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_X86_PLATFORM_DEVICES is not set
+# CONFIG_FIRMWARE_MEMMAP is not set
+CONFIG_GOOGLE_FIRMWARE=y
+CONFIG_GOOGLE_COREBOOT_TABLE_ACPI=y
+CONFIG_GOOGLE_MEMCONSOLE_COREBOOT=y
+CONFIG_GOOGLE_VPD=y
+CONFIG_EXT4_FS=y
+# CONFIG_FILE_LOCKING is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+CONFIG_TMPFS=y
+CONFIG_SQUASHFS=y
+# CONFIG_SQUASHFS_ZLIB is not set
+CONFIG_SQUASHFS_XZ=y
+# CONFIG_NETWORK_FILESYSTEMS is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_FTRACE is not set
+CONFIG_STRICT_DEVMEM=y
+CONFIG_IO_STRICT_DEVMEM=y
+# CONFIG_X86_VERBOSE_BOOTUP is not set
+# CONFIG_EARLY_PRINTK is not set
+# CONFIG_DOUBLEFAULT is not set
+CONFIG_OPTIMIZE_INLINING=y
+# CONFIG_X86_DEBUG_FPU is not set
+CONFIG_UNWINDER_GUESS=y
+CONFIG_SECURITY_DMESG_RESTRICT=y
+CONFIG_FORTIFY_SOURCE=y
+# CONFIG_CRYPTO_ECHAINIV is not set
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_VIRTUALIZATION is not set
diff --git a/payloads/external/LinuxBoot/x86_64/defconfig b/payloads/external/LinuxBoot/x86_64/defconfig
@@ -0,0 +1,166 @@
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_KERNEL_XZ=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_CGROUPS=y
+CONFIG_MEMCG=y
+CONFIG_BLK_CGROUP=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_RDMA=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_PERF=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_RD_LZ4 is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+# CONFIG_MULTIUSER is not set
+# CONFIG_SYSFS_SYSCALL is not set
+# CONFIG_BUG is not set
+# CONFIG_PCSPKR_PLATFORM is not set
+# CONFIG_BASE_FULL is not set
+# CONFIG_AIO is not set
+# CONFIG_KALLSYMS is not set
+CONFIG_BPF_SYSCALL=y
+CONFIG_USERFAULTFD=y
+CONFIG_EMBEDDED=y
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLOB=y
+# CONFIG_SLAB_MERGE_DEFAULT is not set
+CONFIG_GCC_PLUGINS=y
+CONFIG_GCC_PLUGIN_LATENT_ENTROPY=y
+CONFIG_GCC_PLUGIN_STRUCTLEAK=y
+CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL=y
+CONFIG_GCC_PLUGIN_RANDSTRUCT=y
+# CONFIG_VMAP_STACK is not set
+CONFIG_REFCOUNT_FULL=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_MQ_IOSCHED_DEADLINE is not set
+# CONFIG_MQ_IOSCHED_KYBER is not set
+# CONFIG_ZONE_DMA is not set
+# CONFIG_X86_MPPARSE is not set
+# CONFIG_X86_EXTENDED_PLATFORM is not set
+CONFIG_IOSF_MBI=y
+# CONFIG_SCHED_OMIT_FRAME_POINTER is not set
+# CONFIG_DMI is not set
+CONFIG_PREEMPT=y
+# CONFIG_X86_MCE is not set
+# CONFIG_MICROCODE is not set
+CONFIG_X86_MSR=y
+CONFIG_X86_CPUID=y
+# CONFIG_SPARSEMEM_VMEMMAP is not set
+# CONFIG_COMPACTION is not set
+# CONFIG_MTRR is not set
+# CONFIG_X86_INTEL_UMIP is not set
+# CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS is not set
+CONFIG_KEXEC=y
+# CONFIG_RELOCATABLE is not set
+# CONFIG_MODIFY_LDT_SYSCALL is not set
+# CONFIG_SUSPEND is not set
+# CONFIG_ACPI_REV_OVERRIDE_POSSIBLE is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_BATTERY is not set
+CONFIG_ACPI_VIDEO=y
+# CONFIG_ACPI_FAN is not set
+# CONFIG_ACPI_PROCESSOR is not set
+# CONFIG_ACPI_TABLE_UPGRADE is not set
+# CONFIG_X86_PM_TIMER is not set
+# CONFIG_CPU_IDLE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIEASPM_POWER_SUPERSAVE=y
+CONFIG_PCI_MSI=y
+# CONFIG_ISA_DMA_API is not set
+# CONFIG_BINFMT_SCRIPT is not set
+# CONFIG_COREDUMP is not set
+# CONFIG_UEVENT_HELPER is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+# CONFIG_FW_LOADER is not set
+# CONFIG_ALLOW_DEV_COREDUMP is not set
+# CONFIG_PNP_DEBUG_MESSAGES is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_SD=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_CRYPT=y
+CONFIG_HW_RANDOM_TIMERIOMEM=y
+# CONFIG_HW_RANDOM_AMD is not set
+# CONFIG_HW_RANDOM_VIA is not set
+CONFIG_TCG_TPM=y
+CONFIG_TCG_TIS=y
+# CONFIG_DEVPORT is not set
+CONFIG_I2C=y
+CONFIG_POWER_SUPPLY=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_ARB is not set
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+CONFIG_FB_FOREIGN_ENDIAN=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_VGACON_SOFT_SCROLLBACK=y
+CONFIG_VGACON_SOFT_SCROLLBACK_PERSISTENT_ENABLE_BY_DEFAULT=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+# CONFIG_USB_SUPPORT is not set
+CONFIG_SYNC_FILE=y
+# CONFIG_VIRTIO_MENU is not set
+# CONFIG_X86_PLATFORM_DEVICES is not set
+# CONFIG_FIRMWARE_MEMMAP is not set
+CONFIG_GOOGLE_FIRMWARE=y
+CONFIG_GOOGLE_COREBOOT_TABLE_ACPI=y
+CONFIG_GOOGLE_MEMCONSOLE_COREBOOT=y
+CONFIG_GOOGLE_VPD=y
+CONFIG_EXT4_FS=y
+# CONFIG_FILE_LOCKING is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_UTF8=y
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_FTRACE is not set
+# CONFIG_X86_VERBOSE_BOOTUP is not set
+# CONFIG_EARLY_PRINTK is not set
+# CONFIG_DOUBLEFAULT is not set
+CONFIG_OPTIMIZE_INLINING=y
+# CONFIG_X86_DEBUG_FPU is not set
+CONFIG_UNWINDER_GUESS=y
+CONFIG_SECURITY_DMESG_RESTRICT=y
+CONFIG_FORTIFY_SOURCE=y
+# CONFIG_CRYPTO_ECHAINIV is not set
+CONFIG_CRYPTO_SHA256_SSSE3=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_VIRTUALIZATION is not set
diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc
@@ -262,6 +262,8 @@ payloads/external/Memtest86Plus/memtest86plus/memtest: $(DOTCONFIG)
 		LD="$(LD_x86_32)" \
 		OBJCOPY="$(OBJCOPY_x86_32)" \
 		AS="$(AS_x86_32)" \
+		CONFIG_MEMTEST_REVISION=$(CONFIG_MEMTEST_REVISION) \
+		CONFIG_MEMTEST_REVISION_ID=$(CONFIG_MEMTEST_REVISION_ID) \
 		CONFIG_MEMTEST_MASTER=$(CONFIG_MEMTEST_MASTER) \
 		CONFIG_MEMTEST_STABLE=$(CONFIG_MEMTEST_STABLE) \
 		$(MEMTEST_SERIAL_OPTIONS) \
@@ -329,7 +331,7 @@ linuxboot:
 		CONFIG_LINUXBOOT_KERNEL_CONFIGFILE=$(CONFIG_LINUXBOOT_KERNEL_CONFIGFILE) \
 		CONFIG_LINUXBOOT_KERNEL_COMMANDLINE=$(CONFIG_LINUXBOOT_KERNEL_COMMANDLINE) \
 		CONFIG_LINUXBOOT_UROOT_VERSION=$(CONFIG_LINUXBOOT_UROOT_VERSION) \
-		CONFIG_LINUXBOOT_UROOT_COMMANDS="$(CONFIG_LINUXBOOT_UROOT_COMMANDS)" \
+		CONFIG_LINUXBOOT_UROOT_COMMANDS=$(CONFIG_LINUXBOOT_UROOT_COMMANDS) \
 		CONFIG_LINUXBOOT_ARCH=$(CONFIG_LINUXBOOT_ARCH) \
 		CONFIG_LINUXBOOT_UROOT=$(CONFIG_LINUXBOOT_UROOT) \
 		CONFIG_LINUXBOOT_UROOT_FILES=$(CONFIG_LINUXBOOT_UROOT_FILES) \

diff --git a/payloads/external/Memtest86Plus/Kconfig.secondary b/payloads/external/Memtest86Plus/Kconfig.secondary
@@ -0,0 +1,42 @@
+if MEMTEST_SECONDARY_PAYLOAD
+
+choice
+	prompt "Memtest86+ version"
+	default MEMTEST_STABLE
+	depends on MEMTEST_SECONDARY_PAYLOAD
+
+config MEMTEST_STABLE
+	bool "Stable"
+	help
+	  Stable Memtest86+ version.
+
+	  For reproducible builds, this option must be selected.
+config MEMTEST_MASTER
+	bool "Master"
+	help
+	  Newest Memtest86+ version.
+
+	  This option will fetch the newest version of the Memtest86+ code,
+	  updating as new changes are committed.  This makes the build
+	  non-reproducible, as it can fetch different code each time.
+config MEMTEST_REVISION
+	bool "git revision"
+	help
+	  Select this option if you have a specific commit or branch
+	  that you want to use as the revision from which to
+	  build Memtest86+.  This makes the build
+	  non-reproducible, as it can fetch different code each time.
+
+	  You will be able to specify the name of a branch or a commit id
+	  later.
+
+endchoice
+
+config MEMTEST_REVISION_ID
+	string "Insert a commit's SHA-1 or a branch name"
+	depends on MEMTEST_REVISION
+	default "origin/master"
+	help
+	   The commit's SHA-1 or branch name of the revision to use.
+
+endif
diff --git a/payloads/external/Memtest86Plus/Makefile b/payloads/external/Memtest86Plus/Makefile
@@ -17,6 +17,7 @@ TAG-$(CONFIG_MEMTEST_MASTER)=origin/master
 NAME-$(CONFIG_MEMTEST_MASTER)=Master
 TAG-$(CONFIG_MEMTEST_STABLE)=3754fd440f4009b62244e0f95c56bbb12c2fffcb
 NAME-$(CONFIG_MEMTEST_STABLE)=Stable
+TAG-$(CONFIG_MEMTEST_REVISION)=$(CONFIG_MEMTEST_REVISION_ID)
 
 project_name=Memtest86+
 project_dir=$(CURDIR)/memtest86plus
@@ -29,6 +30,14 @@ $(project_dir):
 	git clone $(project_git_repo) $(project_dir)
 
 fetch: $(project_dir)
+ifeq ($(TAG-y),)
+	echo "Error: The specified tag is invalid"
+ifeq ($(CONFIG_MEMTEST_REVISION),y)
+	echo "Error: There is no revision specified for $(project_name)"
+	false
+endif
+	false
+endif
 	-cd $(project_dir); git show $(TAG-y) >/dev/null 2>&1 ; \
 		if [ $$? -ne 0 ] || [ "$(TAG-y)" = "origin/master" ]; then \
 		echo "    Fetching new commits from the $(project_name) git repo"; \

diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig
@@ -106,7 +106,7 @@ config SEABIOS_BOOTMENU_KEY_FILE
 	  Add SeaBIOS boot-menu-key file. From wiki:
 	  "Controls which key activates the boot menu. The value stored is the
 	  DOS scan code (eg, 0x86 for F12, 0x01 for Esc). If this field is set,
-	  be sure to also customize the boot-menu-message field above. 
+	  be sure to also customize the boot-menu-message field above.
 
 	  See: https://www.coreboot.org/SeaBIOS#Configuring_boot_order
 
@@ -133,15 +133,23 @@ config SEABIOS_BOOTMENU_MESSAGE_FILE
 
 	  See: https://www.seabios.org/Runtime_config#Other_Configuration_items
 
-config SEABIOS_SERCON_PORT_FILE
-	string "SeaBIOS sercon-port file"
-	default "$(top)/src/mainboard/$(MAINBOARDDIR)/sercon-port"
+config SEABIOS_ADD_SERCON_PORT_FILE
+	prompt "Add SeaBIOS sercon-port file to CBFS"
+	default n
+	bool
 	help
-	  Enable serial port in SeaBIOS. From wiki:
-	  "Set this to the IO address of a serial port to enable SeaBIOS' VGA
-	  adapter emulation on the given serial port.
+	  Select this option to enable SeaBIOS' VGA adapter emulation
+	  on serial port.
 
-	  See: https://www.coreboot.org/SeaBIOS#Configuring_boot_order
+config SEABIOS_SERCON_PORT_ADDR
+	hex "SeaBIOS sercon-port base address"
+	depends on SEABIOS_ADD_SERCON_PORT_FILE
+	default TTYS0_BASE
+	help
+	  Set this field to the IO address of a serial port for SeaBIOS' VGA
+	  adapter emulation.
+
+	  By default primary console UART defined by TTYS0_BASE is used.
 
 config PAYLOAD_FILE
 	default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf"

diff --git a/payloads/external/iPXE/menu.ipxe b/payloads/external/iPXE/menu.ipxe
@@ -5,13 +5,13 @@ item --gap -- ---------------- iPXE boot menu ----------------
 item shell          ipxe shell
 item boot           autoboot
 choose --default boot --timeout 3000 target && goto ${target}
- 
+
 :boot
-autoboot net0
+autoboot
 goto MENU
- 
+
 :shell
 shell ||
 goto MENU
- 
-autoboot net0
+
+autoboot
diff --git a/payloads/libpayload/arch/x86/exception.c b/payloads/libpayload/arch/x86/exception.c
@@ -32,6 +32,8 @@
 #include <libpayload.h>
 #include <stdint.h>
 
+#define IF_FLAG				(1 << 9)
+
 u32 exception_stack[0x400] __attribute__((aligned(8)));
 
 static exception_hook hook;
@@ -59,7 +61,7 @@ static const char *names[EXC_COUNT] = {
 
 static void print_segment_error_code(u32 code)
 {
-	printf("%#x - descriptor %#x in the ", code, (code >> 3) & 0x1f);
+	printf("%#x - descriptor %#x in the ", code, (code >> 3) & 0x1FFF);
 	if (code & (0x1 << 1)) {
 		printf("IDT");
 	} else {
@@ -182,3 +184,33 @@ void exception_install_hook(exception_hook h)
 	die_if(hook, "Implement support for a list of hooks if you need it.");
 	hook = h;
 }
+
+static uint32_t eflags(void)
+{
+	uint32_t eflags;
+	asm volatile(
+		"pushf\n\t"
+		"pop %0\n\t"
+	: "=rm" (eflags));
+	return eflags;
+}
+
+void enable_interrupts(void)
+{
+	asm volatile (
+		"sti\n"
+		: : : "cc"
+	);
+}
+void disable_interrupts(void)
+{
+	asm volatile (
+		"cli\n"
+		: : : "cc"
+	);
+}
+
+int interrupts_enabled(void)
+{
+	return !!(eflags() & IF_FLAG);
+}
diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c
@@ -304,10 +304,10 @@ xhci_pci_init (pcidev_t addr)
 	u32 reg_addr;
 	hci_t *controller;
 
-	reg_addr = pci_read_config32 (addr, 0x10) & ~0xf;
-	if (pci_read_config32 (addr, 0x14) > 0) {
+	reg_addr = pci_read_config32(addr, PCI_BASE_ADDRESS_0) &
+		   PCI_BASE_ADDRESS_MEM_MASK;
+	if (pci_read_config32(addr, PCI_BASE_ADDRESS_1) > 0)
 		fatal("We don't do 64bit addressing.\n");
-	}
 
 	controller = xhci_init((unsigned long)reg_addr);
 	if (controller) {

diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
@@ -200,7 +200,6 @@ struct cb_gpios {
 	struct cb_gpio gpios[0];
 };
 
-#define CB_TAG_VDAT		0x0015
 #define CB_TAG_VBNV		0x0019
 #define CB_TAG_VBOOT_HANDOFF	0x0020
 #define CB_TAG_DMA		0x0022

diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
@@ -97,8 +97,6 @@ struct sysinfo_t {
 
 	void	*vboot_handoff;
 	u32	vboot_handoff_size;
-	void	*vdat_addr;
-	u32	vdat_size;
 
 #if IS_ENABLED(CONFIG_LP_ARCH_X86)
 	int x86_rom_var_mtrr_index;

diff --git a/payloads/libpayload/include/x86/arch/cpuid.h b/payloads/libpayload/include/x86/arch/cpuid.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright 2018 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _ARCH_CPUID_H
+#define _ARCH_CPUID_H
+
+#define cpuid(fn, eax, ebx, ecx, edx) \
+	asm("cpuid" : "=a"(eax), "=b"(ebx), "=c"(ecx), "=d"(edx) : "0"(fn))
+
+#endif
diff --git a/payloads/libpayload/include/x86/arch/exception.h b/payloads/libpayload/include/x86/arch/exception.h
@@ -34,6 +34,10 @@
 
 void exception_init_asm(void);
 void exception_dispatch(void);
+void enable_interrupts(void);
+void disable_interrupts(void);
+/** Returns 1 if interrupts are enabled. */
+int interrupts_enabled(void);
 
 struct exception_state
 {

diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c
@@ -106,14 +106,6 @@ static void cb_parse_gpios(unsigned char *ptr, struct sysinfo_t *info)
 		info->gpios[i] = gpios->gpios[i];
 }
 
-static void cb_parse_vdat(unsigned char *ptr, struct sysinfo_t *info)
-{
-	struct lb_range *vdat = (struct lb_range *) ptr;
-
-	info->vdat_addr = phys_to_virt(vdat->range_start);
-	info->vdat_size = vdat->range_size;
-}
-
 static void cb_parse_mac_addresses(unsigned char *ptr,
 				   struct sysinfo_t *info)
 {
@@ -357,9 +349,6 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 		case CB_TAG_GPIO:
 			cb_parse_gpios(ptr, info);
 			break;
-		case CB_TAG_VDAT:
-			cb_parse_vdat(ptr, info);
-			break;
 		case CB_TAG_VBNV:
 			cb_parse_vbnv(ptr, info);
 			break;

diff --git a/src/arch/arm/armv7/thread.c b/src/arch/arm/armv7/thread.c
@@ -70,7 +70,7 @@ void arch_prepare_thread(struct thread *t,
 void __attribute__((naked))
 switch_to_thread(uintptr_t new_stack, uintptr_t *saved_stack)
 {
-	/* Defintions for those of us not totally familiar with ARM:
+	/* Definitions for those of us not totally familiar with ARM:
 	 * R15 -- PC, R14 -- LR, R13 -- SP
 	 * R0-R3 need not be saved, nor R12.
 	 * on entry, the only saved state is in LR -- the old PC.

diff --git a/src/arch/arm64/Kconfig b/src/arch/arm64/Kconfig
@@ -31,6 +31,14 @@ config ARM64_USE_ARM_TRUSTED_FIRMWARE
 	default n
 	depends on ARCH_RAMSTAGE_ARM64
 
+config ARM64_BL31_EXTERNAL_FILE
+	string "Path to external BL31.ELF (leave empty to build from source)"
+	depends on ARM64_USE_ARM_TRUSTED_FIRMWARE
+	help
+	  The blob to use instead of building the Arm Trusted Firmware
+	  from tree. It is discouraged as compatibility with out-of-tree
+	  blobs may break anytime.
+
 config ARM64_USE_SECURE_OS
 	bool
 	default n

diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc
@@ -107,6 +107,7 @@ romstage-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c
 romstage-y += memset.S
 romstage-y += memcpy.S
 romstage-y += memmove.S
+romstage-y += romstage.c
 romstage-y += transition.c transition_asm.S
 
 rmodules_arm64-y += memset.S
@@ -156,6 +157,8 @@ $(objcbfs)/ramstage.debug: $$(ramstage-objs)
 
 ifeq ($(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE),y)
 
+ifeq ($(CONFIG_ARM64_BL31_EXTERNAL_FILE),"")
+
 BL31_SOURCE := $(top)/3rdparty/arm-trusted-firmware
 BL31_BUILD := $(abspath $(obj)/3rdparty/arm-trusted-firmware)
 BL31_TARGET := $(BL31_BUILD)/bl31/bl31.elf
@@ -205,6 +208,13 @@ $(BL31): $(obj)/build.h
 
 .PHONY: $(BL31)
 
+else
+
+BL31 := $(call strip_quotes,$(CONFIG_ARM64_BL31_EXTERNAL_FILE))
+
+endif # CONFIG_ARM64_BUILD_ARM_TRUSTED_FIRMWARE
+
+
 BL31_CBFS := $(CONFIG_CBFS_PREFIX)/bl31
 $(BL31_CBFS)-file := $(BL31)
 $(BL31_CBFS)-type := payload

diff --git a/src/arch/arm64/armv8/Makefile.inc b/src/arch/arm64/armv8/Makefile.inc
@@ -15,8 +15,6 @@
 ##
 ################################################################################
 
-subdirs-y += lib/
-
 ifeq ($(CONFIG_ARCH_ARMV8_EXTENSION),0)
 march = armv8-a
 else

diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c
@@ -37,14 +37,6 @@
 #include <arch/lib_helpers.h>
 #include <program_loading.h>
 
-void tlb_invalidate_all(void)
-{
-	 /* TLBIALL includes dTLB and iTLB on systems that have them. */
-	tlbiall_current();
-	dsb();
-	isb();
-}
-
 unsigned int dcache_line_bytes(void)
 {
 	uint32_t ctr_el0;
@@ -118,23 +110,13 @@ void dcache_invalidate_by_mva(void const *addr, size_t len)
 	dcache_op_va(addr, len, OP_DCIVAC);
 }
 
-void cache_sync_instructions(void)
-{
-	uint32_t sctlr = raw_read_sctlr_current();
-	if (sctlr & SCTLR_C)
-		dcache_clean_all();	/* includes trailing DSB (assembly) */
-	else if (sctlr & SCTLR_I)
-		dcache_clean_invalidate_all();
-	icache_invalidate_all(); /* includdes leading DSB and trailing ISB. */
-}
-
 /*
  * For each segment of a program loaded this function is called
  * to invalidate caches for the addresses of the loaded segment
  */
 void arch_segment_loaded(uintptr_t start, size_t size, int flags)
 {
-	uint32_t sctlr = raw_read_sctlr_current();
+	uint32_t sctlr = raw_read_sctlr_el3();
 	if (sctlr & SCTLR_C)
 		dcache_clean_by_mva((void *)start, size);
 	else if (sctlr & SCTLR_I)

diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c
@@ -78,10 +78,10 @@ static void print_regs(struct exc_state *exc_state)
 	struct elx_state *elx = &exc_state->elx;
 	struct regs *regs = &exc_state->regs;
 
-	printk(BIOS_DEBUG, "ELR = 0x%016llx         ESR = 0x%08x\n",
-	       elx->elr, raw_read_esr_current());
-	printk(BIOS_DEBUG, "FAR = 0x%016llx        SPSR = 0x%08x\n",
-	       raw_read_far_current(), raw_read_spsr_current());
+	printk(BIOS_DEBUG, "ELR = 0x%016llx         ESR = 0x%08llx\n",
+	       elx->elr, raw_read_esr_el3());
+	printk(BIOS_DEBUG, "FAR = 0x%016llx        SPSR = 0x%08llx\n",
+	       raw_read_far_el3(), raw_read_spsr_el3());
 	for (i = 0; i < 30; i += 2) {
 		printk(BIOS_DEBUG,
 		       "X%02d = 0x%016llx         X%02d = 0x%016llx\n",
@@ -188,7 +188,7 @@ static int test_exception_handler(struct exc_state *state, uint64_t vector_id)
 {
 	/* Update instruction pointer to next instrution. */
 	state->elx.elr += sizeof(uint32_t);
-	raw_write_elr_current(state->elx.elr);
+	raw_write_elr_el3(state->elx.elr);
 	return EXC_RET_HANDLED;
 }
 

diff --git a/src/arch/arm64/armv8/lib/Makefile.inc b/src/arch/arm64/armv8/lib/Makefile.inc
diff --git a/src/arch/arm64/armv8/lib/cache.c b/src/arch/arm64/armv8/lib/cache.c
diff --git a/src/arch/arm64/armv8/lib/pstate.c b/src/arch/arm64/armv8/lib/pstate.c
diff --git a/src/arch/arm64/armv8/lib/sysctrl.c b/src/arch/arm64/armv8/lib/sysctrl.c
diff --git a/src/arch/arm64/armv8/lib/tlb.c b/src/arch/arm64/armv8/lib/tlb.c
diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c
@@ -219,6 +219,16 @@ static uint64_t get_pte(void *addr)
 	}
 }
 
+/* Func : assert_correct_ttb_mapping
+ * Desc : Asserts that mapping for addr matches the access type used by the
+ * page table walk (i.e. addr is correctly mapped to be part of the TTB). */
+static void assert_correct_ttb_mapping(void *addr)
+{
+	uint64_t pte = get_pte(addr);
+	assert(((pte >> BLOCK_INDEX_SHIFT) & BLOCK_INDEX_MASK)
+	       == BLOCK_INDEX_MEM_NORMAL && !(pte & BLOCK_NS));
+}
+
 /* Func : mmu_config_range
  * Desc : This function repeatedly calls init_xlat_table with the base
  * address. Based on size returned from init_xlat_table, base_addr is updated
@@ -242,7 +252,7 @@ void mmu_config_range(void *start, size_t size, uint64_t tag)
 
 	/* ARMv8 MMUs snoop L1 data cache, no need to flush it. */
 	dsb();
-	tlbiall_current();
+	tlbiall_el3();
 	dsb();
 	isb();
 }
@@ -310,11 +320,8 @@ void mmu_restore_context(const struct mmu_context *mmu_context)
 
 void mmu_enable(void)
 {
-	if (((get_pte(_ttb) >> BLOCK_INDEX_SHIFT) & BLOCK_INDEX_MASK)
-	    != BLOCK_INDEX_MEM_NORMAL ||
-	    ((get_pte(_ettb - 1) >> BLOCK_INDEX_SHIFT) & BLOCK_INDEX_MASK)
-	    != BLOCK_INDEX_MEM_NORMAL)
-		die("TTB memory type must match TCR (normal, cacheable)!");
+	assert_correct_ttb_mapping(_ttb);
+	assert_correct_ttb_mapping(_ettb - 1);
 
 	uint32_t sctlr = raw_read_sctlr_el3();
 	sctlr |= SCTLR_C | SCTLR_M | SCTLR_I;

diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c
@@ -36,25 +36,8 @@ static void run_payload(struct prog *prog)
 
 	if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE))
 		arm_tf_run_bl31((u64)doit, (u64)arg, payload_spsr);
-	else {
-		uint8_t current_el = get_current_el();
-
-		cache_sync_instructions();
-
-		printk(BIOS_SPEW, "entry    = %p\n", doit);
-
-		/* If current EL is not EL3, jump to payload at same EL. */
-		if (current_el != EL3)
-			doit(arg);
-		else {
-			/* If current EL is EL3, we transition to payload in EL2. */
-			struct exc_state exc_state;
-			memset(&exc_state, 0, sizeof(exc_state));
-			exc_state.elx.spsr = payload_spsr;
-
-			transition_with_entry(doit, arg, &exc_state);
-		}
-	}
+	else
+		transition_to_el2(doit, arg, payload_spsr);
 }
 
 void arch_prog_run(struct prog *prog)

diff --git a/src/arch/arm64/include/arch/stages.h b/src/arch/arm64/include/arch/stages.h
@@ -21,4 +21,11 @@
 
 void stage_entry(void);
 
+/* This function is the romstage platform entry point, and should contain all
+   chipset and mainboard setup until DRAM is initialized and accessible. */
+void platform_romstage_main(void);
+/* This is an optional hook to run further chipset or mainboard code after DRAM
+   and associated support frameworks (like CBMEM) have been initialized. */
+void platform_romstage_postram(void);
+
 #endif
diff --git a/src/arch/arm64/include/arch/transition.h b/src/arch/arm64/include/arch/transition.h
@@ -163,16 +163,10 @@ static inline uint8_t get_mode_from_spsr(uint64_t spsr)
  */
 
 /*
- * User of transition library can make a call to transition_with_entry and pass
- * the entry point and its argument which are put into elr and x0 by this
- * function. After that it makes a call to transition.
+ * Transitions to EL2 with given entry point and argument in X0. SPSR can be
+ * partially configured, but the exception level given must be EL2.
  */
-void transition_with_entry(void *entry, void *arg, struct exc_state *exc_state);
-/*
- * transition function sets up all the registers as per the struct elx_state
- * before jumping to trans_switch.
- */
-void transition(struct exc_state *exc_state);
+void transition_to_el2(void *entry, void *arg, uint64_t spsr);
 
 /*
  * exc_exit it called while returning from an exception. It expects pointer to

diff --git a/src/arch/arm64/include/armv8/arch/cache.h b/src/arch/arm64/include/armv8/arch/cache.h
@@ -58,6 +58,7 @@
 #include <stddef.h>
 #include <stdint.h>
 #include <arch/barrier.h>
+#include <arch/lib_helpers.h>
 
 /* dcache clean by virtual address to PoC */
 void dcache_clean_by_mva(void const *addr, size_t len);
@@ -76,21 +77,22 @@ void dcache_clean_invalidate_all(void);
 /* returns number of bytes per cache line */
 unsigned int dcache_line_bytes(void);
 
-/* perform all icache/dcache maintenance needed after loading new code */
-void cache_sync_instructions(void);
-
-/* tlb invalidate all */
-void tlb_invalidate_all(void);
+/* Invalidate all TLB entries. */
+static inline void tlb_invalidate_all(void)
+{
+	/* TLBIALL includes dTLB and iTLB on systems that have them. */
+	tlbiall_el3();
+	dsb();
+	isb();
+}
 
 /* Invalidate all of the instruction cache for PE to PoU. */
 static inline void icache_invalidate_all(void)
 {
-	__asm__ __volatile__(
-		"dsb	sy\n\t"
-		"ic	iallu\n\t"
-		"dsb	sy\n\t"
-		"isb\n\t"
-	: : : "memory");
+	dsb();
+	iciallu();
+	dsb();
+	isb();
 }
 
 #endif /* __ASSEMBLER__ */

diff --git a/src/arch/arm64/include/armv8/arch/exception.h b/src/arch/arm64/include/armv8/arch/exception.h
@@ -57,7 +57,7 @@ struct exception_handler {
 
 /*
  * Register a handler provided with the associated vector id. Returns 0 on
- * sucess, < 0 on error. Note that registration is not thread/interrupt safe.
+ * success, < 0 on error. Note that registration is not thread/interrupt safe.
  */
 int exception_handler_register(uint64_t vid, struct exception_handler *h);
 

diff --git a/src/arch/arm64/include/armv8/arch/lib_helpers.h b/src/arch/arm64/include/armv8/arch/lib_helpers.h
diff --git a/src/arch/arm64/romstage.c b/src/arch/arm64/romstage.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/exception.h>
+#include <arch/stages.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <program_loading.h>
+#include <timestamp.h>
+
+__weak void platform_romstage_main(void) { /* no-op, for bring-up */ }
+__weak void platform_romstage_postram(void) { /* no-op */ }
+
+void main(void)
+{
+	timestamp_add_now(TS_START_ROMSTAGE);
+
+	console_init();
+	exception_init();
+
+	platform_romstage_main();
+	cbmem_initialize_empty();
+	platform_romstage_postram();
+
+	run_ramstage();
+}
diff --git a/src/arch/arm64/transition.c b/src/arch/arm64/transition.c
@@ -15,6 +15,7 @@
 
 #include <arch/cache.h>
 #include <arch/lib_helpers.h>
+#include <arch/mmu.h>
 #include <arch/transition.h>
 #include <assert.h>
 #include <compiler.h>
@@ -37,62 +38,41 @@ void exc_entry(struct exc_state *exc_state, uint64_t id)
 {
 	struct elx_state *elx = &exc_state->elx;
 	struct regs *regs = &exc_state->regs;
-	uint8_t elx_mode, elx_el;
+	uint8_t elx_mode;
 
-	elx->spsr = raw_read_spsr_current();
+	elx->spsr = raw_read_spsr_el3();
 	elx_mode = get_mode_from_spsr(elx->spsr);
-	elx_el = get_el_from_spsr(elx->spsr);
-
-	if (elx_mode == SPSR_USE_H) {
-		if (elx_el == get_current_el())
-			regs->sp = (uint64_t)&exc_state[1];
-		else
-			regs->sp = raw_read_sp_elx(elx_el);
-	} else {
+
+	if (elx_mode == SPSR_USE_H)
+		regs->sp = (uint64_t)&exc_state[1];
+	else
 		regs->sp = raw_read_sp_el0();
-	}
 
-	elx->elr = raw_read_elr_current();
+	elx->elr = raw_read_elr_el3();
 
 	exc_dispatch(exc_state, id);
 }
 
-void transition_with_entry(void *entry, void *arg, struct exc_state *exc_state)
+void transition_to_el2(void *entry, void *arg, uint64_t spsr)
 {
-	/* Argument to entry point goes into X0 */
-	exc_state->regs.x[X0_INDEX] = (uint64_t)arg;
-	/* Entry point goes into ELR */
-	exc_state->elx.elr = (uint64_t)entry;
-
-	transition(exc_state);
-}
+	struct exc_state exc_state;
+	struct elx_state *elx = &exc_state.elx;
+	struct regs *regs = &exc_state.regs;
+	uint32_t sctlr;
 
-void transition(struct exc_state *exc_state)
-{
-	uint64_t sctlr;
-	uint32_t current_el = get_current_el();
-
-	struct elx_state *elx = &exc_state->elx;
-	struct regs *regs = &exc_state->regs;
-
-	uint8_t elx_el = get_el_from_spsr(elx->spsr);
+	regs->x[X0_INDEX] = (uint64_t)arg;
+	elx->elr = (uint64_t)entry;
+	elx->spsr = spsr;
 
 	/*
 	 * Policies enforced:
-	 * 1. We support only elx --> (elx - 1) transitions
+	 * 1. We support only transitions to EL2
 	 * 2. We support transitions to Aarch64 mode only
 	 *
 	 * If any of the above conditions holds false, then we need a proper way
 	 * to update SCR/HCR before removing the checks below
 	 */
-	if ((current_el - elx_el) != 1)
-		die("ARM64 Error: Do not support transition\n");
-
-	if (elx->spsr & SPSR_ERET_32)
-		die("ARM64 Error: Do not support eret to Aarch32\n");
-
-	/* Most parts of coreboot currently don't support EL2 anyway. */
-	assert(current_el == EL3);
+	assert(get_el_from_spsr(spsr) == EL2 && !(spsr & SPSR_ERET_32));
 
 	/* Initialize SCR with defaults for running without secure monitor. */
 	raw_write_scr_el3(SCR_TWE_DISABLE |	/* don't trap WFE */
@@ -113,17 +93,19 @@ void transition(struct exc_state *exc_state)
 			   CPTR_EL3_TFP_DISABLE);
 
 	/* ELR/SPSR: Write entry point and processor state of program */
-	raw_write_elr_current(elx->elr);
-	raw_write_spsr_current(elx->spsr);
+	raw_write_elr_el3(elx->elr);
+	raw_write_spsr_el3(elx->spsr);
 
 	/* SCTLR: Initialize EL with selected properties */
-	sctlr = raw_read_sctlr(elx_el);
+	sctlr = raw_read_sctlr_el2();
 	sctlr &= SCTLR_MASK;
-	raw_write_sctlr(sctlr, elx_el);
+	raw_write_sctlr_el2(sctlr);
 
 	/* SP_ELx: Initialize stack pointer */
-	raw_write_sp_elx(elx->sp_elx, elx_el);
-	isb();
+	raw_write_sp_el2(elx->sp_elx);
+
+	/* Payloads expect to be entered with MMU disabled. Includes an ISB. */
+	mmu_disable();
 
 	/* Eret to the entry point */
 	trans_switch(regs);

diff --git a/src/arch/arm64/transition_asm.S b/src/arch/arm64/transition_asm.S
@@ -164,7 +164,7 @@ ENTRY(exception_init_asm)
 	msr	SPSel, #SPSR_USE_L
 
 	adr	x0, exc_vectors
-	write_current vbar, x0, x1
+	msr	vbar_el3, x0
 	dsb	sy
 	isb
 	ret

diff --git a/src/arch/mips/include/arch/cache.h b/src/arch/mips/include/arch/cache.h
@@ -43,7 +43,6 @@ void cache_invalidate_all(uintptr_t start, size_t size);
 
 /* TODO: Global cache API. Implement properly once we finally have a MIPS board
    again where we can figure out what exactly these should be doing. */
-static inline void cache_sync_instructions(void) {}
 static inline void dcache_clean_all(void) {}
 static inline void dcache_invalidate_all(void) {}
 static inline void dcache_clean_invalidate_all(void) {}

diff --git a/src/arch/power8/include/arch/cache.h b/src/arch/power8/include/arch/cache.h
@@ -32,7 +32,6 @@
 #define ARCH_CACHE_H
 
 /* TODO: implement these API stubs once caching is available on Power 8 */
-static inline void cache_sync_instructions(void) {}
 static inline void dcache_clean_all(void) {}
 static inline void dcache_invalidate_all(void) {}
 static inline void dcache_clean_invalidate_all(void) {}

diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
@@ -3,6 +3,7 @@
 ## This file is part of the coreboot project.
 ##
 ## Copyright (C) 2014 The ChromiumOS Authors
+## Copyright (C) 2018 HardenedLinux
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -39,10 +40,7 @@ COMPILER_RT_ramstage  = $(shell  $(GCC_ramstage) $(riscv_flags) -print-libgcc-fi
 ################################################################################
 ifeq ($(CONFIG_ARCH_BOOTBLOCK_RISCV),y)
 
-bootblock-y += id.S
-$(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h
-
-bootblock-y = bootblock.S stages.c
+bootblock-y = bootblock.S
 bootblock-y += trap_util.S
 bootblock-y += trap_handler.c
 bootblock-y += mcall.c
@@ -82,8 +80,6 @@ romstage-y += \
 	$(top)/src/lib/memmove.c \
 	$(top)/src/lib/memset.c
 
-romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
-
 # Build the romstage
 
 $(objcbfs)/romstage.debug: $$(romstage-objs)
@@ -116,8 +112,6 @@ ramstage-y += \
 
 $(eval $(call create_class_compiler,rmodules,riscv))
 
-ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
-
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c
 
 # Build the ramstage

diff --git a/src/arch/riscv/id.S b/src/arch/riscv/id.S
diff --git a/src/arch/riscv/include/arch/cache.h b/src/arch/riscv/include/arch/cache.h
@@ -32,7 +32,6 @@
 #define ARCH_CACHE_H
 
 /* TODO: implement these API stubs once caching is available on RISC-V */
-static inline void cache_sync_instructions(void) {}
 static inline void dcache_clean_all(void) {}
 static inline void dcache_invalidate_all(void) {}
 static inline void dcache_clean_invalidate_all(void) {}

diff --git a/src/arch/riscv/include/stdint.h b/src/arch/riscv/include/stdint.h
@@ -70,7 +70,10 @@ typedef uint8_t bool;
 #define false	0
 
 /* Types for `void *' pointers.  */
-typedef s64             intptr_t;
-typedef u64		uintptr_t;
+typedef long intptr_t;
+typedef unsigned long uintptr_t;
+
+/* FIXME: This is used in some print code and may be removed in the future. */
+#define PRIu64  "llu"
 
 #endif /* RISCV_STDINT_H */
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
@@ -374,7 +374,7 @@ ramstage-libs ?=
 
 ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y)
 
-# The rmodule_link defintion creates an elf file with .rmod extension.
+# The rmodule_link definition creates an elf file with .rmod extension.
 $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 	cp $< $@
 

diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c
@@ -218,7 +218,7 @@ void acpi_create_madt(acpi_madt_t *madt)
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
 	header->length = sizeof(acpi_madt_t);
-	header->revision = 1; /* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
+	header->revision = get_acpi_table_revision(MADT);
 
 	madt->lapic_addr = LOCAL_APIC_ADDR;
 	madt->flags = 0x1; /* PCAT_COMPAT */
@@ -246,7 +246,7 @@ void acpi_create_mcfg(acpi_mcfg_t *mcfg)
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
 	header->length = sizeof(acpi_mcfg_t);
-	header->revision = 1;
+	header->revision = get_acpi_table_revision(MCFG);
 
 	current = acpi_fill_mcfg(current);
 
@@ -260,14 +260,14 @@ static void *get_tcpa_log(u32 *size)
 	const struct cbmem_entry *ce;
 	const u32 tcpa_default_log_len = 0x10000;
 	void *lasa;
-	ce = cbmem_entry_find(CBMEM_ID_TCPA_LOG);
+	ce = cbmem_entry_find(CBMEM_ID_TCPA_TCG_LOG);
 	if (ce) {
 		lasa = cbmem_entry_start(ce);
 		*size = cbmem_entry_size(ce);
 		printk(BIOS_DEBUG, "TCPA log found at %p\n", lasa);
 		return lasa;
 	}
-	lasa = cbmem_add(CBMEM_ID_TCPA_LOG, tcpa_default_log_len);
+	lasa = cbmem_add(CBMEM_ID_TCPA_TCG_LOG, tcpa_default_log_len);
 	if (!lasa) {
 		printk(BIOS_ERR, "TCPA log creation failed\n");
 		return NULL;
@@ -299,7 +299,7 @@ static void acpi_create_tcpa(acpi_tcpa_t *tcpa)
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
 	header->length = sizeof(acpi_tcpa_t);
-	header->revision = 2;
+	header->revision = get_acpi_table_revision(TCPA);
 
 	tcpa->platform_class = 0;
 	tcpa->laml = tcpa_log_len;
@@ -324,7 +324,7 @@ static void acpi_ssdt_write_cbtable(void)
 	acpigen_write_device("CTBL");
 	acpigen_write_coreboot_hid(COREBOOT_ACPI_ID_CBTABLE);
 	acpigen_write_name_integer("_UID", 0);
-	acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);
+	acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON);
 	acpigen_write_name("_CRS");
 	acpigen_write_resourcetemplate_header();
 	acpigen_write_mem32fixed(0, base, size);
@@ -339,7 +339,7 @@ void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id)
 	memset((void *)ssdt, 0, sizeof(acpi_header_t));
 
 	memcpy(&ssdt->signature, "SSDT", 4);
-	ssdt->revision = 2; /* ACPI 1.0/2.0: ?, ACPI 3.0/4.0: 2 */
+	ssdt->revision = get_acpi_table_revision(SSDT);
 	memcpy(&ssdt->oem_id, OEM_ID, 6);
 	memcpy(&ssdt->oem_table_id, oem_table_id, 8);
 	ssdt->oem_revision = 42;
@@ -410,7 +410,7 @@ void acpi_create_srat(acpi_srat_t *srat,
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
 	header->length = sizeof(acpi_srat_t);
-	header->revision = 1; /* ACPI 1.0: N/A, 2.0: 1, 3.0: 2, 4.0: 3 */
+	header->revision = get_acpi_table_revision(SRAT);
 
 	srat->resv = 1; /* Spec: Reserved to 1 for backwards compatibility. */
 
@@ -436,7 +436,7 @@ void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags,
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
 	header->length = sizeof(acpi_dmar_t);
-	header->revision = 1;
+	header->revision = get_acpi_table_revision(DMAR);
 
 	dmar->host_address_width = cpu_phys_address_size() - 1;
 	dmar->flags = flags;
@@ -569,7 +569,7 @@ void acpi_create_slit(acpi_slit_t *slit,
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
 	header->length = sizeof(acpi_slit_t);
-	header->revision = 1; /* ACPI 1.0: N/A, ACPI 2.0/3.0/4.0: 1 */
+	header->revision = get_acpi_table_revision(SLIT);
 
 	current = acpi_fill_slit(current);
 
@@ -593,7 +593,7 @@ void acpi_create_hpet(acpi_hpet_t *hpet)
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
 	header->length = sizeof(acpi_hpet_t);
-	header->revision = 1; /* Currently 1. Table added in ACPI 2.0. */
+	header->revision = get_acpi_table_revision(HPET);
 
 	/* Fill out HPET address. */
 	addr->space_id = 0; /* Memory */
@@ -626,7 +626,7 @@ void acpi_create_vfct(struct device *device,
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
 	header->length = sizeof(struct acpi_vfct);
-	header->revision = 1; /* ACPI 1.0: N/A, ACPI 2.0/3.0/4.0: 1 */
+	header->revision = get_acpi_table_revision(VFCT);
 
 	current = acpi_fill_vfct(device, vfct, current);
 
@@ -651,7 +651,7 @@ void acpi_create_ivrs(acpi_ivrs_t *ivrs,
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
 	header->length = sizeof(acpi_ivrs_t);
-	header->revision = IVRS_FORMAT_FIXED;
+	header->revision = get_acpi_table_revision(IVRS);
 
 	current = acpi_fill_ivrs(ivrs, current);
 
@@ -696,7 +696,7 @@ void acpi_create_dbg2(acpi_dbg2_header_t *dbg2,
 	current = (uintptr_t)dbg2;
 	memset(dbg2, 0, sizeof(acpi_dbg2_header_t));
 	header = &(dbg2->header);
-	header->revision = 0;
+	header->revision = get_acpi_table_revision(DBG2);
 	memcpy(header->signature, "DBG2", 4);
 	memcpy(header->oem_id, OEM_ID, 6);
 	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
@@ -807,7 +807,7 @@ void acpi_create_facs(acpi_facs_t *facs)
 	facs->flags = 0;
 	facs->x_firmware_waking_vector_l = 0;
 	facs->x_firmware_waking_vector_h = 0;
-	facs->version = 1; /* ACPI 1.0: 0, ACPI 2.0/3.0: 1, ACPI 4.0: 2 */
+	facs->version = get_acpi_table_revision(FACS);
 }
 
 static void acpi_write_rsdt(acpi_rsdt_t *rsdt, char *oem_id, char *oem_table_id)
@@ -821,7 +821,7 @@ static void acpi_write_rsdt(acpi_rsdt_t *rsdt, char *oem_id, char *oem_table_id)
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
 	header->length = sizeof(acpi_rsdt_t);
-	header->revision = 1; /* ACPI 1.0/2.0/3.0/4.0: 1 */
+	header->revision = get_acpi_table_revision(RSDT);
 
 	/* Entries are filled in later, we come with an empty set. */
 
@@ -840,7 +840,7 @@ static void acpi_write_xsdt(acpi_xsdt_t *xsdt, char *oem_id, char *oem_table_id)
 	memcpy(header->asl_compiler_id, ASLC, 4);
 
 	header->length = sizeof(acpi_xsdt_t);
-	header->revision = 1; /* ACPI 1.0: N/A, 2.0/3.0/4.0: 1 */
+	header->revision = get_acpi_table_revision(XSDT);
 
 	/* Entries are filled in later, we come with an empty set. */
 
@@ -870,7 +870,7 @@ static void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt,
 		rsdp->revision = 0;
 	} else {
 		rsdp->xsdt_address = (u64)(uintptr_t)xsdt;
-		rsdp->revision = 2;
+		rsdp->revision = get_acpi_table_revision(RSDP);
 	}
 
 	/* Calculate checksums. */
@@ -950,7 +950,7 @@ void acpi_write_hest(acpi_hest_t *hest,
 	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
 	header->length += sizeof(acpi_hest_t);
-	header->revision = 1;
+	header->revision = get_acpi_table_revision(HEST);
 
 	acpi_fill_hest(hest);
 
@@ -966,7 +966,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
 	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
 	memcpy(header->signature, "FACP", 4);
 	header->length = sizeof(acpi_fadt_t);
-	header->revision = 4;
+	header->revision = get_acpi_table_revision(FADT);
 	memcpy(header->oem_id, OEM_ID, 6);
 	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
 	memcpy(header->asl_compiler_id, ASLC, 4);
@@ -1252,14 +1252,52 @@ void *acpi_find_wakeup_vector(void)
 	return wake_vec;
 }
 
-void acpi_save_gnvs(u32 gnvs_address)
+__weak int acpi_get_gpe(int gpe)
 {
-	u32 *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS_PTR, sizeof(*gnvs));
-	if (gnvs)
-		*gnvs = gnvs_address;
+	return -1; /* implemented by SOC */
 }
 
-__weak int acpi_get_gpe(int gpe)
+int get_acpi_table_revision(enum acpi_tables table)
 {
-	return -1; /* implemented by SOC */
+	switch (table) {
+	case FADT:
+		return ACPI_FADT_REV_ACPI_3_0;
+	case MADT: /* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
+		return 2;
+	case MCFG:
+		return 1;
+	case TCPA:
+		return 2;
+	case SSDT: /* ACPI 1.0/2.0: ?, ACPI 3.0/4.0: 2 */
+		return 2;
+	case SRAT:  /* ACPI 1.0: N/A, 2.0: 1, 3.0: 2, 4.0: 3 */
+		return 1; /* TODO Should probably be upgraded to 2 */
+	case DMAR:
+		return 1;
+	case SLIT:  /* ACPI 1.0: N/A, ACPI 2.0/3.0/4.0: 1 */
+		return 1;
+	case HPET: /* Currently 1. Table added in ACPI 2.0. */
+		return 1;
+	case VFCT:  /* ACPI 1.0: N/A, ACPI 2.0/3.0/4.0: 1 */
+		return 1;
+	case IVRS:
+		return IVRS_FORMAT_FIXED;
+	case DBG2:
+		return 0;
+	case FACS: /* ACPI 1.0: 0, ACPI 2.0/3.0: 1, ACPI 4.0: 2 */
+		return 1;
+	case RSDT: /* ACPI 1.0/2.0/3.0/4.0: 1 */
+		return 1;
+	case XSDT: /* ACPI 1.0: N/A, 2.0/3.0/4.0: 1 */
+		return 1;
+	case RSDP:  /* ACPI 1.0: 0, ACPI 2.0/3.0/4.0: 2. */
+		return 2;
+	case HEST:
+		return 1;
+	case NHLT:
+		return 5;
+	default:
+		return -1;
+	}
+	return -1;
 }
diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c
@@ -226,13 +226,13 @@ void __weak mainboard_suspend_resume(void)
 void acpi_resume(void *wake_vec)
 {
 	if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
-		u32 *gnvs_address = cbmem_find(CBMEM_ID_ACPI_GNVS_PTR);
+		void *gnvs_address = cbmem_find(CBMEM_ID_ACPI_GNVS);
 
 		/* Restore GNVS pointer in SMM if found */
-		if (gnvs_address && *gnvs_address) {
-			printk(BIOS_DEBUG, "Restore GNVS pointer to 0x%08x\n",
-			       *gnvs_address);
-			smm_setup_structures((void *)*gnvs_address, NULL, NULL);
+		if (gnvs_address) {
+			printk(BIOS_DEBUG, "Restore GNVS pointer to %p\n",
+			       gnvs_address);
+			smm_setup_structures(gnvs_address, NULL, NULL);
 		}
 	}
 

diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c
@@ -578,14 +578,10 @@ void acpigen_write_empty_PTC(void)
 	acpigen_write_package(2);
 
 	/* ControlRegister */
-	acpigen_write_resourcetemplate_header();
-	acpigen_write_register(&addr);
-	acpigen_write_resourcetemplate_footer();
+	acpigen_write_register_resource(&addr);
 
 	/* StatusRegister */
-	acpigen_write_resourcetemplate_header();
-	acpigen_write_register(&addr);
-	acpigen_write_resourcetemplate_footer();
+	acpigen_write_register_resource(&addr);
 
 	acpigen_pop_len();
 }
@@ -725,9 +721,7 @@ void acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype)
 void acpigen_write_CST_package_entry(acpi_cstate_t *cstate)
 {
 	acpigen_write_package(4);
-	acpigen_write_resourcetemplate_header();
-	acpigen_write_register(&cstate->resource);
-	acpigen_write_resourcetemplate_footer();
+	acpigen_write_register_resource(&cstate->resource);
 	acpigen_write_dword(cstate->ctype);
 	acpigen_write_dword(cstate->latency);
 	acpigen_write_dword(cstate->power);
@@ -827,7 +821,7 @@ void acpigen_write_mem32fixed(int readwrite, u32 base, u32 size)
 	acpigen_emit_dword(size);
 }
 
-void acpigen_write_register(acpi_addr_t *addr)
+static void acpigen_write_register(const acpi_addr_t *addr)
 {
 	acpigen_emit_byte(0x82);		/* Register Descriptor */
 	acpigen_emit_byte(0x0c);		/* Register Length 7:0 */
@@ -840,6 +834,13 @@ void acpigen_write_register(acpi_addr_t *addr)
 	acpigen_emit_dword(addr->addrh);	/* Register Address High */
 }
 
+void acpigen_write_register_resource(const acpi_addr_t *addr)
+{
+	acpigen_write_resourcetemplate_header();
+	acpigen_write_register(addr);
+	acpigen_write_resourcetemplate_footer();
+}
+
 void acpigen_write_irq(u16 mask)
 {
 	/*
@@ -1338,6 +1339,55 @@ void acpigen_write_dsm_uuid_arr(struct dsm_uuid *ids, size_t count)
 	acpigen_pop_len();	/* Method _DSM */
 }
 
+#define CPPC_PACKAGE_NAME "\\GCPC"
+
+void acpigen_write_CPPC_package(const struct cppc_config *config)
+{
+	u32 i;
+	u32 max;
+	switch (config->version) {
+	case 1:
+		max = CPPC_MAX_FIELDS_VER_1;
+		break;
+	case 2:
+		max = CPPC_MAX_FIELDS_VER_2;
+		break;
+	case 3:
+		max = CPPC_MAX_FIELDS_VER_3;
+		break;
+	default:
+		printk(BIOS_ERR, "ERROR: CPPC version %u is not implemented\n",
+		       config->version);
+		return;
+	}
+	acpigen_write_name(CPPC_PACKAGE_NAME);
+
+	/* Adding 2 to account for length and version fields */
+	acpigen_write_package(max + 2);
+	acpigen_write_dword(max + 2);
+
+	acpigen_write_byte(config->version);
+
+	for (i = 0; i < max; ++i) {
+		const acpi_addr_t *reg = &(config->regs[i]);
+		if (reg->space_id == ACPI_ADDRESS_SPACE_MEMORY &&
+		    reg->bit_width == 32 && reg->access_size == 0) {
+			acpigen_write_dword(reg->addrl);
+		} else {
+			acpigen_write_register_resource(reg);
+		}
+	}
+	acpigen_pop_len();
+}
+
+void acpigen_write_CPPC_method(void)
+{
+	acpigen_write_method("_CPC", 0);
+	acpigen_emit_byte(RETURN_OP);
+	acpigen_emit_namestring(CPPC_PACKAGE_NAME);
+	acpigen_pop_len();
+}
+
 /*
  * Generate ACPI AML code for _ROM method.
  * This function takes as input ROM data and ROM length.
@@ -1404,7 +1454,7 @@ void acpigen_write_rom(void *bios, const size_t length)
 	ASSERT(length)
 
 	/* Method (_ROM, 2, NotSerialized) */
-	acpigen_write_method("_ROM", 2);
+	acpigen_write_method_serialized("_ROM", 2);
 
 	/* OperationRegion("ROMS", SYSTEMMEMORY, current, length) */
 	struct opregion opreg = OPREGION("ROMS", SYSTEMMEMORY,

diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c
@@ -622,7 +622,7 @@ asmlinkage void exception_init(void)
 {
 	int i;
 	uint16_t segment;
-	struct intr_gate *gates = car_get_var_ptr(idt);
+	struct intr_gate *gates;
 
 	segment = get_cs();
 	gates = car_get_var_ptr(idt);

diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
@@ -76,6 +76,18 @@ enum coreboot_acpi_ids {
 	COREBOOT_ACPI_ID_MAX		= 0xFFFF, /* BOOTFFFF */
 };
 
+/* Table 5-30 DESCRIPTION_HEADER Signatures for tables defined by ACPI 6.2a
+ *  Additional tables mssing in 5-30:  MADT, RSDP, VFCT, NHLT
+ */
+enum acpi_tables {
+	APIC, BERT, BGRT, CPEP, DSDT, ECDT, EINJ, ERST, FACP, FADT, FACS,
+	FPDT, GTDT, HEST, MSCT, MPST, NFIT, OEMX, PCCT, PMTT, PSDT, RASF,
+	RSDT, SBST, SDEV, SLIT, SRAT, SSDT, XSDT, BOOT, CSRT, DBG2, DBGP,
+	DMAR, DPPT, DRTM, ETDT, HPET, IBFT, IORT, IVRS, LPIT, MCFG, MCHI,
+	MSDM, SDEI, SLIC, SPCR, SPMI, STAO, TCPA, TPM2, WAET, WDAT, WDRT,
+	WPBT, WSMT, XENV, MADT, RSDP, VFCT, NHLT
+};
+
 /* RSDP (Root System Description Pointer) */
 typedef struct acpi_rsdp {
 	char  signature[8];	/* RSDP signature */
@@ -771,8 +783,6 @@ void acpi_write_hest(acpi_hest_t *hest,
 unsigned long acpi_create_hest_error_source(acpi_hest_t *hest,
 	acpi_hest_esd_t *esd, u16 type, void *data, u16 len);
 
-void acpi_save_gnvs(u32 gnvs_address);
-
 /* For ACPI S3 support. */
 void acpi_fail_wakeup(void);
 void acpi_resume(void *wake_vec);
@@ -847,6 +857,12 @@ static inline uintptr_t acpi_align_current(uintptr_t current)
 	return ALIGN(current, 16);
 }
 
+/* ACPI table revisions should match the revision of the ACPI spec
+ * supported. This function keeps the table versions synced. This could
+ * be made into a weak function if there is ever a need to override the
+ * coreboot default ACPI spec version supported. */
+int get_acpi_table_revision(enum acpi_tables table);
+
 #endif  // !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMC__)
 
 #endif  /* __ASM_ACPI_H */
diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h
@@ -36,6 +36,9 @@
 					 ACPI_STATUS_DEVICE_ENABLED |\
 					 ACPI_STATUS_DEVICE_SHOW_IN_UI |\
 					 ACPI_STATUS_DEVICE_STATE_OK)
+#define ACPI_STATUS_DEVICE_HIDDEN_ON	(ACPI_STATUS_DEVICE_PRESENT |\
+					 ACPI_STATUS_DEVICE_ENABLED |\
+					 ACPI_STATUS_DEVICE_STATE_OK)
 
 /* ACPI Op/Prefix Codes */
 enum {
@@ -167,6 +170,56 @@ struct dsm_uuid {
 	void *arg;
 };
 
+/*version 1 has 15 fields, version 2 has 19, and version 3 has 21 */
+enum cppc_fields {
+	CPPC_HIGHEST_PERF, /* can be DWORD */
+	CPPC_NOMINAL_PERF, /* can be DWORD */
+	CPPC_LOWEST_NONL_PERF, /* can be DWORD */
+	CPPC_LOWEST_PERF, /* can be DWORD */
+	CPPC_GUARANTEED_PERF,
+	CPPC_DESIRED_PERF,
+	CPPC_MIN_PERF,
+	CPPC_MAX_PERF,
+	CPPC_PERF_REDUCE_TOLERANCE,
+	CPPC_TIME_WINDOW,
+	CPPC_COUNTER_WRAP, /* can be DWORD */
+	CPPC_REF_PERF_COUNTER,
+	CPPC_DELIVERED_PERF_COUNTER,
+	CPPC_PERF_LIMITED,
+	CPPC_ENABLE, /* can be System I/O */
+	CPPC_MAX_FIELDS_VER_1,
+	CPPC_AUTO_SELECT = /* can be DWORD */
+		CPPC_MAX_FIELDS_VER_1,
+	CPPC_AUTO_ACTIVITY_WINDOW,
+	CPPC_PERF_PREF,
+	CPPC_REF_PERF, /* can be DWORD */
+	CPPC_MAX_FIELDS_VER_2,
+	CPPC_LOWEST_FREQ = /* can be DWORD */
+		CPPC_MAX_FIELDS_VER_2,
+	CPPC_NOMINAL_FREQ, /* can be DWORD */
+	CPPC_MAX_FIELDS_VER_3,
+};
+
+struct cppc_config {
+	u32 version; /* must be 1, 2, or 3 */
+	/*
+	 * The generic acpi_addr_t structure is being used, though
+	 * anything besides PPC or FFIXED generally requires checking
+	 * if the OS has advertised support for it (via _OSC).
+	 *
+	 * NOTE: some fields permit DWORDs to be used.  If you
+	 * provide a System Memory register with all zeros (which
+	 * represents unsupported) then this will be used as-is.
+	 * Otherwise, a System Memory register with a 32-bit
+	 * width will be converted into a DWORD field (the value
+	 * of which will be the value of 'addrl'.  Any other use
+	 * of System Memory register is currently undefined.
+	 * (i.e., if you have an actual need for System Memory
+	 * then you'll need to adjust this kludge).
+	 */
+	acpi_addr_t regs[CPPC_MAX_FIELDS_VER_3];
+};
+
 void acpigen_write_return_integer(uint64_t arg);
 void acpigen_write_return_string(const char *arg);
 void acpigen_write_len_f(void);
@@ -228,7 +281,7 @@ void acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list);
 void acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype);
 void acpigen_write_mem32fixed(int readwrite, u32 base, u32 size);
 void acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16);
-void acpigen_write_register(acpi_addr_t *addr);
+void acpigen_write_register_resource(const acpi_addr_t *addr);
 void acpigen_write_resourcetemplate_header(void);
 void acpigen_write_resourcetemplate_footer(void);
 void acpigen_write_mainboard_resource_template(void);
@@ -268,6 +321,15 @@ void acpigen_write_dsm(const char *uuid, void (**callbacks)(void *),
 		       size_t count, void *arg);
 void acpigen_write_dsm_uuid_arr(struct dsm_uuid *ids, size_t count);
 
+/*
+ * Generate ACPI AML code for _CPC (Continuous Perfmance Control).
+ * Execute the package function once to create a global table, then
+ * execute the method function within each processor object to
+ * create a method that points to the global table.
+ */
+void acpigen_write_CPPC_package(const struct cppc_config *config);
+void acpigen_write_CPPC_method(void);
+
 /*
  * Generate ACPI AML code for _ROM method.
  * This function takes as input ROM data and ROM length.

diff --git a/src/arch/x86/include/arch/cache.h b/src/arch/x86/include/arch/cache.h
@@ -34,13 +34,6 @@
 #include <arch/early_variables.h>
 #include <cpu/x86/cache.h>
 
-/*
- * For the purposes of the currently executing CPU loading code that will be
- * run there aren't any cache coherency operations required. This just provides
- * symmetry between architectures.
- */
-static inline void cache_sync_instructions(void) {}
-
 /* Executing WBINVD when running out of CAR would not be good, prevent that. */
 static inline void dcache_clean_invalidate_all(void)
 {

diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
@@ -367,7 +367,7 @@ static int smbios_write_type0(unsigned long *current, int handle)
 
 #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
 	/* SMBIOS offsets start at 1 rather than 0 */
-	vboot_data->vbt10 = (u32)t->eos + (version_offset - 1);
+	acpi_get_chromeos_acpi()->vbt10 = (u32)t->eos + (version_offset - 1);
 #endif
 #endif /* CONFIG_CHROMEOS */
 

diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c
@@ -259,6 +259,9 @@ void arch_write_tables(uintptr_t coreboot_table)
 	forwarding_table += sz;
 	/* Align up to page boundary for historical consistency. */
 	forwarding_table = ALIGN_UP(forwarding_table, 4*KiB);
+
+	/* Tell static analysis we know value is left unused. */
+	(void)rom_table_end;
 }
 
 void bootmem_arch_add_ranges(void)

diff --git a/src/arch/x86/thread.c b/src/arch/x86/thread.c
@@ -47,7 +47,7 @@ void arch_prepare_thread(struct thread *t,
 	stack = push_stack(stack, (uintptr_t)arg);
 	stack = push_stack(stack, (uintptr_t)0);
 	stack = push_stack(stack, (uintptr_t)thread_entry);
-	/* Make room for the registers. Ignore intial values. */
+	/* Make room for the registers. Ignore initial values. */
 	stack -= sizeof(struct pushad_regs);
 
 	t->stack_current = stack;

diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h
@@ -19,7 +19,6 @@
 
 #define CBMEM_ID_ACPI		0x41435049
 #define CBMEM_ID_ACPI_GNVS	0x474e5653
-#define CBMEM_ID_ACPI_GNVS_PTR	0x474e5650
 #define CBMEM_ID_AFTER_CAR	0xc4787a93
 #define CBMEM_ID_AGESA_RUNTIME	0x41474553
 #define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
@@ -64,6 +63,7 @@
 #define CBMEM_ID_STAGEx_RAW	0x57a9e200
 #define CBMEM_ID_STORAGE_DATA	0x53746f72
 #define CBMEM_ID_TCPA_LOG	0x54435041
+#define CBMEM_ID_TCPA_TCG_LOG	0x54445041
 #define CBMEM_ID_TIMESTAMP	0x54494d45
 #define CBMEM_ID_VBOOT_HANDOFF	0x780074f0
 #define CBMEM_ID_VBOOT_SEL_REG	0x780074f1
@@ -80,7 +80,6 @@
 #define CBMEM_ID_TO_NAME_TABLE				 \
 	{ CBMEM_ID_ACPI,		"ACPI       " }, \
 	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
-	{ CBMEM_ID_ACPI_GNVS_PTR,	"GNVS PTR   " }, \
 	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
 	{ CBMEM_ID_AFTER_CAR,		"AFTER CAR  " }, \
 	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
@@ -120,6 +119,7 @@
 	{ CBMEM_ID_SMM_SAVE_SPACE,	"SMM BACKUP " }, \
 	{ CBMEM_ID_STORAGE_DATA,	"SD/MMC/eMMC" }, \
 	{ CBMEM_ID_TCPA_LOG,		"TCPA LOG   " }, \
+	{ CBMEM_ID_TCPA_TCG_LOG,	"TCPA TCGLOG" }, \
 	{ CBMEM_ID_TIMESTAMP,		"TIME STAMP " }, \
 	{ CBMEM_ID_VBOOT_HANDOFF,	"VBOOT      " }, \
 	{ CBMEM_ID_VBOOT_SEL_REG,	"VBOOT SEL  " }, \

diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -290,7 +290,6 @@ struct lb_gpios {
 	struct lb_gpio gpios[0];
 };
 
-#define LB_TAG_VDAT		0x0015
 #define LB_TAG_VBNV		0x0019
 #define LB_TAB_VBOOT_HANDOFF	0x0020
 #define LB_TAB_DMA		0x0022
@@ -310,6 +309,7 @@ void lb_ramoops(struct lb_header *header);
 #define LB_TAG_CBMEM_CONSOLE	0x0017
 #define LB_TAG_MRC_CACHE	0x0018
 #define LB_TAG_ACPI_GNVS	0x0024
+#define LB_TAG_TCPA_LOG		0x0034
 #define LB_TAG_WIFI_CALIBRATION	0x0027
 #define LB_TAG_VPD		0x002c
 struct lb_cbmem_ref {
Original file line number	Diff line number	Diff line change
Expand Up		@@ -4,4 +4,5 @@ This section contains documentation about coreboot on specific Intel SOCs.

		## Platforms

		- [Common code development strategy](code_development_model/code_development_model.md)
		- [Ice Lake/9th Gen Core-i series](icelake/index.md)