41 changes: 19 additions & 22 deletions src/arch/x86/pci_ops_conf1.c
View file
Expand Up @@ -19,53 +19,50 @@
*/

#if !IS_ENABLED(CONFIG_PCI_IO_CFG_EXT)
#define CONF_CMD(bus, devfn, where) (0x80000000 | (bus << 16) | \
(devfn << 8) | (where & ~3))
#define CONF_CMD(dev, where) (0x80000000 | ((dev)->bus->secondary << 16) | \
((dev)->path.pci.devfn << 8) | (where & ~3))
#else
#define CONF_CMD(bus, devfn, where) (0x80000000 | (bus << 16) | \
(devfn << 8) | ((where & 0xff) & ~3) |\
#define CONF_CMD(dev, where) (0x80000000 | ((dev)->bus->secondary << 16) | \
((dev)->path.pci.devfn << 8) | ((where & 0xff) & ~3) |\
((where & 0xf00)<<16))
#endif

static uint8_t pci_conf1_read_config8(struct bus *pbus, int bus, int devfn,
int where)
static uint8_t pci_conf1_read_config8(struct device *dev, int where)
{
outl(CONF_CMD(bus, devfn, where), 0xCF8);
outl(CONF_CMD(dev, where), 0xCF8);
return inb(0xCFC + (where & 3));
}

static uint16_t pci_conf1_read_config16(struct bus *pbus, int bus, int devfn,
int where)
static uint16_t pci_conf1_read_config16(struct device *dev, int where)
{
outl(CONF_CMD(bus, devfn, where), 0xCF8);
outl(CONF_CMD(dev, where), 0xCF8);
return inw(0xCFC + (where & 2));
}

static uint32_t pci_conf1_read_config32(struct bus *pbus, int bus, int devfn,
int where)
static uint32_t pci_conf1_read_config32(struct device *dev, int where)
{
outl(CONF_CMD(bus, devfn, where), 0xCF8);
outl(CONF_CMD(dev, where), 0xCF8);
return inl(0xCFC);
}

static void pci_conf1_write_config8(struct bus *pbus, int bus, int devfn,
int where, uint8_t value)
static void pci_conf1_write_config8(struct device *dev, int where,
uint8_t value)
{
outl(CONF_CMD(bus, devfn, where), 0xCF8);
outl(CONF_CMD(dev, where), 0xCF8);
outb(value, 0xCFC + (where & 3));
}

static void pci_conf1_write_config16(struct bus *pbus, int bus, int devfn,
int where, uint16_t value)
static void pci_conf1_write_config16(struct device *dev, int where,
uint16_t value)
{
outl(CONF_CMD(bus, devfn, where), 0xCF8);
outl(CONF_CMD(dev, where), 0xCF8);
outw(value, 0xCFC + (where & 2));
}

static void pci_conf1_write_config32(struct bus *pbus, int bus, int devfn,
int where, uint32_t value)
static void pci_conf1_write_config32(struct device *dev, int where,
uint32_t value)
{
outl(CONF_CMD(bus, devfn, where), 0xCF8);
outl(CONF_CMD(dev, where), 0xCF8);
outl(value, 0xCFC);
}

Expand Down
33 changes: 27 additions & 6 deletions src/arch/x86/smbios.c
View file
Expand Up @@ -371,15 +371,20 @@ static int smbios_write_type0(unsigned long *current, int handle)
#endif
#endif /* CONFIG_CHROMEOS */

/* As a work around to prevent a compiler error, temporarily specify
* 16 MiB flash sizes when ROM size >= 16 MiB. An update is necessary
* once the SMBIOS specification addresses ROM sizes > 16 MiB.
*/
uint32_t rom_size = CONFIG_ROM_SIZE;
rom_size = MIN(CONFIG_ROM_SIZE, 16 * MiB);
t->bios_rom_size = (rom_size / 65535) - 1;

t->system_bios_major_release = 4;
if (CONFIG_ROM_SIZE >= 1 * GiB) {
t->extended_bios_rom_size =
DIV_ROUND_UP(CONFIG_ROM_SIZE, GiB) | (1 << 14);
} else {
t->extended_bios_rom_size = DIV_ROUND_UP(CONFIG_ROM_SIZE, MiB);
}

t->system_bios_major_release = coreboot_major_revision;
t->system_bios_minor_release = coreboot_minor_revision;

t->bios_characteristics =
BIOS_CHARACTERISTICS_PCI_SUPPORTED |
BIOS_CHARACTERISTICS_SELECTABLE_BOOT |
Expand Down Expand Up @@ -450,6 +455,11 @@ const char *__weak smbios_mainboard_sku(void)
return "";
}

int __weak fill_mainboard_smbios_type16(unsigned long *current, int *handle)
{
return 0;
}

#ifdef CONFIG_MAINBOARD_FAMILY
const char *smbios_mainboard_family(void)
{
Expand Down Expand Up @@ -555,7 +565,6 @@ static int smbios_write_type4(unsigned long *current, int handle)
t->processor_version = smbios_processor_name(t->eos);
t->processor_family = (res.eax > 0) ? 0x0c : 0x6;
t->processor_type = 3; /* System Processor */
t->processor_upgrade = 0x06;
t->core_count = (res.ebx >> 16) & 0xff;
t->l1_cache_handle = 0xffff;
t->l2_cache_handle = 0xffff;
Expand Down Expand Up @@ -594,6 +603,16 @@ static int smbios_write_type11(unsigned long *current, int *handle)
return len;
}

static int smbios_write_type16(unsigned long *current, int *handle)
{
int len = fill_mainboard_smbios_type16(current, handle);
if(len){
*current += len;
(*handle)++;
}
return len;
}

static int smbios_write_type17(unsigned long *current, int *handle)
{
int len = sizeof(struct smbios_type17);
Expand Down Expand Up @@ -752,6 +771,8 @@ unsigned long smbios_write_tables(unsigned long current)
if (IS_ENABLED(CONFIG_ELOG))
update_max(len, max_struct_size,
elog_smbios_write_type15(&current,handle++));
update_max(len, max_struct_size, smbios_write_type16(&current,
&handle));
update_max(len, max_struct_size, smbios_write_type17(&current,
&handle));
update_max(len, max_struct_size, smbios_write_type32(&current,
Expand Down
2 changes: 2 additions & 0 deletions src/commonlib/Makefile.inc
View file
Expand Up @@ -36,3 +36,5 @@ verstage-y += lz4_wrapper.c
romstage-y += lz4_wrapper.c
ramstage-y += lz4_wrapper.c
postcar-y += lz4_wrapper.c

ramstage-y += sort.c
1 change: 1 addition & 0 deletions src/commonlib/include/commonlib/fmap_serialized.h
View file
Expand Up @@ -48,6 +48,7 @@ enum fmap_flags {
FMAP_AREA_STATIC = 1 << 0,
FMAP_AREA_COMPRESSED = 1 << 1,
FMAP_AREA_RO = 1 << 2,
FMAP_AREA_PRESERVE = 1 << 3,
};

/* Mapping of volatile and static regions in firmware binary */
Expand Down
5 changes: 5 additions & 0 deletions src/commonlib/include/commonlib/helpers.h
View file
Expand Up @@ -38,6 +38,11 @@
#define ABS(a) (((a) < 0) ? (-(a)) : (a))
#define IS_POWER_OF_2(x) (((x) & ((x) - 1)) == 0)
#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y))
#define SWAP(a, b) do { \
typeof(a) tmp = a; \
a = (typeof(a)) b; \
b = (typeof(b)) tmp; \
} while (0)
/*
* Divide positive or negative dividend by positive divisor and round
* to closest integer. Result is undefined for negative divisors and
Expand Down
27 changes: 27 additions & 0 deletions src/commonlib/include/commonlib/sort.h
View file
@@ -0,0 +1,27 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2019 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _COMMONLIB_SORT_H_
#define _COMMONLIB_SORT_H_

#include <stddef.h>

typedef enum {
NUM_ASCENDING,
NUM_DESCENDING
} sort_order_t;

void bubblesort(int *v, size_t num_entries, sort_order_t order);

#endif /* _COMMONLIB_SORT_H_ */
49 changes: 49 additions & 0 deletions src/commonlib/sort.c
View file
@@ -0,0 +1,49 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2019 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include <commonlib/helpers.h>
#include <commonlib/sort.h>

/* Implement a simple Bubble sort algorithm. Reduce the needed number of
iterations by taking care of already sorted entries in the list. */
void bubblesort(int *v, size_t num_entries, sort_order_t order)
{
size_t i, j;
int swapped;

for (j = 0; j < num_entries - 1; j++) {
swapped = 0;
for (i = 0; i < num_entries - j - 1; i++) {
switch (order) {
case NUM_ASCENDING:
if (v[i] > v[i + 1]) {
SWAP(v[i], v[i + 1]);
swapped = 1;
}
break;
case NUM_DESCENDING:
if (v[i] < v[i + 1]) {
SWAP(v[i], v[i + 1]);
swapped = 1;
}
break;
default:
return;
}
}
if (!swapped)
break;
}
}
1 change: 1 addition & 0 deletions src/commonlib/storage/pci_sdhci.c
View file
Expand Up @@ -21,6 +21,7 @@
#include <assert.h>
#include <commonlib/sdhci.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include "sd_mmc.h"
#include <stdint.h>
#include "storage.h"
Expand Down
2 changes: 1 addition & 1 deletion src/commonlib/storage/sdhci.h
View file
Expand Up @@ -17,7 +17,7 @@
#ifndef __COMMONLIB_STORAGE_SDHCI_H__
#define __COMMONLIB_STORAGE_SDHCI_H__

#include <arch/io.h>
#include <device/mmio.h>
#include <commonlib/sd_mmc_ctrlr.h>

/*
Expand Down
1 change: 0 additions & 1 deletion src/console/die.c
View file
Expand Up @@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/

#include <arch/io.h>
#include <console/console.h>
#include <halt.h>

Expand Down
18 changes: 14 additions & 4 deletions src/console/init.c
View file
Expand Up @@ -15,6 +15,7 @@
*/

#include <arch/early_variables.h>
#include <commonlib/helpers.h>
#include <console/console.h>
#include <console/uart.h>
#include <console/streams.h>
Expand Down Expand Up @@ -64,7 +65,18 @@ static void init_log_level(void)

int console_log_level(int msg_level)
{
return (get_log_level() >= msg_level);
int log_level = get_log_level();

if (log_level < 0)
return CONSOLE_LOG_NONE;

if (msg_level <= log_level)
return CONSOLE_LOG_ALL;

if (IS_ENABLED(CONFIG_CONSOLE_CBMEM) && (msg_level <= BIOS_DEBUG))
return CONSOLE_LOG_FAST;

return 0;
}

asmlinkage void console_init(void)
Expand All @@ -74,10 +86,8 @@ asmlinkage void console_init(void)
if (IS_ENABLED(CONFIG_DEBUG_CONSOLE_INIT))
car_set_var(console_inited, 1);

#if IS_ENABLED(CONFIG_EARLY_PCI_BRIDGE)
if (!ENV_SMM && !ENV_RAMSTAGE)
if (IS_ENABLED(CONFIG_EARLY_PCI_BRIDGE) && !ENV_SMM && !ENV_RAMSTAGE)
pci_early_bridge_init();
#endif

console_hw_init();

Expand Down
5 changes: 4 additions & 1 deletion src/console/post.c
View file
Expand Up @@ -14,12 +14,15 @@
* GNU General Public License for more details.
*/

#include <arch/io.h>
#include <stdint.h>
#include <elog.h>
#include <console/console.h>
#include <device/device.h>
#include <pc80/mc146818rtc.h>
#include <smp/spinlock.h>
#if IS_ENABLED(CONFIG_POST_IO)
#include <arch/io.h>
#endif

/* Write POST information */

Expand Down
43 changes: 26 additions & 17 deletions src/console/printk.c
View file
Expand Up @@ -17,6 +17,7 @@
* blatantly copied from linux/kernel/printk.c
*/

#include <console/cbmem_console.h>
#include <console/console.h>
#include <console/streams.h>
#include <console/vtxprintf.h>
Expand All @@ -36,19 +37,24 @@ void do_putchar(unsigned char byte)

static void wrap_putchar(unsigned char byte, void *data)
{
do_putchar(byte);
console_tx_byte(byte);
}

int do_printk(int msg_level, const char *fmt, ...)
static void wrap_putchar_cbmemc(unsigned char byte, void *data)
{
va_list args;
int i;
__cbmemc_tx_byte(byte);
}

int vprintk(int msg_level, const char *fmt, va_list args)
{
int i, log_this;

if (IS_ENABLED(CONFIG_SQUELCH_EARLY_SMP) && ENV_CACHE_AS_RAM &&
!boot_cpu())
return 0;

if (!console_log_level(msg_level))
log_this = console_log_level(msg_level);
if (log_this < CONSOLE_LOG_FAST)
return 0;

DISABLE_TRACE;
Expand All @@ -60,11 +66,12 @@ int do_printk(int msg_level, const char *fmt, ...)
spin_lock(&console_lock);
#endif

va_start(args, fmt);
i = vtxprintf(wrap_putchar, fmt, args, NULL);
va_end(args);

console_tx_flush();
if (log_this == CONSOLE_LOG_FAST) {
i = vtxprintf(wrap_putchar_cbmemc, fmt, args, NULL);
} else {
i = vtxprintf(wrap_putchar, fmt, args, NULL);
console_tx_flush();
}

#ifdef __PRE_RAM__
#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK)
Expand All @@ -78,12 +85,14 @@ int do_printk(int msg_level, const char *fmt, ...)
return i;
}

#if IS_ENABLED(CONFIG_VBOOT)
void do_printk_va_list(int msg_level, const char *fmt, va_list args)
int do_printk(int msg_level, const char *fmt, ...)
{
if (!console_log_level(msg_level))
return;
vtxprintf(wrap_putchar, fmt, args, NULL);
console_tx_flush();
va_list args;
int i;

va_start(args, fmt);
i = vprintk(msg_level, fmt, args);
va_end(args);

return i;
}
#endif /* CONFIG_VBOOT */
2 changes: 1 addition & 1 deletion src/cpu/allwinner/a10/clock.c
View file
Expand Up @@ -18,7 +18,7 @@

#include "clock.h"

#include <arch/io.h>
#include <device/mmio.h>
#include <console/console.h>
#include <delay.h>
#include <lib.h>
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/allwinner/a10/gpio.c
View file
Expand Up @@ -18,7 +18,7 @@

#include "gpio.h"

#include <arch/io.h>
#include <device/mmio.h>

static struct a10_gpio *const gpio = (void *)GPIO_BASE;

Expand Down
2 changes: 1 addition & 1 deletion src/cpu/allwinner/a10/pinmux.c
View file
Expand Up @@ -20,7 +20,7 @@

#include "gpio.h"

#include <arch/io.h>
#include <device/mmio.h>

static struct a10_gpio *const gpio = (void *)GPIO_BASE;

Expand Down
2 changes: 1 addition & 1 deletion src/cpu/allwinner/a10/raminit.c
View file
Expand Up @@ -29,7 +29,7 @@
#include "memmap.h"
#include "timer.h"

#include <arch/io.h>
#include <device/mmio.h>
#include <delay.h>

static struct a1x_dramc *const dram = (void *)A1X_DRAMC_BASE;
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/allwinner/a10/timer.c
View file
Expand Up @@ -19,7 +19,7 @@

#include "timer.h"

#include <arch/io.h>
#include <device/mmio.h>
#include <delay.h>
#include <timer.h>

Expand Down
2 changes: 1 addition & 1 deletion src/cpu/allwinner/a10/twi.c
View file
Expand Up @@ -23,7 +23,7 @@
#include "memmap.h"
#include "twi.h"

#include <arch/io.h>
#include <device/mmio.h>
#include <delay.h>
#include <device/i2c_simple.h>

Expand Down
2 changes: 1 addition & 1 deletion src/cpu/allwinner/a10/uart.c
View file
Expand Up @@ -19,7 +19,7 @@
*/

#include "uart.h"
#include <arch/io.h>
#include <device/mmio.h>
#include <console/uart.h>
#include <drivers/uart/uart8250reg.h>

Expand Down
1 change: 1 addition & 0 deletions src/cpu/amd/family_10h-family_15h/init_cpus.c
View file
Expand Up @@ -15,6 +15,7 @@
*/

#include <cpu/amd/msr.h>
#include <device/pci_ops.h>
#include "init_cpus.h"

#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)
Expand Down
1 change: 1 addition & 0 deletions src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
View file
Expand Up @@ -21,6 +21,7 @@
#include <cpu/amd/mtrr.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <string.h>
#include <cpu/x86/smm.h>
#include <cpu/x86/pae.h>
Expand Down
1 change: 1 addition & 0 deletions src/cpu/amd/family_10h-family_15h/monotonic_timer.c
View file
Expand Up @@ -19,6 +19,7 @@
#include <cpu/amd/msr.h>
#include <timer.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <northbridge/amd/amdht/AsPsDefs.h>

static struct monotonic_counter {
Expand Down
5 changes: 3 additions & 2 deletions src/cpu/amd/family_10h-family_15h/powernow_acpi.c
View file
Expand Up @@ -23,6 +23,7 @@
#include <arch/acpigen.h>
#include <cpu/amd/powernow.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/amdfam10_sysconf.h>
#include <arch/cpu.h>
Expand Down Expand Up @@ -113,7 +114,7 @@ static void write_cstates_for_core(int coreID)
cstate.resource.bit_offset = 0;
cstate.resource.addrl = rdmsr(MSR_CSTATE_ADDRESS).lo + 1;
cstate.resource.addrh = 0;
cstate.resource.resv = 1;
cstate.resource.access_size = 1;
} else {
cstate.ctype = 2;
cstate.latency = 75;
Expand All @@ -123,7 +124,7 @@ static void write_cstates_for_core(int coreID)
cstate.resource.bit_offset = 0;
cstate.resource.addrl = rdmsr(MSR_CSTATE_ADDRESS).lo;
cstate.resource.addrh = 0;
cstate.resource.resv = 1;
cstate.resource.access_size = 1;
}

acpigen_write_CST_package(&cstate, cstate_count);
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/amd/family_10h-family_15h/ram_calc.c
View file
Expand Up @@ -18,7 +18,7 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>

#include <arch/io.h>
#include <device/pci_ops.h>
#include <device/device.h>
#include <device/pci.h>

Expand Down
2 changes: 1 addition & 1 deletion src/cpu/amd/microcode/microcode.c
View file
Expand Up @@ -20,7 +20,7 @@
#include <cpu/amd/msr.h>
#include <cpu/amd/microcode.h>
#include <cbfs.h>
#include <arch/io.h>
#include <device/mmio.h>
#include <smp/spinlock.h>

#define UCODE_DEBUG(fmt, args...) \
Expand Down
1 change: 0 additions & 1 deletion src/cpu/amd/pi/00630F01/model_15_init.c
View file
Expand Up @@ -26,7 +26,6 @@
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <arch/acpi.h>

static void model_15_init(struct device *dev)
{
Expand Down
1 change: 0 additions & 1 deletion src/cpu/amd/pi/00660F01/model_15_init.c
View file
Expand Up @@ -25,7 +25,6 @@
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <arch/acpi.h>

#include <amdlib.h>
#include <PspBaseLib.h>
Expand Down
1 change: 1 addition & 0 deletions src/cpu/amd/pi/00730F01/Kconfig
View file
Expand Up @@ -16,6 +16,7 @@
config CPU_AMD_PI_00730F01
bool
select X86_AMD_FIXED_MTRRS
select SUPPORT_CPU_UCODE_IN_CBFS

if CPU_AMD_PI_00730F01

Expand Down
1 change: 0 additions & 1 deletion src/cpu/amd/pi/00730F01/model_16_init.c
View file
Expand Up @@ -25,7 +25,6 @@
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <arch/acpi.h>

static void model_16_init(struct device *dev)
{
Expand Down
1 change: 1 addition & 0 deletions src/cpu/amd/quadcore/amd_sibling.c
View file
Expand Up @@ -17,6 +17,7 @@
#include <cpu/x86/lapic.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <pc80/mc146818rtc.h>
#include <smp/spinlock.h>
#include <cpu/x86/mtrr.h>
Expand Down
1 change: 1 addition & 0 deletions src/cpu/amd/quadcore/quadcore.c
View file
Expand Up @@ -17,6 +17,7 @@

#include <arch/cpu.h>
#include <console/console.h>
#include <device/pci_ops.h>
#include <pc80/mc146818rtc.h>
#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)
#include "option_table.h"
Expand Down
1 change: 1 addition & 0 deletions src/cpu/amd/quadcore/quadcore_id.c
View file
Expand Up @@ -18,6 +18,7 @@

#include <arch/cpu.h>
#include <cpu/amd/multicore.h>
#include <device/pci_ops.h>
#ifdef __PRE_RAM__
#include <cpu/amd/msr.h>
#endif
Expand Down
1 change: 0 additions & 1 deletion src/cpu/amd/smm/smm_init.c
View file
Expand Up @@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/

#include <arch/io.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
Expand Down
7 changes: 2 additions & 5 deletions src/cpu/intel/Kconfig
View file
Expand Up @@ -3,9 +3,7 @@ source src/cpu/intel/model_6xx/Kconfig
source src/cpu/intel/model_65x/Kconfig
source src/cpu/intel/model_67x/Kconfig
source src/cpu/intel/model_68x/Kconfig
source src/cpu/intel/model_69x/Kconfig
source src/cpu/intel/model_6bx/Kconfig
source src/cpu/intel/model_6dx/Kconfig
source src/cpu/intel/model_6ex/Kconfig
source src/cpu/intel/model_6fx/Kconfig
source src/cpu/intel/model_1067x/Kconfig
Expand All @@ -20,10 +18,9 @@ source src/cpu/intel/haswell/Kconfig
# Sockets/Slots
source src/cpu/intel/slot_1/Kconfig
source src/cpu/intel/socket_BGA956/Kconfig
source src/cpu/intel/socket_BGA1284/Kconfig
source src/cpu/intel/socket_FCBGA559/Kconfig
source src/cpu/intel/socket_mFCPGA478/Kconfig
source src/cpu/intel/socket_mPGA478MN/Kconfig
source src/cpu/intel/socket_m/Kconfig
source src/cpu/intel/socket_p/Kconfig
source src/cpu/intel/socket_mPGA604/Kconfig
source src/cpu/intel/socket_441/Kconfig
source src/cpu/intel/socket_LGA775/Kconfig
Expand Down
5 changes: 2 additions & 3 deletions src/cpu/intel/Makefile.inc
View file
Expand Up @@ -6,10 +6,9 @@
subdirs-$(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE) += fit
subdirs-$(CONFIG_CPU_INTEL_SOCKET_441) += socket_441
subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += socket_BGA956
subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA1284) += socket_BGA1284
subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559
subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCPGA478) += socket_mFCPGA478
subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478MN) += socket_mPGA478MN
subdirs-$(CONFIG_CPU_INTEL_SOCKET_M) += socket_m
subdirs-$(CONFIG_CPU_INTEL_SOCKET_P) += socket_p
subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/intel/car/non-evict/cache_as_ram.S
View file
Expand Up @@ -118,7 +118,7 @@ addrsize_set_high:
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx
movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax
movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
wrmsr

movl $MTRR_PHYS_MASK(1), %ecx
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/intel/car/p4-netburst/cache_as_ram.S
View file
Expand Up @@ -304,7 +304,7 @@ no_msr_11e:
/* Cache the whole rom to fetch microcode updates */
movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx
movl $CACHE_ROM_BASE | MTRR_TYPE_WRPROT, %eax
movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
wrmsr

movl $MTRR_PHYS_MASK(1), %ecx
Expand Down
10 changes: 3 additions & 7 deletions src/cpu/intel/common/common_init.c
View file
Expand Up @@ -83,7 +83,7 @@ void set_feature_ctrl_lock(void)
msr = rdmsr(IA32_FEATURE_CONTROL);

if (msr.lo & (1 << 0)) {
printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked; ");
printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n");
/* IA32_FEATURE_CONTROL locked. If we set it again we get an
* illegal instruction
*/
Expand Down Expand Up @@ -113,19 +113,15 @@ void cpu_init_cppc_config(struct cppc_config *config, u32 version)
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = 8,
.bit_offset = 0,
{
.access_size = 4
},
.access_size = 4,
.addrl = 0,
.addrh = 0,
};
static const acpi_addr_t unsupported = {
.space_id = ACPI_ADDRESS_SPACE_MEMORY,
.bit_width = 0,
.bit_offset = 0,
{
.resv = 0
},
.access_size = 0,
.addrl = 0,
.addrh = 0,
};
Expand Down
17 changes: 14 additions & 3 deletions src/cpu/intel/common/fsb.c
View file
Expand Up @@ -18,7 +18,7 @@
#include <console/console.h>
#include <commonlib/helpers.h>

int get_ia32_fsb(void)
static int get_fsb(void)
{
struct cpuinfo_x86 c;
static const short core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 };
Expand All @@ -39,8 +39,11 @@ int get_ia32_fsb(void)
case 0x17: /* Enhanced Core */
ret = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7];
break;
case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/
case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/
case 0x25: /* Nehalem BCLK fixed at 133MHz */
ret = 133;
break;
case 0x2a: /* SandyBridge BCLK fixed at 100MHz */
case 0x3a: /* IvyBridge BCLK fixed at 100MHz */
case 0x3c: /* Haswell BCLK fixed at 100MHz */
case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */
ret = 100;
Expand All @@ -60,6 +63,14 @@ int get_ia32_fsb(void)
break;
}
}
return ret;
}

int get_ia32_fsb(void)
{
int ret;

ret = get_fsb();
if (ret == -1)
printk(BIOS_ERR, "FSB not found\n");
if (ret == -2)
Expand Down
1 change: 1 addition & 0 deletions src/cpu/intel/fsp_model_406dx/bootblock.c
View file
Expand Up @@ -20,6 +20,7 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <arch/io.h>
#include <device/pci_ops.h>
#include <reset.h>
#include <southbridge/intel/fsp_rangeley/soc.h>

Expand Down
2 changes: 2 additions & 0 deletions src/cpu/intel/haswell/Makefile.inc
View file
Expand Up @@ -4,6 +4,8 @@ romstage-y += romstage.c
romstage-y += tsc_freq.c
romstage-y += ../car/romstage.c

postcar-y += tsc_freq.c

ramstage-y += acpi.c
ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
Expand Down
5 changes: 1 addition & 4 deletions src/cpu/intel/haswell/romstage.c
View file
Expand Up @@ -24,8 +24,6 @@
#include <halt.h>
#include <lib.h>
#include <timestamp.h>
#include <arch/acpi.h>
#include <arch/io.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <cbmem.h>
Expand Down Expand Up @@ -55,8 +53,7 @@ void platform_enter_postcar(void)
if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
MTRR_TYPE_WRPROT);
postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);

/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
Expand Down
32 changes: 24 additions & 8 deletions src/cpu/intel/model_1067x/mp_init.c
View file
Expand Up @@ -27,6 +27,8 @@ static const void *microcode_patch;

static void pre_mp_init(void)
{
intel_microcode_load_unlocked(microcode_patch);

/* Setup MTRRs based on physical address size. */
x86_setup_mtrrs_with_detect();
x86_mtrr_check();
Expand All @@ -42,6 +44,12 @@ static int get_cpu_count(void)
return cores;
}

static void get_microcode_info(const void **microcode, int *parallel)
{
*microcode = microcode_patch;
*parallel = 1;
}

/* the SMRR enable and lock bit need to be set in IA32_FEATURE_CONTROL
to enable SMRR so configure IA32_FEATURE_CONTROL early on */
static void pre_mp_smm_init(void)
Expand All @@ -60,20 +68,25 @@ static void per_cpu_smm_trigger(void)
/* We don't care if the lock is already setting
as our smm relocation handler is able to handle
setups where SMRR is not enabled here. */
if (!IS_ENABLED(CONFIG_SET_IA32_FC_LOCK_BIT))
printk(BIOS_INFO,
"Overriding CONFIG_SET_IA32_FC_LOCK_BIT to enable SMRR\n");
ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl);
if (ia32_ft_ctrl.lo & (1 << 0)) {
/* IA32_FEATURE_CONTROL locked. If we set it again we
get an illegal instruction. */
printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n");
printk(BIOS_DEBUG, "SMRR status: %senabled\n",
ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
} else {
if (!IS_ENABLED(CONFIG_SET_IA32_FC_LOCK_BIT))
printk(BIOS_INFO,
"Overriding CONFIG_SET_IA32_FC_LOCK_BIT to enable SMRR\n");
ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl);
}
} else {
set_vmx_and_lock();
}

/* Relocate the SMM handler. */
smm_relocate();

/* After SMM relocation a 2nd microcode load is required. */
intel_microcode_load_unlocked(microcode_patch);
}

static void post_mp_init(void)
Expand All @@ -90,6 +103,7 @@ static const struct mp_ops mp_ops = {
.pre_mp_init = pre_mp_init,
.get_cpu_count = get_cpu_count,
.get_smm_info = smm_info,
.get_microcode_info = get_microcode_info,
.pre_mp_smm_init = pre_mp_smm_init,
.per_cpu_smm_trigger = per_cpu_smm_trigger,
.relocation_handler = smm_relocation_handler,
Expand All @@ -98,6 +112,8 @@ static const struct mp_ops mp_ops = {

void bsp_init_and_start_aps(struct bus *cpu_bus)
{
microcode_patch = intel_microcode_find();

if (mp_init_with_smm(cpu_bus, &mp_ops))
printk(BIOS_ERR, "MP initialization failure.\n");
}
1 change: 1 addition & 0 deletions src/cpu/intel/model_2065x/Makefile.inc
View file
Expand Up @@ -12,6 +12,7 @@ subdirs-y += ../common

ramstage-y += tsc_freq.c
romstage-y += tsc_freq.c
postcar-y += tsc_freq.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c

ramstage-y += acpi.c
Expand Down
12 changes: 6 additions & 6 deletions src/cpu/intel/model_2065x/model_2065x_init.c
View file
Expand Up @@ -49,7 +49,7 @@ static acpi_cstate_t cstate_map[] = {
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
}
},
{ /* 2: C1E */
Expand All @@ -60,7 +60,7 @@ static acpi_cstate_t cstate_map[] = {
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
}
},
{ /* 3: C3 */
Expand All @@ -71,7 +71,7 @@ static acpi_cstate_t cstate_map[] = {
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
}
},
{ /* 4: C6 */
Expand All @@ -82,7 +82,7 @@ static acpi_cstate_t cstate_map[] = {
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
}
},
{ /* 5: C7 */
Expand All @@ -93,7 +93,7 @@ static acpi_cstate_t cstate_map[] = {
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
}
},
{ /* 6: C7S */
Expand All @@ -104,7 +104,7 @@ static acpi_cstate_t cstate_map[] = {
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
}
},
{ 0 }
Expand Down
1 change: 1 addition & 0 deletions src/cpu/intel/model_206ax/Makefile.inc
View file
Expand Up @@ -19,6 +19,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += common.c

ramstage-y += tsc_freq.c
romstage-y += tsc_freq.c
postcar-y += tsc_freq.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c

smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
Expand Down
12 changes: 6 additions & 6 deletions src/cpu/intel/model_206ax/model_206ax_init.c
View file
Expand Up @@ -53,7 +53,7 @@ static acpi_cstate_t cstate_map[] = {
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
}
},
{ /* 2: C1E */
Expand All @@ -64,7 +64,7 @@ static acpi_cstate_t cstate_map[] = {
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
}
},
{ /* 3: C3 */
Expand All @@ -75,7 +75,7 @@ static acpi_cstate_t cstate_map[] = {
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
}
},
{ /* 4: C6 */
Expand All @@ -86,7 +86,7 @@ static acpi_cstate_t cstate_map[] = {
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
}
},
{ /* 5: C7 */
Expand All @@ -97,7 +97,7 @@ static acpi_cstate_t cstate_map[] = {
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
}
},
{ /* 6: C7S */
Expand All @@ -108,7 +108,7 @@ static acpi_cstate_t cstate_map[] = {
.space_id = ACPI_ADDRESS_SPACE_FIXED,
.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
}
},
{ 0 }
Expand Down
8 changes: 0 additions & 8 deletions src/cpu/intel/model_69x/Kconfig
View file

This file was deleted.

3 changes: 0 additions & 3 deletions src/cpu/intel/model_69x/Makefile.inc
View file

This file was deleted.

48 changes: 0 additions & 48 deletions src/cpu/intel/model_69x/model_69x_init.c
View file

This file was deleted.

8 changes: 0 additions & 8 deletions src/cpu/intel/model_6dx/Kconfig
View file

This file was deleted.

3 changes: 0 additions & 3 deletions src/cpu/intel/model_6dx/Makefile.inc
View file

This file was deleted.

49 changes: 0 additions & 49 deletions src/cpu/intel/model_6dx/model_6dx_init.c
View file

This file was deleted.

11 changes: 0 additions & 11 deletions src/cpu/intel/socket_BGA1284/Kconfig
View file

This file was deleted.

7 changes: 0 additions & 7 deletions src/cpu/intel/socket_BGA1284/Makefile.inc
View file

This file was deleted.

6 changes: 2 additions & 4 deletions src/cpu/intel/socket_mFCPGA478/Kconfig → src/cpu/intel/socket_m/Kconfig
View file
@@ -1,12 +1,10 @@
config CPU_INTEL_SOCKET_MFCPGA478
config CPU_INTEL_SOCKET_M
bool

if CPU_INTEL_SOCKET_MFCPGA478
if CPU_INTEL_SOCKET_M

config SOCKET_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_INTEL_MODEL_69X
select CPU_INTEL_MODEL_6DX
select CPU_INTEL_MODEL_6EX
select CPU_INTEL_MODEL_6FX
select MMX
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/intel/socket_mFCPGA478/Makefile.inc → src/cpu/intel/socket_m/Makefile.inc
View file
@@ -1,5 +1,3 @@
subdirs-y += ../model_69x
subdirs-y += ../model_6dx
subdirs-y += ../model_6ex
subdirs-y += ../model_6fx
subdirs-y += ../../x86/tsc
Expand Down
9 changes: 0 additions & 9 deletions src/cpu/intel/socket_mPGA478/Makefile.inc
View file

This file was deleted.

4 changes: 2 additions & 2 deletions src/cpu/intel/socket_mPGA478MN/Kconfig → src/cpu/intel/socket_p/Kconfig
View file
@@ -1,11 +1,11 @@
config CPU_INTEL_SOCKET_MPGA478MN
config CPU_INTEL_SOCKET_P
bool
select CPU_INTEL_MODEL_1067X
select CPU_INTEL_MODEL_6FX
select MMX
select SSE

if CPU_INTEL_SOCKET_MPGA478MN
if CPU_INTEL_SOCKET_P

config DCACHE_RAM_BASE
hex
Expand Down
0 src/cpu/intel/socket_mPGA478MN/Makefile.inc → src/cpu/intel/socket_p/Makefile.inc
View file
File renamed without changes.
2 changes: 1 addition & 1 deletion src/cpu/ti/am335x/gpio.c
View file
Expand Up @@ -12,7 +12,7 @@
* GNU General Public License for more details.
*/

#include <arch/io.h>
#include <device/mmio.h>
#include <console/console.h>
#include <cpu/ti/am335x/gpio.h>
#include <stdint.h>
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/ti/am335x/pinmux.c
View file
Expand Up @@ -15,7 +15,7 @@

#include "pinmux.h"

#include <arch/io.h>
#include <device/mmio.h>

static struct am335x_pinmux_regs *regs =
(struct am335x_pinmux_regs *)(uintptr_t)AM335X_PINMUX_REG_ADDR;
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/ti/am335x/uart.c
View file
Expand Up @@ -15,7 +15,7 @@
#include <stdlib.h>
#include <types.h>
#include <console/uart.h>
#include <arch/io.h>
#include <device/mmio.h>
#include <boot/coreboot_tables.h>
#include <cpu/ti/am335x/uart.h>

Expand Down
2 changes: 1 addition & 1 deletion src/cpu/x86/car.c
View file
Expand Up @@ -142,7 +142,7 @@ static void do_car_migrate_variables(void)

static void car_migrate_variables(int is_recovery)
{
if (!IS_ENABLED(PLATFORM_USES_FSP1_0))
if (!IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0))
do_car_migrate_variables();
}
ROMSTAGE_CBMEM_INIT_HOOK(car_migrate_variables)
1 change: 0 additions & 1 deletion src/cpu/x86/lapic/apic_timer.c
View file
Expand Up @@ -18,7 +18,6 @@
#include <console/console.h>
#include <delay.h>
#include <thread.h>
#include <arch/io.h>
#include <arch/cpu.h>
#include <arch/early_variables.h>
#include <cpu/intel/fsb.h>
Expand Down
3 changes: 2 additions & 1 deletion src/cpu/x86/mtrr/mtrr.c
View file
Expand Up @@ -33,9 +33,9 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/lapic.h>
#include <arch/acpi.h>
#include <memrange.h>
#include <cpu/amd/mtrr.h>
#include <assert.h>
#if IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS)
#define MTRR_FIXED_WRBACK_BITS (MTRR_READ_MEM | MTRR_WRITE_MEM)
#else
Expand Down Expand Up @@ -331,6 +331,7 @@ static void commit_fixed_mtrrs(void)

desc = &fixed_mtrr_desc[i];
num_ranges = (desc->end - desc->begin) / desc->step;
ASSERT(num_ranges > 0);
for (j = 0; j < num_ranges; j += RANGES_PER_FIXED_MTRR) {
msr_index[msr_num] = desc->msr_index_base +
(j / RANGES_PER_FIXED_MTRR);
Expand Down
4 changes: 2 additions & 2 deletions src/cpu/x86/pae/pgtbl.c
View file
Expand Up @@ -239,12 +239,12 @@ int paging_enable_for_car(const char *pdpt_name, const char *pt_name)
if (!ENV_CACHE_AS_RAM)
return -1;

if (read_from_cbfs(pdpt_name, _pdpt, _pdpt_size)) {
if (read_from_cbfs(pdpt_name, _pdpt, REGION_SIZE(pdpt))) {
printk(BIOS_ERR, "Couldn't load pdpt\n");
return -1;
}

if (read_from_cbfs(pt_name, _pagetables, _pagetables_size)) {
if (read_from_cbfs(pt_name, _pagetables, REGION_SIZE(pagetables))) {
printk(BIOS_ERR, "Couldn't load page tables\n");
return -1;
}
Expand Down
1 change: 1 addition & 0 deletions src/cpu/x86/smm/smihandler.c
View file
Expand Up @@ -168,6 +168,7 @@ void smi_handler(u32 smm_revision)
smm_save_state(smm_base,
SMM_EM64T101_ARCH_OFFSET, node);
break;
case 0x00020064:
case 0x00030064:
state_save.type = AMD64;
state_save.amd64_state_save =
Expand Down
20 changes: 18 additions & 2 deletions src/device/Kconfig
View file
Expand Up @@ -265,7 +265,7 @@ if FRAMEBUFFER_SET_VESA_MODE

choice
prompt "framebuffer graphics resolution"
default FRAMEBUFFER_VESA_MODE_117
default FRAMEBUFFER_VESA_MODE_118
help
This option sets the resolution used for the coreboot framebuffer (and
bootsplash screen).
Expand Down Expand Up @@ -391,7 +391,7 @@ config FRAMEBUFFER_VESA_MODE
default 0x119 if FRAMEBUFFER_VESA_MODE_119
default 0x11A if FRAMEBUFFER_VESA_MODE_11A
default 0x11B if FRAMEBUFFER_VESA_MODE_11B
default 0x117 if FRAMEBUFFER_VESA_MODE_USER
default 0x118 if FRAMEBUFFER_VESA_MODE_USER

config BOOTSPLASH
prompt "Show graphical bootsplash"
Expand Down Expand Up @@ -445,6 +445,22 @@ config LINEAR_FRAMEBUFFER
def_bool y
depends on VBE_LINEAR_FRAMEBUFFER || GENERIC_LINEAR_FRAMEBUFFER

config LINEAR_FRAMEBUFFER_MAX_WIDTH
int "Maximum width in pixels"
depends on LINEAR_FRAMEBUFFER && MAINBOARD_USE_LIBGFXINIT
default 2560
help
Set the maximum width of the framebuffer. This may help with
default fonts too tiny for high-resolution displays.

config LINEAR_FRAMEBUFFER_MAX_HEIGHT
int "Maximum height in pixels"
depends on LINEAR_FRAMEBUFFER && MAINBOARD_USE_LIBGFXINIT
default 1600
help
Set the maximum height of the framebuffer. This may help with
default fonts too tiny for high-resolution displays.

endmenu # "Display"

config SMBUS_HAS_AUX_CHANNELS
Expand Down
31 changes: 16 additions & 15 deletions src/device/Makefile.inc
View file
Expand Up @@ -2,19 +2,9 @@ ramstage-y += device.c
ramstage-y += root_device.c
ramstage-y += cpu_device.c
ramstage-y += device_util.c
ramstage-$(CONFIG_PCI) += pci_class.c
ramstage-$(CONFIG_PCI) += pci_device.c
ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c
ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c
ramstage-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c
ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c
ramstage-$(CONFIG_AZALIA_PLUGIN_SUPPORT) += azalia_device.c
ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += pnp_device.c
ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_64) += pnp_device.c
ramstage-$(CONFIG_PCI) += pci_ops.c
ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c
ramstage-$(CONFIG_PCI) += pci_early.c
ramstage-$(CONFIG_PCI) += pci_rom.c
ramstage-y += smbus_ops.c

ifeq ($(CONFIG_AZALIA_PLUGIN_SUPPORT),y)
Expand All @@ -28,11 +18,22 @@ verstage-y += device_const.c
romstage-y += device_const.c
ramstage-y += device_const.c

ifeq ($(CONFIG_ARCH_X86),y)
bootblock-$(CONFIG_PCI) += pci_early.c
verstage-$(CONFIG_PCI) += pci_early.c
romstage-$(CONFIG_PCI) += pci_early.c
postcar-$(CONFIG_PCI) += pci_early.c
ifeq ($(CONFIG_PCI),y)
bootblock-y += pci_early.c
verstage-y += pci_early.c
romstage-y += pci_early.c
postcar-y += pci_early.c

ramstage-y += pci_class.c
ramstage-y += pci_device.c
ramstage-y += pci_ops.c
ramstage-y += pci_rom.c

ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c
ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c
ramstage-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c
ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c
ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c
endif

subdirs-y += oprom dram
Expand Down
2 changes: 1 addition & 1 deletion src/device/azalia_device.c
View file
Expand Up @@ -18,7 +18,7 @@
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/azalia_device.h>
#include <arch/io.h>
#include <device/mmio.h>
#include <delay.h>

#define HDA_ICII_REG 0x68
Expand Down
1 change: 1 addition & 0 deletions src/device/cardbus_device.c
View file
Expand Up @@ -18,6 +18,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <device/cardbus.h>

Expand Down
1 change: 0 additions & 1 deletion src/device/device.c
View file
Expand Up @@ -39,7 +39,6 @@
*/

#include <console/console.h>
#include <arch/io.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
Expand Down
1 change: 1 addition & 0 deletions src/device/hypertransport.c
View file
Expand Up @@ -24,6 +24,7 @@
#include <device/device.h>
#include <device/path.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <device/hypertransport.h>

Expand Down
2 changes: 1 addition & 1 deletion src/device/oprom/realmode/x86.c
View file
Expand Up @@ -14,7 +14,7 @@
* GNU General Public License for more details.
*/

#include <arch/io.h>
#include <device/mmio.h>
#include <arch/interrupt.h>
#include <arch/registers.h>
#include <boot/coreboot_tables.h>
Expand Down
1 change: 0 additions & 1 deletion src/device/oprom/realmode/x86_interrupts.c
View file
Expand Up @@ -15,7 +15,6 @@
* GNU General Public License for more details.
*/

#include <arch/io.h>
#include <arch/registers.h>
#include <console/console.h>
#include <device/pci.h>
Expand Down
1 change: 1 addition & 0 deletions src/device/pci_class.c
View file
Expand Up @@ -16,6 +16,7 @@

#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pciexp.h>
#include <device/pci_ids.h>
#include <stdlib.h>
Expand Down
7 changes: 6 additions & 1 deletion src/device/pci_device.c
View file
Expand Up @@ -32,7 +32,7 @@
*/

#include <arch/acpi.h>
#include <arch/io.h>
#include <device/pci_ops.h>
#include <bootmode.h>
#include <console/console.h>
#include <stdlib.h>
Expand Down Expand Up @@ -693,6 +693,11 @@ void pci_dev_enable_resources(struct device *dev)
pci_write_config16(dev, PCI_COMMAND, command);
}

void __noreturn pcidev_die(void)
{
die("PCI: dev is NULL!\n");
}

void pci_bus_enable_resources(struct device *dev)
{
u16 ctrl;
Expand Down
39 changes: 33 additions & 6 deletions src/device/pci_early.c
View file
Expand Up @@ -15,12 +15,12 @@

#define __SIMPLE_DEVICE__

#include <arch/io.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <device/pci_type.h>
#include <delay.h>

#if !ENV_RAMSTAGE
unsigned pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last)
{
unsigned pos = 0;
Expand Down Expand Up @@ -68,9 +68,6 @@ unsigned pci_find_capability(pci_devfn_t dev, unsigned cap)
{
return pci_find_next_capability(dev, cap, 0);
}
#endif

#if IS_ENABLED(CONFIG_EARLY_PCI_BRIDGE)

static void pci_bridge_reset_secondary(pci_devfn_t p2p_bridge)
{
Expand Down Expand Up @@ -167,4 +164,34 @@ void pci_early_bridge_init(void)

pci_early_mmio_window(p2p_bridge, CONFIG_EARLY_PCI_MMIO_BASE, 0x4000);
}
#endif /* CONFIG_EARLY_PCI_BRIDGE */

/* FIXME: A lot of issues using the following, please avoid.
* Assumes 256 PCI busses, scans them all even when PCI bridges are still
* disabled. Probes all functions even if 0 is not present.
*/
pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev)
{
for (; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0, 0, 1)) {
unsigned int id;
id = pci_read_config32(dev, 0);
if (id == pci_id)
return dev;
}
return PCI_DEV_INVALID;
}

pci_devfn_t pci_locate_device_on_bus(unsigned int pci_id, unsigned int bus)
{
pci_devfn_t dev, last;

dev = PCI_DEV(bus, 0, 0);
last = PCI_DEV(bus, 31, 7);

for (; dev <= last; dev += PCI_DEV(0, 0, 1)) {
unsigned int id;
id = pci_read_config32(dev, 0);
if (id == pci_id)
return dev;
}
return PCI_DEV_INVALID;
}
98 changes: 0 additions & 98 deletions src/device/pci_ops.c
View file
@@ -1,10 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2004 Linux Networx
* (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
* Copyright (C) 2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand All @@ -14,97 +10,3 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include <console/console.h>
#include <device/pci.h>
#include <device/pci_ops.h>

static const struct pci_bus_operations *pci_bus_ops(struct bus *bus, struct device *dev)
{
const struct pci_bus_operations *bops;
bops = NULL;
if (bus && bus->dev && bus->dev->ops && bus->dev->ops->ops_pci_bus) {
bops = bus->dev->ops->ops_pci_bus(dev);
}
if (!bops)
bops = pci_bus_default_ops(dev);
return bops;
}

/*
* The only consumer of the return value of get_pbus() is pci_bus_ops().
* pci_bus_ops() can handle being passed NULL and auto-picks working ops.
*/
static struct bus *get_pbus(struct device *dev)
{
struct bus *pbus = NULL;

if (!dev)
die("get_pbus: dev is NULL!\n");
else
pbus = dev->bus;

while (pbus && pbus->dev && !pci_bus_ops(pbus, dev)) {
if (pbus == pbus->dev->bus) {
printk(BIOS_ALERT, "%s in endless loop looking for a "
"parent bus with pci_bus_ops for %s, breaking "
"out.\n", __func__, dev_path(dev));
break;
}
pbus = pbus->dev->bus;
}

if (!pbus || !pbus->dev || !pbus->dev->ops
|| !pbus->dev->ops->ops_pci_bus) {
/* This can happen before the device tree is fully set up. */

// printk(BIOS_EMERG, "%s: Cannot find PCI bus operations.\n",
// dev_path(dev));

pbus = NULL;
}

return pbus;
}

u8 pci_read_config8(struct device *dev, unsigned int where)
{
struct bus *pbus = get_pbus(dev);
return pci_bus_ops(pbus, dev)->read8(pbus, dev->bus->secondary,
dev->path.pci.devfn, where);
}

u16 pci_read_config16(struct device *dev, unsigned int where)
{
struct bus *pbus = get_pbus(dev);
return pci_bus_ops(pbus, dev)->read16(pbus, dev->bus->secondary,
dev->path.pci.devfn, where);
}

u32 pci_read_config32(struct device *dev, unsigned int where)
{
struct bus *pbus = get_pbus(dev);
return pci_bus_ops(pbus, dev)->read32(pbus, dev->bus->secondary,
dev->path.pci.devfn, where);
}

void pci_write_config8(struct device *dev, unsigned int where, u8 val)
{
struct bus *pbus = get_pbus(dev);
pci_bus_ops(pbus, dev)->write8(pbus, dev->bus->secondary,
dev->path.pci.devfn, where, val);
}

void pci_write_config16(struct device *dev, unsigned int where, u16 val)
{
struct bus *pbus = get_pbus(dev);
pci_bus_ops(pbus, dev)->write16(pbus, dev->bus->secondary,
dev->path.pci.devfn, where, val);
}

void pci_write_config32(struct device *dev, unsigned int where, u32 val)
{
struct bus *pbus = get_pbus(dev);
pci_bus_ops(pbus, dev)->write32(pbus, dev->bus->secondary,
dev->path.pci.devfn, where, val);
}
45 changes: 21 additions & 24 deletions src/device/pci_ops_mmconf.c
View file
Expand Up @@ -11,7 +11,7 @@
* GNU General Public License for more details.
*/

#include <arch/io.h>
#include <device/mmio.h>
#include <device/pci.h>
#include <device/pci_ops.h>

Expand All @@ -23,46 +23,43 @@
* Functions for accessing PCI configuration space with mmconf accesses
*/

#define PCI_MMIO_ADDR(SEGBUS, DEVFN, WHERE, MASK) \
#define PCI_MMIO_ADDR(dev, where, mask) \
((void *)(((uintptr_t)CONFIG_MMCONF_BASE_ADDRESS |\
(((SEGBUS) & 0xFFF) << 20) |\
(((DEVFN) & 0xFF) << 12) |\
((WHERE) & 0xFFF)) & ~MASK))
(((dev)->bus->secondary & 0xFFF) << 20) |\
(((dev)->path.pci.devfn & 0xFF) << 12) |\
((where) & 0xFFF)) & ~mask))

static uint8_t pci_mmconf_read_config8(struct bus *pbus, int bus, int devfn,
int where)
static uint8_t pci_mmconf_read_config8(struct device *dev, int where)
{
return read8(PCI_MMIO_ADDR(bus, devfn, where, 0));
return read8(PCI_MMIO_ADDR(dev, where, 0));
}

static uint16_t pci_mmconf_read_config16(struct bus *pbus, int bus, int devfn,
int where)
static uint16_t pci_mmconf_read_config16(struct device *dev, int where)
{
return read16(PCI_MMIO_ADDR(bus, devfn, where, 1));
return read16(PCI_MMIO_ADDR(dev, where, 1));
}

static uint32_t pci_mmconf_read_config32(struct bus *pbus, int bus, int devfn,
int where)
static uint32_t pci_mmconf_read_config32(struct device *dev, int where)
{
return read32(PCI_MMIO_ADDR(bus, devfn, where, 3));
return read32(PCI_MMIO_ADDR(dev, where, 3));
}

static void pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn,
int where, uint8_t value)
static void pci_mmconf_write_config8(struct device *dev, int where,
uint8_t value)
{
write8(PCI_MMIO_ADDR(bus, devfn, where, 0), value);
write8(PCI_MMIO_ADDR(dev, where, 0), value);
}

static void pci_mmconf_write_config16(struct bus *pbus, int bus, int devfn,
int where, uint16_t value)
static void pci_mmconf_write_config16(struct device *dev, int where,
uint16_t value)
{
write16(PCI_MMIO_ADDR(bus, devfn, where, 1), value);
write16(PCI_MMIO_ADDR(dev, where, 1), value);
}

static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn,
int where, uint32_t value)
static void pci_mmconf_write_config32(struct device *dev, int where,
uint32_t value)
{
write32(PCI_MMIO_ADDR(bus, devfn, where, 3), value);
write32(PCI_MMIO_ADDR(dev, where, 3), value);
}

static const struct pci_bus_operations pci_ops_mmconf = {
Expand All @@ -74,7 +71,7 @@ static const struct pci_bus_operations pci_ops_mmconf = {
.write32 = pci_mmconf_write_config32,
};

const struct pci_bus_operations *pci_bus_default_ops(struct device *dev)
const struct pci_bus_operations *pci_bus_default_ops(void)
{
return &pci_ops_mmconf;
}
1 change: 1 addition & 0 deletions src/device/pcix_device.c
View file
Expand Up @@ -17,6 +17,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pcix.h>

static void pcix_tune_dev(struct device *dev)
Expand Down
1 change: 1 addition & 0 deletions src/drivers/aspeed/common/aspeed_coreboot.h
View file
Expand Up @@ -22,6 +22,7 @@
#include <stdint.h>
#include <string.h>
#include <arch/io.h>
#include <device/mmio.h>

#include <console/console.h>
#include <device/device.h>
Expand Down
1 change: 1 addition & 0 deletions src/drivers/dec/21143/21143.c
View file
Expand Up @@ -17,6 +17,7 @@
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <console/console.h>

Expand Down
1 change: 0 additions & 1 deletion src/drivers/elog/gsmi.c
View file
Expand Up @@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/

#include <arch/io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <elog.h>
Expand Down
1 change: 0 additions & 1 deletion src/drivers/emulation/qemu/cirrus.c
View file
Expand Up @@ -19,7 +19,6 @@
#include <edid.h>
#include <stdlib.h>
#include <string.h>
#include <arch/io.h>

#include <boot/coreboot_tables.h>
#include <console/console.h>
Expand Down
1 change: 1 addition & 0 deletions src/drivers/generic/bayhub/bh720.c
View file
Expand Up @@ -19,6 +19,7 @@
#include <device/device.h>
#include <device/path.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "chip.h"
#include "bh720.h"
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/generic/gpio_keys/chip.h
View file
Expand Up @@ -50,8 +50,6 @@ struct key_info {
uint32_t linux_input_type;
/* Descriptive name of the key */
const char *label;
/* Can this key wake-up the system? */
bool is_wakeup_source;
/* Wake GPE */
unsigned int wake;
/* Trigger for Wakeup Event Action as defined in EV_ACT_* enum */
Expand Down
4 changes: 1 addition & 3 deletions src/drivers/generic/gpio_keys/gpio_keys.c
View file
Expand Up @@ -40,10 +40,8 @@ static struct acpi_dp *gpio_keys_add_child_node(
key->linux_input_type);
if (key->label)
acpi_dp_add_string(dsd, "label", key->label);
if (key->is_wakeup_source)
acpi_dp_add_integer(dsd, "wakeup-source",
key->is_wakeup_source);
if (key->wake) {
acpi_dp_add_integer(dsd, "wakeup-source", 1);
acpigen_write_PRW(key->wake, 3);
acpi_dp_add_integer(dsd, "wakeup-event-action",
key->wakeup_event_action);
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/gic/gic.c
View file
Expand Up @@ -13,7 +13,7 @@
* GNU General Public License for more details.
*/

#include <arch/io.h>
#include <device/mmio.h>
#include <console/console.h>
#include <gic.h>
#include <stddef.h>
Expand Down
1 change: 0 additions & 1 deletion src/drivers/i2c/at24rf08c/at24rf08c.c
View file
Expand Up @@ -15,7 +15,6 @@

#include <types.h>
#include <string.h>
#include <arch/io.h>
#include <device/device.h>
#include <device/smbus.h>
#include <smbios.h>
Expand Down
1 change: 0 additions & 1 deletion src/drivers/i2c/at24rf08c/lenovo_serials.c
View file
Expand Up @@ -15,7 +15,6 @@

#include <types.h>
#include <string.h>
#include <arch/io.h>
#include <device/device.h>
#include <device/smbus.h>
#include <smbios.h>
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/i2c/designware/dw_i2c.c
View file
Expand Up @@ -16,7 +16,7 @@
*/

#include <arch/acpigen.h>
#include <arch/io.h>
#include <device/mmio.h>
#include <console/console.h>
#include <device/device.h>
#include <device/i2c_bus.h>
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/i2c/max98373/max98373.c
View file
Expand Up @@ -34,7 +34,7 @@ static void max98373_fill_ssdt(struct device *dev)
struct acpi_i2c i2c = {
.address = dev->path.i2c.device,
.mode_10bit = dev->path.i2c.mode_10bit,
.speed = config->bus_speed ? : I2C_SPEED_STANDARD,
.speed = config->bus_speed ? : I2C_SPEED_FAST,
.resource = scope,
};
struct acpi_dp *dp;
Expand Down
11 changes: 0 additions & 11 deletions src/drivers/intel/fsp1_0/Kconfig
View file
Expand Up @@ -34,17 +34,6 @@ config DCACHE_RAM_SIZE
hex
default 0x4000

config FSP_1_0_DEBUG_LEVEL
int "FSP debug level (0-3)"
default 0
range 0 3
help
Select the debug level, where:
0: DISABLED
1: MINIMUM
2: NORMAL
3: MAXIMUM

config FSP_HEADER_PATH
string "Location of FSP headers"
help
Expand Down
1 change: 0 additions & 1 deletion src/drivers/intel/fsp1_1/romstage.c
View file
Expand Up @@ -17,7 +17,6 @@

#include <stddef.h>
#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/cbfs.h>
#include <arch/early_variables.h>
#include <assert.h>
Expand Down
3 changes: 2 additions & 1 deletion src/drivers/intel/fsp2_0/Kconfig
View file
Expand Up @@ -85,7 +85,8 @@ config FSP_USE_REPO
bool "Use the IntelFSP based binaries"
depends on ADD_FSP_BINARIES
depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \
SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE
SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || \
SOC_INTEL_WHISKEYLAKE
help
When selecting this option, the SoC must set FSP_HEADER_PATH
and FSP_FD_PATH correctly so FSP splitting works.
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/intel/fsp2_0/hand_off_block.c
View file
Expand Up @@ -11,7 +11,7 @@
*/

#include <arch/early_variables.h>
#include <arch/io.h>
#include <device/mmio.h>
#include <cbmem.h>
#include <commonlib/helpers.h>
#include <console/console.h>
Expand Down
5 changes: 5 additions & 0 deletions src/drivers/intel/fsp2_0/include/fsp/api.h
View file
Expand Up @@ -19,6 +19,11 @@
#include <soc/intel/common/mma.h>

#define FSP_SUCCESS EFI_SUCCESS
#define FSP_INVALID_PARAMETER EFI_INVALID_PARAMETER
#define FSP_DEVICE_ERROR EFI_DEVICE_ERROR
#define FSP_NOT_FOUND EFI_NOT_FOUND
#define FSP_NOT_STARTED EFI_NOT_STARTED
#define FSP_UNSUPPORTED EFI_UNSUPPORTED

enum fsp_boot_mode {
FSP_BOOT_WITH_FULL_CONFIGURATION = 0x00,
Expand Down
3 changes: 1 addition & 2 deletions src/drivers/intel/fsp2_0/memory_init.c
View file
Expand Up @@ -12,7 +12,6 @@
*/

#include <security/vboot/antirollback.h>
#include <arch/io.h>
#include <arch/symbols.h>
#include <assert.h>
#include <cbfs.h>
Expand Down Expand Up @@ -398,7 +397,7 @@ void fsp_memory_init(bool s3wake)
memranges_init_empty(&memmap, &freeranges[0], ARRAY_SIZE(freeranges));
memranges_insert(&memmap, (uintptr_t)_car_region_start,
_car_relocatable_data_end - _car_region_start, 0);
memranges_insert(&memmap, (uintptr_t)_program, _program_size, 0);
memranges_insert(&memmap, (uintptr_t)_program, REGION_SIZE(program), 0);

if (!IS_ENABLED(CONFIG_FSP_M_XIP))
status = load_fspm_mem(&hdr, &file_data, &memmap);
Expand Down
1 change: 0 additions & 1 deletion src/drivers/intel/fsp2_0/temp_ram_exit.c
View file
Expand Up @@ -9,7 +9,6 @@
* (at your option) any later version.
*/

#include <arch/io.h>
#include <arch/cpu.h>
#include <console/console.h>
#include <fsp/api.h>
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/intel/fsp2_0/util.c
View file
Expand Up @@ -11,7 +11,7 @@
* (at your option) any later version.
*/

#include <arch/io.h>
#include <device/mmio.h>
#include <cf9_reset.h>
#include <console/console.h>
#include <fsp/util.h>
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/intel/gma/edid.c
View file
Expand Up @@ -15,7 +15,7 @@
* GNU General Public License for more details.
*/

#include <arch/io.h>
#include <device/mmio.h>
#include <console/console.h>
#include <delay.h>

Expand Down
8 changes: 6 additions & 2 deletions src/drivers/intel/gma/hires_fb/gma.adb
View file
@@ -1,3 +1,7 @@
with CB.Config;

use CB;

with HW.GFX;
with HW.GFX.Framebuffer_Filler;
with HW.GFX.GMA;
Expand Down Expand Up @@ -60,8 +64,8 @@ is

success : boolean;

min_h : pos32 := pos32'last;
min_v : pos32 := pos32'last;
min_h : pos32 := Config.LINEAR_FRAMEBUFFER_MAX_WIDTH;
min_v : pos32 := Config.LINEAR_FRAMEBUFFER_MAX_HEIGHT;
begin
lightup_ok := 0;

Expand Down
1 change: 0 additions & 1 deletion src/drivers/intel/gma/intel_ddi.c
View file
Expand Up @@ -34,7 +34,6 @@
#include <console/console.h>
#include <delay.h>
#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
#include <smbios.h>
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/intel/gma/vbt.c
View file
Expand Up @@ -15,7 +15,7 @@
* GNU General Public License for more details.
*/

#include <arch/io.h>
#include <device/pci_ops.h>
#include <delay.h>
#include <device/device.h>
#include <string.h>
Expand Down
5 changes: 5 additions & 0 deletions src/drivers/intel/ish/Kconfig
View file
@@ -0,0 +1,5 @@
config DRIVERS_INTEL_ISH
bool
help
When enabled, chip driver/intel/ish will publish information to the
SSDT _DSD table for the ISH device.
1 change: 1 addition & 0 deletions src/drivers/intel/ish/Makefile.inc
View file
@@ -0,0 +1 @@
ramstage-$(CONFIG_DRIVERS_INTEL_ISH) += ish.c
11 changes: 9 additions & 2 deletions .../delan/include/variant/acpi/mainboard.asl → src/drivers/intel/ish/chip.h
View file
@@ -1,6 +1,8 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2019 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand All @@ -11,5 +13,10 @@
* GNU General Public License for more details.
*/

#include <baseboard/acpi/mainboard.asl>
#include <baseboard/acpi/audio.asl>
/*
* Intel Integrated Sensor Hub (ISH)
*/
struct drivers_intel_ish_config {
/* Firmware name used by kernel for loading ISH firmware */
const char *firmware_name;
};
81 changes: 81 additions & 0 deletions src/drivers/intel/ish/ish.c
View file
@@ -0,0 +1,81 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2019 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include <arch/acpi_device.h>
#include <arch/acpigen.h>
#include <console/console.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include "chip.h"

static void ish_fill_ssdt_generator(struct device *dev)
{
struct drivers_intel_ish_config *config = dev->chip_info;
struct device *root = dev->bus->dev;
struct acpi_dp *dsd;

if (!dev->enabled || !config || !config->firmware_name)
return;

acpigen_write_scope(acpi_device_path(root));

dsd = acpi_dp_new_table("_DSD");
acpi_dp_add_string(dsd, "firmware-name", config->firmware_name);
acpi_dp_write(dsd);

acpigen_pop_len(); /* Scope */

printk(BIOS_INFO, "%s: Set firmware-name: %s\n",
acpi_device_path(root), config->firmware_name);
}

static struct device_operations intel_ish_ops = {
.read_resources = DEVICE_NOOP,
.set_resources = DEVICE_NOOP,
.enable_resources = DEVICE_NOOP,
.acpi_fill_ssdt_generator = ish_fill_ssdt_generator,
};

static void intel_ish_enable(struct device *dev)
{
/* This dev is a generic device that is a child to the ISH PCI device */
dev->ops = &intel_ish_ops;
}

/* Copy of default_pci_ops_dev with scan_bus addition */
static const struct device_operations pci_ish_device_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = pci_dev_init,
.scan_bus = &scan_generic_bus, /* Non-default */
.ops_pci = &pci_dev_ops_pci,
};

static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_INTEL_CNL_ISHB,
0
};

static const struct pci_driver ish_intel_driver __pci_driver = {
.ops = &pci_ish_device_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.devices = pci_device_ids,
};

struct chip_operations drivers_intel_ish_ops = {
CHIP_NAME("Intel ISH Chip")
.enable_dev = intel_ish_enable,
};
27 changes: 2 additions & 25 deletions src/drivers/intel/wifi/wifi.c
View file
Expand Up @@ -20,6 +20,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <elog.h>
#include <sar.h>
Expand Down Expand Up @@ -255,34 +256,9 @@ static const char *intel_wifi_acpi_name(const struct device *dev)
}
#endif

static void pci_dev_apply_quirks(struct device *dev)
{
unsigned int cap;
uint16_t val;
struct device *root = dev->bus->dev;

switch (dev->device) {
case PCI_DEVICE_ID_TP_9260_SERIES_WIFI:
cap = pci_find_capability(root, PCI_CAP_ID_PCIE);
/* Check the LTR for root port and enable it */
if (cap) {
val = pci_read_config16(root, cap +
PCI_EXP_DEV_CAP2_OFFSET);
if (val & LTR_MECHANISM_SUPPORT) {
val = pci_read_config16(root, cap +
PCI_EXP_DEV_CTL_STS2_CAP_OFFSET);
val |= LTR_MECHANISM_EN;
pci_write_config16(root, cap +
PCI_EXP_DEV_CTL_STS2_CAP_OFFSET, val);
}
}
}
}

static void wifi_pci_dev_init(struct device *dev)
{
pci_dev_init(dev);
pci_dev_apply_quirks(dev);

if (IS_ENABLED(CONFIG_ELOG)) {
uint32_t val;
Expand Down Expand Up @@ -350,6 +326,7 @@ static const unsigned short pci_device_ids[] = {
/* Harrison Peak */
PCI_DEVICE_ID_HrP_9560_SERIES_1_WIFI,
PCI_DEVICE_ID_HrP_9560_SERIES_2_WIFI,
PCI_DEVICE_ID_HrP_9560_SERIES_3_WIFI,
0
};

Expand Down
2 changes: 1 addition & 1 deletion src/drivers/maxim/max77686/max77686.c
View file
Expand Up @@ -14,7 +14,7 @@
*/

#include <console/console.h>
#include <arch/io.h>
#include <device/mmio.h>
#include <device/i2c_simple.h>

#include "max77686.h"
Expand Down
2 changes: 2 additions & 0 deletions src/drivers/net/atl1e.c
View file
Expand Up @@ -20,11 +20,13 @@
* This driver sets the macaddress of a Atheros AR8121/AR8113/AR8114
*/

#include <device/mmio.h>
#include <device/device.h>
#include <cbfs.h>
#include <string.h>
#include <console/console.h>
#include <device/pci.h>
#include <device/pci_ops.h>

#define REG_SPI_FLASH_CTRL 0x200
#define SPI_FLASH_CTRL_EN_VPD 0x2000
Expand Down
4 changes: 2 additions & 2 deletions src/drivers/pc80/pc/keyboard.c
View file
Expand Up @@ -259,7 +259,7 @@ uint8_t pc_keyboard_init(uint8_t probe_aux)

/* Run a keyboard controller self-test */
err = kbc_self_test(probe_aux, &aux_dev_detected);
/* Ignore iterface failure as it's non-fatal. */
/* Ignore interface failure as it's non-fatal. */
if (err != CB_SUCCESS && err != CB_KBD_INTERFACE_FAILURE)
return 0;

Expand Down Expand Up @@ -370,7 +370,7 @@ void set_kbc_ps2_mode(void)

/* Run a keyboard controller self-test */
err = kbc_self_test(0, NULL);
/* Ignore iterface failure as it's non-fatal. */
/* Ignore interface failure as it's non-fatal. */
if (err != CB_SUCCESS && err != CB_KBD_INTERFACE_FAILURE)
return;

Expand Down
2 changes: 1 addition & 1 deletion src/drivers/pc80/tpm/tis.c
View file
Expand Up @@ -27,7 +27,7 @@
#include <stdlib.h>
#include <string.h>
#include <delay.h>
#include <arch/io.h>
#include <device/mmio.h>
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <arch/acpi_device.h>
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/ricoh/rce822/rce822.c
View file
Expand Up @@ -17,7 +17,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <device/pci_ops.h>
#include "chip.h"

static void rce822_enable(struct device *dev)
Expand Down
1 change: 1 addition & 0 deletions src/drivers/siemens/nc_fpga/nc_fpga.c
View file
Expand Up @@ -19,6 +19,7 @@
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <string.h>
#include <device/mmio.h>
#include <delay.h>
#include <hwilib.h>
#include <bootstate.h>
Expand Down
1 change: 0 additions & 1 deletion src/drivers/sil/3114/sil_sata.c
View file
Expand Up @@ -17,7 +17,6 @@
#include <delay.h>
#include <stdlib.h>
#include <string.h>
#include <arch/io.h>

#include <console/console.h>
#include <device/device.h>
Expand Down
11 changes: 11 additions & 0 deletions src/drivers/smmstore/Kconfig
View file
Expand Up @@ -37,4 +37,15 @@ config SMMSTORE_FILENAME
string "SMM store file name" if SMMSTORE_IN_CBFS
default "smm_store"

config SMMSTORE_SIZE
hex "size of the SMMSTORE FMAP region"
depends on !SMMSTORE_IN_CBFS
default 0x40000
help
Sets the size of the default SMMSTORE FMAP region.
If using an UEFI payload, note that UEFI specifies at least 64K.
The current implementation of SMMSTORE is append only, so until
garbage collection is implemented it is better to set this to
a rather large value.

endif
4 changes: 2 additions & 2 deletions src/drivers/spi/cbfs_spi.c
View file
Expand Up @@ -105,7 +105,7 @@ static void switch_to_postram_cache(int unused)
boot_device_init();
if (_preram_cbfs_cache != _postram_cbfs_cache)
mmap_helper_device_init(&mdev, _postram_cbfs_cache,
_postram_cbfs_cache_size);
REGION_SIZE(postram_cbfs_cache));
}
ROMSTAGE_CBMEM_INIT_HOOK(switch_to_postram_cache);

Expand All @@ -122,7 +122,7 @@ void boot_device_init(void)

spi_flash_init_done = true;

mmap_helper_device_init(&mdev, _cbfs_cache, _cbfs_cache_size);
mmap_helper_device_init(&mdev, _cbfs_cache, REGION_SIZE(cbfs_cache));
}

/* Return the CBFS boot device. */
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/spi/spi_flash.c
View file
Expand Up @@ -196,7 +196,7 @@ int spi_flash_cmd_wait_ready(const struct spi_flash *flash,
int spi_flash_cmd_erase(const struct spi_flash *flash, u32 offset, size_t len)
{
u32 start, end, erase_size;
int ret;
int ret = -1;
u8 cmd[4];

erase_size = flash->sector_size;
Expand Down
3 changes: 2 additions & 1 deletion src/drivers/uart/oxpcie.c
View file
Expand Up @@ -19,7 +19,8 @@
#include <device/pci_ids.h>
#include <console/console.h>
#include <console/uart.h>
#include <arch/io.h>
#include <device/mmio.h>
#include <device/pci_ops.h>

static void oxford_oxpcie_enable(struct device *dev)
{
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/uart/oxpcie_early.c
View file
Expand Up @@ -17,7 +17,7 @@

#include <stdint.h>
#include <stddef.h>
#include <arch/io.h>
#include <device/pci_ops.h>
#include <arch/early_variables.h>
#include <boot/coreboot_tables.h>
#include <console/uart.h>
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/uart/pl011.c
View file
Expand Up @@ -14,7 +14,7 @@
* GNU General Public License for more details.
*/

#include <arch/io.h>
#include <device/mmio.h>
#include <boot/coreboot_tables.h>
#include <console/uart.h>
#include <drivers/uart/pl011.h>
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/uart/sifive.c
View file
Expand Up @@ -13,7 +13,7 @@
* GNU General Public License for more details.
*/

#include <arch/io.h>
#include <device/mmio.h>
#include <boot/coreboot_tables.h>
#include <console/uart.h>
#include <types.h>
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/uart/uart8250mem.c
View file
Expand Up @@ -14,7 +14,7 @@
* GNU General Public License for more details.
*/

#include <arch/io.h>
#include <device/mmio.h>
#include <boot/coreboot_tables.h>
#include <console/uart.h>
#include <device/device.h>
Expand Down
1 change: 1 addition & 0 deletions src/drivers/usb/ehci_debug.c
View file
Expand Up @@ -18,6 +18,7 @@
#include <console/console.h>
#include <console/usb.h>
#include <arch/io.h>
#include <device/mmio.h>
#include <arch/symbols.h>
#include <arch/early_variables.h>
#include <string.h>
Expand Down
3 changes: 2 additions & 1 deletion src/drivers/usb/pci_ehci.c
View file
Expand Up @@ -17,7 +17,8 @@
#include <stddef.h>
#include <console/console.h>
#include <device/pci_ehci.h>
#include <arch/io.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <string.h>
Expand Down
1 change: 0 additions & 1 deletion src/drivers/xgi/common/xgi_coreboot.c
View file
Expand Up @@ -18,7 +18,6 @@
#include <delay.h>
#include <stdlib.h>
#include <string.h>
#include <arch/io.h>
#include <vbe.h>

#include <console/console.h>
Expand Down
1 change: 1 addition & 0 deletions src/drivers/xgi/common/xgi_coreboot.h
View file
Expand Up @@ -24,6 +24,7 @@
#include <stdint.h>
#include <string.h>
#include <arch/io.h>
#include <device/mmio.h>

#include <console/console.h>
#include <device/device.h>
Expand Down
1 change: 0 additions & 1 deletion src/drivers/xgi/z9s/z9s.c
View file
Expand Up @@ -15,7 +15,6 @@
#include <delay.h>
#include <stdlib.h>
#include <string.h>
#include <arch/io.h>

#include <console/console.h>
#include <device/device.h>
Expand Down
11 changes: 11 additions & 0 deletions src/ec/google/chromeec/acpi/cros_ec.asl
View file
Expand Up @@ -32,6 +32,17 @@ Device (CREC)
})
#endif

#ifdef EC_ENABLE_SYNC_IRQ_GPIO
Name (_CRS, ResourceTemplate ()
{
GpioInt (Level, ActiveLow, Exclusive, PullDefault, 0x0000,
"\\_SB.GPIO", 0x00, ResourceConsumer, ,)
{
EC_SYNC_IRQ
}
})
#endif

#ifdef EC_ENABLE_MKBP_DEVICE
Device (CKSC)
{
Expand Down
1 change: 0 additions & 1 deletion src/ec/google/chromeec/crosec_proto.c
View file
Expand Up @@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/

#include <arch/io.h>
#include <console/console.h>
#include <delay.h>
#include <stdint.h>
Expand Down
5 changes: 2 additions & 3 deletions src/ec/google/chromeec/ec.c
View file
Expand Up @@ -18,7 +18,6 @@
#include <cbmem.h>
#include <console/console.h>
#include <arch/early_variables.h>
#include <arch/io.h>
#include <assert.h>
#include <bootmode.h>
#include <bootstate.h>
Expand Down Expand Up @@ -595,7 +594,7 @@ static int cbi_get_uint32(uint32_t *id, uint32_t tag)
cmd.cmd_dev_index = 0;

rv = google_chromeec_command(&cmd);
if (rv < 0)
if (rv != 0)
return rv;
*id = r;
return 0;
Expand Down Expand Up @@ -627,7 +626,7 @@ static int cbi_get_string(char *buf, size_t bufsize, uint32_t tag)
int rv;

rv = google_chromeec_command(&cmd);
if (rv < 0)
if (rv != 0)
return rv;

/* Ensure NUL termination. */
Expand Down
6 changes: 6 additions & 0 deletions src/ec/google/chromeec/ec.h
View file
Expand Up @@ -155,6 +155,12 @@ typedef int (*crosec_io_t)(size_t req_size, size_t resp_size, void *context);
int crosec_command_proto(struct chromeec_command *cec_command,
crosec_io_t crosec_io, void *context);

/**
* Send a command to a CrOS EC
*
* @param cec_command: CrOS EC command to send
* @return 0 for success. Non-zero for error.
*/
int google_chromeec_command(struct chromeec_command *cec_command);

struct google_chromeec_event_info {
Expand Down
1 change: 0 additions & 1 deletion src/ec/google/chromeec/ec_i2c.c
View file
Expand Up @@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/

#include <arch/io.h>
#include <console/console.h>
#include <delay.h>
#include <device/i2c_simple.h>
Expand Down
20 changes: 19 additions & 1 deletion src/ec/google/wilco/acpi/ec.asl
View file
Expand Up @@ -42,11 +42,14 @@ Device (EC0)
EREG = Arg1

/* Store initial value for power status */
ECPR = R (APWR)
ECPR = R (PWSR)

/* Indicate to EC that OS is ready for queries */
W (ERDY, Arg1)

/* Indicate that the OS supports S0ix */
W (CSOS, One)

/* Tell EC to stop emulating PS/2 mouse */
W (PS2M, Zero)

Expand Down Expand Up @@ -140,13 +143,28 @@ Device (EC0)
Return (ECRW (Arg0, Arg1))
}

/*
* Tell EC that the OS is entering or exiting S0ix
*/
Method (S0IX, 1, Serialized)
{
If (Arg0) {
Printf ("EC Enter S0ix")
W (CSEX, One)
} Else {
Printf ("EC Exit S0ix")
W (CSEX, Zero)
}
}

#include "ec_dev.asl"
#include "ec_ram.asl"
#include "ac.asl"
#include "battery.asl"
#include "event.asl"
#include "lid.asl"
#include "platform.asl"
#include "vbtn.asl"
#ifdef EC_ENABLE_DPTF
#include "dptf.asl"
#endif
Expand Down
28 changes: 28 additions & 0 deletions src/ec/google/wilco/acpi/ec_dev.asl
View file
Expand Up @@ -62,3 +62,31 @@ Device (WLCO)
EndDependentFn ()
})
}

Device (WEVT)
{
Name (_HID, "GOOG000D")
Name (_UID, 1)
Name (_DDN, "Wilco EC Event Interface")

Method (_STA)
{
Return (0xB)
}

/* Get Event Buffer */
Method (QSET, 0, Serialized)
{
/* Get count of event bytes */
Local0 = R (QSEC)
Name (QBUF, Buffer (Local0) {})

/* Fill QS event buffer with Local0 bytes */
For (Local1 = 0, Local1 < Local0, Local1++) {
QBUF[Local1] = R (QSEB)
}

Printf ("QS = %o", QBUF)
Return (QBUF)
}
}
9 changes: 4 additions & 5 deletions src/ec/google/wilco/acpi/ec_ram.asl
View file
Expand Up @@ -53,6 +53,7 @@ Name (P5U1, Package () { 0x04, 0x01, RD }) /* PmSt5_BAT1_UPDATE */
Name (P6ST, Package () { 0x05, 0xff, RD }) /* PmSt6 */
Name (P6AC, Package () { 0x05, 0x08, RD }) /* PmSt6_AC_UPDATE */

Name (PWSR, Package () { 0x06, 0xff, RD }) /* POWER_SOURCE */
Name (ACEX, Package () { 0x06, 0x01, RD }) /* AC Present */
Name (BTEX, Package () { 0x06, 0x02, RD }) /* Battery Present */
Name (BTSC, Package () { 0x06, 0x04, RD }) /* Battery Status Changed */
Expand Down Expand Up @@ -115,17 +116,13 @@ Name (DRHY, Package () { 0x37, 0xff, RD }) /* DPTF: Read Hysteresis */
Name (DRTQ, Package () { 0x38, 0xff, RD }) /* DPTF: Read Trip Query */

Name (ORST, Package () { 0x39, 0xff, RD }) /* Orientation State */
Name (OTBL, Package () { 0x39, 0x02, RD }) /* Orientation: Tablet mode */
Name (OREV, Package () { 0x3a, 0xff, RD }) /* Orientation Events */
Name (OECH, Package () { 0x3a, 0x01, RD }) /* Event: Orientation */
Name (OERL, Package () { 0x3a, 0x02, RD }) /* Event: Rotation Lock */

Name (BCCY, Package () { 0x3e, 0xffff, RD }) /* BCACHE: Cycle Count */

Name (APWR, Package () { 0x47, 0xff, RD }) /* POWER: Full Status */
Name (APAC, Package () { 0x47, 0x01, RD }) /* POWER: AC */
Name (APB1, Package () { 0x47, 0x02, RD }) /* POWER: Main Battery */
Name (APC1, Package () { 0x47, 0x04, RD }) /* POWER: Main Batt Status */

/*
* EC RAM WRITE
*/
Expand All @@ -142,3 +139,5 @@ Name (DWTL, Package () { 0x35, 0xff, WR }) /* DPTF: Write Trip Low */
Name (DWTH, Package () { 0x36, 0xff, WR }) /* DPTF: Write Trip High */
Name (DWHY, Package () { 0x37, 0xff, WR }) /* DPTF: Write Hysteresis */
Name (DWTQ, Package () { 0x38, 0xff, WR }) /* DPTF: Write Trip Query */
Name (CSOS, Package () { 0xb8, 0xff, WR }) /* OS support for S0ix */
Name (CSEX, Package () { 0xb9, 0xff, WR }) /* OS enter(1)/exit(0) S0ix */
48 changes: 26 additions & 22 deletions src/ec/google/wilco/acpi/event.asl
View file
Expand Up @@ -19,17 +19,17 @@ Name (ECPR, 0)

Method (ECQP, 0, Serialized)
{
Local0 = R (APWR)
Local0 = R (PWSR)
Local1 = Local0 ^ ECPR
ECPR = Local0

If (EBIT (APAC, Local1)) {
If (EBIT (ACEX, Local1)) {
Printf ("AC Power Status Changed")
Notify (AC, 0x80)
}

If (EBIT (APB1, Local1)) {
If (EBIT (APB1, Local0)) {
If (EBIT (BTEX, Local1)) {
If (EBIT (BTEX, Local0)) {
Printf ("BAT0 Inserted")
Notify (BAT0, 0x81)
} Else {
Expand All @@ -39,7 +39,7 @@ Method (ECQP, 0, Serialized)
}
}

If (EBIT (APC1, Local1)) {
If (EBIT (BTSC, Local1)) {
Printf ("BAT0 Status Change")
Notify (BAT0, 0x80)
}
Expand Down Expand Up @@ -79,7 +79,17 @@ Method (ECQ2, 1, Serialized)

If (EBIT (E2QS, Arg0)) {
Printf ("QS EVENT")
Notify (^WLCO, 0x90)
Notify (^WEVT, 0x90)
}

If (EBIT (E2OR, Arg0)) {
If (R (OTBL)) {
Printf ("EC event indicates tablet mode")
Notify (^VBTN, ^VTBL)
} Else {
Printf ("EC event indicates laptop mode")
Notify (^VBTN, ^VLAP)
}
}
}

Expand All @@ -88,6 +98,16 @@ Method (ECQ3, 1, Serialized)
{
Printf ("EVT3: %o", Arg0)

If (EBIT (E3CP, Arg0)) {
If (R (P2PB)) {
Printf ("Power button pressed")
Notify (^VBTN, ^VPPB)
} Else {
Printf ("Power button released")
Notify (^VBTN, ^VRPB)
}
}

#ifdef EC_ENABLE_DPTF
/* Theraml Events */
If (EBIT (E3TH, Arg0)) {
Expand Down Expand Up @@ -125,19 +145,3 @@ Method (_Q66, 0, Serialized)
ECQ4 (Local0)
}
}

/* Get Event Buffer */
Method (QSET, 0, Serialized)
{
/* Get count of event bytes */
Local0 = R (QSEC)
Name (QBUF, Buffer (Local0) {})

/* Fill QS event buffer with Local0 bytes */
For (Local1 = 0, Local1 < Local0, Local1++) {
QBUF[Local1] = R (QSEB)
}

Printf ("QS = %o", QBUF)
Return (QBUF)
}
94 changes: 94 additions & 0 deletions src/ec/google/wilco/acpi/vbtn.asl
View file
@@ -0,0 +1,94 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2019 Google LLC
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

/*
* Intel Virtual Button driver compatible with the driver found in
* the Linux kernel at drivers/platform/x86/intel-vbtn.c
*
* For tablet/laptop and dock/undock events to work the board must
* select SYSTEM_TYPE_CONVERTIBLE for the SMBIOS enclosure type to
* indicate the device is a convertible.
*/

Name (FLAP, 0x40) /* Flag indicating device is in laptop mode */

/* Virtual events */
Name (VPPB, 0xc0) /* Power Button press */
Name (VRPB, 0xc1) /* Power Button release */
Name (VPSP, 0xc2) /* Special key press (LEFTMETA in Linux) */
Name (VRSP, 0xc3) /* Special key release (LEFTMETA in Linux) */
Name (VPVU, 0xc4) /* Volume Up press */
Name (VRVU, 0xc5) /* Volume Up release */
Name (VPVD, 0xc6) /* Volume Down press */
Name (VRVD, 0xc7) /* Volume Down release */
Name (VPRL, 0xc8) /* Rotate Lock press */
Name (VRRL, 0xc9) /* Rotate Lock release */
Name (VDOC, 0xca) /* Docked */
Name (VUND, 0xcb) /* Undocked */
Name (VTBL, 0xcc) /* Tablet Mode */
Name (VLAP, 0xcd) /* Laptop Mode */

Device (VBTN)
{
Name (_HID, "INT33D6")
Name (_UID, One)
Name (_DDN, "Intel Virtual Button Driver")

/*
* This method is called at driver probe time and must exist or
* the driver will not load.
*/
Method (VBDL)
{
}

/*
* This method returns flags indicating tablet and dock modes.
* It is called at driver probe time so the OS knows what the
* state of the device is at boot.
*/
Method (VGBS)
{
Local0 = Zero

/* Check EC orientation for tablet mode flag */
If (R (OTBL)) {
Printf ("EC reports tablet mode at boot")
} Else {
Printf ("EC reports laptop mode at boot")
Local0 |= ^^FLAP
}
Return (Local0)
}

Method(_STA, 0)
{
Return (0xF)
}
}

Device (VBTO)
{
Name (_HID, "INT33D3")
Name (_CID, "PNP0C60")
Name (_UID, One)
Name (_DDN, "Laptop/tablet mode indicator driver")

Method (_STA, 0)
{
Return (0xF)
}
}
3 changes: 2 additions & 1 deletion src/ec/google/wilco/bootblock.c
View file
Expand Up @@ -14,8 +14,9 @@
*/

#include <arch/io.h>
#include <endian.h>
#include <device/pnp_ops.h>
#include <device/pnp_def.h>
#include <swab.h>

#include "bootblock.h"

Expand Down
1 change: 1 addition & 0 deletions src/ec/hp/kbc1126/early_init.c
View file
Expand Up @@ -14,6 +14,7 @@
*/

#include <arch/io.h>
#include <device/pnp_ops.h>
#include <device/pnp.h>
#include "ec.h"

Expand Down
6 changes: 5 additions & 1 deletion src/ec/lenovo/h8/Kconfig
View file
Expand Up @@ -7,7 +7,7 @@ if EC_LENOVO_H8
config SEABIOS_PS2_TIMEOUT
int
depends on PAYLOAD_SEABIOS
default 3000
default 5000

config H8_BEEP_ON_DEATH
bool "Beep on fatal error"
Expand All @@ -28,6 +28,10 @@ config H8_SUPPORT_BT_ON_WIFI
Disable BDC detection and assume bluetooth is installed. Required for
bluetooth on wifi cards, as it's not possible to detect it in coreboot.

config H8_HAS_BAT_TRESHOLDS_IMPL
bool
default n

endif

config H8_DOCK_EARLY_INIT
Expand Down
4 changes: 4 additions & 0 deletions src/ec/lenovo/h8/acpi/thinkpad.asl
View file
Expand Up @@ -317,4 +317,8 @@ Device (HKEY)
Store (WWAN, \_SB.PCI0.LPCB.EC.WWEB)
}
}

#if IS_ENABLED(CONFIG_H8_HAS_BAT_TRESHOLDS_IMPL)
#include "thinkpad_bat_thresholds.asl"
#endif
}
182 changes: 182 additions & 0 deletions src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds.asl
View file
@@ -0,0 +1,182 @@
/*
* This file is part of the coreboot project.
*
* Copyright (c) 2017 Arthur Heymans <arthur@aheymans.xyz>
* Copyright (c) 2018 Evgeny Zinoviev <me@ch1p.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

/*
* This defines the battery charging thresholds setting methods tpacpi-bat can
* use. This implements what the vendor defines but is rather ugly...
*/

/* SetBatteryCharge Start/Stop Capacity Threshold
* In Parameter:
* DWORD
* Bit 7-0: Charge stop capacity (Unit:%)
* =0: Use battery default setting
* =1-99: Threshold to stop charging battery (Relative capacity)
* Bit 9-8:BatteryID
* = 0: Any battery
* = 1: Primary battery
* = 2: Secondary battery
* = Others: Reserved (0)
* Bit 31-10: Reserved (0)
* Must be Zero
*
* Out Parameter:
* DWORD
* Bit 30-0: Reserved (0)
* Bit 31: Error status
* 0 ... Success
* 1 ... Fail
*/

#define START_THRESH_ARG 0
#define STOP_THRESH_ARG 1

// Set stop threshold
Method (BCSS, 1, NotSerialized)
{
Local0 = Arg0 & 0xff // Percentage
Local1 = (Arg0 >> 8) & 0x3 // Battery ID

// Any battery
If (Local1 == 0)
{
\_SB.PCI0.LPCB.EC.BAT0.SETT(STOP_THRESH_ARG, Local0)
\_SB.PCI0.LPCB.EC.BAT1.SETT(STOP_THRESH_ARG, Local0)

Local2 = Local0 != \_SB.PCI0.LPCB.EC.BAT0.GETT(STOP_THRESH_ARG)
Local3 = Local0 != \_SB.PCI0.LPCB.EC.BAT1.GETT(STOP_THRESH_ARG)

Return ((Local2 && Local3) << 31)
}

// Battery1
If (Local1 == 1)
{
\_SB.PCI0.LPCB.EC.BAT0.SETT(STOP_THRESH_ARG, Local0)
Return ((Local0 !=
\_SB.PCI0.LPCB.EC.BAT0.GETT(STOP_THRESH_ARG)) << 31)
}

// Battery2
If (Local1 == 2)
{
\_SB.PCI0.LPCB.EC.BAT1.SETT(STOP_THRESH_ARG, Local0)
Return ((Local0 !=
\_SB.PCI0.LPCB.EC.BAT1.GETT(STOP_THRESH_ARG)) << 31)
}

Return (1 << 31) /* Should not be reached */
}

// Set start threshold
Method (BCCS, 1, NotSerialized)
{
Local0 = Arg0 & 0xff // Percentage
Local1 = (Arg0 >> 8) & 0x3 // Battery ID

// Any battery
If (Local1 == 0)
{
\_SB.PCI0.LPCB.EC.BAT0.SETT(START_THRESH_ARG, Local0)
\_SB.PCI0.LPCB.EC.BAT1.SETT(START_THRESH_ARG, Local0)

Local2 = Local0 != \_SB.PCI0.LPCB.EC.BAT0.GETT(START_THRESH_ARG)
Local3 = Local0 != \_SB.PCI0.LPCB.EC.BAT1.GETT(START_THRESH_ARG)

Return ((Local2 && Local3) << 31)
}

// Battery1
If (Local1 == 1)
{
\_SB.PCI0.LPCB.EC.BAT0.SETT(START_THRESH_ARG, Local0)
Return ((Local0 !=
\_SB.PCI0.LPCB.EC.BAT0.GETT(START_THRESH_ARG)) << 31)
}

// Battery2
If (Local1 == 2)
{
\_SB.PCI0.LPCB.EC.BAT1.SETT(START_THRESH_ARG, Local0)
Return ((Local0 !=
\_SB.PCI0.LPCB.EC.BAT1.GETT(START_THRESH_ARG)) << 31)
}

Return (1 << 31) /* Should not be reached */
}

/*
* GetBatteryCharge Start/Stop Capacity Threshold
* In Parameter:
* DWORD
* Bit 7-0:BatteryID
* Bit 31-8: Reserved (0)
* Must be Zero
*
* Out Parameter:
* DWORD
* Bit 7-0: Charge stop capacity (Unit:%)
* =0: Use battery default setting
* =1-99: Threshold to stop charging battery (Relative capacity)
* =Others: Reserved (0)
* Bit 9-8: Capability of BatteryCharge Stop Capacity Threshold
* Bit 8:Batterycharge stop capacity threshold
* (0:Not support 1:Support)
* Bit 9: Specify every battery parameter
* (0:Not support(apply parameter for all battery)
* 1:Support(apply parameter for all battery))
* Bit 30-10: Reserved (0)
* Bit 31: Error status
* 0 ... Success
* 1 ... Fail
*/

// Get stop threshold
Method (BCSG, 1, NotSerialized)
{
// Battery1
If (Arg0 == 1)
{
Return (0x300 | \_SB.PCI0.LPCB.EC.BAT0.GETT(STOP_THRESH_ARG))
}

// Battery2
If (Arg0 == 2)
{
Return (0x300 | \_SB.PCI0.LPCB.EC.BAT1.GETT(STOP_THRESH_ARG))
}

Return (1 << 31)
}

// Get start threshold
Method (BCTG, 1, NotSerialized)
{
// Battery 1
If (Arg0 == 1)
{
Return (0x300 | \_SB.PCI0.LPCB.EC.BAT0.GETT(START_THRESH_ARG))
}

// Battery 2
If (Arg0 == 2)
{
Return (0x300 | \_SB.PCI0.LPCB.EC.BAT1.GETT(START_THRESH_ARG))
}

Return (1 << 31)
}
117 changes: 117 additions & 0 deletions src/ec/lenovo/h8/acpi/thinkpad_bat_thresholds_24.asl
View file
@@ -0,0 +1,117 @@
/*
* This file is part of the coreboot project.
*
* Copyright (c) 2017 Arthur Heymans <arthur@aheymans.xyz>
* Copyright (c) 2018 Evgeny Zinoviev <me@ch1p.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/


Scope(\_SB.PCI0.LPCB.EC)
{
Field (ERAM, ByteAcc, NoLock, Preserve)
{
Offset (0x03),
, 2,
BSTP, 1, /* Battery start/stop threshold */
Offset (0x24),
TSH0, 8, /* Battery0 threshold */
Offset (0x25),
TSH1, 8, /* Battery1 threshold */
}
}

Scope(\_SB.PCI0.LPCB.EC.BAT0)
{
/*
* Set threshold on battery0,
*
* Arg0: 0: Start threshold
* 1: Stop threshold
* Arg1: Percentage
*/
Method (SETT, 2, NotSerialized)
{
if (Arg0 <= 1 && Arg1 <= 100)
{
BSTP = Arg0
#if defined(H8_BAT_THRESHOLDS_BIT7)
TSH0 = Arg1
#else
TSH0 = Arg1 | 0x80
#endif
}
}

/**
* Get threshold on battery0
*
* Arg0: 0: Start threshold
* 1: Stop threshold
*/
Method (GETT, 1, NotSerialized)
{
if (Arg0 <= 1)
{
BSTP = Arg0
#if defined(H8_BAT_THRESHOLDS_BIT7)
Return (TSH0)
#else
Return (TSH0 & ~0x80)
#endif
}
Return (0)
}
}

Scope(\_SB.PCI0.LPCB.EC.BAT1)
{
/*
* Set threshold on battery1
*
* Arg0: 0: Start threshold
* 1: Stop threshold
* Arg1: Percentage
*/
Method (SETT, 2, NotSerialized)
{
if (Arg0 <= 1 && Arg1 <= 100)
{
BSTP = Arg0
#if defined(H8_BAT_THRESHOLDS_BIT7)
TSH1 = Arg1
#else
TSH1 = Arg1 | 0x80
#endif
}
}

/**
* Get threshold on battery1
*
* Arg0: 0: Start threshold
* 1: Stop threshold
*/
Method (GETT, 1, NotSerialized)
{
if (Arg0 <= 1)
{
BSTP = Arg0
#if defined(H8_BAT_THRESHOLDS_BIT7)
Return (TSH1)
#else
Return (TSH1 & ~0x80)
#endif
}
Return (0)
}
}