6 changes: 5 additions & 1 deletion src/drivers/aspeed/common/ast_mode_corebootfb.c
View file
Expand Up @@ -96,7 +96,11 @@ static int ast_select_mode(struct drm_connector *connector,
ast_software_i2c_read(ast, raw);

if (decode_edid(raw, sizeof(raw), edid) != EDID_CONFORMANT) {
dev_err(dev->pdev, "Failed to decode EDID\n");
/*
* Servers often run headless, so a missing EDID is not an error.
* We still need to initialize a framebuffer for KVM, though.
*/
dev_info(dev->pdev, "Failed to decode EDID\n");
printk(BIOS_DEBUG, "Assuming VGA for KVM\n");

memset(edid, 0, sizeof(*edid));
Expand Down
27 changes: 13 additions & 14 deletions src/drivers/aspeed/common/ast_post.c
View file
Expand Up @@ -25,7 +25,6 @@ void ast_enable_mmio(struct drm_device *dev)
ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x04);
}


bool ast_is_vga_enabled(struct drm_device *dev)
{
struct ast_private *ast = dev->dev_private;
Expand Down Expand Up @@ -208,7 +207,6 @@ static int cbrscan_ast2150(struct ast_private *ast, int busw)
return 1;
}


static void cbrdlli_ast2150(struct ast_private *ast, int busw)
{
u32 dll_min[4], dll_max[4], dlli, data, passcnt;
Expand Down Expand Up @@ -239,8 +237,6 @@ static void cbrdlli_ast2150(struct ast_private *ast, int busw)
ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
}



static void ast_init_dram_reg(struct drm_device *dev)
{
struct ast_private *ast = dev->dev_private;
Expand Down Expand Up @@ -370,14 +366,20 @@ void ast_post_gpu(struct drm_device *dev)
ast_enable_mmio(dev);
ast_set_def_ext_reg(dev);

if (ast->chip == AST2500)
ast_post_chip_2500(dev);
else if (ast->chip == AST2300 || ast->chip == AST2400)
ast_post_chip_2300(dev);
else
ast_init_dram_reg(dev);
if (ast->config_mode == ast_use_p2a) {
if (ast->chip == AST2500)
ast_post_chip_2500(dev);
else if (ast->chip == AST2300 || ast->chip == AST2400)
ast_post_chip_2300(dev);
else
ast_init_dram_reg(dev);

ast_init_3rdtx(dev);
ast_init_3rdtx(dev);
} else {
if (ast->tx_chip_type != AST_TX_NONE)
/* Enable DVO */
ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80);
}
}

/* AST 2300 DRAM settings */
Expand Down Expand Up @@ -473,7 +475,6 @@ static u32 mmc_test2(struct ast_private *ast, u32 datagen, u8 test_ctl)
return data;
}


static bool mmc_test_burst(struct ast_private *ast, u32 datagen)
{
return mmc_test(ast, datagen, 0xc1);
Expand Down Expand Up @@ -1225,7 +1226,6 @@ static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
#endif


}

static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *param)
Expand All @@ -1240,7 +1240,6 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
trap_AC2 += 0x00110000;
trap_MRS = 0x00000040 | (trap << 4);


param->reg_MADJ = 0x00034C4C;
param->reg_SADJ = 0x00001800;
param->reg_DRV = 0x000000F0;
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/aspeed/common/ast_tables.h
View file
Expand Up @@ -220,7 +220,6 @@ static const struct ast_vbios_enhtable res_800x600[] = {
(SyncPP | Charx8Dot), 0xFF, 5, 0x30 },
};


static const struct ast_vbios_enhtable res_1024x768[] = {
{1344, 1024, 24, 136, 806, 768, 3, 6, VCLK65, /* 60Hz */
(SyncNN | Charx8Dot), 60, 1, 0x31 },
Expand Down Expand Up @@ -280,7 +279,6 @@ static const struct ast_vbios_enhtable res_1920x1080[] = {
AST2500PreCatchCRT), 0xFF, 1, 0x38 },
};


/* 16:10 */
static const struct ast_vbios_enhtable res_1280x800[] = {
{1440, 1280, 48, 32, 823, 800, 3, 6, VCLK71, /* 60Hz RB */
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/crb/tis.c
View file
Expand Up @@ -30,7 +30,6 @@ static const char *tis_get_dev_name(struct tpm2_info *info)
return "Unknown";
}


int tis_open(void)
{
if (tpm_is_open) {
Expand Down Expand Up @@ -79,7 +78,6 @@ int tis_init(void)
return 0;
}


int tis_sendrecv(const uint8_t *sendbuf, size_t sbuf_size, uint8_t *recvbuf, size_t *rbuf_len)
{
int len = tpm2_process_command(sendbuf, sbuf_size, recvbuf, *rbuf_len);
Expand Down
3 changes: 0 additions & 3 deletions src/drivers/crb/tpm.c
View file
Expand Up @@ -121,7 +121,6 @@ static uint8_t crb_activate_locality(void)
if (rc)
write8(CRB_REG(locality, CRB_REG_LOC_CTRL), LOC_CTRL_REQ_ACCESS);


rc = crb_wait_for_reg32(CRB_REG(locality, CRB_REG_LOC_STATE), 750, LOC_STATE_LOC_ASSIGN,
LOC_STATE_LOC_ASSIGN);
if (rc) {
Expand All @@ -137,7 +136,6 @@ static uint8_t crb_activate_locality(void)
return 0;
}


return locality;
}

Expand Down Expand Up @@ -176,7 +174,6 @@ static int crb_switch_to_ready(void)
int tpm2_init(void)
{


if (crb_probe()) {
printk(BIOS_ERR, "TPM: Probe failed.\n");
return -1;
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/crb/tpm.h
View file
Expand Up @@ -39,7 +39,6 @@
#define CRB_INTF_REG_INTF_SEL (1<<17)
#define CRB_INTF_REG_INTF_LOCK (1<<19)


/*REQUEST Register related */
#define CRB_REG_REQUEST_CMD_RDY 0x01
#define CRB_REG_REQUEST_GO_IDLE 0x02
Expand All @@ -58,7 +57,6 @@ struct tpm2_info {
uint16_t revision;
};


int tpm2_init(void);
void tpm2_get_info(struct tpm2_info *tpm2_info);
size_t tpm2_process_command(const void *tpm2_command, size_t command_size,
Expand Down
6 changes: 0 additions & 6 deletions src/drivers/elog/Kconfig
View file
Expand Up @@ -23,12 +23,6 @@ config ELOG_CBMEM
but it means that events added at runtime via the SMI handler
will not be reflected in the CBMEM copy of the log.

config ELOG_PRERAM
bool
default n
help
This option will enable event logging from the preram stage.

config ELOG_GSMI
depends on HAVE_SMI_HANDLER
bool "SMI interface to write and clear event log"
Expand Down
8 changes: 4 additions & 4 deletions src/drivers/elog/Makefile.inc
View file
@@ -1,7 +1,7 @@
bootblock-$(CONFIG_ELOG_PRERAM) += elog.c
verstage-$(CONFIG_ELOG_PRERAM) += elog.c
romstage-$(CONFIG_ELOG_PRERAM) += elog.c
postcar-$(CONFIG_ELOG_PRERAM) += elog.c
bootblock-$(CONFIG_ELOG) += elog.c
verstage-$(CONFIG_ELOG) += elog.c
romstage-$(CONFIG_ELOG) += elog.c
postcar-$(CONFIG_ELOG) += elog.c
ramstage-$(CONFIG_ELOG) += elog.c

smm-$(CONFIG_ELOG_GSMI) += elog.c gsmi.c
Expand Down
1 change: 0 additions & 1 deletion src/drivers/elog/elog.c
View file
Expand Up @@ -17,7 +17,6 @@
#include <elog.h>
#include "elog_internal.h"


#if CONFIG(ELOG_DEBUG)
#define elog_debug(STR...) printk(BIOS_DEBUG, STR)
#else
Expand Down
1 change: 0 additions & 1 deletion src/drivers/emulation/qemu/cirrus.c
View file
Expand Up @@ -299,7 +299,6 @@ static void cirrus_init_linear_fb(struct device *dev)
vga_sr_write (CIRRUS_SR_EXTENDED_MODE, sr_ext);
write_hidden_dac (hidden_dac);


struct edid edid;
edid.mode.ha = width;
edid.mode.va = height;
Expand Down
1 change: 0 additions & 1 deletion src/drivers/generic/cbfs-serial/cbfs-serial.c
View file
Expand Up @@ -5,7 +5,6 @@
#include <smbios.h>
#include <string.h>


#define MAX_SERIAL_LENGTH 0x100

const char *smbios_mainboard_serial_number(void)
Expand Down
7 changes: 7 additions & 0 deletions src/drivers/genesyslogic/gl9755/Kconfig
View file
@@ -0,0 +1,7 @@
config DRIVERS_GENESYSLOGIC_GL9755
bool "Genesys Logic GL9755"
help
GL9755 is a PCI Express Rev. 2.1 compliant card reader controller
which integrates PCI Express PHY, UHS-II PHY, memory card access
interface, regulators (3.3V-to-1.8V and 3.3V-to-1.2V) and card
power switch.
1 change: 1 addition & 0 deletions src/drivers/genesyslogic/gl9755/Makefile.inc
View file
@@ -0,0 +1 @@
ramstage-$(CONFIG_DRIVERS_GENESYSLOGIC_GL9755) += gl9755.c
47 changes: 47 additions & 0 deletions src/drivers/genesyslogic/gl9755/gl9755.c
View file
@@ -0,0 +1,47 @@
/* SPDX-License-Identifier: GPL-2.0-only */

/* Driver for Genesys Logic GL9755 */

#include <console/console.h>
#include <device/device.h>
#include <device/path.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include "gl9755.h"

static void gl9755_init(struct device *dev)
{
printk(BIOS_INFO, "GL9755: init\n");
pci_dev_init(dev);

/* Set Vendor Config to be configurable */
pci_or_config32(dev, CFG, CFG_EN);
/* Set LTR value */
pci_write_config32(dev, LTR, NO_SNOOP_SCALE|NO_SNOOP_VALUE|SNOOP_SCALE|SNOOP_VALUE);
/* Set Vendor Config to be non-configurable */
pci_and_config32(dev, CFG, ~CFG_EN);
}

static struct device_operations gl9755_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.ops_pci = &pci_dev_ops_pci,
.init = gl9755_init,
};

static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_GLI_9755,
0
};

static const struct pci_driver genesyslogic_gl9755 __pci_driver = {
.ops = &gl9755_ops,
.vendor = PCI_VENDOR_ID_GLI,
.devices = pci_device_ids,
};

struct chip_operations drivers_generic_genesyslogic_gl9755_ops = {
CHIP_NAME("Genesys Logic GL9755")
};
11 changes: 11 additions & 0 deletions src/drivers/genesyslogic/gl9755/gl9755.h
View file
@@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */

/* Definitions for Genesys Logic GL9755 */

#define CFG 0x800
#define CFG_EN 0x1
#define LTR 0x5C
#define SNOOP_VALUE 0x25
#define SNOOP_SCALE (0x3 << 10)
#define NO_SNOOP_VALUE (0x25 << 16)
#define NO_SNOOP_SCALE (0x3 << 26)
1 change: 0 additions & 1 deletion src/drivers/i2c/at24rf08c/lenovo_serials.c
View file
Expand Up @@ -113,7 +113,6 @@ void smbios_system_set_uuid(u8 *uuid)
3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11, 12, 13, 14, 15
};


if (already_read) {
memcpy(uuid, result, 16);
return;
Expand Down
1 change: 0 additions & 1 deletion src/drivers/i2c/ck505/ck505.c
View file
Expand Up @@ -31,7 +31,6 @@ static void ck505_init(struct device *dev)
nregs = MIN(MIN(dev_nregs, config->nregs == 0 ? SMBUS_BLOCK_SIZE
: config->nregs), ARRAY_SIZE(config->mask));


printk(BIOS_DEBUG, "Changing %d of the %d ck505 config bytes.\n",
nregs, dev_nregs);

Expand Down
1 change: 0 additions & 1 deletion src/drivers/i2c/designware/dw_i2c.c
View file
Expand Up @@ -698,7 +698,6 @@ static int dw_i2c_set_speed(unsigned int bus, enum i2c_speed speed,
return 0;
}


/*
* Initialize this bus controller and set the speed.
*
Expand Down
1 change: 0 additions & 1 deletion src/drivers/i2c/pca9538/chip.h
View file
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */


struct drivers_i2c_pca9538_config {
unsigned char in_out; /* Use bit as input(1) or output (0). */
unsigned char invert; /* If a bit is 1, the input will be inverted. */
Expand Down
1 change: 0 additions & 1 deletion src/drivers/i2c/ptn3460/ptn3460.c
View file
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */


#include <console/console.h>
#include <device/i2c_bus.h>
#include <types.h>
Expand Down
1 change: 0 additions & 1 deletion src/drivers/i2c/rt1011/chip.h
View file
Expand Up @@ -4,7 +4,6 @@
* Realtek RT1011 audio codec devicetree bindings
*/


struct drivers_i2c_rt1011_config {
const char *name; /* ACPI Device Name */
const char *desc; /* Device Description */
Expand Down
1 change: 0 additions & 1 deletion src/drivers/i2c/tpm/tpm.c
View file
Expand Up @@ -15,7 +15,6 @@
* Version: 2.1.1
*/


#include <commonlib/endian.h>
#include <string.h>
#include <types.h>
Expand Down
1 change: 0 additions & 1 deletion src/drivers/i2c/ww_ring/ww_ring.c
View file
Expand Up @@ -365,7 +365,6 @@ int ww_ring_display_pattern(unsigned int i2c_bus, enum display_pattern pattern)
return -1;
}


#define LP55231_I2C_BASE_ADDR 0x32

static void ww_ring_init(unsigned int i2c_bus)
Expand Down
1 change: 0 additions & 1 deletion src/drivers/intel/fsp1_1/fsp_util.c
View file
Expand Up @@ -174,7 +174,6 @@ struct fsp_runtime {
uint32_t hob_list;
} __packed;


void fsp_set_runtime(FSP_INFO_HEADER *fih, void *hob_list)
{
struct fsp_runtime *fspr;
Expand Down
1 change: 0 additions & 1 deletion src/drivers/intel/fsp1_1/include/fsp/util.h
View file
Expand Up @@ -85,7 +85,6 @@ void *get_first_hob(uint16_t type);
void *get_next_guid_hob(const EFI_GUID *guid, const void *hob_start);
void *get_first_guid_hob(const EFI_GUID *guid);


asmlinkage void chipset_teardown_car_main(void);

#endif /* FSP1_1_UTIL_H */
44 changes: 44 additions & 0 deletions src/drivers/intel/fsp2_0/Kconfig
View file
Expand Up @@ -213,6 +213,50 @@ config FSP_M_ADDR
help
The address FSP-M will be relocated to during build time

config FSP_STATUS_GLOBAL_RESET_REQUIRED_3
bool
help
FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2

config FSP_STATUS_GLOBAL_RESET_REQUIRED_4
bool
help
FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2

config FSP_STATUS_GLOBAL_RESET_REQUIRED_5
bool
help
FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2

config FSP_STATUS_GLOBAL_RESET_REQUIRED_6
bool
help
FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2

config FSP_STATUS_GLOBAL_RESET_REQUIRED_7
bool
help
FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2

config FSP_STATUS_GLOBAL_RESET_REQUIRED_8
bool
help
FSP Reset Status code used for global reset as per FSP EAS v2.0 section 11.2.2

config FSP_STATUS_GLOBAL_RESET
hex
default 0x40000003 if FSP_STATUS_GLOBAL_RESET_REQUIRED_3
default 0x40000004 if FSP_STATUS_GLOBAL_RESET_REQUIRED_4
default 0x40000005 if FSP_STATUS_GLOBAL_RESET_REQUIRED_5
default 0x40000006 if FSP_STATUS_GLOBAL_RESET_REQUIRED_6
default 0x40000007 if FSP_STATUS_GLOBAL_RESET_REQUIRED_7
default 0x40000008 if FSP_STATUS_GLOBAL_RESET_REQUIRED_8
default 0xffffffff
help
If global reset is supported by SoC then select the correct status value for global
reset type from SoC Kconfig based on available Kconfig options
FSP_STATUS_GLOBAL_RESET_REQUIRED_X. Default is unsupported.

if FSP_PEIM_TO_PEIM_INTERFACE
source "src/drivers/intel/fsp2_0/ppi/Kconfig"
endif
Expand Down
1 change: 0 additions & 1 deletion src/drivers/intel/fsp2_0/include/fsp/api.h
View file
Expand Up @@ -31,7 +31,6 @@ enum fsp_notify_phase {
END_OF_FIRMWARE = 0xF0
};


/* Main FSP stages */
void fsp_memory_init(bool s3wake);
void fsp_silicon_init(bool s3wake);
Expand Down
1 change: 0 additions & 1 deletion src/drivers/intel/fsp2_0/include/fsp/soc_binding.h
View file
Expand Up @@ -31,7 +31,6 @@
#include <FirmwareVersionInfoHob.h>
#endif


#pragma pack(pop)

#endif
239 changes: 0 additions & 239 deletions src/drivers/intel/gma/drm_dp_helper.h
View file

This file was deleted.

1 change: 0 additions & 1 deletion src/drivers/intel/gma/i915.h
View file
Expand Up @@ -4,7 +4,6 @@
#define INTEL_I915_H 1

#include <drivers/intel/gma/i915_reg.h>
#include <drivers/intel/gma/drm_dp_helper.h>
#include <drivers/intel/gma/gma.h>
#include <edid.h>

Expand Down
37 changes: 27 additions & 10 deletions src/drivers/intel/gma/i915_reg.h
View file
Expand Up @@ -27,7 +27,6 @@
#define IVB_GMCH_GMS_SHIFT 4
#define IVB_GMCH_GMS_MASK 0xf


/* PCI config space */

#define HPLLCC 0xc0 /* 855 only */
Expand Down Expand Up @@ -296,7 +295,6 @@
#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */


/*
* Reset registers
*/
Expand Down Expand Up @@ -791,7 +789,6 @@
#define ILK_FBCQ_DIS (1<<22)
#define ILK_PABSTRETCH_DIS (1<<21)


/*
* Framebuffer compression for Sandybridge
*
Expand All @@ -801,7 +798,6 @@
#define SNB_CPU_FENCE_ENABLE (1<<29)
#define DPFC_CPU_FENCE_OFFSET 0x100104


/*
* GPIO regs
*/
Expand Down Expand Up @@ -1213,7 +1209,6 @@
HSW_CXT_RENDER_SIZE(ctx_reg) + \
GEN7_CXT_VFSTATE_SIZE(ctx_reg))


/*
* Overlay regs
*/
Expand Down Expand Up @@ -1254,7 +1249,6 @@
#define _BCLRPAT_B 0x61020
#define _VSYNCSHIFT_B 0x61028


#define HTOTAL(trans) _TRANSCODER(trans, _HTOTAL_A, _HTOTAL_B)
#define HBLANK(trans) _TRANSCODER(trans, _HBLANK_A, _HBLANK_B)
#define HSYNC(trans) _TRANSCODER(trans, _HSYNC_A, _HSYNC_B)
Expand Down Expand Up @@ -1311,7 +1305,6 @@
#define ADPA_DPMS_STANDBY (2<<10)
#define ADPA_DPMS_OFF (3<<10)


/* Hotplug control (945+ only) */
#define PORT_HOTPLUG_EN 0x61110
#define HDMIB_HOTPLUG_INT_EN (1 << 29)
Expand Down Expand Up @@ -1673,6 +1666,33 @@
#define BLM_PCH_POLARITY (1 << 29)
#define BLC_PWM_PCH_CTL2 0xc8254

#define UTIL_PIN_CTL 0x48400
#define UTIL_PIN_ENABLE (1 << 31)

#define UTIL_PIN_PIPE(x) ((x) << 29)
#define UTIL_PIN_PIPE_MASK (3 << 29)
#define UTIL_PIN_MODE_PWM (1 << 24)
#define UTIL_PIN_MODE_MASK (0xf << 24)
#define UTIL_PIN_POLARITY (1 << 22)

/* BXT backlight register definition. */
#define _BXT_BLC_PWM_CTL1 0xC8250
#define BXT_BLC_PWM_ENABLE (1 << 31)
#define BXT_BLC_PWM_POLARITY (1 << 29)
#define _BXT_BLC_PWM_FREQ1 0xC8254
#define _BXT_BLC_PWM_DUTY1 0xC8258

#define _BXT_BLC_PWM_CTL2 0xC8350
#define _BXT_BLC_PWM_FREQ2 0xC8354
#define _BXT_BLC_PWM_DUTY2 0xC8358

#define BXT_BLC_PWM_CTL(controller) _PIPE(controller, \
_BXT_BLC_PWM_CTL1, _BXT_BLC_PWM_CTL2)
#define BXT_BLC_PWM_FREQ(controller) _PIPE(controller, \
_BXT_BLC_PWM_FREQ1, _BXT_BLC_PWM_FREQ2)
#define BXT_BLC_PWM_DUTY(controller) _PIPE(controller, \
_BXT_BLC_PWM_DUTY1, _BXT_BLC_PWM_DUTY2)

/* TV port control */
#define TV_CTL 0x68000
/** Enables the TV encoder */
Expand Down Expand Up @@ -2781,7 +2801,6 @@
#define _PIPEB_FRMCOUNT_GM45 0x71040
#define _PIPEB_FLIPCOUNT_GM45 0x71044


/* Display B control */
#define _DSPBCNTR 0x71180
#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
Expand Down Expand Up @@ -2984,7 +3003,6 @@
#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff


#define _PIPEA_DATA_M1 0x60030
#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
#define TU_SIZE_MASK 0x7e000000
Expand Down Expand Up @@ -3538,7 +3556,6 @@
#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
#define TRANS_CHICKEN2_TIMING_OVERRIDE (1UL<<31)


#define SOUTH_CHICKEN1 0xc2000
#define FDIA_PHASE_SYNC_SHIFT_OVR 19
#define FDIA_PHASE_SYNC_SHIFT_EN 18
Expand Down
1 change: 0 additions & 1 deletion src/drivers/intel/gma/int15.c
View file
Expand Up @@ -98,7 +98,6 @@ int intel_vga_int15_handler(void)
return res;
}


void install_intel_vga_int15_handler(int active_lfp_, int pfit_, int display_, int panel_type_)
{
active_lfp = active_lfp_;
Expand Down
1 change: 0 additions & 1 deletion src/drivers/intel/gma/int15.h
View file
Expand Up @@ -27,7 +27,6 @@ enum {
GMA_INT15_ACTIVE_LFP_EDP = 0x03,
};


#if CONFIG(VGA_ROM_RUN)
/* Install custom int15 handler for VGA OPROM */
void install_intel_vga_int15_handler(int active_lfp, int pfit, int display, int panel_type);
Expand Down
1 change: 0 additions & 1 deletion src/drivers/intel/gma/intel_bios.h
View file
Expand Up @@ -396,7 +396,6 @@ struct bdb_sdvo_lvds_options {
u8 panel_misc_bits_4;
} __packed;


#define BDB_DRIVER_FEATURE_NO_LVDS 0
#define BDB_DRIVER_FEATURE_INT_LVDS 1
#define BDB_DRIVER_FEATURE_SDVO_LVDS 2
Expand Down
1 change: 0 additions & 1 deletion src/drivers/intel/i210/i210.h
View file
Expand Up @@ -16,7 +16,6 @@
#define I210_DONE 0x02 /* command done bit */
#define I210_TARGET_CHECKSUM 0xBABA /* resulting checksum */


/*define some other useful values here */
#define I210_POLL_TIMEOUT_US 300000 /* 300 ms */
/*Define some error states here*/
Expand Down
13 changes: 9 additions & 4 deletions src/drivers/intel/mipi_camera/camera.c
View file
Expand Up @@ -452,7 +452,12 @@ static void camera_fill_sensor(const struct device *dev)
static void camera_fill_nvm(const struct device *dev)
{
struct drivers_intel_mipi_camera_config *config = dev->chip_info;
struct acpi_dp *dsd = acpi_dp_new_table("_DSD");
struct acpi_dp *dsd;

if (!config->nvm_compat)
return;

dsd = acpi_dp_new_table("_DSD");

/* It might be possible to default size or width based on type. */
if (!config->disable_nvm_defaults && !config->nvm_pagesize)
Expand All @@ -473,6 +478,7 @@ static void camera_fill_nvm(const struct device *dev)
if (config->nvm_width)
acpi_dp_add_integer(dsd, "address-width", config->nvm_width);

acpi_dp_add_string(dsd, "compatible", config->nvm_compat);
acpi_dp_write(dsd);
}

Expand Down Expand Up @@ -822,10 +828,9 @@ static void write_i2c_camera_device(const struct device *dev, const char *scope)

if (config->acpi_hid)
acpigen_write_name_string("_HID", config->acpi_hid);
else if (config->device_type == INTEL_ACPI_CAMERA_VCM)
else if (config->device_type == INTEL_ACPI_CAMERA_VCM ||
config->device_type == INTEL_ACPI_CAMERA_NVM)
acpigen_write_name_string("_HID", ACPI_DT_NAMESPACE_HID);
else if (config->device_type == INTEL_ACPI_CAMERA_NVM)
acpigen_write_name_string("_HID", "INT3499");

acpigen_write_name_integer("_UID", config->acpi_uid);
acpigen_write_name_string("_DDN", config->chip_name);
Expand Down
1 change: 1 addition & 0 deletions src/drivers/intel/mipi_camera/chip.h
View file
Expand Up @@ -241,6 +241,7 @@ struct drivers_intel_mipi_camera_config {
uint32_t nvm_pagesize;
uint32_t nvm_readonly;
uint32_t nvm_width;
const char *nvm_compat;

/* Settings specific to vcm */
const char *vcm_compat;
Expand Down
9 changes: 9 additions & 0 deletions src/drivers/ipmi/Kconfig
View file
Expand Up @@ -33,3 +33,12 @@ config BMC_KCS_BASE
help
The PNP base address of BMC KCS. It must be equal to the
pnp port value defined in devicetree for chip drivers/ipmi.

config IPMI_KCS_TIMEOUT_MS
int
default 5000
depends on IPMI_KCS
help
The time unit is millisecond for each IPMI KCS transfer.
IPMI spec v2.0 rev 1.1 Sec. 9.15, a five-second timeout or
greater is recommended.
32 changes: 13 additions & 19 deletions src/drivers/ipmi/ipmi_kcs.c
View file
Expand Up @@ -3,7 +3,7 @@
#include <console/console.h>
#include <device/device.h>
#include <arch/io.h>
#include <delay.h>
#include <timer.h>
#include "ipmi_kcs.h"

#define IPMI_KCS_STATE(_x) ((_x) >> 6)
Expand Down Expand Up @@ -35,30 +35,24 @@ static unsigned char ipmi_kcs_status(int port)

static int wait_ibf_timeout(int port)
{
int timeout = 1000;
do {
if (!(ipmi_kcs_status(port) & IPMI_KCS_IBF))
return 0;
udelay(100);
} while (timeout--);
printk(BIOS_ERR, "wait_ibf timeout!\n");
return timeout;
if (!wait_ms(CONFIG_IPMI_KCS_TIMEOUT_MS, !(ipmi_kcs_status(port) & IPMI_KCS_IBF))) {
printk(BIOS_ERR, "wait_ibf timeout!\n");
return 1;
} else {
return 0;
}
}

static int wait_obf_timeout(int port)
{
int timeout = 1000;
do {
if ((ipmi_kcs_status(port) & IPMI_KCS_OBF))
return 0;
udelay(100);
} while (timeout--);

printk(BIOS_ERR, "wait_obf timeout!\n");
return timeout;
if (!wait_ms(CONFIG_IPMI_KCS_TIMEOUT_MS, (ipmi_kcs_status(port) & IPMI_KCS_OBF))) {
printk(BIOS_ERR, "wait_obf timeout!\n");
return 1;
} else {
return 0;
}
}


static int ipmi_kcs_send_data_byte(int port, const unsigned char byte)
{
unsigned char status;
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/mrc_cache/mrc_cache.c
View file
Expand Up @@ -480,7 +480,7 @@ static int protect_mrc_cache(const char *name)
return 0;

if (lookup_region_by_name(name, &region) < 0) {
printk(BIOS_ERR, "MRC: Could not find region '%s'\n", name);
printk(BIOS_INFO, "MRC: Could not find region '%s'\n", name);
return -1;
}

Expand Down
3 changes: 0 additions & 3 deletions src/drivers/net/ne2k.c
View file
Expand Up @@ -36,7 +36,6 @@ SMC8416 PIO support added by Andrew Bettison (andrewb@zip.com.au) on 4/3/02

#include "ns8390.h"


#define ETH_ALEN 6 /* Size of Ethernet address */
#define ETH_HLEN 14 /* Size of ethernet header */
#define ETH_ZLEN 60 /* Minimum packet */
Expand All @@ -48,7 +47,6 @@ SMC8416 PIO support added by Andrew Bettison (andrewb@zip.com.au) on 4/3/02
#define TX_START 64
#define RX_START (64 + D8390_TXBUF_SIZE)


static unsigned int get_count(unsigned int eth_nic_base)
{
unsigned int ret;
Expand Down Expand Up @@ -146,7 +144,6 @@ static void str2mac(const char *str, unsigned char *mac)
} while (c != '\0');
}


static void ns8390_tx_header(unsigned int eth_nic_base, int pktlen)
{
unsigned short chksum;
Expand Down
1 change: 0 additions & 1 deletion src/drivers/pc80/pc/i8254.c
View file
Expand Up @@ -77,7 +77,6 @@ unsigned long calibrate_tsc_with_pit(void)
if (end.hi)
goto bad_ctc;


/* Error: ECPUTOOSLOW */
if (end.lo <= CALIBRATE_DIVISOR)
goto bad_ctc;
Expand Down
1 change: 0 additions & 1 deletion src/drivers/pc80/pc/isa-dma.c
View file
Expand Up @@ -32,7 +32,6 @@

#define DMA_AUTOINIT 0x10


void isa_dma_init(void)
{
/* slave at 0x00 - 0x0f */
Expand Down
4 changes: 0 additions & 4 deletions src/drivers/pc80/pc/spkmodem.c
View file
Expand Up @@ -5,7 +5,6 @@

#define SPEAKER_PIT_FREQUENCY 0x1234dd


enum {
PIT_COUNTER_0 = 0x40,
PIT_COUNTER_1 = 0x41,
Expand All @@ -14,7 +13,6 @@ enum {
PIT_SPEAKER_PORT = 0x61,
};


enum {
PIT_SPK_TMR2 = 0x01,
PIT_SPK_DATA = 0x02,
Expand Down Expand Up @@ -44,13 +42,11 @@ enum {

PIT_CTRL_HARDSTROBE = 0x0a,


PIT_CTRL_COUNT_MASK = 0x01,
PIT_CTRL_COUNT_BINARY = 0x00,
PIT_CTRL_COUNT_BCD = 0x01
};


static void
make_tone(uint16_t freq_count, unsigned int duration)
{
Expand Down
1 change: 0 additions & 1 deletion src/drivers/pc80/rtc/option.c
View file
Expand Up @@ -228,7 +228,6 @@ int cmos_lb_cks_valid(void)
return cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC);
}


void sanitize_cmos(void)
{
const unsigned char *cmos_default;
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/spi/spi_flash.c
View file
Expand Up @@ -373,7 +373,6 @@ static const struct spi_flash_part_id *find_part(const struct spi_flash_vendor_i
[1] = id[1] & vi->match_id_mask[1],
};


for (i = 0; i < vi->nr_part_ids; i++) {
const struct spi_flash_part_id *part = &vi->ids[i];

Expand Down Expand Up @@ -672,7 +671,6 @@ void lb_spi_flash(struct lb_header *header)
}
}


int spi_flash_ctrlr_protect_region(const struct spi_flash *flash,
const struct region *region,
const enum ctrlr_prot_type type)
Expand Down
1 change: 0 additions & 1 deletion src/drivers/spi/spi_sdcard.c
View file
Expand Up @@ -358,7 +358,6 @@ static int spi_sdcard_do_app_command(const struct spi_sdcard *card,
return spi_sdcard_do_command_help(card, 1, cmd, argument, out_register);
}


size_t spi_sdcard_size(const struct spi_sdcard *card)
{
int wait;
Expand Down
1 change: 0 additions & 1 deletion src/drivers/spi/tpm/tis.c
View file
Expand Up @@ -75,7 +75,6 @@ int tis_init(void)
return 0;
}


int tis_sendrecv(const uint8_t *sendbuf, size_t sbuf_size,
uint8_t *recvbuf, size_t *rbuf_len)
{
Expand Down
56 changes: 39 additions & 17 deletions src/drivers/spi/tpm/tpm.c
View file
Expand Up @@ -348,7 +348,7 @@ static int read_tpm_sts(uint32_t *status)
return tpm2_read_reg(TPM_STS_REG, status, sizeof(*status));
}

static int write_tpm_sts(uint32_t status)
static int __must_check write_tpm_sts(uint32_t status)
{
return tpm2_write_reg(TPM_STS_REG, &status, sizeof(status));
}
Expand Down Expand Up @@ -688,9 +688,9 @@ union fifo_transfer_buffer {
* Transfer requested number of bytes to or from TPM FIFO, accounting for the
* current burst count value.
*/
static void fifo_transfer(size_t transfer_size,
union fifo_transfer_buffer buffer,
enum fifo_transfer_direction direction)
static int __must_check fifo_transfer(size_t transfer_size,
union fifo_transfer_buffer buffer,
enum fifo_transfer_direction direction)
{
size_t transaction_size;
size_t burst_count;
Expand All @@ -711,18 +711,23 @@ static void fifo_transfer(size_t transfer_size,
*/
transaction_size = MIN(transaction_size, 64);

if (direction == fifo_receive)
tpm2_read_reg(TPM_DATA_FIFO_REG,
buffer.rx_buffer + handled_so_far,
transaction_size);
else
tpm2_write_reg(TPM_DATA_FIFO_REG,
buffer.tx_buffer + handled_so_far,
transaction_size);
if (direction == fifo_receive) {
if (!tpm2_read_reg(TPM_DATA_FIFO_REG,
buffer.rx_buffer + handled_so_far,
transaction_size))
return 0;
} else {
if (!tpm2_write_reg(TPM_DATA_FIFO_REG,
buffer.tx_buffer + handled_so_far,
transaction_size))
return 0;
}

handled_so_far += transaction_size;

} while (handled_so_far != transfer_size);

return 1;
}

size_t tpm2_process_command(const void *tpm2_command, size_t command_size,
Expand Down Expand Up @@ -755,7 +760,10 @@ size_t tpm2_process_command(const void *tpm2_command, size_t command_size,
}

/* Let the TPM know that the command is coming. */
write_tpm_sts(TPM_STS_COMMAND_READY);
if (!write_tpm_sts(TPM_STS_COMMAND_READY)) {
printk(BIOS_ERR, "TPM_STS_COMMAND_READY failed\n");
return 0;
}

/*
* TPM commands and responses written to and read from the FIFO
Expand All @@ -769,10 +777,17 @@ size_t tpm2_process_command(const void *tpm2_command, size_t command_size,
* burst count or the maximum PDU size, whatever is smaller.
*/
fifo_buffer.tx_buffer = cmd_body;
fifo_transfer(command_size, fifo_buffer, fifo_transmit);
if (!fifo_transfer(command_size, fifo_buffer, fifo_transmit)) {
printk(BIOS_ERR, "fifo_transfer %zd command bytes failed\n",
command_size);
return 0;
}

/* Now tell the TPM it can start processing the command. */
write_tpm_sts(TPM_STS_GO);
if (!write_tpm_sts(TPM_STS_GO)) {
printk(BIOS_ERR, "TPM_STS_GO failed\n");
return 0;
}

/* Now wait for it to report that the response is ready. */
expected_status_bits = TPM_STS_VALID | TPM_STS_DATA_AVAIL;
Expand Down Expand Up @@ -815,7 +830,11 @@ size_t tpm2_process_command(const void *tpm2_command, size_t command_size,
*/
bytes_to_go = payload_size - 1 - HEADER_SIZE;
fifo_buffer.rx_buffer = rsp_body + HEADER_SIZE;
fifo_transfer(bytes_to_go, fifo_buffer, fifo_receive);
if (!fifo_transfer(bytes_to_go, fifo_buffer, fifo_receive)) {
printk(BIOS_ERR, "fifo_transfer %zd receive bytes failed\n",
bytes_to_go);
return 0;
}

/* Verify that there is still data to read. */
read_tpm_sts(&status);
Expand All @@ -840,7 +859,10 @@ size_t tpm2_process_command(const void *tpm2_command, size_t command_size,
}

/* Move the TPM back to idle state. */
write_tpm_sts(TPM_STS_COMMAND_READY);
if (!write_tpm_sts(TPM_STS_COMMAND_READY)) {
printk(BIOS_ERR, "TPM_STS_COMMAND_READY failed\n");
return 0;
}

return payload_size;
}
Expand Down
1 change: 0 additions & 1 deletion src/drivers/spi/tpm/tpm.h
View file
Expand Up @@ -32,7 +32,6 @@ struct cr50_firmware_version {
*/
int tpm2_init(struct spi_slave *spi_if);


/*
* Each command processing consists of sending the command to the TPM, by
* writing it into the FIFO register, then polling the status register until
Expand Down
7 changes: 7 additions & 0 deletions src/drivers/ti/sn65dsi86bridge/Kconfig
View file
@@ -0,0 +1,7 @@
## SPDX-License-Identifier: GPL-2.0-only

config DRIVERS_TI_SN65DSI86BRIDGE
bool
default n
help
TI SN65DSI86 eDP bridge driver
3 changes: 3 additions & 0 deletions src/drivers/ti/sn65dsi86bridge/Makefile.inc
View file
@@ -0,0 +1,3 @@
## SPDX-License-Identifier: GPL-2.0-only

ramstage-$(CONFIG_DRIVERS_TI_SN65DSI86BRIDGE) += sn65dsi86bridge.c
514 changes: 514 additions & 0 deletions src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c
View file

Large diffs are not rendered by default.

22 changes: 22 additions & 0 deletions src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.h
View file
@@ -0,0 +1,22 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#ifndef __TI_SN65DSI86BRIDGE_H
#define __TI_SN65DSI86BRIDGE_H

#include <edid.h>

enum dp_pll_clk_src {
SN65_SEL_12MHZ = 0x0,
SN65_SEL_19MHZ = 0x1,
SN65_SEL_26MHZ = 0x2,
SN65_SEL_27MHZ = 0x3,
SN65_SEL_38MHZ = 0x4,
};

void sn65dsi86_bridge_init(uint8_t bus, uint8_t chip, enum dp_pll_clk_src ref_clk);
void sn65dsi86_bridge_configure(uint8_t bus, uint8_t chip,
struct edid *edid, uint32_t num_of_lines,
uint32_t dsi_bpp);
enum cb_err sn65dsi86_bridge_read_edid(uint8_t bus, uint8_t chip, struct edid *out);

#endif
1 change: 0 additions & 1 deletion src/drivers/uart/oxpcie.c
View file
Expand Up @@ -26,7 +26,6 @@ static void oxford_oxpcie_enable(struct device *dev)
printk(BIOS_DEBUG, "OXPCIe952: UART BAR: 0x%x\n", (u32)res->base);
}


static void oxford_oxpcie_set_resources(struct device *dev)
{
pci_dev_set_resources(dev);
Expand Down
4 changes: 2 additions & 2 deletions src/drivers/uart/oxpcie_early.c
View file
Expand Up @@ -55,9 +55,9 @@ static int oxpcie_uart_active(void)
return oxpcie_present;
}

uintptr_t uart_platform_base(int idx)
uintptr_t uart_platform_base(unsigned int idx)
{
if ((idx >= 0) && (idx < 8) && oxpcie_uart_active())
if ((idx < 8) && oxpcie_uart_active())
return uart0_base + idx * 0x200;
return 0;
}
Expand Down
8 changes: 4 additions & 4 deletions src/drivers/uart/pl011.c
View file
Expand Up @@ -5,19 +5,19 @@
#include <console/uart.h>
#include <drivers/uart/pl011.h>

void uart_init(int idx)
void uart_init(unsigned int idx)
{
}

void uart_tx_byte(int idx, unsigned char data)
void uart_tx_byte(unsigned int idx, unsigned char data)
{
struct pl011_uart *regs = uart_platform_baseptr(idx);

write8(&regs->dr, data);
uart_tx_flush(idx);
}

void uart_tx_flush(int idx)
void uart_tx_flush(unsigned int idx)
{
struct pl011_uart *regs = uart_platform_baseptr(idx);

Expand All @@ -26,7 +26,7 @@ void uart_tx_flush(int idx)
;
}

unsigned char uart_rx_byte(int idx)
unsigned char uart_rx_byte(unsigned int idx)
{
struct pl011_uart *regs = uart_platform_baseptr(idx);

Expand Down
8 changes: 4 additions & 4 deletions src/drivers/uart/sifive.c
View file
Expand Up @@ -45,7 +45,7 @@ static void sifive_uart_init(struct sifive_uart_registers *regs, int div)
write32(&regs->rxctrl, RXCTRL_RXEN|RXCTRL_RXCNT(0));
}

void uart_init(int idx)
void uart_init(unsigned int idx)
{
unsigned int div;
div = uart_baudrate_divisor(get_uart_baudrate(),
Expand All @@ -58,7 +58,7 @@ static bool uart_can_tx(struct sifive_uart_registers *regs)
return !(read32(&regs->txdata) & TXDATA_FULL);
}

void uart_tx_byte(int idx, unsigned char data)
void uart_tx_byte(unsigned int idx, unsigned char data)
{
struct sifive_uart_registers *regs = uart_platform_baseptr(idx);

Expand All @@ -68,7 +68,7 @@ void uart_tx_byte(int idx, unsigned char data)
write32(&regs->txdata, data);
}

void uart_tx_flush(int idx)
void uart_tx_flush(unsigned int idx)
{
struct sifive_uart_registers *regs = uart_platform_baseptr(idx);
uint32_t ip;
Expand All @@ -79,7 +79,7 @@ void uart_tx_flush(int idx)
} while (!(ip & IP_TXWM));
}

unsigned char uart_rx_byte(int idx)
unsigned char uart_rx_byte(unsigned int idx)
{
struct sifive_uart_registers *regs = uart_platform_baseptr(idx);
uint32_t rxdata;
Expand Down
10 changes: 5 additions & 5 deletions src/drivers/uart/uart8250io.c
View file
Expand Up @@ -85,14 +85,14 @@ static void uart8250_init(unsigned int base_port, unsigned int divisor)

static const unsigned int bases[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };

uintptr_t uart_platform_base(int idx)
uintptr_t uart_platform_base(unsigned int idx)
{
if (idx < ARRAY_SIZE(bases))
return bases[idx];
return 0;
}

void uart_init(int idx)
void uart_init(unsigned int idx)
{
if (!CONFIG(DRIVERS_UART_8250IO_SKIP_INIT)) {
unsigned int div;
Expand All @@ -107,17 +107,17 @@ void uart_init(int idx)
}
}

void uart_tx_byte(int idx, unsigned char data)
void uart_tx_byte(unsigned int idx, unsigned char data)
{
uart8250_tx_byte(uart_platform_base(port_index), data);
}

unsigned char uart_rx_byte(int idx)
unsigned char uart_rx_byte(unsigned int idx)
{
return uart8250_rx_byte(uart_platform_base(port_index));
}

void uart_tx_flush(int idx)
void uart_tx_flush(unsigned int idx)
{
uart8250_tx_flush(uart_platform_base(port_index));
}
Expand Down
8 changes: 4 additions & 4 deletions src/drivers/uart/uart8250mem.c
View file
Expand Up @@ -97,7 +97,7 @@ static void uart8250_mem_init(void *base, unsigned int divisor)
uart8250_write(base, UART8250_LCR, CONFIG_TTYS0_LCS);
}

void uart_init(int idx)
void uart_init(unsigned int idx)
{
void *base = uart_platform_baseptr(idx);
if (!base)
Expand All @@ -109,23 +109,23 @@ void uart_init(int idx)
uart8250_mem_init(base, div);
}

void uart_tx_byte(int idx, unsigned char data)
void uart_tx_byte(unsigned int idx, unsigned char data)
{
void *base = uart_platform_baseptr(idx);
if (!base)
return;
uart8250_mem_tx_byte(base, data);
}

unsigned char uart_rx_byte(int idx)
unsigned char uart_rx_byte(unsigned int idx)
{
void *base = uart_platform_baseptr(idx);
if (!base)
return 0xff;
return uart8250_mem_rx_byte(base);
}

void uart_tx_flush(int idx)
void uart_tx_flush(unsigned int idx)
{
void *base = uart_platform_baseptr(idx);
if (!base)
Expand Down
1 change: 0 additions & 1 deletion src/drivers/usb/ehci.h
View file
Expand Up @@ -40,7 +40,6 @@ struct ehci_caps {
u8 portroute[8]; /* nibbles for routing - offset 0xC */
} __packed;


/* Section 2.3 Host Controller Operational Registers */
struct ehci_regs {

Expand Down
3 changes: 0 additions & 3 deletions src/drivers/usb/ehci_debug.c
View file
Expand Up @@ -421,8 +421,6 @@ static int ehci_wait_for_port(struct ehci_regs *ehci_regs, int port)
return -1; //-ENOTCONN;
}



static int usbdebug_init_(uintptr_t ehci_bar, unsigned int offset, struct ehci_debug_info *info)
{
struct ehci_caps *ehci_caps;
Expand Down Expand Up @@ -549,7 +547,6 @@ static int usbdebug_init_(uintptr_t ehci_bar, unsigned int offset, struct ehci_d
}
dprintk(BIOS_INFO, "EHCI done waiting for port.\n");


/* Enable the debug port */
ctrl = read32(&ehci_debug->control);
ctrl |= DBGP_CLAIM;
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/usb/gadget.c
View file
Expand Up @@ -17,7 +17,6 @@
#define USB_HUB_C_PORT_CONNECTION 16
#define USB_HUB_C_PORT_RESET 20


static int hub_port_status(const char *buf, int feature)
{
return !!(buf[feature>>3] & (1<<(feature&0x7)));
Expand Down Expand Up @@ -73,7 +72,6 @@ static int dbgp_hub_enable(struct ehci_dbg_port *ehci_debug, unsigned char hub_a
if (ret < 0)
goto err;


/* Set PORT_RESET, poll for C_PORT_RESET. */
ret = dbgp_control_msg(ehci_debug, hub_addr,
USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_OTHER,
Expand Down
1 change: 0 additions & 1 deletion src/drivers/usb/pci_xhci/pci_xhci.c
View file
Expand Up @@ -24,7 +24,6 @@ __weak enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe)
return CB_SUCCESS;
}


static void xhci_count_ports(void *context, const struct xhci_supported_protocol *data)
{
struct port_counts *counts = context;
Expand Down
1 change: 0 additions & 1 deletion src/drivers/wifi/generic/generic.c
View file
Expand Up @@ -105,7 +105,6 @@ static void emit_sar_acpi_structures(void)
acpigen_pop_len();
acpigen_pop_len();


if (!CONFIG(GEO_SAR_ENABLE))
return;

Expand Down
3 changes: 0 additions & 3 deletions src/ec/compal/ene932/ec.c
View file
Expand Up @@ -25,7 +25,6 @@ static int kbc_input_buffer_empty(void)
return !!timeout;
}


static int kbc_output_buffer_full(void)
{
u32 timeout;
Expand Down Expand Up @@ -58,7 +57,6 @@ int kbc_cleanup_buffers(void)
return !!timeout;
}


/* The ENE 60/64 EC registers are the same command/status IB/OB KBC pair.
* Check status from 64 port before each command.
*
Expand Down Expand Up @@ -88,7 +86,6 @@ void ec_kbc_write_ib(u8 data)
outb(data, KBD_DATA);
}


/*
* These functions are for accessing the ENE932 device space, but are not
* currently used.
Expand Down
2 changes: 0 additions & 2 deletions src/ec/compal/ene932/ec.h
View file
Expand Up @@ -22,14 +22,12 @@
#define CFG_COMMAND_WRITE_ENABLE (1 << 3)
#define CFG_STATUS (1 << 1)


#define KBD_DATA 0x60
#define KBD_COMMAND 0x64
#define KBD_STATUS 0x64
#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec)
#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host)


/* Wait 400ms for keyboard controller answers */
#define KBC_TIMEOUT_IN_MS 400

Expand Down
21 changes: 20 additions & 1 deletion src/ec/google/chromeec/acpi/ec.asl
View file
Expand Up @@ -10,7 +10,10 @@
#ifdef DPTF_ENABLE_CHARGER
External (\_SB.DPTF.TCHG, DeviceObj)
#endif

/* Enable DPTC interface with AMD ALIB */
#ifdef EC_ENABLE_AMD_DPTC_SUPPORT
External(\_SB.DPTC, MethodObj)
#endif

Device (EC0)
{
Expand Down Expand Up @@ -156,6 +159,17 @@ Device (EC0)

// Initialize LID switch state
Store (LIDS, \LIDS)

#ifdef EC_ENABLE_AMD_DPTC_SUPPORT
/*
* Per the device mode (clamshell or tablet) to initialize
* the thermal setting on OS startup.
*/
If (CondRefOf (\_SB.DPTC)) {
\_SB.DPTC()
}
#endif

}

/* Read requested temperature and check against EC error values */
Expand Down Expand Up @@ -379,6 +393,11 @@ Device (EC0)
#endif
#ifdef EC_ENABLE_TBMC_DEVICE
Notify (TBMC, 0x80)
#endif
#ifdef EC_ENABLE_AMD_DPTC_SUPPORT
If (CondRefOf (\_SB.DPTC)) {
\_SB.DPTC()
}
#endif
}

Expand Down
1 change: 0 additions & 1 deletion src/ec/google/chromeec/chip.h
View file
Expand Up @@ -3,7 +3,6 @@
#ifndef EC_GOOGLE_CHROMEEC_CHIP_H
#define EC_GOOGLE_CHROMEEC_CHIP_H


struct ec_google_chromeec_config {
};

Expand Down
18 changes: 0 additions & 18 deletions src/ec/google/chromeec/ec_commands.h
View file
Expand Up @@ -414,7 +414,6 @@ extern "C" {
/* Current version of ACPI memory address space */
#define EC_ACPI_MEM_VERSION_CURRENT 2


/*
* This header file is used in coreboot both in C and ACPI code. The ACPI code
* is pre-processed to handle constants but the ASL compiler is unable to
Expand Down Expand Up @@ -1254,7 +1253,6 @@ struct ec_response_get_protocol_info {
uint32_t flags;
} __ec_align4;


/*****************************************************************************/
/* Get/Set miscellaneous values */

Expand Down Expand Up @@ -1664,7 +1662,6 @@ struct ec_params_flash_erase_v1 {
/* Rollback information flash region protected now */
#define EC_FLASH_PROTECT_ROLLBACK_NOW BIT(10)


/**
* struct ec_params_flash_protect - Parameters for the flash protect command.
* @mask: Bits in flags to apply.
Expand Down Expand Up @@ -1761,7 +1758,6 @@ struct ec_response_vbnvcontext {
uint8_t block[EC_VBNV_BLOCK_SIZE];
} __ec_align4;


/* Get SPI flash information */
#define EC_CMD_FLASH_SPI_INFO 0x0018

Expand All @@ -1779,7 +1775,6 @@ struct ec_response_flash_spi_info {
uint8_t sr1, sr2;
} __ec_align1;


/* Select flash during flash operations */
#define EC_CMD_FLASH_SELECT 0x0019

Expand All @@ -1791,7 +1786,6 @@ struct ec_params_flash_select {
uint8_t select;
} __ec_align4;


/**
* Request random numbers to be generated and returned.
* Can be used to test the random number generator is truly random.
Expand Down Expand Up @@ -2202,7 +2196,6 @@ struct ec_response_lightbar {
struct lightbar_params_v0 get_params_v0;
struct lightbar_params_v1 get_params_v1;


struct lightbar_params_v2_timing get_params_v2_timing;
struct lightbar_params_v2_tap get_params_v2_tap;
struct lightbar_params_v2_oscillation get_params_v2_osc;
Expand Down Expand Up @@ -2815,7 +2808,6 @@ struct ec_params_motion_sense {
uint16_t scale[3];
} sensor_scale;


/* Used for MOTIONSENSE_CMD_FIFO_INFO */
/* (no params) */

Expand Down Expand Up @@ -3272,7 +3264,6 @@ struct ec_response_thermal_get_threshold {
uint16_t value;
} __ec_align2;


/* The version 1 structs are visible. */
enum ec_temp_thresholds {
EC_TEMP_THRESH_WARN = 0,
Expand Down Expand Up @@ -3388,7 +3379,6 @@ struct ec_params_tmp006_set_calibration_v1 {
float val[0];
} __ec_align4;


/* Read raw TMP006 data */
#define EC_CMD_TMP006_GET_RAW 0x0055

Expand Down Expand Up @@ -3786,7 +3776,6 @@ struct ec_response_keyboard_factory_test {
#define EC_MKBP_FP_ERR_MATCH_YES_UPDATED 3
#define EC_MKBP_FP_ERR_MATCH_YES_UPDATE_FAILED 5


#define EC_CMD_MKBP_WAKE_MASK 0x0069
enum ec_mkbp_event_mask_action {
/* Retrieve the value of a wake mask. */
Expand Down Expand Up @@ -3864,7 +3853,6 @@ struct ec_response_temp_sensor_get_info {
/*****************************************************************************/
/* Host event commands */


/* Obsolete. New implementation should use EC_CMD_HOST_EVENT instead */
/*
* Host event mask params and response structures, shared by all of the host
Expand Down Expand Up @@ -4461,7 +4449,6 @@ struct ec_response_charge_state {
};
} __ec_align4;


/*
* Set maximum battery charging current.
*/
Expand Down Expand Up @@ -4790,7 +4777,6 @@ struct ec_response_i2c_passthru_protect {
uint8_t status; /* Status flags (0: unlocked, 1: locked) */
} __ec_align1;


/*****************************************************************************/
/*
* HDMI CEC commands
Expand Down Expand Up @@ -5400,7 +5386,6 @@ struct ec_response_usb_pd_power_info {
uint32_t max_power;
} __ec_align4;


/*
* This command will return the number of USB PD charge port + the number
* of dedicated port present.
Expand Down Expand Up @@ -5602,7 +5587,6 @@ struct ec_params_pd_write_log_entry {
uint8_t port; /* port#, or 0 for events unrelated to a given port */
} __ec_align1;


/* Control USB-PD chip */
#define EC_CMD_PD_CONTROL 0x0119

Expand Down Expand Up @@ -5886,7 +5870,6 @@ struct ec_response_rollback_info {
int32_t rw_rollback_version;
} __ec_align4;


/* Issue AP reset */
#define EC_CMD_AP_RESET 0x0125

Expand Down Expand Up @@ -5928,7 +5911,6 @@ struct ec_params_locate_chip {
};
} __ec_align2;


struct ec_response_locate_chip {
uint8_t bus_type; /* enum ec_bus_type */
uint8_t reserved; /* Aligning the following union to 2 bytes */
Expand Down
1 change: 0 additions & 1 deletion src/ec/google/chromeec/ec_lpc.c
View file
Expand Up @@ -307,7 +307,6 @@ static int google_chromeec_command_v1(struct chromeec_command *cec_command)
args.checksum = csum;
write_bytes(EC_LPC_ADDR_HOST_ARGS, sizeof(args), (u8*)&args, NULL);


/* Issue the command */
write_byte(cmd_code, EC_LPC_ADDR_HOST_CMD);

Expand Down
1 change: 0 additions & 1 deletion src/ec/lenovo/h8/h8.h
View file
Expand Up @@ -40,7 +40,6 @@ void h8_ssdt_generator(const struct device *dev);
*/
void h8_mb_init(void);


/* EC registers */
#define H8_CONFIG0 0x00
#define H8_CONFIG0_EVENTS_ENABLE 0x02
Expand Down
3 changes: 0 additions & 3 deletions src/ec/quanta/ene_kb3940q/ec.c
View file
Expand Up @@ -26,7 +26,6 @@ static int ec_input_buffer_empty(u8 status_port)
return !!timeout;
}


static int ec_output_buffer_full(u8 status_port)
{
u32 timeout;
Expand All @@ -41,8 +40,6 @@ static int ec_output_buffer_full(u8 status_port)
return !!timeout;
}



/* The ENE 60/64 EC registers are the same command/status IB/OB KBC pair.
* Check status from 64 port before each command.
*
Expand Down
3 changes: 0 additions & 3 deletions src/ec/quanta/ene_kb3940q/ec.h
View file
Expand Up @@ -12,8 +12,6 @@
#define EC_IO_LOW EC_IO + 2
#define EC_IO_DATA EC_IO + 3



// 60h/64h Command Interface
#define KBD_DATA 0x60
#define KBD_COMMAND 0x64
Expand Down Expand Up @@ -192,5 +190,4 @@ void ec_mem_write(u8 addr, u8 data);
#define EC_CMD_BURST_DISABLE 0x83
#define EC_CMD_QUERY_EVENT 0x84


#endif /* _EC_QUANTA_ENE_KB3940Q_EC_H */
5 changes: 0 additions & 5 deletions src/ec/quanta/it8518/ec.c
View file
Expand Up @@ -26,7 +26,6 @@ static int input_buffer_empty(u16 status_reg)
return !!timeout;
}


static int output_buffer_full(u16 status_reg)
{
u32 timeout;
Expand All @@ -42,8 +41,6 @@ static int output_buffer_full(u16 status_reg)
return !!timeout;
}



/* The IT8518 60/64 EC registers are the same command/status IB/OB KBC pair.
* Check status from 64 port before each command.
*
Expand Down Expand Up @@ -73,7 +70,6 @@ void ec_kbc_write_ib(u8 data)
outb(data, KBD_DATA);
}


/*
* These functions are for accessing the IT8518 device RAM space via 0x66/0x68
*/
Expand Down Expand Up @@ -110,7 +106,6 @@ void ec_write(u16 addr, u8 data)
ec_write_ib(data);
}


u8 ec_it8518_get_event(void)
{
u8 cmd = 0;
Expand Down
1 change: 0 additions & 1 deletion src/ec/quanta/it8518/ec.h
View file
Expand Up @@ -58,7 +58,6 @@ void ec_kbc_write_ib(u8 data);
#define EC_IF_MAJ_VER 0xEF
#define EC_MBAT_STATUS 0x0138


// EC 0.83b added status bits:
// BIT0=EC in RO mode
// BIT1=Recovery Key Sequence Detected
Expand Down
6 changes: 6 additions & 0 deletions src/ec/system76/ec/Makefile.inc
View file
@@ -0,0 +1,6 @@
ifeq ($(CONFIG_EC_SYSTEM76_EC),y)

all-y += system76_ec.c
smm-$(CONFIG_DEBUG_SMI) += system76_ec.c

endif
61 changes: 61 additions & 0 deletions src/ec/system76/ec/system76_ec.c
View file
@@ -0,0 +1,61 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <arch/io.h>
#include <console/system76_ec.h>
#include <timer.h>

// This is the command region for System76 EC firmware. It must be
// enabled for LPC in the mainboard.
#define SYSTEM76_EC_BASE 0x0E00
#define SYSTEM76_EC_SIZE 256

#define REG_CMD 0
#define REG_RESULT 1

// When command register is 0, command is complete
#define CMD_FINISHED 0

// Print command. Registers are unique for each command
#define CMD_PRINT 4
#define CMD_PRINT_REG_FLAGS 2
#define CMD_PRINT_REG_LEN 3
#define CMD_PRINT_REG_DATA 4

static inline uint8_t system76_ec_read(uint8_t addr)
{
return inb(SYSTEM76_EC_BASE + (uint16_t)addr);
}

static inline void system76_ec_write(uint8_t addr, uint8_t data)
{
outb(data, SYSTEM76_EC_BASE + (uint16_t)addr);
}

void system76_ec_init(void)
{
// Clear entire command region
for (int i = 0; i < SYSTEM76_EC_SIZE; i++)
system76_ec_write((uint8_t)i, 0);
}

void system76_ec_flush(void)
{
system76_ec_write(REG_CMD, CMD_PRINT);

// Wait for command completion, for up to 10 milliseconds, with a
// test period of 1 microsecond
wait_us(10000, system76_ec_read(REG_CMD) == CMD_FINISHED);

system76_ec_write(CMD_PRINT_REG_LEN, 0);
}

void system76_ec_print(uint8_t byte)
{
uint8_t len = system76_ec_read(CMD_PRINT_REG_LEN);
system76_ec_write(CMD_PRINT_REG_DATA + len, byte);
system76_ec_write(CMD_PRINT_REG_LEN, len + 1);

// If we hit the end of the buffer, or were given a newline, flush
if (byte == '\n' || len >= (SYSTEM76_EC_SIZE - CMD_PRINT_REG_DATA))
system76_ec_flush();
}
20 changes: 20 additions & 0 deletions src/include/acpi/acpi.h
View file
Expand Up @@ -844,6 +844,26 @@ typedef struct acpi_cstate {
acpi_addr_t resource;
} __packed acpi_cstate_t;

struct acpi_sw_pstate {
u32 core_freq;
u32 power;
u32 transition_latency;
u32 bus_master_latency;
u32 control_value;
u32 status_value;
} __packed;

struct acpi_xpss_sw_pstate {
u64 core_freq;
u64 power;
u64 transition_latency;
u64 bus_master_latency;
u64 control_value;
u64 status_value;
u64 control_mask;
u64 status_mask;
} __packed;

typedef struct acpi_tstate {
u32 percent;
u32 power;
Expand Down
5 changes: 5 additions & 0 deletions src/include/acpi/acpigen.h
View file
Expand Up @@ -324,13 +324,18 @@ void acpigen_write_STA_ext(const char *namestring);
void acpigen_write_TPC(const char *gnvs_tpc_limit);
void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat,
u32 busmLat, u32 control, u32 status);
void acpigen_write_pss_object(const struct acpi_sw_pstate *pstate_values, size_t nentries);
typedef enum { SW_ALL = 0xfc, SW_ANY = 0xfd, HW_ALL = 0xfe } PSD_coord;
void acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype);
void acpigen_write_CST_package_entry(acpi_cstate_t *cstate);
void acpigen_write_CST_package(acpi_cstate_t *entry, int nentries);
typedef enum { CSD_HW_ALL = 0xfe } CSD_coord;
void acpigen_write_CSD_package(u32 domain, u32 numprocs, CSD_coord coordtype,
u32 index);
void acpigen_write_pct_package(const acpi_addr_t *perf_ctrl, const acpi_addr_t *perf_sts);
void acpigen_write_xpss_package(const struct acpi_xpss_sw_pstate *pstate_value);
void acpigen_write_xpss_object(const struct acpi_xpss_sw_pstate *pstate_values,
size_t nentries);
void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len);
void acpigen_write_processor_package(const char *name,
unsigned int first_core,
Expand Down
2 changes: 2 additions & 0 deletions src/include/bootblock_common.h
View file
Expand Up @@ -29,6 +29,8 @@ asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist);
asmlinkage void ap_bootblock_c_entry(void);

void bootblock_main_with_basetime(uint64_t base_timestamp);
void bootblock_main_with_timestamp(uint64_t base_timestamp,
struct timestamp_entry *timestamps, size_t num_timestamps);

/* This is the argument structure passed from decompressor to bootblock. */
struct bootblock_arg {
Expand Down
1 change: 0 additions & 1 deletion src/include/console/flash.h
View file
Expand Up @@ -27,5 +27,4 @@ static inline void __flashconsole_tx_byte(u8 data) {}
static inline void __flashconsole_tx_flush(void) {}
#endif /* __CONSOLE_FLASH_ENABLE__ */


#endif /* CONSOLE_FLASH_H */
2 changes: 0 additions & 2 deletions src/include/console/spi.h
View file
Expand Up @@ -52,6 +52,4 @@ struct em100_msg {
char data[MAX_MSG_LENGTH];
} __packed;



#endif /* CONSOLE_SPI_H */
35 changes: 35 additions & 0 deletions src/include/console/system76_ec.h
View file
@@ -0,0 +1,35 @@
#ifndef CONSOLE_SYSTEM76_EC_H
#define CONSOLE_SYSTEM76_EC_H 1

#include <stddef.h>
#include <stdint.h>

void system76_ec_init(void);
void system76_ec_flush(void);
void system76_ec_print(uint8_t byte);

#define __CONSOLE_SYSTEM76_EC_ENABLE__ (CONFIG(CONSOLE_SYSTEM76_EC) && \
(ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_RAMSTAGE \
|| ENV_SEPARATE_VERSTAGE || ENV_POSTCAR \
|| (ENV_SMM && CONFIG(DEBUG_SMI))))

#if __CONSOLE_SYSTEM76_EC_ENABLE__
static inline void __system76_ec_init(void)
{
system76_ec_init();
}
static inline void __system76_ec_tx_flush(void)
{
system76_ec_flush();
}
static inline void __system76_ec_tx_byte(unsigned char byte)
{
system76_ec_print(byte);
}
#else
static inline void __system76_ec_init(void) {}
static inline void __system76_ec_tx_flush(void) {}
static inline void __system76_ec_tx_byte(unsigned char byte) {}
#endif

#endif
12 changes: 6 additions & 6 deletions src/include/console/uart.h
View file
Expand Up @@ -35,14 +35,14 @@ unsigned int uart_input_clock_divider(void);
/* Bitbang out one byte on an 8n1 UART through the output function set_tx(). */
void uart_bitbang_tx_byte(unsigned char data, void (*set_tx)(int line_state));

void uart_init(int idx);
void uart_tx_byte(int idx, unsigned char data);
void uart_tx_flush(int idx);
unsigned char uart_rx_byte(int idx);
void uart_init(unsigned int idx);
void uart_tx_byte(unsigned int idx, unsigned char data);
void uart_tx_flush(unsigned int idx);
unsigned char uart_rx_byte(unsigned int idx);

uintptr_t uart_platform_base(int idx);
uintptr_t uart_platform_base(unsigned int idx);

static inline void *uart_platform_baseptr(int idx)
static inline void *uart_platform_baseptr(unsigned int idx)
{
return (void *)uart_platform_base(idx);
}
Expand Down
1 change: 0 additions & 1 deletion src/include/cpu/intel/em64t100_save_state.h
View file
Expand Up @@ -66,7 +66,6 @@ typedef struct {
u64 rsi;
u64 rdi;


u64 io_mem_addr;
u32 io_misc_info;

Expand Down
2 changes: 0 additions & 2 deletions src/include/cpu/intel/em64t101_save_state.h
View file
Expand Up @@ -6,7 +6,6 @@
#include <types.h>
#include <cpu/x86/smm.h>


/* Intel Revision 30101 SMM State-Save Area
* The following processor architectures use this:
* - Westmere
Expand Down Expand Up @@ -83,7 +82,6 @@ typedef struct {
u64 rsi;
u64 rdi;


u64 io_mem_addr;
u32 io_misc_info;

Expand Down
1 change: 0 additions & 1 deletion src/include/cpu/intel/smm_reloc.h
View file
Expand Up @@ -51,7 +51,6 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_

bool cpu_has_alternative_smrr(void);


#define MSR_PRMRR_PHYS_BASE 0x1f4
#define MSR_PRMRR_PHYS_MASK 0x1f5
#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4
Expand Down
1 change: 0 additions & 1 deletion src/include/cpu/intel/speedstep.h
View file
Expand Up @@ -18,7 +18,6 @@
*/
#define PMB1_BASE 0x800


/* Speedstep related MSRs */
#define MSR_THERM2_CTL 0x19D
#define MSR_EBC_FREQUENCY_ID 0x2c
Expand Down
5 changes: 3 additions & 2 deletions src/include/cpu/x86/msr.h
View file
Expand Up @@ -90,6 +90,9 @@
#define IA32_L3_MASK_1 0xc91
#define IA32_L3_MASK_2 0xc92

#define IA32_CR_SF_QOS_MASK_1 0x1891
#define IA32_CR_SF_QOS_MASK_2 0x1892

#ifndef __ASSEMBLER__
#include <types.h>

Expand Down Expand Up @@ -296,7 +299,6 @@ static inline enum mca_err_code_types mca_err_type(msr_t reg)
return MCA_ERRTYPE_UNKNOWN;
}


/* Helper for setting single MSR bits */
static inline void msr_set_bit(unsigned int reg, unsigned int bit)
{
Expand All @@ -315,6 +317,5 @@ static inline void msr_set_bit(unsigned int reg, unsigned int bit)
wrmsr(reg, msr);
}


#endif /* __ASSEMBLER__ */
#endif /* CPU_X86_MSR_H */
2 changes: 1 addition & 1 deletion src/include/cpu/x86/mtrr.h
View file
Expand Up @@ -27,9 +27,9 @@
#define MTRR_DEF_TYPE_EN (1 << 11)
#define MTRR_DEF_TYPE_FIX_EN (1 << 10)


#define IA32_SMRR_PHYS_BASE 0x1f2
#define IA32_SMRR_PHYS_MASK 0x1f3
#define SMRR_PHYS_MASK_LOCK (1 << 10)

/* Specific to model_6fx and model_1067x */
#define MSR_SMRR_PHYS_BASE 0xa0
Expand Down
1 change: 0 additions & 1 deletion src/include/cpu/x86/post_code.h
View file
Expand Up @@ -3,7 +3,6 @@

#include <console/post_codes.h>


#if CONFIG(POST_IO)
#define post_code(value) \
movb $value, %al; \
Expand Down
5 changes: 5 additions & 0 deletions src/include/cpu/x86/smm.h
View file
Expand Up @@ -193,4 +193,9 @@ int smm_subregion(int sub, uintptr_t *start, size_t *size);
/* Print the SMM memory layout on console. */
void smm_list_regions(void);

#define SMM_REVISION_OFFSET_FROM_TOP (0x8000 - 0x7efc)
/* Return the SMM save state revision. The revision can be fetched from the smm savestate
which is always at the same offset downward from the top of the save state. */
uint32_t smm_revision(void);

#endif /* CPU_X86_SMM_H */
2 changes: 1 addition & 1 deletion src/include/device/azalia_device.h
View file
Expand Up @@ -111,7 +111,7 @@ enum azalia_pin_location_2 {
((type) << 16) | \
((color) << 12) | \
((no_presence_detect) << 8) | \
((sequence) << 4) | \
((association) << 4) | \
((sequence) << 0))

#define AZALIA_ARRAY_SIZES const u32 pc_beep_verbs_size = \
Expand Down
1 change: 0 additions & 1 deletion src/include/device/dram/ddr3.h
View file
Expand Up @@ -19,7 +19,6 @@
#include <device/dram/common.h>
#include <types.h>


/**
* Convenience definitions for SPD offsets
*
Expand Down
6 changes: 5 additions & 1 deletion src/include/device/dram/ddr4.h
View file
Expand Up @@ -21,7 +21,6 @@
#define SPD_DDR4_PART_OFF 329
#define SPD_DDR4_PART_LEN 20


/*
* Module type (byte 3, bits 3:0) of SPD
* This definition is specific to DDR4. DDR2/3 SPDs have a different structure.
Expand Down Expand Up @@ -70,4 +69,9 @@ enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot,
const u16 selected_freq,
const dimm_attr *info);

/**
* Converts DDR4 clock speed in MHz to the standard reported speed in MT/s
*/
uint16_t ddr4_speed_mhz_to_reported_mts(uint16_t speed_mhz);

#endif /* DEVICE_DRAM_DDR4L_H */
239 changes: 0 additions & 239 deletions src/include/device/drm_dp_helper.h
View file

This file was deleted.

1 change: 0 additions & 1 deletion src/include/device/hypertransport_def.h
View file
Expand Up @@ -18,7 +18,6 @@
#define HT_FREQ_2600Mhz 14
#define HT_FREQ_VENDOR 15 /* AMD defines this to be 100Mhz */


static inline bool offset_unit_id(bool is_sb_ht_chain)
{
bool need_offset = (CONFIG_HT_CHAIN_UNITID_BASE != 1)
Expand Down
1 change: 0 additions & 1 deletion src/include/device/path.h
View file
Expand Up @@ -137,7 +137,6 @@ struct device_path {
};
};


#define DEVICE_PATH_MAX 40
#define BUS_PATH_MAX (DEVICE_PATH_MAX+10)

Expand Down
12 changes: 12 additions & 0 deletions src/include/device/pci.h
View file
Expand Up @@ -128,6 +128,18 @@ static inline int pci_base_address_is_memory_space(unsigned int attr)
}

void pci_dev_disable_bus_master(const struct device *dev);

static __always_inline
#if ENV_PCI_SIMPLE_DEVICE
void pci_dev_request_bus_master(pci_devfn_t dev)
#else
void pci_dev_request_bus_master(struct device *dev)
#endif /* ENV_PCI_SIMPLE_DEVICE */
{
if (CONFIG(PCI_ALLOW_BUS_MASTER))
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
}

#endif /* CONFIG_PCI */

void pci_early_bridge_init(void);
Expand Down
2 changes: 0 additions & 2 deletions src/include/device/pci_def.h
View file
Expand Up @@ -305,7 +305,6 @@
#define PCI_MSIX_PBA_OFFSET ~0x7 /* Offset into specified BAR */
#define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */


/* CompactPCI Hotswap Register */

#define PCI_CHSWP_CSR 2 /* Control and Status Register */
Expand Down Expand Up @@ -521,7 +520,6 @@
#define PCI_PWR_CAP 12 /* Capability */
#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */


/*
* The PCI interface treats multi-function devices as independent
* devices. The slot/function address of each device is encoded
Expand Down
9 changes: 6 additions & 3 deletions src/include/device/pci_ids.h
View file
Expand Up @@ -517,7 +517,6 @@
#define PCI_DEVICE_ID_NS_SCx200_XBUS 0x0505
#define PCI_DEVICE_ID_NS_87410 0xd001


#define PCI_VENDOR_ID_TSENG 0x100c
#define PCI_DEVICE_ID_TSENG_W32P_2 0x3202
#define PCI_DEVICE_ID_TSENG_W32P_b 0x3205
Expand Down Expand Up @@ -1664,7 +1663,6 @@
#define PCI_DEVICE_ID_ATT_L56XMF 0x0440
#define PCI_DEVICE_ID_ATT_VENUS_MODEM 0x480


#define PCI_VENDOR_ID_SPECIALIX 0x11cb
#define PCI_DEVICE_ID_SPECIALIX_IO8 0x2000
#define PCI_DEVICE_ID_SPECIALIX_XIO 0x4000
Expand Down Expand Up @@ -2035,6 +2033,7 @@

#define PCI_VENDOR_ID_GLI 0x17a0
#define PCI_DEVICE_ID_GLI_9763E 0xe763
#define PCI_DEVICE_ID_GLI_9755 0x9755

#define PCI_VENDOR_ID_XGI 0x18ca
#define PCI_DEVICE_ID_XGI_20 0x0020
Expand Down Expand Up @@ -2894,7 +2893,7 @@
#define PCI_DEVICE_ID_INTEL_MCC_ESPI_2 0x4b05
#define PCI_DEVICE_ID_INTEL_MCC_ESPI_3 0x4b06
#define PCI_DEVICE_ID_INTEL_MCC_ESPI_4 0x4b07
#define PCI_DEVICE_ID_INTEL_JSP_SUPER_ESPI 0X4d87
#define PCI_DEVICE_ID_INTEL_JSP_SUPER_ESPI 0x4d87
#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_0 0x7a00
#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_1 0x7a01
#define PCI_DEVICE_ID_INTEL_ADP_P_ESPI_2 0x7a02
Expand Down Expand Up @@ -3725,6 +3724,7 @@
#define PCI_DEVICE_ID_INTEL_EHL_ID_10 0x452C
#define PCI_DEVICE_ID_INTEL_EHL_ID_11 0x452E
#define PCI_DEVICE_ID_INTEL_EHL_ID_12 0x4518
#define PCI_DEVICE_ID_INTEL_EHL_ID_13 0x451A
#define PCI_DEVICE_ID_INTEL_JSL_ID_1 0x4e22
#define PCI_DEVICE_ID_INTEL_JSL_ID_2 0x4e26
#define PCI_DEVICE_ID_INTEL_JSL_ID_3 0x4e12
Expand Down Expand Up @@ -3966,10 +3966,13 @@

#define PCI_DEVICE_ID_INTEL_TGL_IPU 0x9a19
#define PCI_DEVICE_ID_INTEL_JSL_IPU 0x4e19
#define PCI_DEVICE_ID_INTEL_ADL_IPU 0x465d

/* Intel Dynamic Tuning Technology Device */
#define PCI_DEVICE_ID_INTEL_CML_DTT 0x1903
#define PCI_DEVICE_ID_INTEL_TGL_DTT 0x9A03
#define PCI_DEVICE_ID_INTEL_JSL_DTT 0x4E03
#define PCI_DEVICE_ID_INTEL_ADL_DTT 0x461d

#define PCI_VENDOR_ID_COMPUTONE 0x8e0e
#define PCI_DEVICE_ID_COMPUTONE_IP2EX 0x0291
Expand Down
1 change: 0 additions & 1 deletion src/include/device/pci_mmio_cfg.h
View file
Expand Up @@ -7,7 +7,6 @@
#include <device/mmio.h>
#include <device/pci_type.h>


/* By not assigning this to CONFIG_MMCONF_BASE_ADDRESS here we
* prevent some sub-optimal constant folding. */
extern u8 *const pci_mmconf;
Expand Down
35 changes: 34 additions & 1 deletion src/include/device/pnp.h
View file
Expand Up @@ -3,6 +3,7 @@

#include <stdint.h>
#include <device/device.h>
/* When <device/pnp.h> is needed, it supposed to provide <device/pnp_{def,type}.h> */
#include <device/pnp_def.h>
#include <device/pnp_type.h>
#include <arch/io.h>
Expand Down Expand Up @@ -67,7 +68,6 @@ struct resource *pnp_get_resource(struct device *dev, unsigned int index);
void pnp_enable_devices(struct device *dev, struct device_operations *ops,
unsigned int functions, struct pnp_info *info);


struct pnp_mode_ops {
void (*enter_conf_mode)(struct device *dev);
void (*exit_conf_mode)(struct device *dev);
Expand Down Expand Up @@ -133,4 +133,37 @@ static inline void pnp_write_index(u16 port, u8 reg, u8 value)
outb(value, port + 1);
}

/*
* void pnp_unset_and_set_index(u16 port, u8 reg, u8 unset, u8 set)
* Description:
* This routine unsets and sets bits from indexed I/O registers. The
* reg byte is written to the index register at I/O address = port.
* The value byte to update is data register at I/O address = port + 1.
*
* Unlike and-then-or style operations, no bitwise negation is necessary
* to specify the bits to unset. Because the bitwise negation implicitly
* promotes operands to int before operating, one may have to explicitly
* downcast the result if the data width is smaller than that of an int.
* Since warnings are errors in coreboot, explicit casting is necessary.
*
* Performing said negation inside this routine alleviates this problem,
* while allowing the compiler to warn if the input parameters overflow.
* Casting outside this function would silence valid compiler warnings.
*
* Parameters:
* @param[in] u16 port = The address of the port index register.
* @param[in] u8 reg = The offset within the indexed space.
* @param[in] u8 unset = Bitmask with ones to the bits to unset from the data register.
* @param[in] u8 set = Bitmask with ones to the bits to set from the data register.
*/
static inline void pnp_unset_and_set_index(u16 port, u8 reg, u8 unset, u8 set)
{
outb(reg, port);

u8 value = inb(port + 1);
value &= (u8)~unset;
value |= set;
outb(value, port + 1);
}

#endif /* DEVICE_PNP_H */
11 changes: 8 additions & 3 deletions src/include/device/pnp_ops.h
View file
Expand Up @@ -6,7 +6,6 @@
#include <stdint.h>
#include <arch/io.h>
#include <device/pnp.h>
#include <device/pnp_type.h>

#if ENV_PNP_SIMPLE_DEVICE

Expand All @@ -22,6 +21,12 @@ static __always_inline uint8_t pnp_read_config(
return pnp_read_index(dev >> 8, reg);
}

static __always_inline void pnp_unset_and_set_config(
pnp_devfn_t dev, uint8_t reg, uint8_t unset, uint8_t set)
{
pnp_unset_and_set_index(dev >> 8, reg, unset, set);
}

static __always_inline
void pnp_set_logical_device(pnp_devfn_t dev)
{
Expand All @@ -32,13 +37,13 @@ void pnp_set_logical_device(pnp_devfn_t dev)
static __always_inline
void pnp_set_enable(pnp_devfn_t dev, int enable)
{
pnp_write_config(dev, 0x30, enable?0x1:0x0);
pnp_write_config(dev, PNP_IDX_EN, enable?0x1:0x0);
}

static __always_inline
int pnp_read_enable(pnp_devfn_t dev)
{
return !!pnp_read_config(dev, 0x30);
return !!pnp_read_config(dev, PNP_IDX_EN);
}

static __always_inline
Expand Down
1 change: 0 additions & 1 deletion src/include/device/resource.h
View file
Expand Up @@ -109,7 +109,6 @@ static inline void *res2mmio(struct resource *res, unsigned long offset,
const struct device *largest_resource(struct bus *bus, struct resource **result_res,
unsigned long type_mask, unsigned long type);


/* Compute and allocate resources. This is the main resource allocator entry point. */
void allocate_resources(const struct device *root);

Expand Down
6 changes: 0 additions & 6 deletions src/include/device_tree.h
View file
Expand Up @@ -43,8 +43,6 @@ struct fdt_property
uint32_t size;
};



/*
* Unflattened device tree structures.
*/
Expand Down Expand Up @@ -88,8 +86,6 @@ struct device_tree
struct device_tree_node *root;
};



/*
* Flattened device tree functions. These generally return the number of bytes
* which were consumed reading the requested value.
Expand All @@ -109,8 +105,6 @@ int fdt_skip_node(const void *blob, uint32_t offset);
invalidates the unflattened one. */
struct device_tree *fdt_unflatten(const void *blob);



/*
* Unflattened device tree functions.
*/
Expand Down
1 change: 0 additions & 1 deletion src/include/elog.h
View file
Expand Up @@ -202,7 +202,6 @@ struct elog_event_mem_cache_update {
#define ELOG_TYPE_MI_HRPC 0xb4
#define ELOG_TYPE_MI_HR 0xb5


struct elog_event_extended_event {
u8 event_type;
u32 event_complement;
Expand Down
15 changes: 15 additions & 0 deletions src/include/fw_config.h
View file
Expand Up @@ -40,6 +40,21 @@ struct fw_config {
*/
bool fw_config_probe(const struct fw_config *match);

/**
* fw_config_for_each_found() - Call a callback for each fw_config field found
* @cb: The callback function
* @arg: A context argument that is passed to the callback
*/
void fw_config_for_each_found(void (*cb)(const struct fw_config *config, void *arg), void *arg);

/**
* fw_config_get_found() - Return a pointer to the fw_config struct for a given field.
* @field_mask: A field mask from static.h, e.g., FW_CONFIG_FIELD_FEATURE_MASK
*
* Return pointer to cached `struct fw_config` if successfully probed, otherwise NULL.
*/
const struct fw_config *fw_config_get_found(uint32_t field_mask);

#else

static inline bool fw_config_probe(const struct fw_config *match)
Expand Down
1 change: 0 additions & 1 deletion src/include/input-event-codes.h
View file
Expand Up @@ -870,7 +870,6 @@
#define ABS_MT_TOOL_X 0x3c /* Center X tool position */
#define ABS_MT_TOOL_Y 0x3d /* Center Y tool position */


#define ABS_MAX 0x3f
#define ABS_CNT (ABS_MAX+1)

Expand Down
14 changes: 14 additions & 0 deletions src/include/memory_info.h
View file
Expand Up @@ -28,6 +28,10 @@ struct dimm_info {
* See the smbios.h smbios_memory_type enum.
*/
uint16_t ddr_type;
/*
* ddr_frequency is deprecated.
* Use max_speed_mts and configured_speed_mts instead.
*/
uint16_t ddr_frequency;
uint8_t rank_per_dimm;
uint8_t channel_num;
Expand Down Expand Up @@ -79,6 +83,16 @@ struct dimm_info {
* Voltage Level
*/
uint16_t vdd_voltage;
/*
* Max speed in MT/s
* If the value is 0, ddr_frequency should be used instead.
*/
uint16_t max_speed_mts;
/*
* Configured speed in MT/s
* If the value is 0, ddr_frequency should be used instead.
*/
uint16_t configured_speed_mts;
} __packed;

struct memory_info {
Expand Down
1 change: 0 additions & 1 deletion src/include/memrange.h
View file
Expand Up @@ -82,7 +82,6 @@ static inline bool memranges_is_empty(const struct memranges *ranges)
#define memranges_each_entry(r, ranges) \
for (r = (ranges)->entries; r != NULL; r = r->next)


/* Initialize memranges structure providing an optional array of range_entry
* to use as the free list. Additionally, it accepts an align parameter that
* represents the required alignment(log 2) of addresses. */
Expand Down
1 change: 0 additions & 1 deletion src/include/nhlt.h
View file
Expand Up @@ -219,7 +219,6 @@ enum {
SPEAKER_TOP_BACK_RIGHT = 1 << 17,
};


/* Supporting structures. Only SoC/chipset and the library code directly should
* be manipulating these structures. */
struct sub_format {
Expand Down
1 change: 0 additions & 1 deletion src/include/pc80/mc146818rtc.h
View file
Expand Up @@ -17,7 +17,6 @@
#define RTC_REG_C 12
#define RTC_REG_D 13


/**********************************************************************
* register details
**********************************************************************/
Expand Down
1 change: 0 additions & 1 deletion src/include/reg_script.h
View file
Expand Up @@ -355,7 +355,6 @@ struct reg_script_bus_entry {
#define REG_RES_XOR32(bar_, reg_, value_) \
REG_RES_RXW32(bar_, reg_, 0xffffffff, value_)


#if CONFIG(SOC_INTEL_BAYTRAIL)
/*
* IO Sideband Function
Expand Down
17 changes: 15 additions & 2 deletions src/include/region_file.h
View file
Expand Up @@ -31,9 +31,22 @@ int region_file_init(struct region_file *f, const struct region_device *p);
*/
int region_file_data(const struct region_file *f, struct region_device *rdev);

/*
* Create region file entry struct to insert multiple data buffers
* into the same region_file.
*/
struct update_region_file_entry {
/* size of this entry */
size_t size;
/* data pointer */
const void *data;
};

/* Update region file with latest data. Returns < 0 on error, 0 on success. */
int region_file_update_data(struct region_file *f, const void *buf,
size_t size);
int region_file_update_data_arr(struct region_file *f,
const struct update_region_file_entry *entries,
size_t num_entries);
int region_file_update_data(struct region_file *f, const void *buf, size_t size);

/* Declared here for easy object allocation. */
struct region_file {
Expand Down
3 changes: 0 additions & 3 deletions src/include/smp/atomic.h
View file
Expand Up @@ -31,7 +31,6 @@ typedef struct { int counter; } atomic_t;
*/
#define atomic_set(v, i) (((v)->counter) = (i))


/**
* atomic_inc - increment atomic variable
* @param v: pointer of type atomic_t
Expand All @@ -41,7 +40,6 @@ typedef struct { int counter; } atomic_t;
*/
#define atomic_inc(v) (((v)->counter)++)


/**
* atomic_dec - decrement atomic variable
* @param v: pointer of type atomic_t
Expand All @@ -51,7 +49,6 @@ typedef struct { int counter; } atomic_t;
*/
#define atomic_dec(v) (((v)->counter)--)


#endif /* CONFIG_SMP */

#endif /* SMP_ATOMIC_H */
1 change: 0 additions & 1 deletion src/include/spd.h
View file
Expand Up @@ -136,7 +136,6 @@
/* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */
#define SPD_tRFC 42


/* SPD_MEMORY_TYPE values. */
enum spd_memory_type {
SPD_MEMORY_TYPE_UNDEFINED = 0x00,
Expand Down
44 changes: 36 additions & 8 deletions src/include/superio/hwm5_conf.h
View file
Expand Up @@ -12,14 +12,14 @@
* of the corresponding IO address region, but at offset 5 and 6. */

/*
* u8 pnp_read_hwm5_index(u16 port, u8 reg)
* u8 pnp_read_hwm5_index(u16 base, u8 reg)
* Description:
* This routine reads indexed I/O registers. The reg byte is written
* to the index register at I/O address = port + 5. The result is then
* read from the data register at I/O address = port + 6.
* to the index register at I/O address = base + 5. The result is then
* read from the data register at I/O address = base + 6.
*
* Parameters:
* @param[in] u16 base = The I/O address of the port index register.
* @param[in] u16 base = The I/O address of the base index register.
* @param[in] u8 reg = The offset within the indexed space.
* @param[out] u8 result = The value read back from the data register.
*/
Expand All @@ -29,14 +29,14 @@ static inline u8 pnp_read_hwm5_index(u16 base, u8 reg)
}

/*
* void pnp_write_hwm5_index(u16 port, u8 reg, u8 value)
* void pnp_write_hwm5_index(u16 base, u8 reg, u8 value)
* Description:
* This routine writes indexed I/O registers. The reg byte is written
* to the index register at I/O address = port + 5. The value byte is then
* written to the data register at I/O address = port + 6.
* to the index register at I/O address = base + 5. The value byte is then
* written to the data register at I/O address = base + 6.
*
* Parameters:
* @param[in] u16 base = The address of the port index register.
* @param[in] u16 base = The address of the base index register.
* @param[in] u8 reg = The offset within the indexed space.
* @param[in] u8 value = The value to be written to the data register.
*/
Expand All @@ -45,4 +45,32 @@ static inline void pnp_write_hwm5_index(u16 base, u8 reg, u8 value)
pnp_write_index(base + 5, reg, value);
}

/*
* void pnp_unset_and_set_hwm5_index(u16 base, u8 reg, u8 unset, u8 set)
* Description:
* This routine unsets and sets bits from indexed I/O registers. The
* reg byte is written to the index register at I/O address = base + 5.
* The value byte to update is data register at I/O address = base + 6.
*
* Unlike and-then-or style operations, no bitwise negation is necessary
* to specify the bits to unset. Because the bitwise negation implicitly
* promotes operands to int before operating, one may have to explicitly
* downcast the result if the data width is smaller than that of an int.
* Since warnings are errors in coreboot, explicit casting is necessary.
*
* Performing said negation inside this routine alleviates this problem,
* while allowing the compiler to warn if the input parameters overflow.
* Casting outside this function would silence valid compiler warnings.
*
* Parameters:
* @param[in] u16 base = The address of the base index register.
* @param[in] u8 reg = The offset within the indexed space.
* @param[in] u8 unset = Bitmask with ones to the bits to unset from the data register.
* @param[in] u8 set = Bitmask with ones to the bits to set from the data register.
*/
static inline void pnp_unset_and_set_hwm5_index(u16 base, u8 reg, u8 unset, u8 set)
{
pnp_unset_and_set_index(base + 5, reg, unset, set);
}

#endif /* DEVICE_PNP_HWM5_CONF_H */
29 changes: 16 additions & 13 deletions src/include/symbols.h
View file
Expand Up @@ -13,8 +13,20 @@ extern u8 _dram[];
extern u8 _##name[]; \
extern u8 _e##name[];

/*
* Regions can be declared optional if not all configurations provide them in
* memlayout and you want code to be able to check for their existence at
* runtime. Not every region that is architecture or platform-specific should
* use this -- only declare regions optional if the code *accessing* them runs
* both on configurations that have the region and those that don't. That code
* should then check (REGION_SIZE(name) != 0) before accessing it.
*/
#define DECLARE_OPTIONAL_REGION(name) \
__weak extern u8 _##name[]; \
__weak extern u8 _e##name[];

DECLARE_REGION(sram)
DECLARE_REGION(timestamp)
DECLARE_OPTIONAL_REGION(timestamp)
DECLARE_REGION(preram_cbmem_console)
DECLARE_REGION(cbmem_init_hooks)
DECLARE_REGION(stack)
Expand Down Expand Up @@ -53,24 +65,15 @@ DECLARE_REGION(ramstage)

DECLARE_REGION(pagetables)
DECLARE_REGION(ttb)
DECLARE_REGION(ttb_subtables)
DECLARE_OPTIONAL_REGION(ttb_subtables)
DECLARE_REGION(dma_coherent)
DECLARE_REGION(soc_registers)
DECLARE_REGION(framebuffer)
DECLARE_REGION(pdpt)
DECLARE_REGION(opensbi)
DECLARE_REGION(bl31)
DECLARE_OPTIONAL_REGION(opensbi)
DECLARE_OPTIONAL_REGION(bl31)
DECLARE_REGION(transfer_buffer)

/*
* Put this into a .c file accessing a linker script region to mark that region
* as "optional". If it is defined in memlayout.ld (or anywhere else), the
* values from that definition will be used. If not, start, end and size will
* all evaluate to 0. (We can't explicitly assign the symbols to 0 in the
* assembly due to https://sourceware.org/bugzilla/show_bug.cgi?id=1038.)
*/
#define DECLARE_OPTIONAL_REGION(name) asm (".weak _" #name ", _e" #name)

/* Returns true when pre-RAM symbols are known to the linker.
* (Does not necessarily mean that the memory is accessible.) */
static inline int preram_symbols_available(void)
Expand Down
5 changes: 2 additions & 3 deletions src/lib/Kconfig
View file
Expand Up @@ -30,12 +30,11 @@ config FLATTENED_DEVICE_TREE
Selected by features that require to parse and manipulate a flattened
devicetree in ramstage.

config GENERIC_SPD_BIN
config HAVE_SPD_IN_CBFS
bool
help
If enabled, add support for adding spd.hex files in cbfs as spd.bin
and locating it runtime to load SPD. Additionally provide provision to
fetch SPD over SMBus.
and locating it runtime to load SPD.

config DIMM_MAX
int
Expand Down
13 changes: 7 additions & 6 deletions src/lib/Makefile.inc
View file
Expand Up @@ -68,10 +68,7 @@ verstage-y += libgcc.c
verstage-y += memcmp.c
verstage-y += string.c

# TODO: Remove this when PSP bootblock timestamps are implemented.
ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),)
verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
endif
verstage-y += boot_device.c
verstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c

Expand Down Expand Up @@ -354,20 +351,24 @@ endif # CONFIG_RAMSTAGE_LIBHWBASE
romstage-y += spd_bin.c
ramstage-y += spd_bin.c

ifeq ($(CONFIG_GENERIC_SPD_BIN),y)
ifeq ($(CONFIG_HAVE_SPD_IN_CBFS),y)
LIB_SPD_BIN = $(obj)/spd.bin

LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)

# Include spd ROM data
$(LIB_SPD_BIN): $(LIB_SPD_DEPS)
test -n "$(SPD_SOURCES)" || \
(echo "HAVE_SPD_BIN_IN_CBFS is set but SPD_SOURCES is empty" && exit 1)
test -n "$(LIB_SPD_DEPS)" || \
(echo "SPD_SOURCES is set but no SPD file was found" && exit 1)
for f in $(LIB_SPD_DEPS); \
do for c in $$(cat $$f | grep --binary-files=text -v ^#); \
do printf $$(printf '\%o' 0x$$c); \
do printf $$(printf '\\%o' 0x$$c); \
done; \
done > $@

cbfs-files-$(CONFIG_GENERIC_SPD_BIN) += spd.bin
cbfs-files-y += spd.bin
spd.bin-file := $(LIB_SPD_BIN)
spd.bin-type := spd
endif
Expand Down
4 changes: 1 addition & 3 deletions src/lib/bootblock.c
View file
Expand Up @@ -10,8 +10,6 @@
#include <symbols.h>
#include <timestamp.h>

DECLARE_OPTIONAL_REGION(timestamp);

__weak void bootblock_mainboard_early_init(void) { /* no-op */ }
__weak void bootblock_soc_early_init(void) { /* do nothing */ }
__weak void bootblock_soc_init(void) { /* do nothing */ }
Expand All @@ -25,7 +23,7 @@ __weak void bootblock_mainboard_init(void) { /* do nothing */ }
* entered from C code. This function assumes that the timer has already been
* initialized, so it does not call init_timer().
*/
static void bootblock_main_with_timestamp(uint64_t base_timestamp,
void bootblock_main_with_timestamp(uint64_t base_timestamp,
struct timestamp_entry *timestamps, size_t num_timestamps)
{
/* Initialize timestamps if we have TIMESTAMP region in memlayout.ld. */
Expand Down
4 changes: 4 additions & 0 deletions src/lib/fmap.c
View file
Expand Up @@ -46,6 +46,10 @@ static void setup_preram_cache(struct mem_region_device *cache_mrdev)
if (CONFIG(NO_FMAP_CACHE))
return;

/* No need to use FMAP cache in SMM */
if (ENV_SMM)
return;

if (!ENV_ROMSTAGE_OR_BEFORE) {
/* We get here if ramstage makes an FMAP access before calling
cbmem_initialize(). We should avoid letting it come to that,
Expand Down
37 changes: 37 additions & 0 deletions src/lib/fw_config.c
View file
@@ -1,11 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <assert.h>
#include <bootstate.h>
#include <cbfs.h>
#include <console/console.h>
#include <device/device.h>
#include <ec/google/chromeec/ec.h>
#include <fw_config.h>
#include <lib.h>
#include <stdbool.h>
#include <stdint.h>

Expand Down Expand Up @@ -66,6 +68,40 @@ bool fw_config_probe(const struct fw_config *match)
}

#if ENV_RAMSTAGE

/*
* The maximum number of fw_config fields is limited by the 32-bit mask that is used to
* represent them.
*/
#define MAX_CACHE_ELEMENTS (8 * sizeof(uint32_t))

static const struct fw_config *cached_configs[MAX_CACHE_ELEMENTS];

static size_t probe_index(uint32_t mask)
{
assert(mask);
return __ffs(mask);
}

const struct fw_config *fw_config_get_found(uint32_t field_mask)
{
const struct fw_config *config;
config = cached_configs[probe_index(field_mask)];
if (config && config->mask == field_mask)
return config;

return NULL;
}

void fw_config_for_each_found(void (*cb)(const struct fw_config *config, void *arg), void *arg)
{
size_t i;

for (i = 0; i < MAX_CACHE_ELEMENTS; ++i)
if (cached_configs[i])
cb(cached_configs[i], arg);
}

static void fw_config_init(void *unused)
{
struct device *dev;
Expand All @@ -80,6 +116,7 @@ static void fw_config_init(void *unused)
for (probe = dev->probe_list; probe && probe->mask != 0; probe++) {
if (fw_config_probe(probe)) {
match = true;
cached_configs[probe_index(probe->mask)] = probe;
break;
}
}
Expand Down