diff --git a/Documentation/code_of_conduct.md b/Documentation/code_of_conduct.md
@@ -0,0 +1,112 @@
+# Code of Conduct
+
+This code of conduct outlines our rules and expectations for everybody
+participating in the coreboot community.
+
+## coreboot community etiquette
+
+We have a friendly and productive atmosphere on our mailing lists,
+development / code review tools, IRC chat rooms and when we meet in
+person.  Our principles evolve around the following:
+
+* It's not the user's fault if something goes wrong.
+* Attempt collaboration before conflict.
+* People who intentionally insult others (users, developers, corporations,
+  other projects, or the coreboot project itself) will be dealt with. See
+  policy below.
+* We are dealing with hardware with lots of undocumented pitfalls. It is quite
+  possible that you did everything right, but coreboot or its tools still
+  won't work for you.
+
+Refrain from insulting anyone or the group they belong to. Remember that
+people might be sensitive to other things than you are.
+
+Most of our community members are not native English speakers, thus
+misunderstandings can (and do) happen. Always assume that others are
+friendly and may have picked less-than-stellar wording by accident.
+
+If you have a grievance due to conduct in this community, we want to hear
+about it so we can handle the situation. Please contact our arbitration
+team directly: They will listen to you and react in a timely fashion.
+
+For transparency there is no alias or private mailing list address for
+you to reach out to, since we want to make sure that you know who will
+(and who won't) read your message.
+
+However since people might be on travel or otherwise be unavailable at
+times, consider reaching out to multiple persons.
+
+The team will treat your messages confidential as far as the law permits.
+For the purpose of knowing what law applies, the list provides the usual
+country of residence of each team member.
+
+## Unacceptable Behavior
+
+Unacceptable behaviors include: intimidating, harassing, abusive,
+discriminatory, derogatory or demeaning speech or actions by any
+participant in our community online, at all related events and in
+one-on-one communications carried out in the context of community
+business. Community event venues may be shared with members of the public;
+please be respectful to all patrons of these locations.
+
+Examples of behaviors we do not accept in our community:
+
+* harmful or prejudicial verbal or written comments related to gender,
+  sexual orientation, race, religion, disability;
+* inappropriate physical contact, and unwelcome sexual advances;
+* deliberate intimidation, stalking or following;
+* harassing photography or recording;
+* sustained disruption of talks or other events.
+
+Using this code of conduct aggressively against other people in the
+community might also be harassment. Be considerate when enforcing the code
+of conduct and always try to listen to both sides before passing judgment.
+
+## Consequences of Unacceptable Behavior
+
+Unacceptable behavior from any community member, including sponsors and
+those with decision-making authority, will not be tolerated.
+
+Anyone asked to stop unacceptable behavior is expected to comply
+immediately.
+
+If a community member engages in unacceptable behavior, the community
+organizers may take any action they deem appropriate, up to and including
+a temporary ban or permanent expulsion from the community without warning
+(and without refund in the case of a paid event). Community organizers
+can be part of the arbitration team, or organizers of events and online
+communities.
+
+## If You Witness or Are Subject to Unacceptable Behavior
+
+If you are subject to or witness unacceptable behavior, or have any other
+concerns, please notify someone from the arbitration team immediately.
+
+
+## Addressing Grievances
+
+If you feel you have been falsely or unfairly accused of violating this
+Code of Conduct, you should notify the arbitration team with a concise
+description of your grievance.
+
+## Scope
+
+We expect all community participants (contributors, paid or otherwise;
+sponsors; and other guests) to abide by this Code of Conduct in all
+community venues, online and in-person, as well as in all one-on-one
+communications pertaining to community business.
+
+## Contact info
+
+Our arbitration team consists of the following people
+* Stefan Reinauer <stefan.reinauer@coreboot.org> (USA)
+* Patrick Georgi <patrick@coreboot.org> (Germany)
+* Ronald Minnich <rminnich@coreboot.org> (USA)
+* Marc Jones <mjones@coreboot.org> (USA)
+
+## License and attribution
+
+This Code of Conduct is distributed under
+a [Creative Commons Attribution-ShareAlike
+license](http://creativecommons.org/licenses/by-sa/3.0/).  It is based
+on the [Citizen Code of Conduct](http://citizencodeofconduct.org/)
diff --git a/Documentation/flash_tutorial/index.md b/Documentation/flash_tutorial/index.md
@@ -63,15 +63,21 @@ possible methods:
 **WARNING:** Using the wrong method or accidentally using the wrong pinout might
   permanently damage your hardware!
 
+**WARNING:** Do not rely on dots *painted* on flash ICs to orient the pins!
+Any dots painted on flash ICs may only indicate if they've been tested.  Dots
+that appear in datasheets to indicate pin 1 correspond to some kind of physical
+marker, such as a drilled hole, or one side being more flat than the other.
+
 ## Using a layout file
 On platforms where the flash IC is shared with other components you might want
 to write only a part of the flash IC. On Intel for example there are IFD, ME and
 GBE which don't need to be updated to install coreboot.
 To make [flashrom] only write the *bios* region, leaving Intel ME and Intel IFD
-untouched, you can use a layout file, which can be created using ifdtool
+untouched, you can use a layout file, which can be created with ifdtool and a backup
+of the original firmware.
 
 ```bash
-ifdtool -f rom.layout coreboot.rom
+ifdtool -f rom.layout backup.rom
 ```
 
 and looks similar to:

diff --git a/Documentation/getting_started/gerrit_guidelines.md b/Documentation/getting_started/gerrit_guidelines.md
@@ -150,24 +150,28 @@ together so people can easily see the connection at the top level of
 gerrit. Topics can be set for individual patches in gerrit by going into
 the patch and clicking on the icon next to the topic line. Topics can also
 be set when you push the patches into gerrit. For example, to push a set of
-commits with the the i915-kernel-x60 set, use the command:
-        git push origin HEAD:refs/for/master/i915-kernel-x60
+commits with the i915-kernel-x60 set, use the command:
+        git push origin HEAD:refs/for/master%topic=i915-kernel-x60
 
 * If one of your patches isn't ready to be merged, make sure it's obvious
 that you don't feel it's ready for merge yet. The preferred way to show
 this is by marking in the commit message that it’s not ready until X. The
 commit message can be updated easily when it’s ready to be pushed.
 Examples of this are "WIP: title" or "[NEEDS_TEST]: title".  Another way to
 mark the patch as not ready would be to give it a -1 or -2 review, but
-isn't as obvious as the commit message. These patches can also be pushed as
-drafts as shown in the next guideline.
+isn't as obvious as the commit message. These patches can also be pushed with
+the wip flag:
+	git push origin HEAD:refs/for/master%wip
 
 * When pushing patches that are not for submission, these should be marked
 as such. This can be done in the title ‘[DONOTSUBMIT]’, or can be pushed as
-draft commits, so that only explicitly added reviewers will see them. These
+private changes, so that only explicitly added reviewers will see them. These
 sorts of patches are frequently posted as ideas or RFCs for the community
-to look at. To push a draft, use the command:
-        git push origin HEAD:refs/for/master%private,wip
+to look at. To push a private change, use the command:
+        git push origin HEAD:refs/for/master%private
+
+* Multiple push options can be combined:
+        git push origin HEAD:refs/for/master%private,wip,topic=experiment
 
 * Respond to anyone who has taken the time to review your patches, even if
 it's just to say that you disagree. While it may seem annoying to address a

diff --git a/Documentation/index.md b/Documentation/index.md
@@ -9,6 +9,7 @@ Contents:
 
 * [Getting Started](getting_started/index.md)
 * [Rookie Guide](lessons/index.md)
+* [Code of Conduct](code_of_conduct.md)
 * [Timestamps](timestamp.md)
 * [Intel IFD Binary Extraction](Binary_Extraction.md)
 * [Dealing with Untrusted Input in SMM](technotes/2017-02-dealing-with-untrusted-input-in-smm.md)

diff --git a/Documentation/lessons/lesson2.md b/Documentation/lessons/lesson2.md
@@ -60,24 +60,29 @@ just generated.
 
 ## Part 3: Clone coreboot and configure it for submitting patches
 
-Go to the **Projects** tab in the upper left corner and select **List**.
-From the dropdown menu that appears, select "coreboot".
+On Gerrit, click on the **Browse** tab in the upper left corner and select
+**Repositories**.  From the listing, select the "coreboot" repo.  You may have
+to click the next page arrow at the bottom a few times to find it.
 
-If you are using SSH keys, select **ssh** from the tabs under "Project coreboot"
-and run the command that appears. This should prompt you for your id_rsa passphrase,
-if you previously set one.
+If you are using SSH keys, select **ssh** from the tabs under "Project
+coreboot" and run the "clone with commit-msg hook" command that's provided.
+This should prompt you for your id_rsa passphrase, if you previously set one.
 
 If you are using HTTP, instead, select **http** from the tabs under "Project coreboot"
 and run the command that appears
 
-After it finishes cloning, "cd coreboot" will take you into the local
-git repository. Run "make gitconfig" to set up the hooks and configurations.
-For example, you will be asked to run the following commands to set your
-username and email.
+Now is a good time to configure your global git identity, if you haven't
+already.
 
 	git config --global user.name "Your Name"
 	git config --global user.email "Your Email"
 
+Finally, enter the local git repository and set up repository specific hooks
+and other configurations.
+
+	cd coreboot
+	make gitconfig
+
 ## Part 4: Submit a commit
 
 An easy first commit to make is fixing existing checkpatch errors and warnings
@@ -148,6 +153,11 @@ coreboot.org. **Note:** To submit as a draft, use
 your commit will be on coreboot.org, but is only visible to those you add
 as reviewers.
 
+This has been a quick primer on how to submit a change to Gerrit for review
+using git.  You may wish to review the [Gerrit code review workflow
+documentation](https://gerrit-review.googlesource.com/Documentation/intro-user.html#code-review),
+especially if you plan to work on multiple changes at the same time.
+
 ## Part 4b: Using git cola to stage and submit a commit
 
 If git cola is not installed on your machine, see
@@ -209,7 +219,7 @@ only visible to those you add as reviewers.
 
 ## Part 5: Getting your commit reviewed
 
-Your commits can now be seen on review.coreboot.org if you select “My”
+Your commits can now be seen on review.coreboot.org if you select “Your”
 and click on “Changes” and can be reviewed by others. Your code will
 first be reviewed by build bot (Jenkins), which will either give you a warning
 or verify a successful build; if so, your commit will receive a +1. Other
@@ -278,4 +288,4 @@ next to checkout by clicking **Copy to clipboard**. Then, run the copied
 command in your coreboot repository. Now, the last commit should be the most
 recent commit to that patch; to update it, make your desired changes, stage
 the files, then amend and push the commit using the instructions in the above
-paragraph.
+paragraph.
diff --git a/Documentation/lib/payloads/fit.md b/Documentation/lib/payloads/fit.md
@@ -25,7 +25,7 @@ The section must be named in order to be found by the FIT parser:
 
 The FIT parser needs architecure support.
 ### aarch64
-The source code can be found in `src/arch/arm64/fit.c`.
+The source code can be found in `src/arch/arm64/fit_payload.c`.
 
 On aarch64 the kernel (a section named 'kernel') must be in **Image**
 format and it needs a devicetree (a section named 'fdt') to boot.

diff --git a/Documentation/mainboard/asrock/h81m-hds.md b/Documentation/mainboard/asrock/h81m-hds.md
@@ -4,24 +4,10 @@ This page describes how to run coreboot on the [ASRock H81M-HDS].
 
 ## Required proprietary blobs
 
-This board currently requires a proprietary blob in order to initialise
-the RAM and a few other components. The blob largely consists of Intel's
-Memory Reference Code (shortened to mrc), and is just under 200 KiB
-in size. It is also known as a system agent binary. Unfortunately,
-it is not currently possible to distribute this as part of coreboot.
-However, the mrc can be obtained from a Haswell Chromebook firmware
-image, and you might find one online. The mrc from a ChromeOS image can
-be extracted with the following command. If extracting from a "standard"
-coreboot image, omit `-r RO_SECTION`.
-
-```bash
-cbfstool coreboot.rom extract -f mrc.bin -n mrc.bin -r RO_SECTION
+```eval_rst
+Please see :doc:`../../northbridge/intel/haswell/mrc.bin`.
 ```
 
-Now, place mrc.bin in the root of the coreboot directory.
-Alternatively, place it anywhere you want, and set `MRC_FILE` to its
-location when building coreboot.
-
 ## Building coreboot
 
 A fully working image should be possible just by setting your MAC
@@ -81,9 +67,6 @@ facing towards the bottom of the board.
 
 ## Known issues
 
-- PCIe graphics is non-functional. The PCIe 16x slot doesn't work
-  with other devices, either.
-
 - The VGA port doesn't work until the OS reinitialises the display.
 
 - There is no automatic, OS-independent fan control. This is because
@@ -92,6 +75,10 @@ facing towards the bottom of the board.
   in coreboot. The `coretemp` driver can still be used for accurate CPU
   temperature readings from an OS.
 
+```eval_rst
+Please also see :doc:`../../northbridge/intel/haswell/known-issues`.
+```
+
 ## Untested
 
 - parallel port
@@ -108,7 +95,7 @@ facing towards the bottom of the board.
 - S3 suspend/resume
 - Gigabit Ethernet
 - integrated graphics
-- PCIe (but not the 16x slot, see [Known issues](#known-issues))
+- PCIe
 - SATA
 - PS/2 mouse
 - serial port
@@ -126,7 +113,7 @@ facing towards the bottom of the board.
 
 ```eval_rst
 +------------------+--------------------------------------------------+
-| Northbridge      | Intel Haswell                                    |
+| Northbridge      | :doc:`../../northbridge/intel/haswell/index`     |
 +------------------+--------------------------------------------------+
 | Southbridge      | Intel Lynx Point (H81)                           |
 +------------------+--------------------------------------------------+

diff --git a/Documentation/mainboard/google/dragonegg.md b/Documentation/mainboard/google/dragonegg.md
@@ -0,0 +1,40 @@
+# Google Dragonegg (Chromebook)
+
+This page describes how to run coreboot on the google dragonegg board.
+
+Dragonegg is based on Intel Ice Lake platform, please refer to below link to get more details
+```eval_rst
+:doc:`../../soc/intel/icelake/iceLake_coreboot_development`
+```
+
+## Building coreboot
+
+* Follow build instructions mentioned in Ice Lake document
+```eval_rst
+:doc:`../../soc/intel/icelake/iceLake_coreboot_development`
+```
+
+* The default options for this board should result in a fully working image:
+```bash
+	# echo "CONFIG_VENDOR_GOOGLE=y" > .config
+	# echo "CONFIG_BOARD_GOOGLE_DRAGONEGG=y" >> .config
+	# make olddefconfig && make
+```
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | no         |
++---------------------+------------+
+| Vendor              | Winbond    |
++---------------------+------------+
+| Size                | 32 MiB     |
++---------------------+------------+
+| Internal flashing   | yes        |
++---------------------+------------+
+| External flashing   | yes        |
++---------------------+------------+
+```
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
@@ -23,6 +23,8 @@ The boards in this section are not real mainboards, but emulators.
 ## Intel
 
 - [DG43GT](intel/dg43gt.md)
+- [IceLake RVP](intel/icelake_rvp.md)
+- [KBLRVP11](intel/kblrvp11.md)
 
 ## Foxconn
 
@@ -32,6 +34,10 @@ The boards in this section are not real mainboards, but emulators.
 
 - [GA-H61M-S2PV](gigabyte/ga-h61m-s2pv.md)
 
+## Google
+
+- [Dragonegg](google/dragonegg.md)
+
 ## Open Cellular
 
 - [Elgon](opencellular/elgon.md)
@@ -55,7 +61,12 @@ The boards in this section are not real mainboards, but emulators.
 - [T530](lenovo/w530.md)
 - [W530](lenovo/w530.md)
 - [T430 / T530 / X230 / W530 common](lenovo/xx30_series.md)
+- [T431s](lenovo/t431s.md)
 
 ## SiFive
 
 - [SiFive HiFive Unleashed](sifive/hifive-unleashed.md)
+
+## Supermicro
+
+- [X10SLM+-F](supermicro/x10slm-f.md)
diff --git a/Documentation/mainboard/intel/icelake_rvp.md b/Documentation/mainboard/intel/icelake_rvp.md
@@ -0,0 +1,40 @@
+# Intel Ice Lake RVP (Reference Validation Platform)
+
+This page describes how to run coreboot on the Intel icelake_rvp board.
+
+Ice Lake RVP is based on Intel Ice Lake platform, please refer to below link to get more details
+```eval_rst
+:doc:`../../soc/intel/icelake/iceLake_coreboot_development`
+```
+
+## Building coreboot
+
+* Follow build instructions mentioned in Ice Lake document
+```eval_rst
+:doc:`../../soc/intel/icelake/iceLake_coreboot_development`
+```
+
+* The default options for this board should result in a fully working image:
+```bash
+	# echo "CONFIG_VENDOR_INTEL=y" > .config
+	# echo "CONFIG_BOARD_INTEL_ICELAKE_RVPU=y" >> .config
+	# make olddefconfig && make
+```
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | no         |
++---------------------+------------+
+| Vendor              | Winbond    |
++---------------------+------------+
+| Size                | 32 MiB     |
++---------------------+------------+
+| Internal flashing   | yes        |
++---------------------+------------+
+| External flashing   | yes        |
++---------------------+------------+
+```
diff --git a/Documentation/mainboard/intel/kblrvp11.md b/Documentation/mainboard/intel/kblrvp11.md
@@ -0,0 +1,79 @@
+# Intel Kaby lake RVP11
+
+## Specs
+
+* 1 SATA cable connect
+* 1 SATAe direct
+* 2 USB2.0 connector
+* 4 USB3.0 connector
+* 1 Gigabit Ethernet
+* 1 x4 PCIe slot
+* 1 x1 PCIe slot
+* 1 X16 PEG slot
+* UART debug DB9 connector
+* 4 DIMMS with DDR4 memory
+* SPI flash
+* Audio Jack
+* PS2 Keyboard and Mouse
+* Display: HDMI, DP, VGA
+
+## Target Audience
+
+* OEMs, internal only
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | no         |
++---------------------+------------+
+| Vendor              | Winbond    |
++---------------------+------------+
+| Model               | W25Q128FV  |
++---------------------+------------+
+| Size                | 16 MiB     |
++---------------------+------------+
+| Package             | SOIC-8     |
++---------------------+------------+
+| Write protection    | No         |
++---------------------+------------+
+| Dual BIOS feature   | No         |
++---------------------+------------+
+```
+
+### Instruction to flash coreboot to SPI
+
+### Internal programming
+
+The SPI flash can be accessed internally using [flashrom].
+The following command is used to flash BIOS region.
+
+```bash
+$ flashrom -p internal --ifd -i bios -w coreboot.rom --noverify-all
+```
+
+### External programming
+
+1. Dediprog SF600 with adapter B is used.
+2. Make sure power supply is disconnected from board.
+3. Connect Dediprog SF600 to header at J7H1.
+4. Ensure that "currently working on" is in "application memory chip 1"
+5. Go to "file" and select the .rom file (16 MB) to program chip1.
+6. Execute the batch operation to erase and program the chip.
+
+## Technology
+
+```eval_rst
++------------------+---------------------------------------------------+
+| CPU              | Kaby lake H (i7-7820EQ)                           |
++------------------+---------------------------------------------------+
+| PCH              | Skylake PCH-H (called SPT-H)                      |
++------------------+---------------------------------------------------+
+| Coprocessor      | Intel ME                                          |
++------------------+---------------------------------------------------+
+```
+
+[W25Q128FV]: https://www.winbond.com/resource-files/w25q128fv%20rev.m%2005132016%20kms.pdf
+[flashrom]: https://flashrom.org/Flashrom
diff --git a/Documentation/mainboard/lenovo/t420.md b/Documentation/mainboard/lenovo/t420.md
@@ -1,8 +1,17 @@
 # Lenovo T420
 
 ## Flashing instructions
-You have to disassemble the whole device, as the flash IC is on the bottom
-of the mainboard.
+The flash IC is located at the bottom center of the mainboard.  Sadly,
+access to the IC is blocked by the magnesum frame, so you need to disassemble
+the entire laptop and remove the mainboard.
+
+Below is a picture of IC on the mainboard, with the pinouts labeled.
+
+![t420_chip_location](t420_chip_location.jpg)
+
+The chip will either be a Macronix MX25L6404E (shown above) or a Winbond
+W25Q64CVSIG.  Do not rely on dots painted in the corner of the chip (such as
+the blue dot pictured) to orient the pins!
 
 For more details have a look at [T420 / T520 / X220 / T420s / W520 common] and
 

diff --git a/Documentation/mainboard/lenovo/t420_chip_location.jpg b/Documentation/mainboard/lenovo/t420_chip_location.jpg
diff --git a/Documentation/mainboard/lenovo/t431s.md b/Documentation/mainboard/lenovo/t431s.md
@@ -0,0 +1,42 @@
+# Lenovo T431s
+
+## Disassembly Instructions
+
+You must remove the following parts before flipping the mainboard
+off the main frame:
+
+![t431s_bc_removed](t431s_bc_removed.jpg)
+
+* Base cover
+* Hard disk drive
+* Battery pack
+* Keyboard
+
+Its [Hardware Maintenance Manual](https://thinkpads.com/support/hmm/hmm_pdf/t431s_hmm_en_0c10894_02.pdf) could be used as a guidance of disassembly.
+
+![t431s_flash_chip](t431s_flash_chip.jpg)
+
+The WSON-8 flash chip (surrounded with red circle in the photo above)
+sits on the opposite side of the mainboard, under a piece of insulating
+tape. If solders between the chip and soldering pads fortunately
+overflows beside the chip as tiny tin balls attached to soldering pads,
+it will be possible to use a pomona 5250 clip to hold the chip, with
+its metal tips just attached to tin balls, thus connecting the chip to
+the programmer.
+
+![t431s_programming](t431s_programming.jpg)
+
+```eval_rst
+:doc:`../../flash_tutorial/ext_power`
+```
+
+Currently, detecting the model of soldered RAM at runtime and loading
+the corresponding SPD datum from CBFS is not implemented yet. You may
+have to dump the SPD data when running the vendor firmware with
+inteltool, and replace the content of the SPD hex with what is dumped.
+
+(the mechanism may be similar to that on x1_carbon_gen1 and s230u, but
+I do not know how to find gpio ports for that, and SPD data stored in
+vendor firmware.)
+
+[T420 / T520 / X220 / T420s / W520 common]: xx20_series.md
diff --git a/Documentation/mainboard/lenovo/t431s_bc_removed.jpg b/Documentation/mainboard/lenovo/t431s_bc_removed.jpg
diff --git a/Documentation/mainboard/lenovo/t431s_flash_chip.jpg b/Documentation/mainboard/lenovo/t431s_flash_chip.jpg
diff --git a/Documentation/mainboard/lenovo/t431s_programming.jpg b/Documentation/mainboard/lenovo/t431s_programming.jpg
diff --git a/Documentation/mainboard/supermicro/x10slm-f.md b/Documentation/mainboard/supermicro/x10slm-f.md
@@ -0,0 +1,203 @@
+# Supermicro X10SLM+-F
+
+This section details how to run coreboot on the [Supermicro X10SLM+-F].
+
+## Required proprietary blobs
+
+```eval_rst
+Please see :doc:`../../northbridge/intel/haswell/mrc.bin`.
+```
+
+## Building coreboot
+
+```eval_rst
+If you haven't already, build the coreboot toolchain as described in
+:doc:`../../lessons/lesson1`.
+```
+
+A fully working image should be possible so long as you have the
+Haswell `mrc.bin` file. You can set the basic config with the following
+commands. However, it is strongly advised to use `make menuconfig`
+afterwards (or instead), so that you can see all of the settings.
+
+```bash
+make distclean # Note: this will remove your current config, if it exists.
+touch .config
+./util/scripts/config --enable VENDOR_SUPERMICRO
+./util/scripts/config --enable BOARD_SUPERMICRO_X10SLM_PLUS_F
+./util/scripts/config --enable HAVE_MRC
+make olddefconfig
+```
+
+If you don't plan on using coreboot's serial console to collect logs,
+you might want to disable it at this point (`./util/scripts/config
+--disable CONSOLE_SERIAL`). It should reduce the boot time by several
+seconds. However, a more flexible method is to change the console log
+level from within an OS using `util/nvramtool`, or with the `nvramcui`
+payload.
+
+Now, run `make` to build the coreboot image.
+
+## Flashing coreboot
+
+```eval_rst
+In addition to the information here, please see the
+:doc:`../../flash_tutorial/index`.
+```
+
+### Internal programming
+
+Under the vendor firmware, the BIOS region of the flash chip is
+write-protected. Additionally, the vendor flashing tool does not work
+with a coreboot image. So, [external programming](#external-programming)
+needs to be used when first installing coreboot. By default, coreboot is
+not configured to write-protect the BIOS region, so internal programming
+can be used thereafter.
+
+[flashrom] may be used to flash coreboot internally:
+
+```bash
+sudo flashrom -p internal --ifd -i bios --noverify-all -w coreboot.rom
+```
+
+The use of `--noverify-all` is required since the Management Engine
+region is not readable even by the host.
+
+### External programming
+
+The main firmware flash chip is an SOIC-8 package located near the CMOS
+battery and SATA ports. It should come with a sticker attached that
+states the firmware revision (e.g. "X10SLH 4.424"). The chip model is
+an N25Q128A, and the datasheet can be found [here][N25Q128A].
+
+As with [internal programming](#internal-programming), [flashrom] works
+reliably:
+
+```bash
+flashrom -p <your-programmer> --ifd -i bios -w coreboot.rom
+```
+
+For flashing to work, power to the board should be disconnected (ACPI
+G3), and power should be supplied from the external programmer. There is
+a diode attached to Vcc, so such flashing should not damage the board.
+During testing, a single X10SLM+-F has been flashed dozens of times this
+way without issue.
+
+## BMC (IPMI)
+
+This board has an ASPEED [AST2400], which has BMC functionality. The
+BMC firmware resides in a 32 MiB SOIC-16 chip just above the [AST2400].
+This chip is an MX25L25635F, whose datasheet can be found
+[here][MX25L25635F].
+
+### Removing the BMC functionality
+
+The BMC functionality on this board can be removed. If you do not need
+its features, removing the BMC functionality might increase security.
+This topic has not been widely explored, and you should only **undertake
+this process at your own risk.**
+
+There is a jumper labelled `JPB1` on the board that states the ability
+to disable the BMC. Though, pins 1 and 2 are fixed together, keeping
+the BMC enabled. It might be possible to disable the BMC by cutting the
+connection between pins 1 and 2 (and then connecting pins 2 and 3). This
+has not been tested so far.
+
+Another approach is to erase the entire BMC firmware chip. However, if
+this is done, and the board's power cycled, the voltage changes on some
+pins of the flash chip, **so it will be harder to flash it again!**
+
+To remove the firmware, connect an external programmer to the BMC
+firmware chip. Vcc should **not** be connected via the external
+programmer. The system should be turned off, but the power still
+connected (ACPI S5). Then, erase the chip with [flashrom]. Power cycle
+the board, and the BMC should no longer be active.
+
+If you erase the BMC firmware while using the **vendor BIOS**, you
+will need to cut the connection between pins 1 and 2 of `JPB1`. The
+system will stall for two minutes each time when booting, but it will
+eventually start. There is no such delay when running coreboot.
+
+## ECC DRAM
+
+```eval_rst
+ECC DRAM seems to work, but please see
+:doc:`../../northbridge/intel/haswell/mrc.bin`
+for caveats.
+```
+
+## Known issues
+
+- Broadwell CPUs are not supported. They might work with minimal changes
+  to the code, but this has not been tested.
+
+- The PCH thermal sensor doesn't yet have a driver in coreboot, so it
+  can't be used for temperature readings.
+
+- There is no automatic, OS-independent fan control. This is because
+  the super I/O hardware monitor can only obtain valid CPU temperature
+  readings from the PECI agent, but the required driver doesn't exist
+  in coreboot. The `coretemp` driver can still be used for accurate CPU
+  temperature readings from an OS, and hence the OS can do fan control.
+
+```eval_rst
+Please also see :doc:`../../northbridge/intel/haswell/known-issues`.
+```
+
+## Untested
+
+- TPM
+- PCIe (likely to work, but maybe not at Gen 3 speeds)
+- BMC (IPMI) functionality
+- internal serial port
+- chassis intrusion header
+- SATA DOM header
+- standby power header
+- serial GPIO headers
+- power supply SMBus header
+- jumpers not otherwise mentioned
+- LEDs
+
+## Working
+
+- USB
+- S3 suspend/resume
+- Gigabit Ethernet
+- SATA
+- external serial port
+- VGA graphics
+- disabling VGA graphics using the jumper
+- hiding the AST2400 using the CMOS setting
+- super I/O hardware monitor (see [Known issues](#known-issues))
+- initialisation with Haswell MRC version 1.6.1 build 2
+- flashrom under coreboot
+- Wake-on-LAN
+- front panel header
+- internal buzzer
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| CPU              | :doc:`../../northbridge/intel/haswell/index`     |
++------------------+--------------------------------------------------+
+| PCH              | Intel Lynx Point (C224)                          |
++------------------+--------------------------------------------------+
+| Super I/O        | Nuvoton NCT6776                                  |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel SPS (server version of the ME)             |
++------------------+--------------------------------------------------+
+| Coprocessor      | ASPEED AST2400                                   |
++------------------+--------------------------------------------------+
+```
+
+## Extra links
+
+- [Board manual]
+
+[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376
+[Board manual]: https://www.supermicro.com/manuals/motherboard/C224/MNL-1500.pdf
+[flashrom]: https://flashrom.org/Flashrom
+[MX25L25635F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L25635F.pdf
+[N25Q128A]: https://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/Serial%20NOR/N25Q/n25q_128mb_3v_65nm.pdf
+[Supermicro X10SLM+-F]: https://www.supermicro.com/products/motherboard/xeon/c220/x10slm_-f.cfm
diff --git a/Documentation/northbridge/intel/haswell/index.md b/Documentation/northbridge/intel/haswell/index.md
@@ -0,0 +1,12 @@
+# Intel Haswell documentation
+
+This section describes the Intel Haswell architecture as it relates to
+coreboot.
+
+## Proprietary blobs
+
+- [mrc.bin](mrc.bin.md)
+
+## Issues
+
+- [Known issues](known-issues.md)
diff --git a/Documentation/northbridge/intel/haswell/known-issues.md b/Documentation/northbridge/intel/haswell/known-issues.md
@@ -0,0 +1,28 @@
+# Known issues with Haswell
+
+These issues are specific to the Haswell architecture. For a given
+mainboard, there might be additional issues to those listed here.
+
+## PCIe graphics
+
+```eval_rst
+Using a PCIe graphics card for display output is not currently
+supported. This is because :doc:`./mrc.bin` requires workarounds to
+have such a feature working correctly.
+```
+
+However, there is a [patch on Gerrit][hsw-gfx-gerrit] that allows PCIe
+graphics to be used for display output. This patch is not guaranteed to
+be of the same level of quality as code committed to coreboot.
+
+Still, in some cases, a PCIe graphics card can be used for rendering,
+while the integrated graphics device is used for display output. This
+can be achieved under GNU/Linux by using [PRIME GPU offloading][PRIME].
+
+## PCIe 3.0
+
+Only PCIe 2.0 has been tested so far. PCIe 3.0 could potentially have
+stability issues.
+
+[PRIME]: https://wiki.archlinux.org/index.php/PRIME
+[hsw-gfx-gerrit]: https://review.coreboot.org/c/30456
diff --git a/Documentation/northbridge/intel/haswell/mrc.bin.md b/Documentation/northbridge/intel/haswell/mrc.bin.md
@@ -0,0 +1,36 @@
+# mrc.bin
+
+All Haswell boards supported by coreboot currently require a proprietary
+blob in order to initialise the DRAM and a few other components. The
+blob, named `mrc.bin`, largely consists of Intel's memory reference code
+(MRC), but it has been tailored specifically for Chrome OS. It is just
+under 200 KiB in size. Another name for `mrc.bin` is the system agent
+binary.
+
+Having a replacement for `mrc.bin` using native coreboot code is very
+much desired, but it is not an easy task.
+
+## Obtaining mrc.bin
+
+Unfortunately, it is not currently possible to distribute `mrc.bin` as
+part of coreboot. Though, it can be obtained from a Haswell Chromebook
+firmware image like so, starting in the root of the coreboot directory:
+
+```bash
+make -C util/cbfstool
+cd util/chromeos
+./crosfirmware.sh peppy
+../cbfstool/cbfstool coreboot-*.bin extract -f mrc.bin -n mrc.bin -r RO_SECTION
+```
+
+Now, place `mrc.bin` in the root of the coreboot directory.
+Alternatively, place `mrc.bin` anywhere you want, and set `MRC_FILE` to
+its location when building coreboot.
+
+## ECC DRAM
+
+When `mrc.bin` has finished executing, ECC is active on the channels
+populated with ECC DIMMs. However, `mrc.bin` was tailored specifically
+for Haswell Chromebooks and Chomeboxes, none of which support ECC DRAM.
+While ECC likely functions correctly, it is advised to further validate
+the correct operation of ECC if data integrity is absolutely critical.
diff --git a/Documentation/northbridge/intel/index.md b/Documentation/northbridge/intel/index.md
@@ -4,4 +4,5 @@ This section contains documentation about coreboot on specific Intel Northbridge
 
 ## Platforms
 
+- [Haswell](haswell/index.md)
 - [Sandy Bridge](sandybridge/index.md)
diff --git a/Documentation/releases/checklist.md b/Documentation/releases/checklist.md
@@ -0,0 +1,210 @@
+# coreboot Release Process
+
+This document describes our release process and all prerequisites to implement
+it successfully.
+
+## Purpose of coreboot releases
+Our releases aren't primarily a vehicle for code that is stable across all
+boards: The logistics of testing the more than 100 boards that are spread out
+all continents (except Antarctica, probably) on a given tree state are
+prohibitive for project of our size.
+
+Instead, the releases are regular breakpoints that serve multiple purposes:
+They support cooperation between multiple groups (corporations or otherwise)
+in that it's easier to keep source trees synchronized based on a limited set
+of commits. They allow a quick assessment of the age of any given build or
+source tree based on its git version (4.8-1234 was merged into master a few
+months after 4.8, which came out in April 2018. 4.0-21718's age is harder to
+guess).
+
+And finally we use releases to as points in time where we remove old code:
+Once we decide that a certain part of coreboot gets in the way of future
+development, we announce on the next release that we intend to remove that
+part - and everything that depends on it - after the following release.
+So removing feature FOO will be announced in release X for release
+X+1. The first commit after X+1 is fair game for such removal.
+
+Together with our 6 months release horizon, this provides time to plan
+any migrations necessary to keep older boards in the tree by bringing
+them up to current standards.
+
+## Needed credentials & authorizations
+* Website access is required to post the release files to the website.
+* IRC admin access is required to update the topic.
+* Git access rights are needed to post the tag.
+* Blog post access is needed to do the blog post.
+* A PGP key is required to sign the release tarballs and git tag.
+
+This set of required credentials implies that releases can only be done
+by a coreboot admin.
+
+## When to release
+Releases are done roughly on a 6-month schedule, ideally around end
+of April and end of October (can be a bit earlier or delay into May
+or November).
+
+We initially followed a 3 month release schedule, but we found that to
+be more frequent than was needed, so we scaled it back to twice a year.
+
+## Checklist
+### ~2 weeks prior to release
+- [ ] Announce upcoming release to mailing list, ask people to test and
+      to update release notes
+
+### ~1 week prior to release
+- [ ] Send reminder email to mailing list, ask for people to test,
+      and to update the release notes
+- [ ] Update the topic in the irc channel with the date of the upcoming
+      release
+
+### Day of release
+- [ ] Update release notes, without specifying release commit ids
+- [ ] Select a commit ID to base the release upon, announce to IRC,
+      ask for testing.
+- [ ] Test the commit selected for release
+- [ ] Run release script
+- [ ] Test the release from the actual release tarballs
+- [ ] Push signed Tag to repo
+- [ ] Announce that the release tag is done on IRC
+- [ ] Update release notes with actual commit id, push to repo
+- [ ] Upload release files to web server
+- [ ] Update download page to point to files, push to repo
+- [ ] Write and publish blog post with release notes.
+- [ ] Update the topic in the irc channel that the release is done.
+
+## Pre-Release tasks
+Announce the upcoming release to the mailing list release 2 weeks ahead
+of the planned release date.
+
+The announcement should state the planned release date, point to the
+release notes that are in the making and ask people to test the hardware
+they have to make sure it's working with the current master branch,
+from which the release will ultimately be derived from.
+
+People should also be encouraged to provide additions to the
+release notes, for example by putting them on some [collaborative
+editor](https://www.piratenpad.de).
+
+The final release notes will reside in coreboot's Documentation/releases
+directory, so asking for additions to that through the regular Gerrit
+process works as well. Note that git requires lots of conflict resolution
+on heavily edited text files though.
+
+Frequently, we will want to wait until particular things are in the
+release.  Once those are in, you can select the commit ID that you want
+to use for your release.  For the 4.6 release, we waited until we had
+time to do the release, then pulled in a few patches that we wanted
+to have in the release.  The release was based on the final of those
+patches to be pulled in.
+
+When a release candidate has been selected, announce the commit ID to
+the #coreboot irc channel, and request that it get some testing, just
+to make sure that everything is sane.
+
+## Generate the release
+After the commit for the release has been selected and verified, run the
+release script - util/release/build-release.  This will download a new
+tree, checkout the commit that you specified, download the submodules,
+create a tag, then generate and sign the tarballs.
+
+Be prepared to type in your PGP key’s passphrase.
+
+````
+usage: util/release/build-release <version> [commit id] [username] [gpg key id]
+Tags a new coreboot version and creates a tar archive
+
+version:    New version name to tag the tree with
+commit id:  check out this commit-id after cloning the coreboot tree
+username:   clone the tree using ssh://USERNAME - defaults to https://
+gpg key id: used to tag the version, and generate a gpg signature
+````
+
+After running the script, you should have a new directory for the release,
+along with 4 files - 2 tarballs, and 2 signature files.
+
+````
+drwxr-xr-x   9 martin martin      4096 Apr 30 19:57 coreboot-4.6
+-rw-r--r--   1 martin martin  29156788 Apr 30 19:58 coreboot-4.6.tar.xz
+-rw-r--r--   1 martin martin       836 Apr 30 19:58 coreboot-4.6.tar.xz.sig
+-rw-r--r--   1 martin martin   5902076 Apr 30 19:58 coreboot-blobs-4.6.tar.xz
+-rw-r--r--   1 martin martin       836 Apr 30 19:58 coreboot-blobs-4.6.tar.xz.sig
+````
+
+Here’s the command that was used to generate the 4.6 release:
+````
+% util/release/build-release 4.6 db508565 Gaumless 3E4F7DF7
+````
+
+## Test the release from the tarballs
+* Run “make what-jenkins-does” and verify that everything is building.
+* Build and test qemu
+  ````
+  cp configs/config.emulation_qemu_x86_i440fx .config; make olddefconfig; make
+  qemu-system-x86_64 -bios build/coreboot.rom -serial stdio
+  ````
+* Build and test any other platforms you can.
+* Compare the directory from the tarballs to the coreboot repo to make sure nothing went wrong.
+* Push the tag to git
+
+A good tag will look like this:
+````
+% git show 4.6
+tag 4.6
+Tagger: Martin Roth <martinroth@google.com>
+Date:   Sun Apr 30 19:48:38 2017 -0600
+
+coreboot version 4.6
+-----BEGIN PGP SIGNATURE-----
+Version: GnuPG v1
+
+iQIcBAABCQAGBQJZBpP2AAoJEBl5bCs+T333xfgQAKhilfDTzqlr3MLJC4VChbmr
+...
+678e0NzyWsyqU1Vx2rdFdLANx6hghH1R7E5ybzHHUQrhb55BoEsnQMU1oS0npnT4
+dwfLho1afk0ZLPUU1JFW
+=25y8
+-----END PGP SIGNATURE-----
+
+commit db508565d2483394b709654c57533e55eebace51 (HEAD, tag: 4.6, origin/master, origin/HEAD)
+...
+````
+
+When you used the script to generate the release, a tag was generated in the tree that was downloaded.
+From the coreboot-X.Y tree, just run: `git push -f origin <TAG (X.Y)>`
+
+You will need write access for tags to the coreboot git repo to do this.
+
+## After the release is tagged in git
+Announce that the release has been tagged - this lets people know that
+they should update their trees to grab the new tag.  Until they do this,
+the version number in build.h will still be based on the previous tag.
+
+Copy the tarballs and .sig files generated by the script to
+the coreboot server, and put them in the release directory at
+`/srv/docker/www.coreboot.org-staticfiles/releases/`
+
+````
+% sha256sum -b coreboot-*.tar.xz > sha256suma.txt # Update the sha256sum file
+% diff sha256sum.txt sha256suma.txt # make sure that the two new files are present (and that nothing else has changed)
+% mv sha256suma.txt sha256sum.txt
+````
+
+People can now see the release tarballs on the website at
+https://www.coreboot.org/releases/
+
+The downloads page is the official place to download the releases from, and it needs to be updated with links to the new release tarballs and .sig files. It can be found at https://review.coreboot.org/cgit/homepage.git/tree/downloads.html
+
+Here is an example commit to change it: https://review.coreboot.org/#/c/19515/
+
+## After the release is complete
+Post the release notes on https://blogs.coreboot.org
+
+## Making a branch
+At times we will need to create a branch, generally for patch fixes.
+When making a branch, do NOT name it the same as the release tag: X.Y - this creates trouble when trying to check it out, as git can’t tell whether you want the tag or the branch.
+Instead, name it X.Y\_branch: `git checkout 4.8; git checkout -b 4.8_branch; git push origin 4.8_branch`
+
+You can then cherry-pick changes and push them up to the branch:
+````
+git cherry-pick c6d134988c856d0025153fb885045d995bc8c397
+git push origin HEAD:refs/for/4.8_branch
+````
diff --git a/Documentation/releases/coreboot-4.10-relnotes.md b/Documentation/releases/coreboot-4.10-relnotes.md
@@ -0,0 +1,24 @@
+Upcoming release - coreboot 4.10
+===========================
+
+The 4.10 release is planned for April/May 2019
+
+Update this document with changes that should be in the release
+notes.
+* Please use Markdown.
+* See the [4.7](coreboot-4.7-relnotes.md) and [4.9](coreboot-4.9-relnotes.md)
+ release notes for the general format.
+* The chip and board additions and removals will be updated right
+before the release, so those do not need to be added.
+
+Significant changes
+-------------------
+
+### `device_t` is no more
+coreboot used to have a data type, `device_t` that changed shape depending on
+whether it is compiled for romstage (with limited memory) or ramstage (with
+unlimited memory as far as coreboot is concerned). It's an old relic from the
+time when romstage wasn't operated in Cache-As-RAM mode, but compiled with
+our romcc compiler.
+
+That data type is now gone.
diff --git a/Documentation/releases/coreboot-4.9-relnotes.md b/Documentation/releases/coreboot-4.9-relnotes.md
@@ -1,30 +1,267 @@
-Upcoming release - coreboot 4.9
+coreboot 4.9 release notes
 ==========================
 
-The 4.9 release is planned for November 2018
+The 4.9 release covers commit 532b8d5f25 to commit 7f520c8fe6
+There is a pgp signed 4.9 tag in the git repository, and a branch will
+be created as needed.
 
-Update this document with changes that should be in the release
-notes.
-* Please use Markdown.
-* See the [4.7](coreboot-4.7-relnotes.md) and [4.8](coreboot-4.8.1-relnotes.md)
- release notes for the general format.
-* The chip and board additions and removals will be updated right
-before the release, so those do not need to be added.
+In the little more than 7 months since 4.8.1 we had 175 authors commit
+2610 changes to master. The changes were, for the most part, all over
+the place, touching every part of the repository: chipsets, mainboards,
+tools, build system, documentation.
 
+In that time we also had 70 authors made their first commit to coreboot:
+Welcome and to many more!
 
+Finally, a big Thank You to all contributors who helped shape the
+coreboot project, community and code with their effort, no matter if
+through development, review, testing, documentation or by helping people
+asking questions on our venues like IRC or our mailing list.
+
+Clean up
+--------
+If there's any topic to give to this release, "clean up" might be the
+most appropriate: There was lots of effort to bring the codebase into
+compliance with our coding style, to remove old idioms that we'd like
+to retire like the overloaded `device_t` data type, and to let features
+percolate through the entire tree to bring more uniformity to its parts.
+
+For example, during the coreboot 4.4 cycle, coreboot gained the notion
+of mainboard variants to avoid duplication of code in rather similar
+mainboards.
+
+Back then, this feature was developed and used mostly for the benefit
+of Chrome OS devices, but more recently the code for various Lenovo
+Thinkpads was deduplicated in the same way.
+
+Another part of cleaning up our tree is improving our tools that help
+developers follow coding style and avoid mistakes, as well as the
+infrastructure we have for automated build tests and we've seen quite
+some activity in that space as well.
+
+Documentation
+-------------
+Since the last release we also moved the documentation into the
+repository. No need for a special wiki account to edit the documentation,
+and by colocating sources and documentation, it's easier to keep the
+latter in sync with the code, too.
+
+This effort is still under way, which is why we still host the old wiki (now
+read-only) in parallel to the [new documentation
+site](https://doc.coreboot.org) that is rendered from coreboot.git's
+Documentation/ directory.
+
+Blobs handling
+--------------
+Another big change is in our blobs handling: Given that Intel now
+provides a reasonably licensed repository with FSP binaries, we were
+able to mirror it to coreboot.org and integrate it in the build system.
+This makes it easier to have working images out of the box for devices
+that depend on Intel's proprietary init code.
+
+As usual the blobs aren't part of the coreboot tree and only downloaded
+with the `USE_BLOBS` options.
+
+Deprecations
+------------
+One of the first changes to coreboot after the 4.8 release was to remove
+boards that didn't support certain new features and were apparently
+unmaintained, as discussed in the release notes of coreboot 4.6.
+
+We didn't follow up on all plans made back then to deprecate boards more
+aggressively: The board status reporting mechanism is still rather raw
+and therefore places quite a burden on otherwise sympathetic contributors
+of build results.
+
+Also, there will be no deprecations after 4.10: Due to its slipping
+schedule, coreboot 4.9 is released rather late, and as a result 4.10
+will only see about 4 months of development. We considered that a rather
+short timeframe in which to bring old boards up to new standards, and
+so the next deprecation cycle may be announced with 4.10 to occur after
+4.11 is released, in late 2019.
 
 General changes
 ---------------
-
 * Various code cleanups
- * Removed `device_t` in favor of `struct device*` in ramstage code
- * Improve adherence to coding style
+  * Removed `device_t` in favor of `struct device*` in ramstage code
+  * Removed unnecessary include directives
+  * Improved adherence to coding style
+  * Deduplicated boards by using the variants mechanism
 * Expand use of the postcar stage
 * Add bootblock compression capability: on systems that copy the bootblock
-  from very slow flash to ERAM, allow adding a stub that decompresses the
-  bootblock into ERAM to minimize the amount of flash reads
+  from very slow flash to SRAM, allow adding a stub that decompresses the
+  bootblock into SRAM to minimize the amount of flash reads
+* Rename the POWER8 architecture port to PPC64 to reflect that it isn't limited
+  to POWER8
+* Added support for booting FIT (uImage) payloads on arm64
+* Added SPI flash write protection API
+  * Implemented on Winbond
+* Implemented TCPA log for measured boot
+* Implemented GDB support for arm64 architecture in libpayload
+* Dropped support for unmaintained code paths
+* Measured boot support
+
+Added 56 mainboards
+-------------------
+* ASROCK G41C-GS
+* ASROCK G41M-GS
+* ASROCK G41M-S3
+* ASROCK G41M-VS3 R2.0
+* ASROCK H81M-HDS
+* ASUS P5QC
+* ASUS P5QL-PRO
+* ASUS P5Q-PRO
+* ASUS P8H61-M-LX
+* ASUS P8H61-M-PRO
+* CAVIUM CN8100-SFF-EVB
+* FACEBOOK WATSON
+* FOXCONN D41S
+* GIGABYTE GA-H61M-S2PV
+* GOOGLE ALEENA
+* GOOGLE AMPTON
+* GOOGLE ARCADA
+* GOOGLE ASUKA
+* GOOGLE BOBBA
+* GOOGLE BUDDY
+* GOOGLE CAREENA
+* GOOGLE CAROLINE
+* GOOGLE CASTA
+* GOOGLE CAVE
+* GOOGLE DELAN
+* GOOGLE DRAGONEGG
+* GOOGLE FLEEX
+* GOOGLE HATCH
+* GOOGLE KARMA
+* GOOGLE KUKUI
+* GOOGLE LIARA
+* GOOGLE MEEP
+* GOOGLE RAMMUS
+* GOOGLE SARIEN
+* GOOGLE SENTRY
+* HEWLETT PACKARD HP COMPAQ 8200 ELITE SFF PC
+* INTEL COFFEELAKE RVP11
+* INTEL COFFEELAKE RVP8
+* INTEL COFFEELAKE RVPU
+* INTEL DG41WV
+* INTEL ICELAKE RVPU
+* INTEL ICELAKE RVPY
+* INTEL WHISKEYLAKE RVP
+* LENOVO T431S
+* LENOVO THINKCENTRE A58
+* LENOVO W500
+* LENOVO W530
+* OPENCELLULAR ELGON
+* OPENCELLULAR ROTUNDU
+* OPENCELLULAR SUPABRCKV1
+* SIEMENS MC-APL2
+* SIEMENS MC-APL3
+* SIEMENS MC-APL4
+* SIEMENS MC-APL5
+
+Dropped 71 mainboards
+---------------------
+* AAEON PFM-540I REVB
+* AMD DB800
+* AMD DBM690T
+* AMD F2950
+* AMD MAHOGANY
+* AMD NORWICH
+* AMD PISTACHIO
+* AMD SERENGETI-CHEETAH
+* ARTECGROUP DBE61
+* ASROCK 939A785GMH
+* ASUS A8N-E
+* ASUS A8N-SLI
+* ASUS A8V-E DELUXE
+* ASUS A8V-E SE
+* ASUS K8V-X
+* ASUS KFSN4-DRE K8
+* ASUS M2N-E
+* ASUS M2V
+* ASUS M2V MX-SE
+* BACHMANN OT200
+* BCOM WINNETP680
+* BROADCOM BLAST
+* DIGITALLOGIC MSM800SEV
+* GIGABYTE GA-2761GXDK
+* GIGABYTE M57SLI
+* GOOGLE KAHLEE
+* GOOGLE MEOWTH
+* GOOGLE PURIN
+* GOOGLE ROTOR
+* GOOGLE ZOOMBINI
+* HP DL145-G1
+* HP DL145-G3
+* IEI PCISA LX-800 R10
+* IEI PM LX2-800 R10
+* IEI PM LX-800 R11
+* INTEL COUGAR-CANYON2
+* INTEL STARGO2
+* IWILL DK8 HTX
+* JETWAY J7F2
+* JETWAY J7F4K1G2E
+* JETWAY J7F4K1G5D
+* KONTRON KT690
+* LINUTOP LINUTOP1
+* LIPPERT HURRICANE LX
+* LIPPERT LITERUNNER LX
+* LIPPERT ROADRUNNER LX
+* LIPPERT SPACERUNNER LX
+* LOWRISC NEXYS4DDR
+* MSI MS7135
+* MSI MS7260
+* MSI MS9185
+* MSI MS9282
+* NVIDIA L1-2PVV
+* SIEMENS SITEMP-G1P1
+* SUNW ULTRA40
+* SUNW ULTRA40M2
+* SUPERMICRO H8DME
+* SUPERMICRO H8DMR
+* TECHNEXION TIM5690
+* TECHNEXION TIM8690
+* TRAVERSE GEOS
+* TYAN S2912
+* VIA EPIA-CN
+* VIA EPIA-M700
+* VIA PC2500E
+* VIA VT8454C
+* WINENT MB6047
+* WINENT PL6064
+* WINNET G170
+
+CPU changes
+-----------
+* cpu/intel/model\_2065x,206ax,haswell: Switch to `POSTCAR_STAGE`
+* cpu/intel/slot\_1: Switch to different CAR setup
+* Dropped support for the FSP1.0 sandy-/ivy-bridge bootpath
+
+SoC changes
+-----------
+* Added Cavium CN81xx, Intel Ice Lake and Mediatek MT8183
+* Dropped Broadcom Cygnus, Lowrisc and Marvell mvmap2315
+
+Northbridge changes
+-------------------
+* Dropped AMD K8, VIA CN700, VIA CX700, VIA VX800 because they lack `EARLY_CBMEM` support
+* intel/e7505: Moved to `EARLY_CBMEM`
+* nb/intel/i945,e7505,pineview,x4x,gm45,i440bx: Moved to `POSTCAR_STAGE`
+* nb/intel/i440bx, e7505: Moved to `RELOCATABLE_RAMSTAGE`
+* intel/x4x: Add DDR3 support
+* nb/intel/pineview: Speed up fetching SPD
+* nb/intel/i945,gm45,x4x,pineview: Use TSEG in SMI
+
+Southbridge changes
+-------------------
+* sb/intel/i82801{g,i,j}x, lynxpoint: Use the common ACPI pirq generator
+* sb/intel/i82801{g,i,j}x: Use common code to set up SMM and for the smihandler
+* Use common functions for PMBASE configuration
+
+Payload changes
+---------------
+* Support initrd in uImage/FIT to be placed above 4GiB
+* Added documentation for uImage/FIT payloads
 
 Toolchain
 ---------
-
-* Update IASL to version 10280531
+* Update to gcc 8.1.0, binutils 2.30, IASL 20180810, clang 6
diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md
@@ -10,6 +10,12 @@ Release notes for previous releases
 * [4.7 - January 2018](coreboot-4.7-relnotes.md)
 * [4.8 - May 2018](coreboot-4.8.1-relnotes.md)
 
+The checklist contains instructions to ensure that a release covers all
+important things and provides a reliable format for tarballs, branch
+names etc.
+
+* [checklist](checklist.md)
+
 Upcoming release
 ----------------
 

diff --git a/Documentation/soc/intel/icelake/iceLake_coreboot_development.md b/Documentation/soc/intel/icelake/iceLake_coreboot_development.md
@@ -0,0 +1,72 @@
+# Intel Ice Lake coreboot development
+
+## Introduction
+
+This document captures the coreboot development strategy for Intel SoC named Ice lake.
+
+The Ice Lake processor family is the next generation Intel® Core processor family.
+These processors are built using Intel's 10 nm+ process.
+
+* [What is Ice Lake?](https://www.intel.in/content/www/in/en/design/products-and-solutions/processors-and-chipsets/ice-lake/overview.html)
+
+## Development Strategy
+
+Like any other Intel SoC, Ice Lake coreboot development is also based on "Intel common code development model".
+
+1. Intel develops initial Firmware code for Ice Lake SoC.
+
+2. Additionally provides Firmware code support for Intel Reference Platform (RVP), known as Ice lake RVP with same SoC.
+   ```eval_rst
+   :doc:`../../../mainboard/intel/icelake_rvp`
+   ```
+
+3. OEMs to design based on reference platform and make use of mainboard sample code. Dragonegg is Ice Lake based mainboard developed by Google
+   ```eval_rst
+   :doc:`../../../mainboard/google/dragonegg`
+   ```
+
+### Summary:
+* SoC is Ice Lake.
+* Reference platform is icelake_rvp.
+* OEM board is Dragonegg.
+
+## Create coreboot Image
+
+1. Clone latest coreboot code as below
+   ```bash
+   $ git clone https://review.coreboot.org/coreboot.git
+   ```
+
+2. Place blobs (ucode, me.bin and FSP packages) in appropriate locations
+
+   Note:
+   Consider the fact that ucode and ME kit for Ice Lake SoC will be available from Intel VIP site.
+   After product launch, FSP binary will be available externally as any other program.
+
+3. Create coreboot .config
+
+4. Build toolchain
+   ```bash
+   CPUS=$(nproc--ignore=1)  make  crossgcc-i386  iasl
+   ```
+
+5. Build image
+   ```bash
+   $ make # the image is generated as build/coreboot.rom
+   ```
+
+## Flashing coreboot
+
+Flashing mechanism might be different between Intel RVP (Reference Validation Platform) and Chromebooks:
+
+* Make use of dediprog while flashing coreboot image on Intel-RVP
+* For Chromebook related platform like dragonegg, one can flash via servo:
+
+```bash
+   $ dut-control spi2_vref:pp3300 spi2_buf_en:on spi2_buf_on_flex_en:on warm_reset:on
+   $ sudo flashrom -n -p ft2232_spi:type=servo-v2 -w <bios_image>
+   $ dut-control spi2_vref:off spi2_buf_en:off spi2_buf_on_flex_en:off warm_reset:off
+```
+### References
+* [flashrom](https://flashrom.org/Flashrom)
+* [Servo](https://www.chromium.org/chromium-os/servo)
diff --git a/Documentation/soc/intel/icelake/index.md b/Documentation/soc/intel/icelake/index.md
@@ -2,6 +2,10 @@
 
 This section contains documentation about coreboot on specific Intel "Ice Lake" SOCs.
 
+## Ice Lake coreboot development
+
+- [Ice Lake coreboot development](iceLake_coreboot_development.md)
+
 ## Multiprocessor Init
 
 - [Multiprocessor Init](MultiProcessorInit.md)
diff --git a/Documentation/util.md b/Documentation/util.md
@@ -18,7 +18,7 @@ Technologies, for example the Pistachio SoC. `C`
 `Yacc`
 * __board_status__ - Tools to collect logs and upload them to the board
 status repository `Bash` `Go`
-* __broadcom__ - Generate Broadcom secure boot image. `C`
+* __bucts__ - A tool to manipulate the BUC.TS bit on Intel targets. `C`
 * __cavium__ - Devicetree_convert Tool to convert a DTB to a static C
 file `Python`
 * __cbfstool__
@@ -40,6 +40,7 @@ _coreboot.org-status_ and _docs.coreboot.org_
 Controller (EC). `C`
 * __exynos__ - Computes and fills Exynos ROM checksum (for BL1 or BL2).
 `Python2`
+* __find_usbdebug__ - Help find USB debug ports
 * __futility__ - Firmware utility for signing ChromeOS images `Make`
 * __fuzz-tests__ - Create test cases that crash the jpeg code. `C`
 * __genbuild_h__ - Generate build system definitions `Shell`

diff --git a/MAINTAINERS b/MAINTAINERS
@@ -136,6 +136,7 @@ Maintainers List (try to look for most precise areas first)
 RISC-V ARCHITECTURE
 M:	Ronald Minnich <rminnich@gmail.com>
 M:	Jonathan Neuschäfer <j.neuschaefer@gmx.net>
+R:	Philipp Hug <philipp@hug.cx>
 S:	Maintained
 F:	src/arch/riscv/
 F:	src/soc/sifive/
@@ -144,11 +145,11 @@ F:	src/mainboard/emulation/*-riscv/
 F:	src/mainboard/sifive/
 F:	util/riscv/
 
-POWER8 ARCHITECTURE
+PPC64 ARCHITECTURE
 M:	Ronald Minnich <rminnich@gmail.com>
 M:	Timothy Pearson <tpearson@raptorengineeringinc.com>
 S:	Maintained
-F:	src/arch/power8/
+F:	src/arch/ppc64/
 F:	src/cpu/qemu-power8/
 F:	src/mainboard/emulation/qemu-power8/
 
@@ -163,6 +164,11 @@ M:	Patrick Rudolph <siro@das-labor.org>
 S:	Maintained
 F:	src/mainboard/lenovo/
 
+GETAC P470 MAINBOARD
+M:	Patrick Georgi <patrick@georgi.software>
+S:	Maintained
+F:	src/mainboard/getac/p470
+
 INTEL PINEVIEW CHIPSET
 M:	Damien Zammit <damien@zamaudio.com>
 S:	Odd Fixes
@@ -183,11 +189,55 @@ M:	Damien Zammit <damien@zamaudio.com>
 S:	Odd Fixes
 F:	src/mainboard/gigabyte/ga-g41m-es2l
 
+GIGABYTE GA-H61M-S2PV MAINBOARD
+M:	Angel Pons <th3fanbus@gmail.com>
+S:	Maintained
+F:	src/mainboard/gigabyte/ga-h61m-s2pv
+
 GOOGLE PANTHER MAINBOARD
 M:	Stefan Reinauer <stefan.reinauer@coreboot.org>
 S:	Supported
 F:	src/mainboard/google/panther/
 
+GOOGLE MAINBOARDS (Intel-based, legacy/inactive)
+M:	Matt DeVillier <MrChromebox@gmail.com>
+S:	Maintained
+F:	src/mainboard/google/auron/
+F:	src/mainboard/google/beltino/
+F:	src/mainboard/google/butterfly/
+F:	src/mainboard/google/cyan/
+F:	src/mainboard/google/glados/
+F:	src/mainboard/google/jecht/
+F:	src/mainboard/google/link/
+F:	src/mainboard/google/parrot/
+F:	src/mainboard/google/slippy/
+F:	src/mainboard/google/stout/
+
+OCP MAINBOARDS
+M:	Philipp Deppenwiese <zaolin.daisuki@gmail.com>
+M:	Patrick Rudolph <patrick.rudolph@9elements.com>
+S:	Supported
+F:	src/mainboard/ocp/wedge100s/
+F:	src/mainboard/ocp/monolake/
+
+OPENCELLULAR MAINBOARDS
+M:	Philipp Deppenwiese <zaolin.daisuki@gmail.com>
+M:	Patrick Rudolph <patrick.rudolph@9elements.com>
+S:	Supported
+F:	src/mainboard/opencellular/rotundu/
+F:	src/mainboard/opencellular/elgon/
+
+PURISM MAINBOARDS
+M:	Matt DeVillier <matt.devillier@puri.sm>
+S:	Supported
+F:	src/mainboard/purism
+
+SAMSUNG CHROMEOS MAINBOARDS
+M:	Matt DeVillier <MrChromebox@gmail.com>
+S:	Maintained
+F:	src/mainboard/samsung/lumpy/
+F:	src/mainboard/samsung/stumpy/
+
 INTEL MINNOWBOARD MAX MAINBOARD
 M:	Huang Jin <huang.jin@intel.com>
 M:	York Yang <york.yang@intel.com>
@@ -197,6 +247,7 @@ F:	src/mainboard/intel/minnowmax/
 INTEL FSP BAYTRAIL CHIP & CRBs
 M:	Huang Jin <huang.jin@intel.com>
 M:	York Yang <york.yang@intel.com>
+M:	Philipp Deppenwiese <zaolin.daisuki@gmail.com>
 S:	Supported
 F:	src/soc/intel/fsp_baytrail/
 F:	src/vendorcode/intel/fsp1_0/baytrail/
@@ -205,18 +256,16 @@ F:	src/mainboard/intel/bayleybay_fsp/
 
 INTEL FSP BROADWELL-DE SOC & CRB
 M:	York Yang <york.yang@intel.com>
+M:	Philipp Deppenwiese <zaolin.daisuki@gmail.com>
 S:	Supported
 F:	src/soc/intel/fsp_broadwell_de/
 F:	src/vendorcode/intel/fsp1_0/broadwell_de/
 F:	src/mainboard/intel/camelbackmountain_fsp/
 
 INTEL FSP DENVERTON-NS SOC & HARCUVAR CRB
-M:	SweeHeng Wong <swee.heng.wong@intel.com>
-M:	Jeff Daly <jeffrey.daly@intel.com>
 M:	Vanessa Eusebio <vanessa.f.eusebio@intel.com>
 M:	David Guckian <david.guckian@intel.com>
-M:	Shine Liu <shine.liu@intel.com>
-S:	Supported
+S:	Odd Fixes
 F:	src/mainboard/intel/harcuvar/
 F:	src/soc/intel/denverton_ns/
 F:	src/vendorcode/intel/fsp/fsp2_0/denverton_ns/
@@ -234,8 +283,10 @@ F:	src/mainboard/intel/mohonpeak/
 INTEL FSP 1.0
 M:	Huang Jin <huang.jin@intel.com>
 M:	York Yang <york.yang@intel.com>
+M:	Philipp Deppenwiese <zaolin.daisuki@gmail.com>
 S:	Supported
 F:	src/drivers/intel/fsp1_0/
+F:	src/vendorcode/intel/fsp1_0/broadwell_de/
 
 INTEL FSP 1.1
 M:	Lee Leahy <leroy.p.leahy@intel.com>
@@ -265,6 +316,16 @@ M:	Andrey Petrov <andrey.petrov@gmail.com>
 S:	Maintained
 F:	src/soc/intel/apollolake/
 
+ASROCK G41C-GS MAINBOARD & VARIANTS
+M:	Angel Pons <th3fanbus@gmail.com>
+S:	Maintained
+F:	src/mainboard/asrock/g41c-gs/
+
+ASROCK H81M-HDS MAINBOARD
+M:	Tristan Corrick <tristan@corrick.kiwi>
+S:	Maintained
+F:	src/mainboard/asrock/h81m-hds/
+
 ASUS KFSN4-DRE & KFSN4-DRE_K8 MAINBOARDS
 M:	Timothy Pearson <tpearson@raptorengineeringinc.com>
 S:	Supported
@@ -281,12 +342,44 @@ M:	Timothy Pearson <tpearson@raptorengineeringinc.com>
 S:	Supported
 F:	src/mainboard/asus/kgpe-d16/
 
+ASUS MAXIMUS IV GENE-Z MAINBOARD
+M:	Tristan Corrick <tristan@corrick.kiwi>
+S:	Maintained
+F:	src/mainboard/asus/maximus_iv_gene-z/
+
+ASUS P5QC PRO MAINBOARD & VARIANTS
+M:	Angel Pons <th3fanbus@gmail.com>
+S:	Maintained
+F:	src/mainboard/asus/p5qc/
+
+ASUS P8H61-M LX MAINBOARD
+M:	Tristan Corrick <tristan@corrick.kiwi>
+S:	Maintained
+F:	src/mainboard/asus/p8h61-m_lx/
+
+ASUS P8H61-M PRO MAINBOARD
+M:	Angel Pons <th3fanbus@gmail.com>
+S:	Maintained
+F:	src/mainboard/asus/p8h61-m_pro/
+
 PC ENGINES ALL MAINBOARDS
 M:	Piotr Król <piotr.krol@3mdeb.com>
 M:	Michał Żygowski <michal.zygowski@3mdeb.com>
 S:	Supported
 F:	src/mainboard/pcengines/
 
+SIEMENS MC_xxxx MAINBOARDS
+M:	Werner Zeh <werner.zeh@siemens.com>
+S:	Maintained
+F:	src/mainboard/siemens/mc_apl1/
+F:	src/mainboard/siemens/mc_bdx1/
+F:	src/mainboard/siemens/mc_tcu3/
+
+SUPERMICRO X10SLM+-F MAINBOARD
+M:	Tristan Corrick <tristan@corrick.kiwi>
+S:	Maintained
+F:	src/mainboard/supermicro/x10slm-f/
+
 AMD FAMILY10H & FAMILY15H (NON-AGESA) CPUS & NORTHBRIDGE
 M:	Timothy Pearson <tpearson@raptorengineeringinc.com>
 S:	Supported
@@ -349,12 +442,10 @@ S:	Orphaned
 F:	src/cpu/allwinner/
 F:	src/cpu/armltd/
 F:	src/cpu/ti/
-F:	src/soc/broadcom/
 F:	src/soc/marvell/
 F:	src/soc/qualcomm/
 F:	src/soc/samsung/
 F:	util/arm_boot_tools/
-F:	util/broadcom/
 F:	util/exynos/
 F:	util/ipqheader/
 
@@ -484,16 +575,22 @@ M:	Stefan Reinauer <stefan.reinauer@coreboot.org>
 M:	Martin Roth <gaumless@gmail.com>
 F:	payloads/external
 
+LINUXBOOT PAYLOAD INTEGRATION
+M:	Philipp Deppenwiese <zaolin.daisuki@gmail.com>
+M:	Marcello Sylvester Bauer <info@marcellobauer.com>
+S:	Supported
+F:	payloads/external/LinuxBoot
+
 VERIFIED BOOT 2
 M:	Aaron Durbin <adurbin@chromium.org>
-F:	src/vendorcode/google/chromeos/vboot2/
+F:	src/security/vboot/
 
 TPM SUPPORT
 M:	Philipp Deppenwiese <zaolin.daisuki@gmail.com>
+S:	Supported
 F:	src/drivers/*/tpm/
-F:	src/security/tpm12/
-F:	src/security/tpm20/
-F:	util/tss-generator/
+F:	src/security/vboot/vboot_crtm.*
+F:	src/security/tpm
 
 DOCKER
 M:	Martin Roth <gaumless@gmail.com>
@@ -535,13 +632,6 @@ MISSING: ELOG
 
 MISSING: SPI
 
-THE REST
-M:	Stefan Reinauer <stefan.reinauer@coreboot.org>
-T:	git https://review.coreboot.org/coreboot
-S:	Buried alive in mainboards
-F:	*
-F:	*/
-
 # *** Infrastructure Owners***
 # This is intended to let people know who they should contact for issues with various infrastructure pieces.
 # Hardware

diff --git a/Makefile b/Makefile
@@ -176,7 +176,7 @@ real-all: real-target
 .SECONDEXPANSION:
 .DELETE_ON_ERROR:
 
-$(KCONFIG_AUTOHEADER): $(KCONFIG_CONFIG)
+$(KCONFIG_AUTOHEADER): $(KCONFIG_CONFIG) $(objutil)/kconfig/conf
 	+$(MAKE) oldconfig
 
 # Add a new class of source/object files to the build system

diff --git a/Makefile.inc b/Makefile.inc
@@ -83,7 +83,7 @@ files_added:: build_complete
 
 #######################################################################
 # our phony targets
-PHONY+= clean-abuild coreboot build-dirs build_complete
+PHONY+= clean-abuild coreboot check-style build-dirs build_complete
 
 #######################################################################
 # root source directories of coreboot
@@ -93,7 +93,7 @@ subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*)
 subdirs-y += src/superio
 subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*)
 subdirs-y += src/cpu src/vendorcode
-subdirs-y += util/cbfstool util/sconfig util/nvramtool util/broadcom
+subdirs-y += util/cbfstool util/sconfig util/nvramtool
 subdirs-y += util/futility util/marvell util/bincfg
 subdirs-y += $(wildcard src/arch/*)
 subdirs-y += src/mainboard/$(MAINBOARDDIR)
@@ -120,7 +120,7 @@ $(foreach supported_arch,$(ARCH_SUPPORTED), \
 # values are space separated if using more than one value
 #
 # int-add:        adds an arbitrary length list of integers
-# int-subtract:   subtracts the the second of two integers from the first
+# int-subtract:   subtracts the second of two integers from the first
 # int-multiply:   multiplies an arbitrary length list of integers
 # int-divide:     divides the first integer by the second
 # int-remainder:  arithmetic remainder of the first number divided by the second
@@ -287,7 +287,7 @@ cbfs-files-processor-vsa= \
 # arg1: input
 # arg2: output
 cbfs-files-processor-defconfig= \
-	$(eval $(2): $(1) $(obj)/build.h; \
+	$(eval $(2): $(1) $(obj)/build.h $(objutil)/kconfig/conf; \
 		+printf "    CREATE     $(2) (from $(1))\n"; \
 		printf "\# This image was built using coreboot " > $(2).tmp && \
 		grep "\<COREBOOT_VERSION\>" $(obj)/build.h |cut -d\" -f2 >> $(2).tmp && \
@@ -606,6 +606,12 @@ printcrt0s:
 update:
 	dongle.py -c /dev/term/1 $(obj)/coreboot.rom EOF
 
+check-style:
+	grep "^# DESCR:" util/lint/check-style | sed "s,.*DESCR: *,,"
+	echo "========"
+	util/lint/check-style
+	echo "========"
+
 gitconfig:
 	util/gitconfig/gitconfig.sh "$(MAKE)"
 

diff --git a/configs/config.pcengines_apu1 b/configs/config.pcengines_apu1
@@ -1,16 +1,18 @@
-CONFIG_LOCALVERSION="v4.8.0.7"
+CONFIG_LOCALVERSION="v4.9.0.1"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU1=y
 CONFIG_NO_GFX_INIT=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
 CONFIG_SEABIOS_REVISION=y
-CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.7"
+CONFIG_SEABIOS_REVISION_ID="rel-1.12.0.1"
 CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder"
 CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
 CONFIG_IPXE_MASTER=y
 # CONFIG_PXE_SERIAL_CONSOLE is not set
+CONFIG_PXE_CUSTOM_BUILD_ID="12345678"
 CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
 CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
+CONFIG_USER_TPM2=y
diff --git a/configs/config.pcengines_apu2 b/configs/config.pcengines_apu2
@@ -1,18 +1,20 @@
-CONFIG_LOCALVERSION="v4.8.0.7"
+CONFIG_LOCALVERSION="v4.9.0.1"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU2=y
 CONFIG_NO_GFX_INIT=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
 CONFIG_SEABIOS_REVISION=y
-CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.7"
+CONFIG_SEABIOS_REVISION_ID="rel-1.12.0.1"
 CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
 CONFIG_IPXE_MASTER=y
 CONFIG_PXE_ROM_ID="8086,157b"
 # CONFIG_PXE_SERIAL_CONSOLE is not set
+CONFIG_PXE_CUSTOM_BUILD_ID="12345678"
 CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
 CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
 CONFIG_MEMTEST_MASTER=y
+CONFIG_USER_TPM2=y
diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu3
@@ -1,18 +1,19 @@
-CONFIG_LOCALVERSION="v4.8.0.7"
+CONFIG_LOCALVERSION="v4.9.0.1"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU3=y
 CONFIG_NO_GFX_INIT=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
 CONFIG_SEABIOS_REVISION=y
-CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.7"
+CONFIG_SEABIOS_REVISION_ID="rel-1.12.0.1"
 CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
 CONFIG_IPXE_MASTER=y
 CONFIG_PXE_ROM_ID="8086,1539"
 # CONFIG_PXE_SERIAL_CONSOLE is not set
+CONFIG_PXE_CUSTOM_BUILD_ID="12345678"
 CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
 CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
 CONFIG_MEMTEST_MASTER=y
diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_apu4
@@ -1,18 +1,19 @@
-CONFIG_LOCALVERSION="v4.8.0.7"
+CONFIG_LOCALVERSION="v4.9.0.1"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU4=y
 CONFIG_NO_GFX_INIT=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
 CONFIG_SEABIOS_REVISION=y
-CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.7"
+CONFIG_SEABIOS_REVISION_ID="rel-1.12.0.1"
 CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
 CONFIG_IPXE_MASTER=y
 CONFIG_PXE_ROM_ID="8086,1539"
 # CONFIG_PXE_SERIAL_CONSOLE is not set
+CONFIG_PXE_CUSTOM_BUILD_ID="12345678"
 CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
 CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
 CONFIG_MEMTEST_MASTER=y
diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu5
@@ -1,18 +1,20 @@
-CONFIG_LOCALVERSION="v4.8.0.7"
+CONFIG_LOCALVERSION="v4.9.0.1"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU5=y
 CONFIG_NO_GFX_INIT=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
 CONFIG_SEABIOS_REVISION=y
-CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.7"
+CONFIG_SEABIOS_REVISION_ID="rel-1.12.0.1"
 CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y
 CONFIG_BUILD_IPXE=y
 CONFIG_IPXE_MASTER=y
 CONFIG_PXE_ROM_ID="8086,1539"
 # CONFIG_PXE_SERIAL_CONSOLE is not set
+CONFIG_PXE_CUSTOM_BUILD_ID="12345678"
 CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
 CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
 CONFIG_MEMTEST_MASTER=y
+CONFIG_USER_TPM2=y
diff --git a/payloads/external/LinuxBoot/Kconfig b/payloads/external/LinuxBoot/Kconfig
@@ -1,6 +1,7 @@
 ## This file is part of the coreboot project.
 ##
 ## Copyright (C) 2017 Facebook Inc.
+## Copyright (C) 2018 9elements Cyber Security
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -16,6 +17,7 @@ if PAYLOAD_LINUXBOOT
 
 choice
 	prompt "Architecture"
+	depends on LINUXBOOT_COMPILE_KERNEL || LINUXBOOT_BUILD_INITRAMFS
 	default LINUXBOOT_X86_64
 
 config LINUXBOOT_X86_64
@@ -42,9 +44,22 @@ endchoice
 config LINUXBOOT_ARCH
 	string
 	default "amd64" if LINUXBOOT_X86_64
-	default "386" if LINUXBOOT_X86
+	default "i386" if LINUXBOOT_X86
 	default "arm64" if LINUXBOOT_ARM64
 
+comment "Linux kernel"
+
+config LINUXBOOT_COMPILE_KERNEL
+	bool "Compile kernel"
+	default n
+
+config LINUXBOOT_KERNEL_PATH
+	string "Path to kernel"
+	default "Image"
+	depends on !LINUXBOOT_COMPILE_KERNEL
+
+if LINUXBOOT_COMPILE_KERNEL
+
 choice
 	prompt "Kernel version"
 	default LINUXBOOT_KERNEL_STABLE
@@ -73,19 +88,35 @@ config LINUXBOOT_KERNEL_CONFIGFILE
 	  Add your own kernel configuration file. Otherwise a default
 	  minimal defconfig is used.
 
+config LINUXBOOT_DTB_FILE
+	string "Compiled devicetree file"
+	depends on LINUXBOOT_ARM64
+	default ""
+
+endif #LINUXBOOT_COMPILE_KERNEL
+
 config LINUX_COMMAND_LINE
 	string "Kernel command-line"
 	default ""
 	help
 	  Add your own kernel command-line arguments.
 
-config LINUXBOOT_DTB_FILE
-	string "Compiled devicetree file"
-	depends on LINUXBOOT_ARM64
-	default ""
-
 config PAYLOAD_FILE
-	default "payloads/external/LinuxBoot/linuxboot/kernel-image"
+	default "payloads/external/LinuxBoot/linuxboot/bzImage" if LINUXBOOT_COMPILE_KERNEL && ( LINUXBOOT_X86 || LINUXBOOT_X86_64 )
+	default "payloads/external/LinuxBoot/linuxboot/uImage" if LINUXBOOT_COMPILE_KERNEL && LINUXBOOT_ARM64
+	default LINUXBOOT_KERNEL_PATH if !LINUXBOOT_COMPILE_KERNEL
+
+comment "Linux initramfs"
+
+config LINUXBOOT_BUILD_INITRAMFS
+	bool "Build initramfs"
+	default n
+
+config LINUXBOOT_INITRAMFS_PATH
+	string "Path to initramfs"
+	depends on !LINUXBOOT_BUILD_INITRAMFS
+
+if LINUXBOOT_BUILD_INITRAMFS
 
 choice
 	prompt "Payload Mode"
@@ -96,6 +127,7 @@ config LINUXBOOT_UROOT
 	help
 	  Enable u-root linuxboot mode.
 	  See http://u-root.tk/ for more information.
+
 endchoice
 
 if LINUXBOOT_UROOT
@@ -104,33 +136,109 @@ choice
 	prompt "U-root version"
 	default LINUXBOOT_UROOT_MASTER
 
+config LINUXBOOT_UROOT_CUSTOM
+	bool "custom"
+	help
+	  choose a custom u-root branch
+
 config LINUXBOOT_UROOT_MASTER
 	bool "master"
 	help
 	  Latest u-root version
+
+config LINUXBOOT_UROOT_V3_0_0
+	bool "v3.0.0"
+
+config LINUXBOOT_UROOT_V2_0_0
+	bool "v2.0.0"
+
+config LINUXBOOT_UROOT_V1_0_0
+	bool "v1.0.0"
+
 endchoice
 
+config LINUXBOOT_UROOT_CHECKOUT
+	string "U-root custom branch"
+	depends on LINUXBOOT_UROOT_CUSTOM
+
 config LINUXBOOT_UROOT_VERSION
 	string
+	default LINUXBOOT_UROOT_CHECKOUT if LINUXBOOT_UROOT_CUSTOM
 	default "master" if LINUXBOOT_UROOT_MASTER
+	default "v3.0.0" if LINUXBOOT_UROOT_V3_0_0
+	default "v2.0.0" if LINUXBOOT_UROOT_V2_0_0
+	default "v1.0.0" if LINUXBOOT_UROOT_V1_0_0
 
-config LINUXBOOT_UROOT_COMMANDS
-	string "Select u-root commands"
-	default ""
+choice
+	prompt "Build format"
+	default LINUXBOOT_UROOT_BB
 	help
-	  List of additional modules to include, separated by space. Otherwise
-	  all modules of u-root are included.
+	  u-root build format (e.g. bb or source). (default "bb")
+
+config LINUXBOOT_UROOT_BB
+	bool "bb"
+
+config LINUXBOOT_UROOT_SOURCE
+	bool "source (experimental)"
+
+endchoice
+
+config LINUXBOOT_UROOT_FORMAT
+	string
+	default "bb" if LINUXBOOT_UROOT_BB
+	default "source" if LINUXBOOT_UROOT_SOURCE
 
 config LINUXBOOT_UROOT_FILES
 	string "Add files to u-root base"
-	default ""
 	help
-	  Path to directory containing root structure for embedding into the
-	  initramfs.
+	  Additional files, directories, and binaries (with their ldd dependencies) to add to archive.
+	  Can be speficified multiple times.
+
+config LINUXBOOT_UROOT_INITCMD
+	string "Init target"
+	default "init"
+	help
+	  Symlink target for /init.
+	  Can be an absolute path or a u-root command name. (default "init")
+
+config LINUXBOOT_UROOT_SHELL
+	string "default shell"
+	default "elvish"
+	help
+	  Default shell.
+	  Can be an absolute path or a u-root command name. (default "elvish")
+
+config LINUXBOOT_UROOT_COMMANDS
+	string "U-root commands"
+	default "coreboot-app"
+	help
+	  List of additional modules to include,
+	  separated by space. (default "coreboot-app")
+
+endif #LINUXBOOT_UROOT
+
+endif #LINUXBOOT_BUILD_INITRAMFS
+
+choice LINUXBOOT_INITRAMFS_COMPRESSION
+	prompt "Initramfs compression format"
+	default LINUXBOOT_INITRAMFS_COMPRESSION_XZ
+
+config LINUXBOOT_INITRAMFS_COMPRESSION_NONE
+	bool "none"
+
+config LINUXBOOT_INITRAMFS_COMPRESSION_XZ
+	bool "xz compression"
+
+endchoice
 
 config LINUX_INITRD
 	string
-	default "payloads/external/LinuxBoot/linuxboot/initramfs.cpio.xz"
+	default "payloads/external/LinuxBoot/linuxboot/initramfs_u-root.cpio" if LINUXBOOT_UROOT
+	default LINUXBOOT_INITRAMFS_PATH if !LINUXBOOT_BUILD_INITRAMFS
+
+config LINUXBOOT_INITRAMFS_SUFFIX
+	string
+	default "" if LINUXBOOT_INITRAMFS_COMPRESSION_NONE
+	default ".xz" if LINUXBOOT_INITRAMFS_COMPRESSION_XZ
 
-endif
-endif
+endif #PAYLOAD_LINUXBOOT
diff --git a/payloads/external/LinuxBoot/Makefile b/payloads/external/LinuxBoot/Makefile
@@ -1,6 +1,7 @@
 ## This file is part of the coreboot project.
 ##
 ## Copyright (C) 2017 Facebook Inc.
+## Copyright (C) 2018 9elements Cyber Security
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -12,96 +13,59 @@
 ## GNU General Public License for more details.
 ##
 
-kernel_tarball=https://cdn.kernel.org/pub/linux/kernel/v4.x/linux-$(CONFIG_LINUXBOOT_KERNEL_VERSION).tar.xz
 project_dir=linuxboot
 kernel_dir=$(project_dir)/kernel
 
 unexport $(COREBOOT_EXPORTS)
-unexport MAKEFLAGS
-
-XGCCPATH?=$(PWD)/util/crossgcc/xgcc/bin
-ifeq ($(CONFIG_LINUXBOOT_ARCH),386)
-LINUXBOOT_COMPILE?=$(XGCCPATH)/i386-linux-
-ARCH?=x86
-else ifeq ($(CONFIG_LINUXBOOT_ARCH),amd64)
-LINUXBOOT_COMPILE?=$(XGCCPATH)/x86_64-linux-
-ARCH?=x86_64
-else ifeq ($(CONFIG_LINUXBOOT_ARCH),arm64)
-LINUXBOOT_COMPILE?=$(XGCCPATH)/aarch64-linux-
-ARCH?=arm64
-endif
-
-OBJCOPY:=$(LINUXBOOT_COMPILE)objcopy
 
 all: linuxboot
 
-toolchain:
-	if [[ ! -x "$(LINUXBOOT_COMPILE)gcc" ]]; then \
-	echo "Toolchain '$(LINUXBOOT_COMPILE)*' is missing."; \
+u-root:
+	$(MAKE) -f targets/u-root.mk
+
+ifeq ($(CONFIG_LINUXBOOT_BUILD_INITRAMFS),y)
+ifeq ($(CONFIG_LINUXBOOT_UROOT),y)
+initramfs: u-root
+endif
+else
+ifneq ($(CONFIG_LINUXBOOT_INITRAMFS),)
+initramfs:
+	if [[ ! -f "$(top)/$(CONFIG_LINUXBOOT_INITRAMFS)" ]]; then \
+	echo "<< Linux initramfs '$(CONFIG_LINUXBOOT_INITRAMFS)' is missing. >>"; \
 	exit 1; \
 	fi
-
-$(kernel_dir)/.config:
-	echo "    WWW        Download Linux $(CONFIG_LINUXBOOT_KERNEL_VERSION)"
-	mkdir -p $(kernel_dir)
-ifeq ("$(wildcard $(kernel_dir)/README)","")
-	curl -s $(kernel_tarball) | tar xJ -C $(kernel_dir) --strip 1
 endif
-
-config: $(kernel_dir)/.config
-	echo "    CONFIG     Linux $(CONFIG_LINUXBOOT_KERNEL_VERSION)"
-ifneq ($(CONFIG_LINUXBOOT_KERNEL_CONFIGFILE),)
-	cp $(CONFIG_LINUXBOOT_KERNEL_CONFIGFILE) $(kernel_dir)/.config
-else ifeq ($(CONFIG_LINUXBOOT_ARCH),386)
-	cp x86/defconfig $(kernel_dir)/.config
-else ifeq ($(CONFIG_LINUXBOOT_ARCH),amd64)
-	cp x86_64/defconfig $(kernel_dir)/.config
-else ifeq ($(CONFIG_LINUXBOOT_ARCH),arm64)
-	cp arm64/defconfig $(kernel_dir)/.config
 endif
 
-ifneq (,$(filter $(CONFIG_LINUXBOOT_ARCH),386 amd64))
-$(kernel_dir)/arch/x86/boot/bzImage: config toolchain
-else ifeq ($(CONFIG_LINUXBOOT_ARCH),arm64)
-$(kernel_dir)/vmlinux: config toolchain
+initramfs_compressed: initramfs
+ifeq ($(CONFIG_LINUXBOOT_INITRAMFS_COMPRESSION_XZ),y)
+	xz --keep --force --check=crc32 --lzma2=dict=1MiB $(top)/$(CONFIG_LINUXBOOT_INITRAMFS)
 endif
-	echo "    MAKE       Kernel $(CONFIG_LINUXBOOT_KERNEL_VERSION)"
-	$(MAKE) -C $(kernel_dir) olddefconfig CROSS_COMPILE=$(LINUXBOOT_COMPILE) ARCH=$(ARCH)
-	$(MAKE) -C $(kernel_dir) -j $(CPUS) CROSS_COMPILE=$(LINUXBOOT_COMPILE) ARCH=$(ARCH)
 
-ifneq (,$(filter $(CONFIG_LINUXBOOT_ARCH),386 amd64))
-$(project_dir)/kernel-image: $(kernel_dir)/arch/x86/boot/bzImage
-	cp $< $@
-else ifeq ($(CONFIG_LINUXBOOT_ARCH),arm64)
-$(project_dir)/vmlinux.bin: $(kernel_dir)/vmlinux
-	$(OBJCOPY) -O binary $< $@
-
-$(project_dir)/target.dtb: $(PWD)/$(CONFIG_LINUXBOOT_DTB_FILE)
-	cp $< $@
-
-$(project_dir)/vmlinux.bin.lzma: $(project_dir)/vmlinux.bin
-	xz -c -k -f --format=lzma --lzma1=dict=1MiB,lc=3,lp=0,pb=3 $< > $@
-
-$(project_dir)/kernel-image: $(project_dir)/vmlinux.bin.lzma $(project_dir)/../arm64/kernel_fdt_lzma.its $(project_dir)/target.dtb $(PWD)/$(CONFIG_LINUX_INITRD)
-	cp $(project_dir)/../arm64/kernel_fdt_lzma.its $(project_dir)
-	mkimage -f $(project_dir)/kernel_fdt_lzma.its $@
+ifeq ($(CONFIG_LINUXBOOT_COMPILE_KERNEL),y)
+ifeq ($(CONFIG_LINUXBOOT_ARCH),arm64)
+kernel: initramfs
+	$(MAKE) -f targets/linux.mk
+else
+kernel:
+	$(MAKE) -f targets/linux.mk
 endif
-
-ifeq ($(CONFIG_LINUXBOOT_UROOT),y)
-$(PWD)/$(CONFIG_LINUX_INITRD):
-	$(MAKE) -f targets/u-root.mk
 else
-$(PWD)/$(CONFIG_LINUX_INITRD):
-	echo "Building without u-root support"
+kernel:
+	if [[ ! -f "$(top)/$(CONFIG_LINUXBOOT_KERNEL)" ]]; then \
+	echo "<< Linux kernel '$(CONFIG_LINUXBOOT_KERNEL)' is missing. >>"; \
+	exit 1; \
+	fi
 endif
 
-linuxboot: $(project_dir)/kernel-image $(PWD)/$(CONFIG_LINUX_INITRD)
+linuxboot: kernel initramfs_compressed
 
 clean:
 	if [ -d "$(kernel_dir)" ]; then rm -rf $(kernel_dir); fi
-	rm -f $(project_dir)/initramfs.cpio.xz
+	rm -f $(project_dir)/u-root
+	rm -f $(project_dir)/initramfs*
 
 distclean:
 	rm -rf $(project_dir)
 
-.PHONY: config patch payload clean distclean clone fetch all toolchain
+.PHONY: linuxboot kernel initramfs_compressed initramfs u-root clean distclean
diff --git a/payloads/external/LinuxBoot/arm64/kernel_fdt_lzma.its b/payloads/external/LinuxBoot/arm64/kernel_fdt_lzma.its
@@ -45,20 +45,20 @@
 			};
 		};
 		ramdisk-1 {
-                        description = "Compressed Initramfs";
-                        data = /incbin/("initramfs.cpio.xz");
-                        type = "ramdisk";
-                        arch = "arm64";
-                        os = "linux";
-                        compression = "none";
-                        load = <00000000>;
-                        entry = <00000000>;
-                        hash-1 {
-                                algo = "sha1";
-                        };
-                        hash-2 {
-                                algo = "sha256";
-                        };
+			description = "Compressed Initramfs";
+			data = /incbin/("u-initramfs");
+			type = "ramdisk";
+			arch = "arm64";
+			os = "linux";
+			compression = "none";
+			load = <00000000>;
+			entry = <00000000>;
+			hash-1 {
+				algo = "sha1";
+			};
+			hash-2 {
+				algo = "sha256";
+			};
 		};
 	};
 

diff --git a/payloads/external/LinuxBoot/targets/linux.mk b/payloads/external/LinuxBoot/targets/linux.mk
@@ -0,0 +1,95 @@
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2017 Facebook Inc.
+## Copyright (C) 2018 9elements Cyber Security
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+kernel_tarball=https://cdn.kernel.org/pub/linux/kernel/v4.x/linux-$(CONFIG_LINUXBOOT_KERNEL_VERSION).tar.xz
+project_dir=linuxboot
+kernel_dir=$(project_dir)/kernel
+
+XGCCPATH?=$(PWD)/util/crossgcc/xgcc/bin
+ifeq ($(CONFIG_LINUXBOOT_ARCH),i386)
+LINUXBOOT_COMPILE?=$(XGCCPATH)/i386-linux-
+ARCH?=x86
+else ifeq ($(CONFIG_LINUXBOOT_ARCH),amd64)
+LINUXBOOT_COMPILE?=$(XGCCPATH)/x86_64-linux-
+ARCH?=x86_64
+else ifeq ($(CONFIG_LINUXBOOT_ARCH),arm64)
+LINUXBOOT_COMPILE?=$(XGCCPATH)/aarch64-linux-
+ARCH?=arm64
+endif
+
+OBJCOPY:=$(LINUXBOOT_COMPILE)objcopy
+
+all: kernel
+
+toolchain:
+	if [[ ! -x "$(LINUXBOOT_COMPILE)gcc" ]]; then \
+	echo "Toolchain '$(LINUXBOOT_COMPILE)*' is missing."; \
+	exit 1; \
+	fi
+
+$(kernel_dir)/.config:
+	echo "    WWW        Download Linux $(CONFIG_LINUXBOOT_KERNEL_VERSION)"
+	mkdir -p $(kernel_dir)
+ifeq ("$(wildcard $(kernel_dir)/README)","")
+	curl -s $(kernel_tarball) | tar xJ -C $(kernel_dir) --strip 1
+endif
+
+config: $(kernel_dir)/.config
+	echo "    CONFIG     Linux $(CONFIG_LINUXBOOT_KERNEL_VERSION)"
+ifneq ($(CONFIG_LINUXBOOT_KERNEL_CONFIGFILE),)
+	cp $(CONFIG_LINUXBOOT_KERNEL_CONFIGFILE) $(kernel_dir)/.config
+else ifeq ($(CONFIG_LINUXBOOT_ARCH),i386)
+	cp x86/defconfig $(kernel_dir)/.config
+else ifeq ($(CONFIG_LINUXBOOT_ARCH),amd64)
+	cp x86_64/defconfig $(kernel_dir)/.config
+else ifeq ($(CONFIG_LINUXBOOT_ARCH),arm64)
+	cp arm64/defconfig $(kernel_dir)/.config
+endif
+
+ifneq (,$(filter $(CONFIG_LINUXBOOT_ARCH),i386 amd64))
+$(kernel_dir)/arch/x86/boot/bzImage: config toolchain
+else ifeq ($(CONFIG_LINUXBOOT_ARCH),arm64)
+$(kernel_dir)/vmlinux: config toolchain
+endif
+	echo "    MAKE       Kernel $(CONFIG_LINUXBOOT_KERNEL_VERSION)"
+	$(MAKE) -C $(kernel_dir) olddefconfig CROSS_COMPILE=$(LINUXBOOT_COMPILE) ARCH=$(ARCH)
+	$(MAKE) -C $(kernel_dir) -j $(CPUS) CROSS_COMPILE=$(LINUXBOOT_COMPILE) ARCH=$(ARCH)
+
+ifneq (,$(filter $(CONFIG_LINUXBOOT_ARCH),i386 amd64))
+$(project_dir)/bzImage: $(kernel_dir)/arch/x86/boot/bzImage
+	cp $< $@
+else ifeq ($(CONFIG_LINUXBOOT_ARCH),arm64)
+$(project_dir)/vmlinux.bin: $(kernel_dir)/vmlinux
+	$(OBJCOPY) -O binary $< $@
+
+$(project_dir)/target.dtb: $(PWD)/$(CONFIG_LINUXBOOT_DTB_FILE)
+	cp $< $@
+
+$(project_dir)/vmlinux.bin.lzma: $(project_dir)/vmlinux.bin
+	xz -c -k -f --format=lzma --lzma1=dict=1MiB,lc=3,lp=0,pb=3 $< > $@
+
+$(project_dir)/uImage: $(project_dir)/vmlinux.bin.lzma $(project_dir)/../arm64/kernel_fdt_lzma.its $(project_dir)/target.dtb
+	cp $(project_dir)/../arm64/kernel_fdt_lzma.its $(project_dir)
+	cp $(PWD)/$(CONFIG_LINUXBOOT_INITRAMFS)$(CONFIG_LINUXBOOT_INITRAMFS_SUFFIX) $(project_dir)/u-initramfs
+	mkimage -f $(project_dir)/kernel_fdt_lzma.its $@
+endif
+
+ifneq (,$(filter $(CONFIG_LINUXBOOT_ARCH),i386 amd64))
+kernel: $(project_dir)/bzImage
+else ifeq ($(CONFIG_LINUXBOOT_ARCH),arm64)
+kernel: $(project_dir)/uImage
+endif
+
+.PHONY: kernel config toolchain
diff --git a/payloads/external/LinuxBoot/targets/u-root.mk b/payloads/external/LinuxBoot/targets/u-root.mk
@@ -1,6 +1,7 @@
 ## This file is part of the coreboot project.
 ##
 ## Copyright (C) 2017 Facebook Inc.
+## Copyright (C) 2018 9elements Cyber Security
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -12,19 +13,27 @@
 ## GNU General Public License for more details.
 ##
 
-uroot_git_repo=https://github.com/u-root/u-root.git
-uroot_dir=$(project_dir)/go/src/github.com/u-root/u-root
+project_dir=$(shell pwd)/linuxboot
+go_path_dir=$(project_dir)/go
+uroot_bin=$(project_dir)/u-root
+uroot_package=github.com/u-root/u-root
+
 go_version=$(shell go version | sed -nr 's/.*go([0-9]+\.[0-9]+.?[0-9]?).*/\1/p' )
 go_version_major=$(shell echo $(go_version) |  sed -nr 's/^([0-9]+)\.([0-9]+)\.?([0-9]*)$$/\1/p')
 go_version_minor=$(shell echo $(go_version) |  sed -nr 's/^([0-9]+)\.([0-9]+)\.?([0-9]*)$$/\2/p')
 
-project_dir=$(shell pwd)/linuxboot
-project_name=u-root
-go_path_dir=$(shell pwd)/linuxboot/go
+uroot_args+=-build=$(CONFIG_LINUXBOOT_UROOT_FORMAT)
+uroot_args+=-initcmd $(CONFIG_LINUXBOOT_UROOT_INITCMD)
+uroot_args+=-defaultsh $(CONFIG_LINUXBOOT_UROOT_SHELL)
+ifneq (CONFIG_LINUXBOOT_UROOT_FILES,)
+uroot_args+=$(foreach file,$(CONFIG_LINUXBOOT_UROOT_FILES),-files $(PWD)/$(file))
+endif
+
+uroot_cmds=$(CONFIG_LINUXBOOT_UROOT_COMMANDS)
 
-all: build
+all: u-root
 
-check:
+version:
 ifeq ("$(go_version)","")
 	printf "\n<<Please install Golang >= 1.9 for u-root mode>>\n\n"
 	exit 1
@@ -36,59 +45,26 @@ ifeq ($(shell if [ $(go_version_minor) -lt 9 ]; then echo y; fi),y)
 	exit 1
 endif
 endif
-	mkdir -p $(project_dir)/go/src/github.com/u-root
 
-$(uroot_dir)/.git:
-	echo "    Git        Cloning u-root $(CONFIG_LINUXBOOT_UROOT_VERSION)"
-	git clone $(uroot_git_repo) $(uroot_dir)
-
-fetch: check $(uroot_dir)/.git
-	-cd "$(uroot_dir)" && git fetch origin
-
-checkout: fetch
-	cd "$(uroot_dir)" && \
-	if ! git diff --quiet _cb_checkout "$(CONFIG_LINUXBOOT_UROOT_VERSION)" -- 2>/dev/null; \
-	then \
-		printf "    CHECKOUT    $(project_name) [$(CONFIG_LINUXBOOT_UROOT_VERSION)]\n"; \
-		git checkout $$(git rev-parse HEAD) >/dev/null 2>&1; \
-		git branch -f _cb_checkout "$(CONFIG_LINUXBOOT_UROOT_VERSION)" && \
-		git checkout _cb_checkout && \
-		$(if $(project_patches), \
-		for patch in $(project_patches); do \
-			printf "    PATCH       $$patch\n"; \
-			git am --keep-cr "$$patch" || \
-				( printf "Error when applying patches.\n"; \
-				  git am --abort; exit 1; ); \
-		done;,true;) \
+get: version
+	if [ -d "$(go_path_dir)/src/$(uroot_package)" ]; then \
+	git -C $(go_path_dir)/src/$(uroot_package) checkout --quiet master; \
+	GOPATH=$(go_path_dir) go get -d -u -v $(uroot_package) || \
+	echo -e "\n<<u-root package update failed>>\n"; \
+	else \
+	GOPATH=$(go_path_dir) go get -d -u -v $(uroot_package) || \
+	(echo -e "\n<<failed to get u-root package. Please check your internet access>>\n" && \
+	exit 1); \
 	fi
 
-$(uroot_dir)/u-root: $(uroot_dir)/u-root.go
-	echo "    GO        u-root"
-	cd $(uroot_dir); GOPATH=$(go_path_dir) go build u-root.go
+checkout: get
+	git -C $(go_path_dir)/src/$(uroot_package) checkout --quiet $(CONFIG_LINUXBOOT_UROOT_VERSION)
 
-$(project_dir)/initramfs.cpio.xz: checkout $(uroot_dir)/u-root
-	echo "    MAKE       u-root $(CONFIG_LINUXBOOT_UROOT_VERSION)"
-ifneq ($(CONFIG_LINUXBOOT_UROOT_COMMANDS),)
-ifneq ($(CONFIG_LINUXBOOT_UROOT_FILES),)
-	cd $(uroot_dir); GOARCH=$(CONFIG_LINUXBOOT_ARCH) GOPATH=$(go_path_dir) ./u-root \
-	-build=bb -files $(CONFIG_LINUXBOOT_UROOT_FILES) -o $(project_dir)/initramfs.cpio \
-	$(patsubst %,cmds/%,$(CONFIG_LINUXBOOT_UROOT_COMMANDS))
-else
-	cd $(uroot_dir); GOARCH=$(CONFIG_LINUXBOOT_ARCH) GOPATH=$(go_path_dir) ./u-root \
-	-build=bb -o $(project_dir)/initramfs.cpio \
-	$(patsubst %,cmds/%,$(CONFIG_LINUXBOOT_UROOT_COMMANDS))
-endif
-else
-ifneq ($(CONFIG_LINUXBOOT_UROOT_FILES),)
-	cd $(uroot_dir); GOARCH=$(CONFIG_LINUXBOOT_ARCH) GOPATH=$(go_path_dir) ./u-root \
-	-build=bb -files $(CONFIG_LINUXBOOT_UROOT_FILES) -o $(project_dir)/initramfs.cpio coreboot-app
-else
-	cd $(uroot_dir); GOARCH=$(CONFIG_LINUXBOOT_ARCH) GOPATH=$(go_path_dir) ./u-root \
-	-build=bb -o $(project_dir)/initramfs.cpio coreboot-app
-endif
-endif
-	xz -f --check=crc32 -9 --lzma2=dict=1MiB --threads=$(CPUS) $(project_dir)/initramfs.cpio
+build: checkout
+	GOPATH=$(go_path_dir) go build -o $(uroot_bin) $(uroot_package)
 
-build: $(project_dir)/initramfs.cpio.xz
+u-root: build
+	GOARCH=$(CONFIG_LINUXBOOT_ARCH) GOPATH=$(go_path_dir) $(uroot_bin) \
+	$(uroot_args) -o $(project_dir)/initramfs_u-root.cpio $(uroot_cmds)
 
-.PHONY: build checkout fetch all check
+.PHONY: all u-root build checkout get version
diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc
@@ -37,7 +37,10 @@ ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUX_COMMAND_LINE))),)
       ADDITIONAL_PAYLOAD_CONFIG+=-C $(CONFIG_LINUX_COMMAND_LINE)
 endif
 ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUX_INITRD))),)
-      ADDITIONAL_PAYLOAD_CONFIG+=-I $(CONFIG_LINUX_INITRD)
+ifneq ($(CONFIG_LINUXBOOT_ARM64),y)
+      ADDITIONAL_PAYLOAD_CONFIG+=-I $(CONFIG_LINUX_INITRD)$(CONFIG_LINUXBOOT_INITRAMFS_SUFFIX)
+      prebuilt-files += $(strip $(call strip_quotes,$(CONFIG_LINUX_INITRD)))
+endif
 endif
 endif
 ifneq ($(strip $(call strip_quotes,$(CONFIG_PAYLOAD_OPTIONS))),)
@@ -310,28 +313,37 @@ payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG)
 	CONFIG_TTYS0_BAUD=$(CONFIG_TTYS0_BAUD) \
 	CONFIG_PXE_CUSTOM_GENERAL_H=$(CONFIG_PXE_CUSTOM_GENERAL_H) \
 	CONFIG_PXE_CUSTOM_BOOTMENU_FILE=$(CONFIG_PXE_CUSTOM_BOOTMENU_FILE) \
+	CONFIG_PXE_CUSTOM_BUILD_ID=$(CONFIG_PXE_CUSTOM_BUILD_ID) \
 	MFLAGS= MAKEFLAGS=
 
 # LinuxBoot
 
 linuxboot:
 	$(MAKE) -C payloads/external/LinuxBoot \
 		CPUS=$(CPUS) \
+		CONFIG_LINUXBOOT_ARCH=$(CONFIG_LINUXBOOT_ARCH) \
+		CONFIG_LINUXBOOT_KERNEL=$(CONFIG_PAYLOAD_FILE) \
+		CONFIG_LINUXBOOT_INITRAMFS=$(CONFIG_LINUX_INITRD) \
+		CONFIG_LINUXBOOT_INITRAMFS_SUFFIX=$(CONFIG_LINUXBOOT_INITRAMFS_SUFFIX) \
+		CONFIG_LINUXBOOT_COMPILE_KERNEL=$(CONFIG_LINUXBOOT_COMPILE_KERNEL) \
+		CONFIG_LINUXBOOT_BUILD_INITRAMFS=$(CONFIG_LINUXBOOT_BUILD_INITRAMFS) \
 		CONFIG_LINUXBOOT_KERNEL_VERSION=$(CONFIG_LINUXBOOT_KERNEL_VERSION) \
 		CONFIG_LINUXBOOT_KERNEL_CONFIGFILE=$(CONFIG_LINUXBOOT_KERNEL_CONFIGFILE) \
+		CONFIG_LINUXBOOT_INITRAMFS_COMPRESSION_XZ=$(CONFIG_LINUXBOOT_INITRAMFS_COMPRESSION_XZ) \
+		CONFIG_LINUXBOOT_UROOT=$(CONFIG_LINUXBOOT_UROOT) \
 		CONFIG_LINUXBOOT_UROOT_VERSION=$(CONFIG_LINUXBOOT_UROOT_VERSION) \
+		CONFIG_LINUXBOOT_UROOT_FORMAT=$(CONFIG_LINUXBOOT_UROOT_FORMAT) \
+		CONFIG_LINUXBOOT_UROOT_INITCMD=$(CONFIG_LINUXBOOT_UROOT_INITCMD) \
+		CONFIG_LINUXBOOT_UROOT_SHELL=$(CONFIG_LINUXBOOT_UROOT_SHELL) \
 		CONFIG_LINUXBOOT_UROOT_COMMANDS=$(CONFIG_LINUXBOOT_UROOT_COMMANDS) \
-		CONFIG_LINUXBOOT_ARCH=$(CONFIG_LINUXBOOT_ARCH) \
-		CONFIG_LINUXBOOT_UROOT=$(CONFIG_LINUXBOOT_UROOT) \
 		CONFIG_LINUXBOOT_UROOT_FILES=$(CONFIG_LINUXBOOT_UROOT_FILES) \
-		CONFIG_LINUXBOOT_DTB_FILE=$(CONFIG_LINUXBOOT_DTB_FILE) \
-		CONFIG_LINUX_INITRD=$(CONFIG_LINUX_INITRD)
+		CONFIG_LINUXBOOT_DTB_FILE=$(CONFIG_LINUXBOOT_DTB_FILE)
 
+payloads/external/LinuxBoot/linuxboot/bzImage: linuxboot
+payloads/external/LinuxBoot/linuxboot/uImage: linuxboot
+payloads/external/LinuxBoot/linuxboot/initramfs_u-root.cpio: linuxboot
 
-payloads/external/LinuxBoot/linuxboot/kernel-image: linuxboot
-payloads/external/LinuxBoot/linuxboot/initramfs.cpio.xz: linuxboot
-payloads/external/LinuxBoot/linuxboot/kernel/.config: linuxboot
-payloads/external/LinuxBoot/linuxboot/go/src/github.com/u-root/u-root/.git: linuxboot
+# Yabits
 
 payloads/external/Yabits/uefi/build/uefi.elf yabits:
 	$(MAKE) -C payloads/external/Yabits all \

diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig
@@ -5,7 +5,7 @@ choice
 	default SEABIOS_STABLE
 
 config SEABIOS_STABLE
-	bool "1.11.2"
+	bool "1.12.0"
 	help
 	  Stable SeaBIOS version
 config SEABIOS_MASTER
@@ -54,7 +54,7 @@ config SEABIOS_THREAD_OPTIONROMS
 config SEABIOS_VGA_COREBOOT
 	prompt "Include generated option rom that implements legacy VGA BIOS compatibility"
 	default y if !VENDOR_EMULATION
-	depends on !(VGA_BIOS || VGA_ROM_RUN) && (VGA_TEXT_FRAMEBUFFER || LINEAR_FRAMEBUFFER)
+	depends on !VGA_ROM_RUN && (VGA_TEXT_FRAMEBUFFER || LINEAR_FRAMEBUFFER)
 	bool
 	help
 	  coreboot can initialize the GPU of some mainboards.

diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile
@@ -1,5 +1,5 @@
 TAG-$(CONFIG_SEABIOS_MASTER)=origin/master
-TAG-$(CONFIG_SEABIOS_STABLE)=f9626ccb91e771f990fbb2da92e427a399d7d918
+TAG-$(CONFIG_SEABIOS_STABLE)=a698c8995ffb2838296ec284fe3c4ad33dfca307
 TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID)
 
 project_git_repo=https://github.com/pcengines/seabios.git

diff --git a/payloads/external/iPXE/Kconfig b/payloads/external/iPXE/Kconfig
@@ -99,5 +99,12 @@ config PXE_SERIAL_CONSOLE
 
 	  Unselect to let only SeaBIOS handle printing output.
 
+config PXE_CUSTOM_BUILD_ID
+	string "iPXE custom build_id variable"
+	default ""
+	help
+	  This option allows user to customize build_id for reproducible builds.
+	  It is 32-bit hexadecimal number without "0x" prefix.
+
 endmenu
 endif
diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile
@@ -31,6 +31,13 @@ unexport KCONFIG_SPLITCONFIG
 unexport KCONFIG_TRISTATE
 unexport KCONFIG_NEGATIVES
 
+ifneq ($(CONFIG_PXE_CUSTOM_BUILD_ID),)
+PXE_MAKE_OPTS := BUILD_ID_CMD="echo 0x$(CONFIG_PXE_CUSTOM_BUILD_ID)"
+endif
+ifneq ($(CONFIG_PXE_CUSTOM_BOOTMENU_FILE),)
+PXE_MAKE_OPTS += EMBED=./menu.ipxe
+endif
+
 all: build
 
 $(project_dir):
@@ -80,11 +87,7 @@ endif
 
 build: config
 	echo "    MAKE       $(project_name) $(TAG-y)"
-ifneq ($(CONFIG_PXE_CUSTOM_BOOTMENU_FILE),)
-	$(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom EMBED=./menu.ipxe
-else
-	$(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom
-endif
+	$(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom $(PXE_MAKE_OPTS)
 	cp $(project_dir)/src/bin/$(PXE_ROM_PCI_ID).rom $(project_dir)/ipxe.rom
 ifeq ($(CONSOLE_SERIAL),yy)
 	cp "$(project_dir)/src/config/console.h.cb" "$(project_dir)/src/config/console.h"

diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig
@@ -258,11 +258,6 @@ config IPQ40XX_SERIAL_CONSOLE
 	depends on SERIAL_CONSOLE
 	default n
 
-config BG4CD_SERIAL_CONSOLE
-	bool "Serial port driver for Marvell's BG4CD"
-	depends on SERIAL_CONSOLE
-	default n
-
 config PL011_SERIAL_CONSOLE
 	bool "PL011 compatible serial port driver"
 	depends on 8250_SERIAL_CONSOLE

diff --git a/payloads/libpayload/configs/config.purin b/payloads/libpayload/configs/config.purin
diff --git a/payloads/libpayload/curses/PDCurses/pdcurses/clear.c b/payloads/libpayload/curses/PDCurses/pdcurses/clear.c
@@ -23,7 +23,7 @@ RCSID("$Id: clear.c,v 1.35 2008/07/13 16:08:18 wmcbrine Exp $")
         every cell of the window.
 
         clear() and wclear() are similar to erase() and werase(), but
-        they also call clearok() to ensure that the the window is
+        they also call clearok() to ensure that the window is
         cleared on the next wrefresh().
 
         clrtobot() and wclrtobot() clear the window from the current

diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc
@@ -37,7 +37,6 @@ libc-$(CONFIG_LP_8250_SERIAL_CONSOLE) += serial/8250.c serial/serial.c
 libc-$(CONFIG_LP_S5P_SERIAL_CONSOLE) += serial/s5p.c serial/serial.c
 libc-$(CONFIG_LP_IPQ806X_SERIAL_CONSOLE) += serial/ipq806x.c serial/serial.c
 libc-$(CONFIG_LP_IPQ40XX_SERIAL_CONSOLE) += serial/ipq40xx.c serial/serial.c
-libc-$(CONFIG_LP_BG4CD_SERIAL_CONSOLE) += serial/bg4cd.c serial/serial.c
 libc-$(CONFIG_LP_PC_KEYBOARD) += i8042/keyboard.c
 libc-$(CONFIG_LP_PC_MOUSE) += i8042/mouse.c
 libc-$(CONFIG_LP_PC_I8042) += i8042/i8042.c
@@ -55,8 +54,6 @@ libc-y += timer/generic.c
 endif
 libc-$(CONFIG_LP_TIMER_RDTSC) += timer/rdtsc.c
 libc-$(CONFIG_LP_TIMER_IMG_PISTACHIO) += timer/img_pistachio.c
-libc-$(CONFIG_LP_TIMER_ARMADA38X) += timer/armada38x.c
-libc-$(CONFIG_LP_TIMER_MVMAP2315) += timer/mvmap2315.c
 libc-$(CONFIG_LP_TIMER_ARM64_ARCH) += timer/arm64_arch_timer.c
 
 # Video console drivers

diff --git a/payloads/libpayload/drivers/timer/Kconfig b/payloads/libpayload/drivers/timer/Kconfig
@@ -33,12 +33,6 @@ config TIMER_TEGRA_1US
 config TIMER_IPQ806X
 	bool "Timer for ipq806x platforms"
 
-config TIMER_ARMADA38X
-        bool "Timer for armada38x platforms"
-	help
-	  This is the timer driver for marvell armada38x
-	  platforms.
-
 config TIMER_IPQ40XX
 	bool "Timer for ipq40xx platforms"
 	help
@@ -56,43 +50,16 @@ config TIMER_RK3288
 config TIMER_RK3399
 	bool "Timer for Rockchip RK3399"
 
-config TIMER_CYGNUS
-	bool "Timer for Cygnus"
-
 config TIMER_IMG_PISTACHIO
 	bool "Timer for IMG Pistachio"
 
 config TIMER_MTK
 	bool "Timer for MediaTek MT8173"
 
-config TIMER_MVMAP2315
-	bool "Timer for Marvell MVMAP2315"
-
 endchoice
 
-config ARMADA38X_TIMER_FREQ
-        int "Hardware timer frequency"
-        depends on TIMER_ARMADA38X
-        default 25000000
-
-config ARMADA38X_TIMER_REG
-        hex "Timer register address"
-        default 0xF1020314
-        depends on TIMER_ARMADA38X
-
-config MVMAP2315_TIMER_FREQ
-	int "Hardware timer frequency"
-	depends on TIMER_MVMAP2315
-	default 1000000
-
-config MVMAP2315_TIMER_REG
-	hex "Timer register address"
-	depends on TIMER_MVMAP2315
-	default 0xE1020004
-
 config TIMER_GENERIC_HZ
 	int "Generic Timer Frequency"
-	default 500000000 if TIMER_CYGNUS
 	default 48000000 if TIMER_IPQ40XX
 	default 6250000 if TIMER_IPQ806X
 	default 24000000 if TIMER_MCT
@@ -107,7 +74,6 @@ config TIMER_GENERIC_HZ
 
 config TIMER_GENERIC_REG
 	hex "Generic Timer Register Address"
-	default 0x19020200 if TIMER_CYGNUS
 	default 0x004A2000 if TIMER_IPQ40XX
 	default 0x0200A028 if TIMER_IPQ806X
 	default 0x101C0100 if TIMER_MCT
@@ -121,7 +87,6 @@ config TIMER_GENERIC_REG
 
 config TIMER_GENERIC_HIGH_REG
 	hex "Generic Timer High Register Address"
-	default 0x19020204 if TIMER_CYGNUS
 	default 0x004A2004 if TIMER_IPQ40XX
 	default 0x101C0104 if TIMER_MCT
 	default 0xff81002C if TIMER_RK3288

diff --git a/payloads/libpayload/drivers/timer/armada38x.c b/payloads/libpayload/drivers/timer/armada38x.c
diff --git a/payloads/libpayload/drivers/timer/mvmap2315.c b/payloads/libpayload/drivers/timer/mvmap2315.c
diff --git a/payloads/libpayload/drivers/video/video.c b/payloads/libpayload/drivers/video/video.c
@@ -87,6 +87,9 @@ static void video_console_fixup_cursor(void)
 		cursory++;
 	}
 
+	if (console->rows <= 0)
+		return;
+
 	while(cursory >= console->rows) {
 		console->scroll_up();
 		cursory--;

diff --git a/payloads/libpayload/libcbfs/cbfs.c b/payloads/libpayload/libcbfs/cbfs.c
@@ -193,7 +193,7 @@ const struct cbfs_header *get_cbfs_header(void) {
 void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer,
 			     struct cbfs_media *media,
 			     size_t offset, size_t count) {
-	void *address = buffer->buffer + buffer->allocated;;
+	void *address = buffer->buffer + buffer->allocated;
 	DEBUG("simple_buffer_map(offset=%zu, count=%zu): "
 	      "allocated=%zu, size=%zu, last_allocate=%zu\n",
 	    offset, count, buffer->allocated, buffer->size,
Original file line number	Diff line number	Diff line change
Expand Up		@@ -4,4 +4,5 @@ This section contains documentation about coreboot on specific Intel Northbridge

		## Platforms

		- [Haswell](haswell/index.md)
		- [Sandy Bridge](sandybridge/index.md)