29 changes: 29 additions & 0 deletions payloads/libpayload/drivers/usb/ohci.c
View file
Expand Up @@ -212,6 +212,8 @@ ohci_init (unsigned long physical_bar)
udelay (10); /* at most 10us for reset to complete. State must be set to Operational within 2ms (5.1.1.4) */
OHCI_INST (controller)->opreg->HcFmInterval = interval;
OHCI_INST (controller)->hcca = dma_memalign(256, 256);
if (!OHCI_INST(controller)->hcca)
fatal("Not enough DMA memory for OHCI HCCA.\n");
memset((void*)OHCI_INST (controller)->hcca, 0, 256);

if (dma_initialized()) {
Expand All @@ -223,6 +225,8 @@ ohci_init (unsigned long physical_bar)
/* Initialize interrupt table. */
u32 *const intr_table = OHCI_INST(controller)->hcca->HccaInterruptTable;
ed_t *const periodic_ed = dma_memalign(sizeof(ed_t), sizeof(ed_t));
if (!periodic_ed)
fatal("Not enough DMA memory for OHCI interrupt table.\n");
memset((void *)periodic_ed, 0, sizeof(*periodic_ed));
for (i = 0; i < 32; ++i)
intr_table[i] = virt_to_phys(periodic_ed);
Expand Down Expand Up @@ -378,6 +382,8 @@ ohci_control (usbdev_t *dev, direction_t dir, int drlen, void *setup, int dalen,

/* First TD. */
td_t *const first_td = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t));
if (!first_td)
fatal("Not enough DMA memory for OHCI first TD in buffer.\n");
memset((void *)first_td, 0, sizeof(*first_td));
cur = first_td;

Expand All @@ -392,6 +398,8 @@ ohci_control (usbdev_t *dev, direction_t dir, int drlen, void *setup, int dalen,
while (pages > 0) {
/* One more TD. */
td_t *const next = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t));
if (!next)
fatal("Not enough DMA memory for OHCI new page.\n");
memset((void *)next, 0, sizeof(*next));
/* Linked to the previous. */
cur->next_td = virt_to_phys(next);
Expand Down Expand Up @@ -426,6 +434,8 @@ ohci_control (usbdev_t *dev, direction_t dir, int drlen, void *setup, int dalen,

/* One more TD. */
td_t *const next_td = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t));
if (!next_td)
fatal("Not enough DMA memory for OHCI additional TD.\n");
memset((void *)next_td, 0, sizeof(*next_td));
/* Linked to the previous. */
cur->next_td = virt_to_phys(next_td);
Expand All @@ -441,12 +451,16 @@ ohci_control (usbdev_t *dev, direction_t dir, int drlen, void *setup, int dalen,

/* Final dummy TD. */
td_t *const final_td = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t));
if (!final_td)
fatal("Not enough DMA memory for OHCI dummy TD!\n");
memset((void *)final_td, 0, sizeof(*final_td));
/* Linked to the previous. */
cur->next_td = virt_to_phys(final_td);

/* Data structures */
ed_t *head = dma_memalign(sizeof(ed_t), sizeof(ed_t));
if (!head)
fatal("Not enough DMA memory for OHCI data structures.\n");
memset((void*)head, 0, sizeof(*head));
head->config = (dev->address << ED_FUNC_SHIFT) |
(0 << ED_EP_SHIFT) |
Expand Down Expand Up @@ -519,6 +533,8 @@ ohci_bulk (endpoint_t *ep, int dalen, u8 *src, int finalize)

/* First TD. */
td_t *const first_td = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t));
if (!first_td)
fatal("Not enough DMA memory for OHCI bulk transfer.\n");
memset((void *)first_td, 0, sizeof(*first_td));
cur = next = first_td;

Expand Down Expand Up @@ -557,6 +573,8 @@ ohci_bulk (endpoint_t *ep, int dalen, u8 *src, int finalize)
}
/* One more TD. */
next = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t));
if (!next)
fatal("Not enough DMA mem for TD bulk transfer.\n");
memset((void *)next, 0, sizeof(*next));
/* Linked to the previous. */
cur->next_td = virt_to_phys(next);
Expand All @@ -569,6 +587,8 @@ ohci_bulk (endpoint_t *ep, int dalen, u8 *src, int finalize)

/* Data structures */
ed_t *head = dma_memalign(sizeof(ed_t), sizeof(ed_t));
if (!head)
fatal("Not enough DMA memory for OHCI bulk transfer's head.\n");
memset((void*)head, 0, sizeof(*head));
head->config = (ep->dev->address << ED_FUNC_SHIFT) |
((ep->endpoint & 0xf) << ED_EP_SHIFT) |
Expand Down Expand Up @@ -665,6 +685,11 @@ ohci_create_intr_queue(endpoint_t *const ep, const int reqsize,

intr_queue_t *const intrq =
(intr_queue_t *)dma_memalign(sizeof(intrq->ed), sizeof(*intrq));
if (!intrq) {
usb_debug("Not enough DMA memory for intr queue.\n");
free(intrq);
return NULL;
}
memset(intrq, 0, sizeof(*intrq));
intrq->data = (u8 *)dma_malloc(reqcount * reqsize);
intrq->reqsize = reqsize;
Expand All @@ -674,6 +699,8 @@ ohci_create_intr_queue(endpoint_t *const ep, const int reqsize,
u8 *cur_data = intrq->data;
for (i = 0; i < reqcount; ++i) {
intrq_td_t *const td = dma_memalign(sizeof(td->td), sizeof(*td));
if (!td)
fatal("Not enough DMA mem to transfer descriptor.\n");
++intrq->remaining_tds;
ohci_fill_intrq_td(td, intrq, cur_data);
cur_data += reqsize;
Expand All @@ -686,6 +713,8 @@ ohci_create_intr_queue(endpoint_t *const ep, const int reqsize,

/* Create last, dummy TD. */
intrq_td_t *dummy_td = dma_memalign(sizeof(dummy_td->td), sizeof(*dummy_td));
if (!dummy_td)
fatal("Not enough memory to add dummy TD.\n");
memset(dummy_td, 0, sizeof(*dummy_td));
dummy_td->intrq = intrq;
if (last_td)
Expand Down
4 changes: 4 additions & 0 deletions payloads/libpayload/drivers/usb/uhci.c
View file
Expand Up @@ -317,6 +317,8 @@ uhci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq, int dalen
unsigned short req = ((unsigned short *) devreq)[0];
int i;
td_t *tds = memalign (16, sizeof (td_t) * count);
if (!tds)
fatal("Not enough memory for uhci control.\n");
memset (tds, 0, sizeof (td_t) * count);
count--; /* to compensate for 0-indexed array */
for (i = 0; i < count; i++) {
Expand Down Expand Up @@ -386,6 +388,8 @@ create_schedule (int numpackets)
if (numpackets == 0)
return 0;
td_t *tds = memalign (16, sizeof (td_t) * numpackets);
if (!tds)
fatal("Not enough memory for packets scheduling.\n");
memset (tds, 0, sizeof (td_t) * numpackets);
int i;
for (i = 0; i < numpackets; i++) {
Expand Down
15 changes: 15 additions & 0 deletions payloads/libpayload/include/compiler.h
View file
Expand Up @@ -26,4 +26,19 @@
#define __always_unused __attribute__((unused))
#define __must_check __attribute__((warn_unused_result))

/* This evaluates to the type of the first expression, unless that is constant
in which case it evalutates to the type of the second. This is useful when
assigning macro parameters to temporary variables, because that would
normally circumvent the special loosened type promotion rules for integer
literals. By using this macro, the promotion can happen at the time the
literal is assigned to the temporary variable. If the literal doesn't fit in
the chosen type, -Werror=overflow will catch it, so this should be safe. */
#define __TYPEOF_UNLESS_CONST(expr, fallback_expr) typeof( \
__builtin_choose_expr(__builtin_constant_p(expr), fallback_expr, expr))

/* This creates a unique local variable name for use in macros. */
#define __TMPNAME_3(i) __tmpname_##i
#define __TMPNAME_2(i) __TMPNAME_3(i)
#define __TMPNAME __TMPNAME_2(__COUNTER__)

#endif
26 changes: 24 additions & 2 deletions payloads/libpayload/include/libpayload.h
View file
Expand Up @@ -66,10 +66,32 @@
#include <pci.h>
#include <archive.h>

#define MIN(a,b) ((a) < (b) ? (a) : (b))
#define MAX(a,b) ((a) > (b) ? (a) : (b))
/* Double-evaluation unsafe min/max, for bitfields and outside of functions */
#define __CMP_UNSAFE(a, b, op) ((a) op (b) ? (a) : (b))
#define MIN_UNSAFE(a, b) __CMP_UNSAFE(a, b, <)
#define MAX_UNSAFE(a, b) __CMP_UNSAFE(a, b, >)

#define __CMP_SAFE(a, b, op, var_a, var_b) ({ \
__TYPEOF_UNLESS_CONST(a, b) var_a = (a); \
__TYPEOF_UNLESS_CONST(b, a) var_b = (b); \
var_a op var_b ? var_a : var_b; \
})

#define __CMP(a, b, op) __builtin_choose_expr( \
__builtin_constant_p(a) && __builtin_constant_p(b), \
__CMP_UNSAFE(a, b, op), __CMP_SAFE(a, b, op, __TMPNAME, __TMPNAME))

#define MIN(a, b) __CMP(a, b, <)
#define MAX(a, b) __CMP(a, b, >)

#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))

#define DIV_ROUND_UP(x, y) ({ \
typeof(x) _div_local_x = (x); \
typeof(y) _div_local_y = (y); \
(_div_local_x + _div_local_y - 1) / _div_local_y; \
})

static inline u32 div_round_up(u32 n, u32 d) { return (n + d - 1) / d; }

#define LITTLE_ENDIAN 1234
Expand Down
17 changes: 15 additions & 2 deletions payloads/libpayload/include/limits.h
View file
Expand Up @@ -40,7 +40,20 @@
# endif
#endif

#define UINT_MAX (unsigned int)0xffffffff
#define INT_MAX (unsigned int)0x7fffffff
#define USHRT_MAX ((unsigned short int)~0U)
#define SHRT_MIN ((short int)(USHRT_MAX & ~(USHRT_MAX >> 1)))
#define SHRT_MAX ((short int)(USHRT_MAX >> 1))

#define UINT_MAX ((unsigned int)~0U)
#define INT_MIN ((int)(UINT_MAX & ~(UINT_MAX >> 1)))
#define INT_MAX ((int)(UINT_MAX >> 1))

#define ULONG_MAX ((unsigned long int)~0UL)
#define LONG_MIN ((long int)(ULONG_MAX & ~(ULONG_MAX >> 1)))
#define LONG_MAX ((long int)(ULONG_MAX >> 1))

#define ULLONG_MAX ((unsigned long long int)~0UL)
#define LLONG_MIN ((long long int)(ULLONG_MAX & ~(ULLONG_MAX >> 1)))
#define LLONG_MAX ((long long int)(ULLONG_MAX >> 1))

#endif
187 changes: 89 additions & 98 deletions payloads/libpayload/include/stdlib.h
View file
Expand Up @@ -45,112 +45,102 @@
* @defgroup malloc Memory allocation functions
* @{
*/
#if CONFIG(LP_DEBUG_MALLOC) && !defined(IN_MALLOC_C)
#define free(p) \
({ \
extern void print_malloc_map(void); \
extern void free(void *); \
printf("free(%p) called from %s:%s:%d...\n", p, __FILE__, __func__, \
__LINE__);\
printf("PRE free()\n"); \
print_malloc_map(); \
free(p); \
printf("POST free()\n"); \
print_malloc_map(); \
})
#define malloc(s) \
({ \
extern void print_malloc_map(void); \
extern void *malloc(size_t); \
void *ptr; \
printf("malloc(%u) called from %s:%s:%d...\n", s, __FILE__, __func__, \
__LINE__);\
printf("PRE malloc\n"); \
print_malloc_map(); \
ptr = malloc(s); \
printf("POST malloc (ptr = %p)\n", ptr); \
print_malloc_map(); \
ptr; \
})
#define calloc(n,s) \
({ \
extern void print_malloc_map(void); \
extern void *calloc(size_t,size_t); \
void *ptr; \
printf("calloc(%u, %u) called from %s:%s:%d...\n", n, s, __FILE__, \
__func__, __LINE__);\
printf("PRE calloc\n"); \
print_malloc_map(); \
ptr = calloc(n,s); \
printf("POST calloc (ptr = %p)\n", ptr); \
print_malloc_map(); \
ptr; \
})
#define realloc(p,s) \
({ \
extern void print_malloc_map(void); \
extern void *realloc(void*,size_t); \
void *ptr; \
printf("realloc(%p, %u) called from %s:%s:%d...\n", p, s, __FILE__, \
__func__, __LINE__);\
printf("PRE realloc\n"); \
print_malloc_map(); \
ptr = realloc(p,s); \
printf("POST realloc (ptr = %p)\n", ptr); \
print_malloc_map(); \
ptr; \
})
#define memalign(a,s) \
({ \
extern void print_malloc_map(void); \
extern void *memalign(size_t, size_t); \
void *ptr; \
printf("memalign(%u, %u) called from %s:%s:%d...\n", a, s, __FILE__, \
__func__, __LINE__);\
printf("PRE memalign\n"); \
print_malloc_map(); \
ptr = memalign(a,s); \
printf("POST memalign (ptr = %p)\n", ptr); \
print_malloc_map(); \
ptr; \
})
#define dma_malloc(s) \
({ \
extern void print_malloc_map(void); \
extern void *dma_malloc(size_t); \
void *ptr; \
printf("dma_malloc(%u) called from %s:%s:%d...\n", s, __FILE__, \
__func__, __LINE__);\
printf("PRE dma_malloc\n"); \
print_malloc_map(); \
ptr = dma_malloc(s); \
printf("POST dma_malloc (ptr = %p)\n", ptr); \
print_malloc_map(); \
ptr; \
})
#define dma_memalign(a,s) \
({ \
extern void print_malloc_map(void); \
extern void *dma_memalign(size_t, size_t); \
void *ptr; \
printf("dma_memalign(%u, %u) called from %s:%s:%d...\n", a, s, \
__FILE__, __func__, __LINE__);\
printf("PRE dma_memalign\n"); \
print_malloc_map(); \
ptr = dma_memalign(a,s); \
printf("POST dma_memalign (ptr = %p)\n", ptr); \
print_malloc_map(); \
ptr; \
})
#else
void free(void *ptr);
void *malloc(size_t size);
void *calloc(size_t nmemb, size_t size);
void *realloc(void *ptr, size_t size);
void *memalign(size_t align, size_t size);
void *dma_malloc(size_t size);
void *dma_memalign(size_t align, size_t size);

#if CONFIG(LP_DEBUG_MALLOC) && !defined(IN_MALLOC_C)
#include <stdio.h>
void print_malloc_map(void);
#define free(p) ({ \
void *__p = p; \
printf("free(%p) called from %s:%s:%d...\n", __p, __FILE__, __func__, \
__LINE__);\
printf("PRE free()\n"); \
print_malloc_map(); \
free(__p); \
printf("POST free()\n"); \
print_malloc_map(); \
})
#define malloc(s) ({ \
size_t __s = s; \
void *ptr; \
printf("malloc(%zu) called from %s:%s:%d...\n", __s, __FILE__, \
__func__, __LINE__);\
printf("PRE malloc\n"); \
print_malloc_map(); \
ptr = malloc(__s); \
printf("POST malloc (ptr = %p)\n", ptr); \
print_malloc_map(); \
ptr; \
})
#define calloc(n, s) ({ \
size_t __n = n, __s = s; \
void *ptr; \
printf("calloc(%zu, %zu) called from %s:%s:%d...\n", __n, __s, \
__FILE__, __func__, __LINE__);\
printf("PRE calloc\n"); \
print_malloc_map(); \
ptr = calloc(__n, __s); \
printf("POST calloc (ptr = %p)\n", ptr); \
print_malloc_map(); \
ptr; \
})
#define realloc(p, s) ({ \
void *__p = p; \
size_t __s = s; \
void *ptr; \
printf("realloc(%p, %zu) called from %s:%s:%d...\n", __p, __s, \
__FILE__, __func__, __LINE__);\
printf("PRE realloc\n"); \
print_malloc_map(); \
ptr = realloc(__p, __s); \
printf("POST realloc (ptr = %p)\n", ptr); \
print_malloc_map(); \
ptr; \
})
#define memalign(a, s) ({ \
size_t __a = a, __s = s; \
void *ptr; \
printf("memalign(%zu, %zu) called from %s:%s:%d...\n", __a, __s, \
__FILE__, __func__, __LINE__);\
printf("PRE memalign\n"); \
print_malloc_map(); \
ptr = memalign(__a, __s); \
printf("POST memalign (ptr = %p)\n", ptr); \
print_malloc_map(); \
ptr; \
})
#define dma_malloc(s) ({ \
size_t __s = s; \
void *ptr; \
printf("dma_malloc(%zu) called from %s:%s:%d...\n", __s, __FILE__, \
__func__, __LINE__);\
printf("PRE dma_malloc\n"); \
print_malloc_map(); \
ptr = dma_malloc(__s); \
printf("POST dma_malloc (ptr = %p)\n", ptr); \
print_malloc_map(); \
ptr; \
})
#define dma_memalign(a, s) ({ \
size_t __a = a, __s = s; \
void *ptr; \
printf("dma_memalign(%zu, %zu) called from %s:%s:%d...\n", __a, __s, \
__FILE__, __func__, __LINE__);\
printf("PRE dma_memalign\n"); \
print_malloc_map(); \
ptr = dma_memalign(__a, __s); \
printf("POST dma_memalign (ptr = %p)\n", ptr); \
print_malloc_map(); \
ptr; \
})
#endif

void init_dma_memory(void *start, u32 size);
int dma_initialized(void);
int dma_coherent(void *ptr);
Expand Down Expand Up @@ -196,6 +186,7 @@ static inline void *xmemalign_work(size_t align, size_t size, const char *file,
* @{
*/
long int strtol(const char *s, char **nptr, int base);
long long int strtoll(const char *s, char **nptr, int base);
unsigned long int strtoul(const char *s, char **nptr, int base);
unsigned long long int strtoull(const char *s, char **nptr, int base);
long atol(const char *nptr);
Expand Down
6 changes: 3 additions & 3 deletions payloads/libpayload/libc/malloc.c
View file
Expand Up @@ -480,7 +480,7 @@ static void *alloc_aligned(size_t align, size_t size, struct memory_type *type)
if ((reg->alignment == align) && (reg->free >= (size + align - 1)/align))
{
#if CONFIG(LP_DEBUG_MALLOC)
printf(" found memalign region. %x free, %x required\n", reg->free, (size + align - 1)/align);
printf(" found memalign region. %u free, %zu required\n", reg->free, (size + align - 1)/align);
#endif
break;
}
Expand Down Expand Up @@ -563,7 +563,7 @@ void print_malloc_map(void)

/* FIXME: Verify the size of the block. */

printf("%s %x: %s (%x bytes)\n", type->name,
printf("%s %x: %s (%llx bytes)\n", type->name,
(unsigned int)(ptr - type->start),
hdr & FLAG_FREE ? "FREE" : "USED", SIZE(hdr));

Expand All @@ -575,7 +575,7 @@ void print_malloc_map(void)

if (free_memory && (type->minimal_free > free_memory))
type->minimal_free = free_memory;
printf("%s: Maximum memory consumption: %u bytes\n", type->name,
printf("%s: Maximum memory consumption: %zu bytes\n", type->name,
(type->end - type->start) - HDRSIZE - type->minimal_free);

if (type != dma) {
Expand Down
65 changes: 25 additions & 40 deletions payloads/libpayload/libc/string.c
View file
Expand Up @@ -33,6 +33,7 @@
#include <string.h>
#include <ctype.h>
#include <inttypes.h>
#include <limits.h>
#include <errno.h>

/**
Expand Down Expand Up @@ -419,59 +420,43 @@ static int _offset(char ch, int base)
* @return A signed integer representation of the string
*/

long int strtol(const char *ptr, char **endptr, int base)
long long int strtoll(const char *orig_ptr, char **endptr, int base)
{
int ret = 0;
int negative = 1;

if (endptr != NULL)
*endptr = (char *) ptr;
const char *ptr = orig_ptr;
int is_negative = 0;

/* Purge whitespace */

for( ; *ptr && isspace(*ptr); ptr++);

if (ptr[0] == '-') {
negative = -1;
is_negative = 1;
ptr++;
}

if (!*ptr)
return 0;
unsigned long long uval = strtoull(ptr, endptr, base);

/* Determine the base */
/* If the whole string is unparseable, endptr should point to start. */
if (endptr && *endptr == ptr)
*endptr = (char *)orig_ptr;

if (base == 0) {
if (ptr[0] == '0' && (ptr[1] == 'x' || ptr[1] == 'X'))
base = 16;
else if (ptr[0] == '0') {
base = 8;
ptr++;
}
else
base = 10;
}

/* Base 16 allows the 0x on front - so skip over it */
if (uval > (unsigned long long)LLONG_MAX + !!is_negative)
uval = (unsigned long long)LLONG_MAX + !!is_negative;

if (base == 16) {
if (ptr[0] == '0' && (ptr[1] == 'x' || ptr[1] == 'X'))
ptr += 2;
}

/* If the first character isn't valid, then don't
* bother */

if (!*ptr || !_valid(*ptr, base))
return 0;

for( ; *ptr && _valid(*ptr, base); ptr++)
ret = (ret * base) + _offset(*ptr, base);

if (endptr != NULL)
*endptr = (char *) ptr;
if (is_negative)
return -uval;
else
return uval;
}

return ret * negative;
long int strtol(const char *ptr, char **endptr, int base)
{
long long int val = strtoll(ptr, endptr, base);
if (val > LONG_MAX)
return LONG_MAX;
if (val < LONG_MIN)
return LONG_MIN;
return val;
}

long atol(const char *nptr)
Expand Down Expand Up @@ -534,7 +519,7 @@ unsigned long long int strtoull(const char *ptr, char **endptr, int base)
unsigned long int strtoul(const char *ptr, char **endptr, int base)
{
unsigned long long val = strtoull(ptr, endptr, base);
if (val > UINT32_MAX) return UINT32_MAX;
if (val > ULONG_MAX) return ULONG_MAX;
return val;
}

Expand Down
4 changes: 1 addition & 3 deletions src/Kconfig
View file
Expand Up @@ -370,8 +370,6 @@ source "src/superio/*/*/Kconfig"
comment "Embedded Controllers"
source "src/ec/acpi/Kconfig"
source "src/ec/*/*/Kconfig"
# FIXME move to vendorcode
source "src/drivers/intel/fsp1_0/Kconfig"

source "src/southbridge/intel/common/firmware/Kconfig"
source "src/vendorcode/*/Kconfig"
Expand Down Expand Up @@ -428,6 +426,7 @@ config RTC

config HEAP_SIZE
hex
default 0x100000 if FLATTENED_DEVICE_TREE
default 0x4000

config STACK_SIZE
Expand Down Expand Up @@ -1154,7 +1153,6 @@ config GENERIC_SPD_BIN
config DIMM_MAX
int
default 4
depends on GENERIC_SPD_BIN
help
Total number of memory DIMM slots available on motherboard.
It is multiplication of number of channel to number of DIMMs per
Expand Down
2 changes: 1 addition & 1 deletion src/arch/arm64/arm_tf.c
View file
Expand Up @@ -18,9 +18,9 @@
#include <arch/mmu.h>
#include <arch/transition.h>
#include <arm_tf.h>
#include <assert.h>
#include <bootmem.h>
#include <cbfs.h>
#include <console/console.h>
#include <program_loading.h>

/*
Expand Down
1 change: 0 additions & 1 deletion src/arch/riscv/boot.c
View file
Expand Up @@ -17,7 +17,6 @@
#include <vm.h>
#include <arch/boot.h>
#include <arch/encoding.h>
#include <console/console.h>
#include <arch/smp/smp.h>
#include <mcall.h>

Expand Down
1 change: 0 additions & 1 deletion src/arch/riscv/sbi.c
View file
Expand Up @@ -20,7 +20,6 @@
#include <sbi.h>
#include <vm.h>
#include <console/uart.h>
#include <console/console.h>
#include <commonlib/helpers.h>

static uintptr_t send_ipi(uintptr_t *pmask, intptr_t type)
Expand Down
8 changes: 8 additions & 0 deletions src/arch/x86/Kconfig
View file
Expand Up @@ -265,6 +265,14 @@ config SKIP_MAX_REBOOT_CNT_CLEAR
Note that it is the responsibility of the payload to reset the
normal boot bit to 1 after each successful boot.

config ACPI_NO_PCAT_8259
bool
help
Selected by platforms that don't expose a PC/AT 8259 PIC pair.

config ACPI_HAVE_PCAT_8259
def_bool y if !ACPI_NO_PCAT_8259

config ACPI_CPU_STRING
string
default "\\_PR.CP%02d"
Expand Down
30 changes: 29 additions & 1 deletion src/arch/x86/acpi.c
View file
Expand Up @@ -229,7 +229,8 @@ void acpi_create_madt(acpi_madt_t *madt)
header->revision = get_acpi_table_revision(MADT);

madt->lapic_addr = LOCAL_APIC_ADDR;
madt->flags = 0x1; /* PCAT_COMPAT */
if (CONFIG(ACPI_HAVE_PCAT_8259))
madt->flags |= 1;

current = acpi_fill_madt(current);

Expand Down Expand Up @@ -568,6 +569,33 @@ unsigned long acpi_create_dmar_atsr(unsigned long current, u8 flags,
return atsr->length;
}

unsigned long acpi_create_dmar_rhsa(unsigned long current, u64 base_addr,
u32 proximity_domain)
{
dmar_rhsa_entry_t *rhsa = (dmar_rhsa_entry_t *)current;
memset(rhsa, 0, sizeof(*rhsa));
rhsa->type = DMAR_RHSA;
rhsa->length = sizeof(*rhsa);
rhsa->base_address = base_addr;
rhsa->proximity_domain = proximity_domain;

return rhsa->length;
}

unsigned long acpi_create_dmar_andd(unsigned long current, u8 device_number,
const char *device_name)
{
dmar_andd_entry_t *andd = (dmar_andd_entry_t *)current;
int andd_len = sizeof(dmar_andd_entry_t) + strlen(device_name) + 1;
memset(andd, 0, andd_len);
andd->type = DMAR_ANDD;
andd->length = andd_len;
andd->device_number = device_number;
memcpy(&andd->device_name, device_name, strlen(device_name));

return andd->length;
}

void acpi_dmar_drhd_fixup(unsigned long base, unsigned long current)
{
dmar_entry_t *drhd = (dmar_entry_t *)base;
Expand Down
8 changes: 4 additions & 4 deletions src/arch/x86/acpi_device.c
View file
Expand Up @@ -377,7 +377,7 @@ void acpi_device_write_i2c(const struct acpi_i2c *i2c)
desc_length = acpi_device_write_zero_len();

/* Byte 3: Revision ID */
acpigen_emit_byte(ACPI_SERIAL_BUS_REVISION_ID);
acpigen_emit_byte(ACPI_I2C_SERIAL_BUS_REVISION_ID);

/* Byte 4: Resource Source Index is Reserved */
acpigen_emit_byte(0);
Expand All @@ -401,7 +401,7 @@ void acpi_device_write_i2c(const struct acpi_i2c *i2c)
acpigen_emit_word(i2c->mode_10bit);

/* Byte 9: Type Specific Revision ID */
acpigen_emit_byte(ACPI_SERIAL_BUS_REVISION_ID);
acpigen_emit_byte(ACPI_I2C_TYPE_SPECIFIC_REVISION_ID);

/* Byte 10-11: I2C Type Data Length */
type_length = acpi_device_write_zero_len();
Expand Down Expand Up @@ -435,7 +435,7 @@ void acpi_device_write_spi(const struct acpi_spi *spi)
desc_length = acpi_device_write_zero_len();

/* Byte 3: Revision ID */
acpigen_emit_byte(ACPI_SERIAL_BUS_REVISION_ID);
acpigen_emit_byte(ACPI_SPI_SERIAL_BUS_REVISION_ID);

/* Byte 4: Resource Source Index is Reserved */
acpigen_emit_byte(0);
Expand Down Expand Up @@ -464,7 +464,7 @@ void acpi_device_write_spi(const struct acpi_spi *spi)
acpigen_emit_word(flags);

/* Byte 9: Type Specific Revision ID */
acpigen_emit_byte(ACPI_SERIAL_BUS_REVISION_ID);
acpigen_emit_byte(ACPI_SPI_TYPE_SPECIFIC_REVISION_ID);

/* Byte 10-11: SPI Type Data Length */
type_length = acpi_device_write_zero_len();
Expand Down
1 change: 1 addition & 0 deletions src/arch/x86/acpigen.c
View file
Expand Up @@ -28,6 +28,7 @@
#include <lib.h>
#include <string.h>
#include <arch/acpigen.h>
#include <assert.h>
#include <console/console.h>
#include <device/device.h>

Expand Down
5 changes: 4 additions & 1 deletion src/arch/x86/car.ld
View file
Expand Up @@ -34,7 +34,9 @@
/* Vboot measured boot TCPA log measurements.
* Needs to be transferred until CBMEM is available
*/
#if CONFIG(VBOOT_MEASURED_BOOT)
VBOOT2_TPM_LOG(., 2K)
#endif
/* Stack for CAR stages. Since it persists across all stages that
* use CAR it can be reused. The chipset/SoC is expected to provide
* the stack size. */
Expand Down Expand Up @@ -89,7 +91,8 @@
_car_global_end = .;
_car_relocatable_data_end = .;

#if CONFIG(NORTHBRIDGE_INTEL_SANDYBRIDGE) && \
#if (CONFIG(NORTHBRIDGE_INTEL_SANDYBRIDGE) || \
CONFIG(NORTHBRIDGE_INTEL_IVYBRIDGE)) && \
!CONFIG(USE_NATIVE_RAMINIT)
. = ABSOLUTE(0xff7e1000);
_mrc_pool = .;
Expand Down
26 changes: 23 additions & 3 deletions src/arch/x86/include/arch/acpi.h
View file
Expand Up @@ -335,9 +335,9 @@ enum {
};

enum dmar_flags {
DMAR_INTR_REMAP = 1,
DMAR_X2APIC_OPT_OUT = 2,
DMA_CTRL_PLATFORM_OPT_IN_FLAG = 3,
DMAR_INTR_REMAP = 1 << 0,
DMAR_X2APIC_OPT_OUT = 1 << 1,
DMA_CTRL_PLATFORM_OPT_IN_FLAG = 1 << 2,
};

typedef struct dmar_entry {
Expand Down Expand Up @@ -366,6 +366,22 @@ typedef struct dmar_atsr_entry {
u16 segment;
} __packed dmar_atsr_entry_t;

typedef struct dmar_rhsa_entry {
u16 type;
u16 length;
u32 reserved;
u64 base_address;
u32 proximity_domain;
} __packed dmar_rhsa_entry_t;

typedef struct dmar_andd_entry {
u16 type;
u16 length;
u8 reserved[3];
u8 device_number;
u8 device_name[];
} __packed dmar_andd_entry_t;

/* DMAR (DMA Remapping Reporting Structure) */
typedef struct acpi_dmar {
struct acpi_table_header header;
Expand Down Expand Up @@ -850,6 +866,10 @@ unsigned long acpi_create_dmar_rmrr(unsigned long current, u16 segment,
u64 bar, u64 limit);
unsigned long acpi_create_dmar_atsr(unsigned long current, u8 flags,
u16 segment);
unsigned long acpi_create_dmar_rhsa(unsigned long current, u64 base_addr,
u32 proximity_domain);
unsigned long acpi_create_dmar_andd(unsigned long current, u8 device_number,
const char *device_name);
void acpi_dmar_drhd_fixup(unsigned long base, unsigned long current);
void acpi_dmar_rmrr_fixup(unsigned long base, unsigned long current);
void acpi_dmar_atsr_fixup(unsigned long base, unsigned long current);
Expand Down
9 changes: 6 additions & 3 deletions src/arch/x86/include/arch/acpi_device.h
View file
Expand Up @@ -309,9 +309,12 @@ void acpi_device_write_gpio(const struct acpi_gpio *gpio);
* ACPI Descriptors for Serial Bus interfaces
*/

#define ACPI_SERIAL_BUS_TYPE_I2C 1
#define ACPI_SERIAL_BUS_TYPE_SPI 2
#define ACPI_SERIAL_BUS_REVISION_ID 1
#define ACPI_SERIAL_BUS_TYPE_I2C 1
#define ACPI_SERIAL_BUS_TYPE_SPI 2
#define ACPI_I2C_SERIAL_BUS_REVISION_ID 1 /* TODO: upgrade to 2 */
#define ACPI_I2C_TYPE_SPECIFIC_REVISION_ID 1
#define ACPI_SPI_SERIAL_BUS_REVISION_ID 1
#define ACPI_SPI_TYPE_SPECIFIC_REVISION_ID 1

/*
* ACPI I2C Bus
Expand Down
98 changes: 84 additions & 14 deletions src/arch/x86/include/arch/acpigen.h
View file
Expand Up @@ -18,7 +18,6 @@
#ifndef LIBACPI_H
#define LIBACPI_H

#include <assert.h>
#include <stdlib.h>
#include <stdint.h>
#include <arch/acpi.h>
Expand All @@ -42,29 +41,57 @@

/* ACPI Op/Prefix Codes */
enum {
ZERO_OP = 0x00,
ZERO_OP = 0x00,
ONE_OP = 0x01,
NAME_OP = 0x08,
SCOPE_OP = 0x10,
BUFFER_OP = 0x11,
ALIAS_OP = 0x06,
NAME_OP = 0x08,
BYTE_PREFIX = 0x0A,
WORD_PREFIX = 0x0B,
DWORD_PREFIX = 0x0C,
STRING_PREFIX = 0x0D,
QWORD_PREFIX = 0x0E,
SCOPE_OP = 0x10,
BUFFER_OP = 0x11,
PACKAGE_OP = 0x12,
VARIABLE_PACKAGE_OP = 0x13,
METHOD_OP = 0x14,
EXTERNAL_OP = 0x15,
DUAL_NAME_PREFIX = 0x2E,
MULTI_NAME_PREFIX = 0x2F,
EXT_OP_PREFIX = 0x5B,
MUTEX_OP = 0x01,
EVENT_OP = 0x01,
SF_RIGHT_OP = 0x10,
SF_LEFT_OP = 0x11,
COND_REFOF_OP = 0x12,
CREATEFIELD_OP = 0x13,
LOAD_TABLE_OP = 0x1f,
LOAD_OP = 0x20,
STALL_OP = 0x21,
SLEEP_OP = 0x22,
ACQUIRE_OP = 0x23,
SIGNAL_OP = 0x24,
WAIT_OP = 0x25,
RST_OP = 0x26,
RELEASE_OP = 0x27,
FROM_BCD_OP = 0x28,
TO_BCD_OP = 0x29,
UNLOAD_OP = 0x2A,
REVISON_OP = 0x30,
DEBUG_OP = 0x31,
FATAL_OP = 0x32,
TIMER_OP = 0x33,
OPREGION_OP = 0x80,
FIELD_OP = 0x81,
DEVICE_OP = 0x82,
PROCESSOR_OP = 0x83,
POWER_RES_OP = 0x84,
THERMAL_ZONE_OP = 0x85,
INDEX_FIELD_OP = 0x86,
BANK_FIELD_OP = 0x87,
DATA_REGION_OP = 0x88,
ROOT_PREFIX = 0x5C,
PARENT_PREFIX = 0x5D,
LOCAL0_OP = 0x60,
LOCAL1_OP = 0x61,
LOCAL2_OP = 0x62,
Expand All @@ -73,29 +100,68 @@ enum {
LOCAL5_OP = 0x65,
LOCAL6_OP = 0x66,
LOCAL7_OP = 0x67,
ARG0_OP = 0x68,
ARG1_OP = 0x69,
ARG2_OP = 0x6A,
ARG3_OP = 0x6B,
ARG4_OP = 0x6C,
ARG5_OP = 0x6D,
ARG6_OP = 0x6E,
ARG0_OP = 0x68,
ARG1_OP = 0x69,
ARG2_OP = 0x6A,
ARG3_OP = 0x6B,
ARG4_OP = 0x6C,
ARG5_OP = 0x6D,
ARG6_OP = 0x6E,
STORE_OP = 0x70,
REF_OF_OP = 0x71,
ADD_OP = 0x72,
CONCATENATE_OP = 0x73,
SUBTRACT_OP = 0x74,
INCREMENT_OP = 0x75,
DECREMENT_OP = 0x76,
MULTIPLY_OP = 0x77,
DIVIDE_OP = 0x78,
SHIFT_LEFT_OP = 0x79,
SHIFT_RIGHT_OP = 0x7A,
AND_OP = 0x7B,
NAND_OP = 0x7C,
OR_OP = 0x7D,
NOR_OP = 0x7E,
XOR_OP = 0x7F,
NOT_OP = 0x80,
FD_SHIFT_LEFT_BIT_OR = 0x81,
FD_SHIFT_RIGHT_BIT_OR = 0x82,
DEREF_OP = 0x83,
CONCATENATE_TEMP_OP = 0x84,
MOD_OP = 0x85,
NOTIFY_OP = 0x86,
SIZEOF_OP = 0x87,
INDEX_OP = 0x88,
MATCH_OP = 0x89,
CREATE_DWORD_OP = 0x8A,
CREATE_WORD_OP = 0x8B,
CREATE_BYTE_OP = 0x8C,
CREATE_BIT_OP = 0x8D,
OBJ_TYPE_OP = 0x8E,
CREATE_QWORD_OP = 0x8F,
LAND_OP = 0x90,
LOR_OP = 0x91,
LNOT_OP = 0x92,
LEQUAL_OP = 0x93,
LGREATER_OP = 0x94,
LLESS_OP = 0x95,
TO_BUFFER_OP = 0x96,
TO_DEC_STRING_OP = 0x97,
TO_HEX_STRING_OP = 0x98,
TO_INTEGER_OP = 0x99,
TO_STRING_OP = 0x9C,
CP_OBJ_OP = 0x9D,
MID_OP = 0x9E,
CONTINUE_OP = 0x9F,
IF_OP = 0xA0,
ELSE_OP = 0xA1,
ELSE_OP = 0xA1,
WHILE_OP = 0xA2,
NOOP_OP = 0xA3,
RETURN_OP = 0xA4,
ONES_OP = 0xFF,
BREAK_OP = 0xA5,
COMMENT_OP = 0xA9,
BREAKPIONT_OP = 0xCC,
ONES_OP = 0xFF,
};

#define FIELDLIST_OFFSET(X) { .type = OFFSET, \
Expand Down Expand Up @@ -146,6 +212,10 @@ enum region_space {
CMOS,
PCIBARTARGET,
IPMI,
GPIO_REGION,
GPSERIALBUS,
PCC,
FIXED_HARDWARE = 0x7F,
REGION_SPACE_MAX,
};

Expand Down
51 changes: 51 additions & 0 deletions src/arch/x86/include/arch/cpu.h
View file
Expand Up @@ -158,6 +158,47 @@ static inline unsigned int cpuid_edx(unsigned int op)
#define CPUID_FEATURE_PAE (1 << 6)
#define CPUID_FEATURE_PSE36 (1 << 17)

// Intel leaf 0x4, AMD leaf 0x8000001d EAX

#define CPUID_CACHE(x, res) \
(((res) >> CPUID_CACHE_##x##_SHIFT) & CPUID_CACHE_##x##_MASK)

#define CPUID_CACHE_FULL_ASSOC_SHIFT 9
#define CPUID_CACHE_FULL_ASSOC_MASK 0x1
#define CPUID_CACHE_FULL_ASSOC(res) CPUID_CACHE(FULL_ASSOC, (res).eax)

#define CPUID_CACHE_SELF_INIT_SHIFT 8
#define CPUID_CACHE_SELF_INIT_MASK 0x1
#define CPUID_CACHE_SELF_INIT(res) CPUID_CACHE(SELF_INIT, (res).eax)

#define CPUID_CACHE_LEVEL_SHIFT 5
#define CPUID_CACHE_LEVEL_MASK 0x7
#define CPUID_CACHE_LEVEL(res) CPUID_CACHE(LEVEL, (res).eax)

#define CPUID_CACHE_TYPE_SHIFT 0
#define CPUID_CACHE_TYPE_MASK 0x1f
#define CPUID_CACHE_TYPE(res) CPUID_CACHE(TYPE, (res).eax)

// Intel leaf 0x4, AMD leaf 0x8000001d EBX

#define CPUID_CACHE_WAYS_OF_ASSOC_SHIFT 22
#define CPUID_CACHE_WAYS_OF_ASSOC_MASK 0x3ff
#define CPUID_CACHE_WAYS_OF_ASSOC(res) CPUID_CACHE(WAYS_OF_ASSOC, (res).ebx)

#define CPUID_CACHE_PHYS_LINE_SHIFT 12
#define CPUID_CACHE_PHYS_LINE_MASK 0x3ff
#define CPUID_CACHE_PHYS_LINE(res) CPUID_CACHE(PHYS_LINE, (res).ebx)

#define CPUID_CACHE_COHER_LINE_SHIFT 0
#define CPUID_CACHE_COHER_LINE_MASK 0xfff
#define CPUID_CACHE_COHER_LINE(res) CPUID_CACHE(COHER_LINE, (res).ebx)

// Intel leaf 0x4, AMD leaf 0x8000001d ECX

#define CPUID_CACHE_NO_OF_SETS_SHIFT 0
#define CPUID_CACHE_NO_OF_SETS_MASK 0xffffffff
#define CPUID_CACHE_NO_OF_SETS(res) CPUID_CACHE(NO_OF_SETS, (res).ecx)

int cpu_cpuid_extended_level(void);
int cpu_have_cpuid(void);

Expand All @@ -166,6 +207,16 @@ void smm_init_completion(void);
void smm_lock(void);
void smm_setup_structures(void *gnvs, void *tcg, void *smi1);

static inline bool cpu_is_amd(void)
{
return CONFIG(CPU_AMD_AGESA) || CONFIG(CPU_AMD_PI);
}

static inline bool cpu_is_intel(void)
{
return CONFIG(CPU_INTEL_COMMON) || CONFIG(SOC_INTEL_COMMON);
}

#ifndef __SIMPLE_DEVICE__

struct device;
Expand Down
86 changes: 86 additions & 0 deletions src/arch/x86/include/arch/intel-family.h
View file
@@ -0,0 +1,86 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#ifndef ARCH_INTEL_FAMILY_H
#define ARCH_INTEL_FAMILY_H

#define CPU_MODEL_INTEL_CORE_YONAH 0x0E

#define CPU_MODEL_INTEL_CORE2_MEROM 0x0F
#define CPU_MODEL_INTEL_CORE2_MEROM_L 0x16
#define CPU_MODEL_INTEL_CORE2_PENRYN 0x17
#define CPU_MODEL_INTEL_CORE2_DUNNINGTON 0x1D

#define CPU_MODEL_INTEL_NEHALEM 0x1E
/* Auburndale / Havendale */
#define CPU_MODEL_INTEL_NEHALEM_G 0x1F
#define CPU_MODEL_INTEL_NEHALEM_EP 0x1A
#define CPU_MODEL_INTEL_NEHALEM_EX 0x2E

#define CPU_MODEL_INTEL_WESTMERE 0x25
#define CPU_MODEL_INTEL_WESTMERE_EP 0x2C
#define CPU_MODEL_INTEL_WESTMERE_EX 0x2F

#define CPU_MODEL_INTEL_SANDYBRIDGE 0x2A
#define CPU_MODEL_INTEL_SANDYBRIDGE_X 0x2D
#define CPU_MODEL_INTEL_IVYBRIDGE 0x3A
#define CPU_MODEL_INTEL_IVYBRIDGE_X 0x3E

#define CPU_MODEL_INTEL_HASWELL_CORE 0x3C
#define CPU_MODEL_INTEL_HASWELL_X 0x3F
#define CPU_MODEL_INTEL_HASWELL_ULT 0x45
#define CPU_MODEL_INTEL_HASWELL_GT3E 0x46

#define CPU_MODEL_INTEL_BROADWELL_CORE 0x3D
#define CPU_MODEL_INTEL_BROADWELL_GT3E 0x47
#define CPU_MODEL_INTEL_BROADWELL_X 0x4F
#define CPU_MODEL_INTEL_BROADWELL_XEON_D 0x56

#define CPU_MODEL_INTEL_SKYLAKE_MOBILE 0x4E
#define CPU_MODEL_INTEL_SKYLAKE_DESKTOP 0x5E
#define CPU_MODEL_INTEL_SKYLAKE_X 0x55
#define CPU_MODEL_INTEL_KABYLAKE_MOBILE 0x8E
#define CPU_MODEL_INTEL_KABYLAKE_DESKTOP 0x9E
#define CPU_MODEL_INTEL_CANNONLAKE_MOBILE 0x66
#define CPU_MODEL_INTEL_ICELAKE_MOBILE 0x7E

/* "Small Core" Processors (Atom) */

#define CPU_MODEL_INTEL_ATOM_PINEVIEW 0x1C
#define CPU_MODEL_INTEL_ATOM_LINCROFT 0x26
#define CPU_MODEL_INTEL_ATOM_PENWELL 0x27
#define CPU_MODEL_INTEL_ATOM_CLOVERVIEW 0x35
#define CPU_MODEL_INTEL_ATOM_CEDARVIEW 0x36
/* BayTrail/BYT / Valleyview */
#define CPU_MODEL_INTEL_ATOM_SILVERMONT1 0x37
/* Avaton/Rangely */
#define CPU_MODEL_INTEL_ATOM_SILVERMONT2 0x4D
/* CherryTrail / Braswell */
#define CPU_MODEL_INTEL_ATOM_AIRMONT 0x4C
/* Tangier */
#define CPU_MODEL_INTEL_ATOM_MERRIFIELD 0x4A
/* Anniedale */
#define CPU_MODEL_INTEL_ATOM_MOOREFIELD 0x5A
#define CPU_MODEL_INTEL_ATOM_GOLDMONT 0x5C
/* Goldmont Microserver */
#define CPU_MODEL_INTEL_ATOM_DENVERTON 0x5F
#define CPU_MODEL_INTEL_ATOM_GEMINI_LAKE 0x7A

/* Xeon Phi */

/* Knights Landing */
#define CPU_MODEL_INTEL_XEON_PHI_KNL 0x57
/* Knights Mill */
#define CPU_MODEL_INTEL_XEON_PHI_KNM 0x85

#endif /* ARCH_INTEL_FAMILY_H */
72 changes: 72 additions & 0 deletions src/arch/x86/include/arch/pci_mmio_cfg_romcc.h
View file
@@ -0,0 +1,72 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#ifndef _PCI_MMIO_CFG_ROMCC_H
#define _PCI_MMIO_CFG_ROMCC_H

#include <stdint.h>
#include <device/mmio.h>
#include <device/pci_type.h>


static __always_inline
uint8_t pci_mmio_read_config8(pci_devfn_t dev, uint16_t reg)
{
void *addr;
addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | reg);
return read8(addr);
}

static __always_inline
uint16_t pci_mmio_read_config16(pci_devfn_t dev, uint16_t reg)
{
void *addr;
addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~1));
return read16(addr);
}

static __always_inline
uint32_t pci_mmio_read_config32(pci_devfn_t dev, uint16_t reg)
{
void *addr;
addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~3));
return read32(addr);
}

static __always_inline
void pci_mmio_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value)
{
void *addr;
addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | reg);
write8(addr, value);
}

static __always_inline
void pci_mmio_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value)
{
void *addr;
addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~1));
write16(addr, value);
}

static __always_inline
void pci_mmio_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value)
{
void *addr;
addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~3));
write32(addr, value);
}

#endif /* _PCI_MMIO_CFG_ROMCC_H */
6 changes: 6 additions & 0 deletions src/arch/x86/include/arch/pci_ops.h
View file
Expand Up @@ -15,6 +15,12 @@
#define ARCH_I386_PCI_OPS_H

#include <arch/pci_io_cfg.h>

#if defined(__ROMCC__)
/* Must come before <device/pci_mmio_cfg.h> */
#include <arch/pci_mmio_cfg_romcc.h>
#endif

#include <device/pci_mmio_cfg.h>

#endif /* ARCH_I386_PCI_OPS_H */
346 changes: 330 additions & 16 deletions src/arch/x86/smbios.c
View file

Large diffs are not rendered by default.

2 changes: 1 addition & 1 deletion src/commonlib/cbfs.c
View file
Expand Up @@ -25,7 +25,7 @@
#if !defined(LOG)
#define LOG(x...) printk(BIOS_INFO, "CBFS: " x)
#endif
#if defined(IS_ENABLED)
#if defined(CONFIG)

#if CONFIG(DEBUG_CBFS)
#define DEBUG(x...) printk(BIOS_SPEW, "CBFS: " x)
Expand Down
15 changes: 15 additions & 0 deletions src/commonlib/include/commonlib/compiler.h
View file
Expand Up @@ -48,4 +48,19 @@
#define __always_inline inline __attribute__((always_inline))
#endif

/* This evaluates to the type of the first expression, unless that is constant
in which case it evalutates to the type of the second. This is useful when
assigning macro parameters to temporary variables, because that would
normally circumvent the special loosened type promotion rules for integer
literals. By using this macro, the promotion can happen at the time the
literal is assigned to the temporary variable. If the literal doesn't fit in
the chosen type, -Werror=overflow will catch it, so this should be safe. */
#define __TYPEOF_UNLESS_CONST(expr, fallback_expr) __typeof__( \
__builtin_choose_expr(__builtin_constant_p(expr), fallback_expr, expr))

/* This creates a unique local variable name for use in macros. */
#define __TMPNAME_3(i) __tmpname_##i
#define __TMPNAME_2(i) __TMPNAME_3(i)
#define __TMPNAME __TMPNAME_2(__COUNTER__)

#endif
77 changes: 57 additions & 20 deletions src/commonlib/include/commonlib/helpers.h
View file
Expand Up @@ -16,6 +16,7 @@
/* This file is for helpers for both coreboot firmware and its utilities. */

#ifndef __ASSEMBLER__
#include <commonlib/compiler.h>
#include <stddef.h>
#endif

Expand All @@ -29,35 +30,71 @@
#define ALIGN_DOWN(x, a) ((x) & ~((__typeof__(x))(a)-1UL))
#define IS_ALIGNED(x, a) (((x) & ((__typeof__(x))(a)-1UL)) == 0)

/* Double-evaluation unsafe min/max, for bitfields and outside of functions */
#define __CMP_UNSAFE(a, b, op) ((a) op (b) ? (a) : (b))
#define MIN_UNSAFE(a, b) __CMP_UNSAFE(a, b, <)
#define MAX_UNSAFE(a, b) __CMP_UNSAFE(a, b, >)

#define __CMP_SAFE(a, b, op, var_a, var_b) ({ \
__TYPEOF_UNLESS_CONST(a, b) var_a = (a); \
__TYPEOF_UNLESS_CONST(b, a) var_b = (b); \
var_a op var_b ? var_a : var_b; \
})

#ifdef __ROMCC__ /* romcc doesn't support __builtin_choose_expr() */
#define __CMP(a, b, op) __CMP_UNSAFE(a, b, op)
#else
#define __CMP(a, b, op) __builtin_choose_expr( \
__builtin_constant_p(a) && __builtin_constant_p(b), \
__CMP_UNSAFE(a, b, op), __CMP_SAFE(a, b, op, __TMPNAME, __TMPNAME))
#endif

#ifndef MIN
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#define MIN(a, b) __CMP(a, b, <)
#endif
#ifndef MAX
#define MAX(a, b) ((a) > (b) ? (a) : (b))
#define MAX(a, b) __CMP(a, b, >)
#endif
#define ABS(a) (((a) < 0) ? (-(a)) : (a))
#define IS_POWER_OF_2(x) (((x) & ((x) - 1)) == 0)
#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y))
#define SWAP(a, b) do { \
typeof(a) tmp = a; \
a = (typeof(a)) b; \
b = (typeof(b)) tmp; \
} while (0)

#ifndef ABS
#define ABS(a) ({ \
__typeof__(a) _abs_local_a = (a); \
(_abs_local_a < 0) ? (-_abs_local_a) : _abs_local_a; \
})
#endif

#define IS_POWER_OF_2(x) ({ \
__typeof__(x) _power_local_x = (x); \
(_power_local_x & (_power_local_x - 1)) == 0; \
})

#define DIV_ROUND_UP(x, y) ({ \
__typeof__(x) _div_local_x = (x); \
__typeof__(y) _div_local_y = (y); \
(_div_local_x + _div_local_y - 1) / _div_local_y; \
})

#define SWAP(a, b) do { \
__typeof__(&(a)) _swap_local_a = &(a); \
__typeof__(&(b)) _swap_local_b = &(b); \
__typeof__(a) _swap_local_tmp = *_swap_local_a; \
*_swap_local_a = *_swap_local_b; \
*_swap_local_b = _swap_local_tmp; \
} while (0)

/*
* Divide positive or negative dividend by positive divisor and round
* to closest integer. Result is undefined for negative divisors and
* for negative dividends if the divisor variable type is unsigned.
*/
#define DIV_ROUND_CLOSEST(x, divisor)( \
{ \
typeof(x) __x = x; \
typeof(divisor) __d = divisor; \
(((typeof(x))-1) > 0 || \
((typeof(divisor))-1) > 0 || (__x) > 0) ? \
(((__x) + ((__d) / 2)) / (__d)) : \
(((__x) - ((__d) / 2)) / (__d)); \
} \
)
#define DIV_ROUND_CLOSEST(x, divisor)({ \
__typeof__(x) _div_local_x = (x); \
__typeof__(divisor) _div_local_d = (divisor); \
(((__typeof__(x))-1) > 0 || \
((__typeof__(divisor))-1) > 0 || (_div_local_x) > 0) ? \
((_div_local_x + (_div_local_d / 2)) / _div_local_d) : \
((_div_local_x - (_div_local_d / 2)) / _div_local_d); \
})

/* Standard units. */
#define KiB (1<<10)
Expand Down
1 change: 0 additions & 1 deletion src/commonlib/storage/pci_sdhci.c
View file
Expand Up @@ -18,7 +18,6 @@
#endif

#include <arch/early_variables.h>
#include <assert.h>
#include <commonlib/sdhci.h>
#include <device/pci.h>
#include <device/pci_ops.h>
Expand Down
3 changes: 1 addition & 2 deletions src/commonlib/storage/sd.c
View file
Expand Up @@ -19,14 +19,13 @@
* GNU General Public License for more details.
*/

#include <assert.h>
#include <commonlib/sd_mmc_ctrlr.h>
#include <commonlib/storage.h>
#include <delay.h>
#include <endian.h>

#include "sd_mmc.h"
#include "storage.h"
#include <timer.h>

int sd_send_if_cond(struct storage_media *media)
{
Expand Down
5 changes: 2 additions & 3 deletions src/commonlib/storage/sd_mmc.c
View file
Expand Up @@ -20,15 +20,14 @@
* GNU General Public License for more details.
*/

#include <assert.h>
#include <commonlib/storage.h>
#include <delay.h>
#include <endian.h>
#include <string.h>

#include "mmc.h"
#include "sd_mmc.h"
#include "storage.h"
#include <string.h>
#include <timer.h>

uint64_t sd_mmc_extract_uint32_bits(const uint32_t *array, int start, int count)
{
Expand Down
1 change: 0 additions & 1 deletion src/commonlib/storage/sdhci.c
View file
Expand Up @@ -17,7 +17,6 @@
* GNU General Public License for more details.
*/

#include <assert.h>
#include "bouncebuf.h"
#include <commonlib/sd_mmc_ctrlr.h>
#include <commonlib/sdhci.h>
Expand Down
6 changes: 3 additions & 3 deletions src/commonlib/storage/sdhci_adma.c
View file
Expand Up @@ -17,16 +17,16 @@
* GNU General Public License for more details.
*/

#include <assert.h>
#include <commonlib/sdhci.h>
#include <commonlib/storage.h>
#include <console/console.h>
#include <delay.h>
#include <endian.h>
#include <string.h>

#include "sdhci.h"
#include "sd_mmc.h"
#include "storage.h"
#include <string.h>
#include <timer.h>

static void sdhci_alloc_adma_descs(struct sdhci_ctrlr *sdhci_ctrlr,
u32 need_descriptors)
Expand Down
1 change: 0 additions & 1 deletion src/commonlib/storage/storage.c
View file
Expand Up @@ -21,7 +21,6 @@
* GNU General Public License for more details.
*/

#include <assert.h>
#include <commonlib/storage.h>
#include "sd_mmc.h"
#include "storage.h"
Expand Down
8 changes: 5 additions & 3 deletions src/console/vtxprintf.c
View file
Expand Up @@ -56,8 +56,10 @@ static int number(void (*tx_byte)(unsigned char byte, void *data),
int count = 0;
#ifdef SUPPORT_64BIT_INTS
unsigned long long num = inum;
long long snum = num;
#else
unsigned long num = (long)inum;
unsigned long num = (unsigned long)inum;
long snum = (long)num;

if (num != inum) {
/* Alert user to an incorrect result by printing #^!. */
Expand All @@ -76,9 +78,9 @@ static int number(void (*tx_byte)(unsigned char byte, void *data),
c = (type & ZEROPAD) ? '0' : ' ';
sign = 0;
if (type & SIGN) {
if ((signed long long)num < 0) {
if (snum < 0) {
sign = '-';
num = -num;
num = -snum;
size--;
} else if (type & PLUS) {
sign = '+';
Expand Down
5 changes: 2 additions & 3 deletions src/cpu/allwinner/a10/timer.c
View file
Expand Up @@ -17,11 +17,10 @@
*
*/

#include "timer.h"

#include <device/mmio.h>
#include <delay.h>
#include <timer.h>

#include "timer.h"

struct a1x_timer_module *const timer_module = (void *)A1X_TIMER_BASE;
struct a1x_timer *const tmr0 =
Expand Down
1 change: 1 addition & 0 deletions src/cpu/amd/family_10h-family_15h/fidvid.c
View file
Expand Up @@ -89,6 +89,7 @@ b.- prep_fid_change(...)
*/

#include <console/console.h>
#include <cpu/amd/msr.h>
#include <inttypes.h>
#include <northbridge/amd/amdht/AsPsDefs.h>
Expand Down
1 change: 1 addition & 0 deletions src/cpu/amd/family_10h-family_15h/init_cpus.c
View file
Expand Up @@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/

#include <console/console.h>
#include <cpu/amd/msr.h>
#include <device/pci_ops.h>
#include "init_cpus.h"
Expand Down
1 change: 0 additions & 1 deletion src/cpu/amd/family_10h-family_15h/init_cpus.h
View file
Expand Up @@ -17,7 +17,6 @@
#define INIT_CPUS_H

#include <stdlib.h>
#include <console/console.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
Expand Down
5 changes: 5 additions & 0 deletions src/cpu/intel/car/non-evict/cache_as_ram.S
View file
Expand Up @@ -33,6 +33,11 @@ _cache_as_ram_setup:

bootblock_pre_c_entry:

#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
movl $cache_as_ram, %esp /* return address */
jmp check_mtrr /* Check if CPU properly reset */
#endif

cache_as_ram:
post_code(0x20)

Expand Down
5 changes: 1 addition & 4 deletions src/cpu/intel/haswell/Kconfig
View file
Expand Up @@ -23,10 +23,7 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select PARALLEL_MP
select CPU_INTEL_COMMON

config BOOTBLOCK_CPU_INIT
string
default "cpu/intel/haswell/bootblock.c"
select NO_FIXED_XIP_ROM_SIZE

config SMM_TSEG_SIZE
hex
Expand Down
8 changes: 7 additions & 1 deletion src/cpu/intel/haswell/Makefile.inc
View file
Expand Up @@ -21,9 +21,15 @@ ramstage-y += monotonic_timer.c
smm-y += monotonic_timer.c
endif

cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
bootblock-y += ../car/non-evict/cache_as_ram.S
bootblock-y += ../car/bootblock.c
bootblock-y += ../../x86/early_reset.S
bootblock-y += bootblock.c

postcar-y += ../car/non-evict/exit_car.S

verstage-y += tsc_freq.c

subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/mtrr
subdirs-y += ../../x86/lapic
Expand Down
57 changes: 3 additions & 54 deletions src/cpu/intel/haswell/bootblock.c
View file
Expand Up @@ -14,7 +14,7 @@
*/

#include <stdint.h>
#include <cpu/x86/cache.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <arch/io.h>
Expand All @@ -23,41 +23,8 @@
#include <cpu/intel/microcode/microcode.c>
#include "haswell.h"

#if CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT)
/* Needed for RCBA access to set Soft Reset Data register */
#include <southbridge/intel/lynxpoint/pch.h>
#else
#error "CPU must be paired with Intel LynxPoint southbridge"
#endif

static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size,
unsigned int type)

{
/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
/* FIXME: It only support 4G less range */
msr_t basem, maskm;
basem.lo = base | type;
basem.hi = 0;
wrmsr(MTRR_PHYS_BASE(reg), basem);
maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
wrmsr(MTRR_PHYS_MASK(reg), maskm);
}

static void enable_rom_caching(void)
{
msr_t msr;

disable_cache();
set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
enable_cache();

/* Enable Variable MTRRs */
msr.hi = 0x00000000;
msr.lo = 0x00000800;
wrmsr(MTRR_DEF_TYPE_MSR, msr);
}
#include <cpu/intel/car/bootblock.h>

static void set_flex_ratio_to_tdp_nominal(void)
{
Expand Down Expand Up @@ -105,26 +72,8 @@ static void set_flex_ratio_to_tdp_nominal(void)
halt();
}

static void check_for_clean_reset(void)
{
msr_t msr;
msr = rdmsr(MTRR_DEF_TYPE_MSR);

/* Use the MTRR default type MSR as a proxy for detecting INIT#.
* Reset the system if any known bits are set in that MSR. That is
* an indication of the CPU not being properly reset. */
if (msr.lo & (MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)) {
outb(0x0, 0xcf9);
outb(0x6, 0xcf9);
halt();
}
}

static void bootblock_cpu_init(void)
void bootblock_early_cpu_init(void)
{
/* Set flex ratio and reset if needed */
set_flex_ratio_to_tdp_nominal();
check_for_clean_reset();
enable_rom_caching();
intel_update_microcode_from_cbfs();
}
1 change: 0 additions & 1 deletion src/cpu/intel/hyperthreading/intel_sibling.c
View file
Expand Up @@ -17,7 +17,6 @@
#include <device/device.h>
#include <pc80/mc146818rtc.h>
#include <smp/spinlock.h>
#include <assert.h>

#if CONFIG(PARALLEL_CPU_INIT)
#error Intel hyper-threading requires serialized CPU init
Expand Down
5 changes: 1 addition & 4 deletions src/cpu/intel/model_2065x/Kconfig
View file
Expand Up @@ -19,6 +19,7 @@ config CPU_SPECIFIC_OPTIONS
#select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
select CPU_INTEL_COMMON
select NO_FIXED_XIP_ROM_SIZE

config BOOTBLOCK_CPU_INIT
string
Expand All @@ -28,8 +29,4 @@ config SMM_TSEG_SIZE
hex
default 0x800000

config XIP_ROM_SIZE
hex
default 0x20000

endif
5 changes: 1 addition & 4 deletions src/cpu/intel/model_206ax/Kconfig
View file
Expand Up @@ -25,15 +25,12 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_COMMON
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
select PARALLEL_MP
select NO_FIXED_XIP_ROM_SIZE

config BOOTBLOCK_CPU_INIT
string
default "cpu/intel/model_206ax/bootblock.c"

config XIP_ROM_SIZE
hex
default 0x20000 if USE_NATIVE_RAMINIT

config SMM_TSEG_SIZE
hex
default 0x800000
Expand Down
1 change: 0 additions & 1 deletion src/cpu/intel/model_206ax/model_206ax_init.c
View file
Expand Up @@ -15,7 +15,6 @@
* GNU General Public License for more details.
*/

#include <assert.h>
#include <console/console.h>
#include <device/device.h>
#include <arch/acpi.h>
Expand Down
1 change: 1 addition & 0 deletions src/cpu/intel/socket_FCBGA559/Kconfig
View file
Expand Up @@ -11,6 +11,7 @@ config SOCKET_SPECIFIC_OPTIONS
select MMX
select SSE
select CPU_HAS_L2_ENABLE_MSR
select NO_FIXED_XIP_ROM_SIZE

config DCACHE_RAM_BASE
hex
Expand Down
31 changes: 7 additions & 24 deletions src/cpu/intel/speedstep/acpi.c
View file
Expand Up @@ -21,6 +21,7 @@
#include <arch/acpigen.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <cpu/intel/fsb.h>
#include <cpu/intel/speedstep.h>
#include <device/device.h>

Expand All @@ -40,29 +41,6 @@ static int determine_total_number_of_cores(void)
return count;
}

/**
* @brief Returns three times the FSB clock in MHz
*
* The result of calculations with the returned value shall be divided by 3.
* This helps to avoid rounding errors.
*/
static int get_fsb(void)
{
const u32 fsbcode = rdmsr(MSR_FSB_FREQ).lo & 7;
switch (fsbcode) {
case 0: return 800; /* / 3 == 266 */
case 1: return 400; /* / 3 == 133 */
case 2: return 600; /* / 3 == 200 */
case 3: return 500; /* / 3 == 166 */
case 4: return 1000; /* / 3 == 333 */
case 5: return 300; /* / 3 == 100 */
case 6: return 1200; /* / 3 == 400 */
}
printk(BIOS_WARNING,
"Warning: No supported FSB frequency. Assuming 200MHz\n");
return 600;
}

static void gen_pstate_entries(const sst_table_t *const pstates,
const int cpuID, const int cores_per_package,
const uint8_t coordination)
Expand All @@ -75,7 +53,12 @@ static void gen_pstate_entries(const sst_table_t *const pstates,
cpuID, cores_per_package, coordination);
acpigen_write_name("_PSS");

const int fsb3 = get_fsb();
int fsb3 = get_ia32_fsb_x3();
if (fsb3 <= 0) {
printk(BIOS_ERR, "CPU or FSB not supported. Assuming 200MHz\n");
fsb3 = 600;
}

const int min_ratio2 = SPEEDSTEP_DOUBLE_RATIO(
pstates->states[pstates->num_states - 1]);
const int max_ratio2 = SPEEDSTEP_DOUBLE_RATIO(pstates->states[0]);
Expand Down
45 changes: 45 additions & 0 deletions src/cpu/x86/early_reset.S
View file
@@ -0,0 +1,45 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

/*
* input %esp: return address (not pointer to return address!)
* clobber the content of eax, ecx, edx
*/

#include <cpu/x86/mtrr.h>

.section .text
.global check_mtrr

check_mtrr:
/* Use the MTRR default type MSR as a proxy for detecting INIT#.
* Reset the system if any known bits are set in that MSR. That is
* an indication of the CPU not being properly reset. */

check_for_clean_reset:
movl $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
andl $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax
cmp $0, %eax
jnz warm_reset
jmp *%esp
/* perform warm reset */
warm_reset:
movw $0xcf9, %dx
movb $0x06, %al
outb %al, %dx
/* Should not reach this*/
.Lhlt:
hlt
jmp .Lhlt
1 change: 1 addition & 0 deletions src/cpu/x86/mp_init.c
View file
Expand Up @@ -36,6 +36,7 @@
#include <smp/atomic.h>
#include <smp/spinlock.h>
#include <symbols.h>
#include <timer.h>
#include <thread.h>

#define MAX_APIC_IDS 256
Expand Down
8 changes: 7 additions & 1 deletion src/device/Makefile.inc
View file
Expand Up @@ -26,9 +26,15 @@ postcar-y += pci_early.c

ramstage-y += pci_class.c
ramstage-y += pci_device.c
ramstage-y += pci_ops.c
ramstage-y += pci_rom.c

bootblock-y += pci_ops.c
verstage-y += pci_ops.c
romstage-y += pci_ops.c
postcar-y += pci_ops.c
ramstage-y += pci_ops.c
smm-y += pci_ops.c

ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c
ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c
ramstage-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c
Expand Down
5 changes: 4 additions & 1 deletion src/device/device_util.c
View file
Expand Up @@ -628,7 +628,7 @@ void disable_children(struct bus *bus)

/*
* Returns true if the device is an enabled bridge that has at least
* one enabled device on its secondary bus.
* one enabled device on its secondary bus that is not of type NONE.
*/
bool dev_is_active_bridge(struct device *dev)
{
Expand All @@ -643,6 +643,9 @@ bool dev_is_active_bridge(struct device *dev)

for (link = dev->link_list; link; link = link->next) {
for (child = link->children; child; child = child->sibling) {
if (child->path.type == DEVICE_PATH_NONE)
continue;

if (child->enabled)
return 1;
}
Expand Down
5 changes: 2 additions & 3 deletions src/device/dram/ddr3.c
View file
Expand Up @@ -136,7 +136,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd)
u8 reg8;
u32 mtb; /* medium time base */
u32 ftb; /* fine time base */
unsigned int val, param;
unsigned int val;

ret = SPD_STATUS_OK;

Expand Down Expand Up @@ -173,8 +173,7 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd)
printram(" Invalid number of memory banks\n");
ret = SPD_STATUS_INVALID_FIELD;
}
param = 1 << (val + 3);
printram(" Banks : %u\n", param);
printram(" Banks : %u\n", 1 << (val + 3));
/* SDRAM capacity */
capacity_shift = reg8 & 0x0f;
if (capacity_shift > 0x06) {
Expand Down
1 change: 0 additions & 1 deletion src/device/oprom/include/x86emu/x86emu.h
View file
Expand Up @@ -42,7 +42,6 @@
#define __X86EMU_X86EMU_H

#include <stddef.h>
#include <console/console.h>
#if CONFIG(X86EMU_DEBUG)
#define DEBUG
#endif
Expand Down
2 changes: 2 additions & 0 deletions src/device/oprom/x86emu/debug.h
View file
Expand Up @@ -39,6 +39,8 @@
#ifndef __X86EMU_DEBUG_H
#define __X86EMU_DEBUG_H

#include <console/console.h>

/*---------------------- Macros and type definitions ----------------------*/

/* printf is not available in coreboot... use printk */
Expand Down
1 change: 1 addition & 0 deletions src/device/oprom/yabel/biosemu.c
View file
Expand Up @@ -53,6 +53,7 @@
#include "compat/rtas.h"

#if CONFIG(X86EMU_DEBUG_TIMINGS)
#include <timer.h>
struct mono_time zero;
#endif

Expand Down
4 changes: 4 additions & 0 deletions src/device/pci_ops.c
View file
Expand Up @@ -10,3 +10,7 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include <stdint.h>

u8 *const pci_mmconf = (void *)(uintptr_t)CONFIG_MMCONF_BASE_ADDRESS;
1 change: 1 addition & 0 deletions src/drivers/amd/agesa/def_callouts.c
View file
Expand Up @@ -15,6 +15,7 @@
*/

#include <cbfs.h>
#include <console/console.h>
#include <spd_bin.h>
#include <string.h>

Expand Down
1 change: 1 addition & 0 deletions src/drivers/amd/agesa/heapmanager.c
View file
Expand Up @@ -20,6 +20,7 @@
#include <northbridge/amd/agesa/BiosCallOuts.h>

#include <arch/acpi.h>
#include <console/console.h>
#include <string.h>

/* BIOS_HEAP_START_ADDRESS is only for cold boots. */
Expand Down
1 change: 1 addition & 0 deletions src/drivers/amd/agesa/oem_s3.c
View file
Expand Up @@ -17,6 +17,7 @@
#include <spi_flash.h>
#include <string.h>
#include <cbmem.h>
#include <console/console.h>
#include <program_loading.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <AGESA.h>
Expand Down
4 changes: 1 addition & 3 deletions src/drivers/amd/agesa/state_machine.c
View file
Expand Up @@ -16,17 +16,15 @@

#include <stdint.h>
#include <string.h>

#include <arch/acpi.h>
#include <arch/cpu.h>
#include <bootstate.h>
#include <cbfs.h>

#include <console/console.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <amdlib.h>

#include <AMD.h>

#if CONFIG(CPU_AMD_AGESA_OPENSOURCE)
Expand Down
4 changes: 1 addition & 3 deletions src/drivers/aspeed/ast2050/ast2050.c
View file
Expand Up @@ -12,17 +12,15 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <delay.h>

#include <stdlib.h>
#include <arch/io.h>
#include <edid.h>

#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>

#include <pc80/vga.h>

#include "../common/aspeed_coreboot.h"
Expand Down
2 changes: 2 additions & 0 deletions src/drivers/aspeed/common/ast_dp501.c
View file
Expand Up @@ -15,6 +15,8 @@
* GNU General Public License for more details.
*/

#include <delay.h>

#include "ast_drv.h"

static void send_ack(struct ast_private *ast)
Expand Down
4 changes: 3 additions & 1 deletion src/drivers/aspeed/common/ast_main.c
View file
Expand Up @@ -26,8 +26,10 @@
/*
* Authors: Dave Airlie <airlied@redhat.com>
*/
#include "ast_drv.h"

#include <delay.h>

#include "ast_drv.h"
#include "ast_dram_tables.h"

void ast_set_index_reg_mask(struct ast_private *ast,
Expand Down
3 changes: 2 additions & 1 deletion src/drivers/aspeed/common/ast_post.c
View file
Expand Up @@ -29,8 +29,9 @@

#define COREBOOT_AST_FAILOVER_TIMEOUT 10000000

#include "ast_drv.h"
#include <delay.h>

#include "ast_drv.h"
#include "ast_dram_tables.h"

static void ast_init_dram_2300(struct drm_device *dev);
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/emulation/qemu/bochs.c
View file
Expand Up @@ -12,11 +12,9 @@
*/

#include <stdint.h>
#include <delay.h>
#include <edid.h>
#include <stdlib.h>
#include <arch/io.h>

#include <boot/coreboot_tables.h>
#include <console/console.h>
#include <device/device.h>
Expand Down
3 changes: 0 additions & 3 deletions src/drivers/emulation/qemu/cirrus.c
View file
Expand Up @@ -15,17 +15,14 @@
*/

#include <stdint.h>
#include <delay.h>
#include <edid.h>
#include <stdlib.h>

#include <boot/coreboot_tables.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>

#include <pc80/vga.h>
#include <pc80/vga_io.h>

Expand Down
1 change: 0 additions & 1 deletion src/drivers/generic/gpio_keys/gpio_keys.c
View file
Expand Up @@ -15,7 +15,6 @@

#include <arch/acpi_device.h>
#include <arch/acpigen.h>
#include <console/console.h>
#include <device/device.h>
#include <device/path.h>
#include <string.h>
Expand Down
1 change: 0 additions & 1 deletion src/drivers/generic/gpio_regulator/gpio_regulator.c
View file
Expand Up @@ -15,7 +15,6 @@

#include <arch/acpi_device.h>
#include <arch/acpigen.h>
#include <console/console.h>
#include <device/device.h>
#include <device/path.h>
#include <string.h>
Expand Down
19 changes: 19 additions & 0 deletions src/drivers/i2c/hid/hid.c
View file
Expand Up @@ -18,6 +18,8 @@
#include <stdint.h>
#include <string.h>
#include "chip.h"
#include <gpio.h>
#include <console/console.h>

#if CONFIG(HAVE_ACPI_TABLES)
static void i2c_hid_fill_dsm(struct device *dev)
Expand Down Expand Up @@ -60,6 +62,23 @@ static void i2c_hid_enable(struct device *dev)
{
struct drivers_i2c_hid_config *config = dev->chip_info;

if (!config)
return;

/* Check if device is present by reading GPIO */
if (config->generic.device_present_gpio) {
int present = gpio_get(config->generic.device_present_gpio);
present ^= config->generic.device_present_gpio_invert;

printk(BIOS_INFO, "%s is %spresent\n",
dev->chip_ops->name, present ? "" : "not ");

if (!present) {
dev->enabled = 0;
return;
}
}

dev->ops = &i2c_hid_ops;

if (config && config->generic.desc) {
Expand Down
18 changes: 14 additions & 4 deletions src/drivers/i2c/sx9310/chip.h
View file
Expand Up @@ -22,10 +22,20 @@
#define REGISTER(NAME) uint8_t NAME

struct drivers_i2c_sx9310_config {
const char *desc; /* Device Description */
unsigned int uid; /* ACPI _UID */
enum i2c_speed speed; /* Bus speed in Hz, default is I2C_SPEED_FAST */
struct acpi_irq irq; /* Interrupt */
/* Device Description */
const char *desc;

/* ACPI _UID */
unsigned int uid;

/* Bus speed in Hz, default is I2C_SPEED_FAST */
enum i2c_speed speed;

/* Use GPIO-based interrupt instead of IO-APIC */
struct acpi_gpio irq_gpio;

/* IO-APIC interrupt */
struct acpi_irq irq;
#include "registers.h"
};

Expand Down
7 changes: 6 additions & 1 deletion src/drivers/i2c/sx9310/sx9310.c
View file
Expand Up @@ -59,7 +59,12 @@ static void i2c_sx9310_fill_ssdt(struct device *dev)
acpigen_write_name("_CRS");
acpigen_write_resourcetemplate_header();
acpi_device_write_i2c(&i2c);
acpi_device_write_interrupt(&config->irq);

if (config->irq_gpio.pin_count)
acpi_device_write_gpio(&config->irq_gpio);
else
acpi_device_write_interrupt(&config->irq);

acpigen_write_resourcetemplate_footer();

/* DSD */
Expand Down
5 changes: 2 additions & 3 deletions src/drivers/i2c/tpm/tis.c
View file
Expand Up @@ -18,15 +18,14 @@
#include <string.h>
#include <assert.h>
#include <commonlib/endian.h>
#include <console/console.h>
#include <delay.h>
#include <device/i2c_simple.h>
#include <endian.h>
#include <lib.h>
#include <security/tpm/tis.h>
#include "tpm.h"
#include <timer.h>

#include <console/console.h>
#include "tpm.h"

/* global structure for tpm chip data */
static struct tpm_chip g_chip CAR_GLOBAL;
Expand Down
2 changes: 2 additions & 0 deletions src/drivers/intel/fsp1_0/fsp_util.h
View file
Expand Up @@ -17,6 +17,8 @@
#define FSP_UTIL_H

#include <chipset_fsp_util.h>
#include <console/console.h>

#include "fsp_values.h"

#if CONFIG(ENABLE_MRC_CACHE)
Expand Down
40 changes: 26 additions & 14 deletions src/drivers/intel/fsp1_1/Kconfig
View file
Expand Up @@ -25,15 +25,40 @@ if PLATFORM_USES_FSP1_1

comment "Intel FSP 1.1"

config FSP_USE_REPO
bool "Use FSP binary from 3rdparty/fsp repo"
select HAVE_FSP_BIN
depends on SOC_INTEL_BRASWELL && !USE_GOOGLE_FSP
default y

config HAVE_FSP_BIN
bool "Should the Intel FSP binary be added to the flash image"
bool "Add Intel FSP binary to flash image"
help
Select this option to add an Intel FSP binary to
the resulting coreboot image.

Note: Without this binary, coreboot builds relying on the FSP
will not boot

config FSP_FILE
string
prompt "Intel FSP binary path and filename" if !FSP_USE_REPO
depends on HAVE_FSP_BIN
default "3rdparty/fsp/BraswellFspBinPkg/FspBin/BSWFSP.fd" if FSP_USE_REPO
default ""
help
The path and filename of the Intel FSP binary for this platform.

config FSP_LOC
hex "Intel FSP Binary location in CBFS"
default 0xfff6e000 if SOC_INTEL_BRASWELL && USE_GOOGLE_FSP
default 0xfff20000 if SOC_INTEL_BRASWELL
default 0xffee0000 if SOC_INTEL_SKYLAKE
help
The location in CBFS that the FSP is located. This must match the
value that is set in the FSP binary. If the FSP needs to be moved,
rebase the FSP with Intel's BCT (tool).

config CPU_MICROCODE_CBFS_LEN
hex "Microcode update region length in bytes"
default 0x0
Expand All @@ -47,19 +72,6 @@ config CPU_MICROCODE_CBFS_LOC
The location (base address) in CBFS that contains the microcode update
binary.

config FSP_FILE
string "Intel FSP binary path and filename"
help
The path and filename of the Intel FSP binary for this platform.

config FSP_LOC
hex "Intel FSP Binary location in CBFS"
default 0xffee0000
help
The location in CBFS that the FSP is located. This must match the
value that is set in the FSP binary. If the FSP needs to be moved,
rebase the FSP with Intel's BCT (tool).

config DISPLAY_HOBS
bool "Display hand-off-blocks (HOBs)"
default n
Expand Down
14 changes: 7 additions & 7 deletions src/drivers/intel/fsp1_1/cache_as_ram.inc
View file
Expand Up @@ -24,9 +24,8 @@
* performs the final stage of initialization.
*/


#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */

/* I/O delay between post codes on failure */
#define LHLT_DELAY 0x50000
/*
* Per FSP1.1 specs, following registers are preserved:
* EBX, EDI, ESI, EBP, MM0, MM1
Expand Down Expand Up @@ -165,8 +164,8 @@ halt1:
* 0x01 - FV signature, "_FVH" not present
* 0x02 - FFS GUID not present
* 0x03 - FSP INFO Header not found
* 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased to
* a different location, or does it need to be?
* 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased
* to a different location, or does it need to be?
* 0x05 - FSP INFO Header signature "FSPH" not found
* 0x06 - FSP Image ID is not the expected ID.
*/
Expand All @@ -181,7 +180,8 @@ halt2:
* 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid.
* 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met.
* 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed
* 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region.
* 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode
* region.
* 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked
*/
movb $0xBB, %ah
Expand Down Expand Up @@ -213,7 +213,7 @@ CAR_init_params:
.long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */
.long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */
.long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */
.long CONFIG_ROM_SIZE /* Total Firmware Length */
.long CONFIG_ROM_SIZE /* Firmware Length */

CAR_init_stack:
.long CAR_init_done
Expand Down
14 changes: 12 additions & 2 deletions src/drivers/intel/fsp1_1/include/fsp/romstage.h
View file
Expand Up @@ -3,6 +3,7 @@
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2015-2016 Intel Corporation
* Copyright (C) 2018 Eltan B.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
Expand All @@ -17,20 +18,28 @@
#ifndef _COMMON_ROMSTAGE_H_
#define _COMMON_ROMSTAGE_H_

#include <stddef.h>
#include <stdint.h>
#include <arch/cpu.h>
#include <memory_info.h>
#include <fsp/car.h>
#include <fsp/util.h>
#include <soc/intel/common/mma.h>
#include <soc/pei_wrapper.h>
#include <soc/pm.h> /* chip_power_state */

struct romstage_params {
uint32_t fsp_version;
struct chipset_power_state *power_state;
struct pei_data *pei_data;
void *chipset_context;

/* Fast boot and S3 resume MRC data */
size_t saved_data_size;
const void *saved_data;
bool disable_saved_data;

/* New save data from MRC */
size_t data_to_save_size;
const void *data_to_save;
};

/*
Expand Down Expand Up @@ -91,5 +100,6 @@ void soc_pre_ram_init(struct romstage_params *params);
/* Update the SOC specific memory config param for mma. */
void soc_update_memory_params_for_mma(MEMORY_INIT_UPD *memory_cfg,
struct mma_config_param *mma_cfg);
void mainboard_after_memory_init(void);

#endif /* _COMMON_ROMSTAGE_H_ */
24 changes: 15 additions & 9 deletions src/drivers/intel/fsp1_1/raminit.c
View file
Expand Up @@ -28,6 +28,7 @@

void raminit(struct romstage_params *params)
{
const bool s3wake = params->power_state->prev_sleep_state == ACPI_S3;
const EFI_GUID bootldr_tolum_guid = FSP_BOOTLOADER_TOLUM_HOB_GUID;
EFI_HOB_RESOURCE_DESCRIPTOR *cbmem_root;
FSP_INFO_HEADER *fsp_header;
Expand All @@ -46,7 +47,6 @@ void raminit(struct romstage_params *params)
u32 *mrc_hob;
u32 fsp_reserved_bytes;
MEMORY_INIT_UPD *original_params;
struct pei_data *pei_ptr;
EFI_STATUS status;
VPD_DATA_REGION *vpd_ptr;
UPD_DATA_REGION *upd_ptr;
Expand Down Expand Up @@ -80,10 +80,9 @@ void raminit(struct romstage_params *params)

/* Zero fill RT Buffer data and start populating fields. */
memset(&fsp_rt_common_buffer, 0, sizeof(fsp_rt_common_buffer));
pei_ptr = params->pei_data;
if (pei_ptr->boot_mode == ACPI_S3) {
if (s3wake) {
fsp_rt_common_buffer.BootMode = BOOT_ON_S3_RESUME;
} else if (pei_ptr->saved_data != NULL) {
} else if (params->saved_data != NULL) {
fsp_rt_common_buffer.BootMode =
BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;
} else {
Expand All @@ -93,7 +92,7 @@ void raminit(struct romstage_params *params)
fsp_rt_common_buffer.BootLoaderTolumSize = cbmem_overhead_size();

/* Get any board specific changes */
fsp_memory_init_params.NvsBufferPtr = (void *)pei_ptr->saved_data;
fsp_memory_init_params.NvsBufferPtr = (void *)params->saved_data;
fsp_memory_init_params.RtBufferPtr = &fsp_rt_common_buffer;
fsp_memory_init_params.HobListPtr = &hob_list_ptr;

Expand Down Expand Up @@ -125,6 +124,7 @@ void raminit(struct romstage_params *params)
timestamp_add_now(TS_FSP_MEMORY_INIT_START);
post_code(POST_FSP_MEMORY_INIT);
status = fsp_memory_init(&fsp_memory_init_params);
mainboard_after_memory_init();
post_code(0x37);
timestamp_add_now(TS_FSP_MEMORY_INIT_END);

Expand Down Expand Up @@ -157,7 +157,7 @@ void raminit(struct romstage_params *params)

/* Migrate CAR data */
printk(BIOS_DEBUG, "0x%p: cbmem_top\n", cbmem_top());
if (pei_ptr->boot_mode != ACPI_S3) {
if (!s3wake) {
cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
fsp_reserved_bytes);
} else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
Expand Down Expand Up @@ -219,7 +219,7 @@ void raminit(struct romstage_params *params)
}
hob_ptr.Raw = get_next_guid_hob(&mrc_guid, hob_list_ptr);
if (hob_ptr.Raw == NULL) {
if (params->pei_data->saved_data == NULL) {
if (params->saved_data == NULL) {
printk(BIOS_ERR, "7.3: FSP_NON_VOLATILE_STORAGE_HOB missing!\n");
fsp_verification_failure = 1;
}
Expand Down Expand Up @@ -293,8 +293,8 @@ void raminit(struct romstage_params *params)
"Memory Configuration Data Hob not present\n");
else if (!vboot_recovery_mode_enabled()) {
/* Do not save MRC data in recovery path */
pei_ptr->data_to_save = GET_GUID_HOB_DATA(mrc_hob);
pei_ptr->data_to_save_size = ALIGN(
params->data_to_save = GET_GUID_HOB_DATA(mrc_hob);
params->data_to_save_size = ALIGN(
((u32)GET_HOB_LENGTH(mrc_hob)), 16);
}
}
Expand Down Expand Up @@ -322,3 +322,9 @@ __weak void soc_memory_init_params(
{
printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
}

/* Initialize the SoC after MemoryInit */
__weak void mainboard_after_memory_init(void)
{
printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
}
41 changes: 13 additions & 28 deletions src/drivers/intel/fsp1_1/romstage.c
View file
Expand Up @@ -41,9 +41,7 @@
asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
{
void *top_of_stack;
struct pei_data pei_data;
struct romstage_params params = {
.pei_data = &pei_data,
.chipset_context = fih,
};

Expand All @@ -55,8 +53,6 @@ asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS))
intel_update_microcode_from_cbfs();

memset(&pei_data, 0, sizeof(pei_data));

/* Display parameters */
if (!CONFIG(NO_MMCONF_SUPPORT))
printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n",
Expand Down Expand Up @@ -94,14 +90,11 @@ void romstage_common(struct romstage_params *params)
{
bool s3wake;
struct region_device rdev;
struct pei_data *pei_data;

post_code(0x32);

timestamp_add_now(TS_BEFORE_INITRAM);

pei_data = params->pei_data;
pei_data->boot_mode = params->power_state->prev_sleep_state;
s3wake = params->power_state->prev_sleep_state == ACPI_S3;

if (CONFIG(ELOG_BOOT_COUNT) && !s3wake)
Expand All @@ -112,9 +105,9 @@ void romstage_common(struct romstage_params *params)
post_code(0x33);

/* Check recovery and MRC cache */
params->pei_data->saved_data_size = 0;
params->pei_data->saved_data = NULL;
if (!params->pei_data->disable_saved_data) {
params->saved_data_size = 0;
params->saved_data = NULL;
if (!params->disable_saved_data) {
if (vboot_recovery_mode_enabled()) {
/* Recovery mode does not use MRC cache */
printk(BIOS_DEBUG,
Expand All @@ -124,12 +117,11 @@ void romstage_common(struct romstage_params *params)
params->fsp_version,
&rdev))) {
/* MRC cache found */
params->pei_data->saved_data_size =
region_device_sz(&rdev);
params->pei_data->saved_data = rdev_mmap_full(&rdev);
params->saved_data_size = region_device_sz(&rdev);
params->saved_data = rdev_mmap_full(&rdev);
/* Assume boot device is memory mapped. */
assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
} else if (params->pei_data->boot_mode == ACPI_S3) {
} else if (s3wake) {
/* Waking from S3 and no cache. */
printk(BIOS_DEBUG,
"No MRC cache found in S3 resume path.\n");
Expand All @@ -147,15 +139,15 @@ void romstage_common(struct romstage_params *params)

/* Save MRC output */
if (CONFIG(CACHE_MRC_SETTINGS)) {
printk(BIOS_DEBUG, "MRC data at %p %d bytes\n",
pei_data->data_to_save, pei_data->data_to_save_size);
if ((params->pei_data->boot_mode != ACPI_S3)
&& (params->pei_data->data_to_save_size != 0)
&& (params->pei_data->data_to_save != NULL))
printk(BIOS_DEBUG, "MRC data at %p %zu bytes\n",
params->data_to_save, params->data_to_save_size);
if (!s3wake
&& (params->data_to_save_size != 0)
&& (params->data_to_save != NULL))
mrc_cache_stash_data(MRC_TRAINING_DATA,
params->fsp_version,
params->pei_data->data_to_save,
params->pei_data->data_to_save_size);
params->data_to_save,
params->data_to_save_size);
}

/* Save DIMM information */
Expand Down Expand Up @@ -343,13 +335,6 @@ __weak int mrc_cache_stash_data(int type, uint32_t version,
return -1;
}

/* Transition RAM from off or self-refresh to active */
__weak void raminit(struct romstage_params *params)
{
post_code(POST_MEM_PREINIT_PREP_START);
die("ERROR - No RAM initialization specified!\n");
}

/* Display the memory configuration */
__weak void report_memory_config(void)
{
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/intel/fsp2_0/Makefile.inc
View file
Expand Up @@ -69,7 +69,7 @@ $(CONFIG_FSP_S_CBFS)-type := fsp

ifeq ($(CONFIG_FSP_USE_REPO),y)
$(obj)/Fsp_M.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH))
python2 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)"
python2 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)" -n "Fsp.fd"

$(obj)/Fsp_S.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(obj)/Fsp_M.fd
true
Expand Down
9 changes: 7 additions & 2 deletions src/drivers/intel/fsp2_0/memory_init.c
View file
Expand Up @@ -310,8 +310,6 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake,
post_code(POST_FSP_MEMORY_EXIT);
timestamp_add_now(TS_FSP_MEMORY_INIT_END);

fsp_debug_after_memory_init(status);

/* Handle any errors returned by FspMemoryInit */
fsp_handle_reset(status);
if (status != FSP_SUCCESS) {
Expand All @@ -320,6 +318,13 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake,
}

do_fsp_post_memory_init(s3wake, fsp_version);

/*
* fsp_debug_after_memory_init() checks whether the end of the tolum
* region is the same as the top of cbmem, so must be called here
* after cbmem has been initialised in do_fsp_post_memory_init().
*/
fsp_debug_after_memory_init(status);
}

/* Load the binary into the memory specified by the info header. */
Expand Down
11 changes: 1 addition & 10 deletions src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
View file
Expand Up @@ -13,7 +13,7 @@
* GNU General Public License for more details.
*/

#include <assert.h>
#include <console/console.h>
#include <cpu/cpu.h>
#include <cpu/x86/mp.h>
#include <cpu/x86/lapic.h>
Expand Down Expand Up @@ -45,9 +45,6 @@ static efi_return_status_t mp_get_processor_info(const
efi_uintn_t processor_number,
efi_processor_information *processor_info_buffer)
{
if (cpu_index() < 0)
return FSP_DEVICE_ERROR;

if (processor_info_buffer == NULL)
return FSP_INVALID_PARAMETER;

Expand All @@ -71,9 +68,6 @@ static efi_return_status_t mp_startup_all_aps(const
efi_ap_procedure procedure, efi_boolean_t ignored3,
efi_uintn_t timeout_usec, void *argument)
{
if (cpu_index() < 0)
return FSP_DEVICE_ERROR;

if (procedure == NULL)
return FSP_INVALID_PARAMETER;

Expand All @@ -91,9 +85,6 @@ static efi_return_status_t mp_startup_this_ap(const
efi_ap_procedure procedure, efi_uintn_t processor_number,
efi_uintn_t timeout_usec, void *argument)
{
if (cpu_index() < 0)
return FSP_DEVICE_ERROR;

if (processor_number > get_cpu_count())
return FSP_NOT_FOUND;

Expand Down
2 changes: 2 additions & 0 deletions src/drivers/intel/gma/int15.c
View file
Expand Up @@ -16,6 +16,8 @@

#include <x86emu/x86emu.h>
#include <arch/interrupt.h>
#include <console/console.h>

#include "int15.h"

static int active_lfp, pfit, display, panel_type;
Expand Down
3 changes: 1 addition & 2 deletions src/drivers/intel/gma/intel_ddi.c
View file
Expand Up @@ -25,20 +25,19 @@
* Eugeni Dodonov <eugeni.dodonov@intel.com>
*
*/

#include <types.h>
#include <stdlib.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <delay.h>
#include <arch/acpi.h>
#include <arch/interrupt.h>
#include <boot/coreboot_tables.h>
#include <smbios.h>
#include <device/pci.h>
#include <ec/google/chromeec/ec.h>

#include <cpu/x86/tsc.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
Expand Down
1 change: 0 additions & 1 deletion src/drivers/intel/gma/vbt.c
View file
Expand Up @@ -16,7 +16,6 @@
*/

#include <device/pci_ops.h>
#include <delay.h>
#include <device/device.h>
#include <string.h>
#include <device/pci.h>
Expand Down
1 change: 0 additions & 1 deletion src/drivers/net/ne2k.c
View file
Expand Up @@ -29,7 +29,6 @@ SMC8416 PIO support added by Andrew Bettison (andrewb@zip.com.au) on 4/3/02

#include <arch/io.h>
#include <console/ne2k.h>
#include <delay.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
Expand Down
6 changes: 5 additions & 1 deletion src/drivers/pc80/rtc/mc146818rtc.c
View file
Expand Up @@ -3,6 +3,7 @@
*
* Copyright 2014 The Chromium OS Authors. All rights reserved.
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
* Copyright (C) 2018-2019 Eltan B.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
Expand Down Expand Up @@ -38,6 +39,9 @@
#define LB_CKS_LOC 0
#endif

/* Don't warn for checking >= LB_CKS_RANGE_START even though it may be 0. */
#pragma GCC diagnostic ignored "-Wtype-limits"

#include <smp/spinlock.h>

#if (defined(__PRE_RAM__) && \
Expand Down Expand Up @@ -144,7 +148,7 @@ static bool __cmos_init(bool invalid)
cmos_write(0, i);
}

if (cmos_invalid)
if (cmos_invalid || invalid)
cmos_reset_date();

printk(BIOS_WARNING, "RTC:%s%s%s%s\n",
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/siemens/nc_fpga/nc_fpga.c
View file
Expand Up @@ -19,9 +19,9 @@
#include <device/pci_ops.h>
#include <device/pci_def.h>
#include <device/mmio.h>
#include <delay.h>
#include <hwilib.h>
#include <bootstate.h>

#include "nc_fpga.h"

static void *nc_fpga_bar0;
Expand Down
1 change: 0 additions & 1 deletion src/drivers/sil/3114/sil_sata.c
View file
Expand Up @@ -14,7 +14,6 @@
* GNU General Public License for more details.
*/

#include <delay.h>
#include <stdlib.h>
#include <console/console.h>
#include <device/device.h>
Expand Down
6 changes: 3 additions & 3 deletions src/drivers/spi/spi_flash.c
View file
Expand Up @@ -10,15 +10,15 @@
#include <arch/early_variables.h>
#include <assert.h>
#include <boot_device.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <delay.h>
#include <stdlib.h>
#include <string.h>
#include <spi-generic.h>
#include <spi_flash.h>
#include <timer.h>

#include "spi_flash_internal.h"
#include <timer.h>

static void spi_flash_addr(u32 addr, u8 *cmd)
{
Expand Down Expand Up @@ -339,7 +339,7 @@ int spi_flash_generic_probe(const struct spi_slave *spi,
printk(BIOS_INFO, "Manufacturer: %02x\n", *idp);

/* search the table for matches in shift and id */
for (i = 0; i < ARRAY_SIZE(flashes); ++i)
for (i = 0; i < (int)ARRAY_SIZE(flashes); ++i)
if (flashes[i].shift == shift && flashes[i].idcode == *idp) {
/* we have a match, call probe */
if (flashes[i].probe(spi, idp, flash) == 0) {
Expand Down
42 changes: 42 additions & 0 deletions src/drivers/spi/spi_winbond.h
View file
@@ -0,0 +1,42 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2008, Network Appliance Inc.
* Author: Jason McMullan <mcmullan <at> netapp.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

/* Winbond specific function */
/* M25Pxx-specific commands */
#define CMD_W25_WREN 0x06 /* Write Enable */
#define CMD_W25_WRDI 0x04 /* Write Disable */
#define CMD_W25_RDSR 0x05 /* Read Status Register */
#define CMD_W25_WRSR 0x01 /* Write Status Register */
#define CMD_W25_RDSR2 0x35 /* Read Status2 Register */
#define CMD_W25_WRSR2 0x31 /* Write Status2 Register */
#define CMD_W25_READ 0x03 /* Read Data Bytes */
#define CMD_W25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */
#define CMD_W25_PP 0x02 /* Page Program */
#define CMD_W25_SE 0x20 /* Sector (4K) Erase */
#define CMD_W25_RDID 0x9f /* Read ID */
#define CMD_W25_BE 0xd8 /* Block (64K) Erase */
#define CMD_W25_CE 0xc7 /* Chip Erase */
#define CMD_W25_DP 0xb9 /* Deep Power-down */
#define CMD_W25_RES 0xab /* Release from DP and Read Signature */
#define CMD_VOLATILE_SREG_WREN 0x50 /* Write Enable for Volatile SREG */
#define CMD_W25_RD_SEC 0x48 /* Read security registers */

#define ADDR_W25_SEC1 0x10
#define ADDR_W25_SEC2 0x20
#define ADDR_W25_SEC3 0x30

/* tw: Maximum time to write a flash cell in milliseconds */
#define WINBOND_FLASH_TIMEOUT 30
3 changes: 1 addition & 2 deletions src/drivers/spi/sst.c
View file
Expand Up @@ -187,7 +187,7 @@ sst_byte_write(const struct spi_flash *flash, u32 offset, const void *buf)
static int sst_write_256(const struct spi_flash *flash, u32 offset, size_t len,
const void *buf)
{
size_t actual, chunk_len, cmd_len;
size_t actual, chunk_len;
unsigned long byte_addr;
unsigned long page_size;
int ret = 0;
Expand All @@ -208,7 +208,6 @@ static int sst_write_256(const struct spi_flash *flash, u32 offset, size_t len,
if (ret)
goto done;

cmd_len = 4;
cmd[0] = CMD_SST_AAI_WP;
cmd[1] = offset >> 16;
cmd[2] = offset >> 8;
Expand Down
40 changes: 12 additions & 28 deletions src/drivers/spi/winbond.c
View file
@@ -1,45 +1,29 @@
/*
* Copyright 2008, Network Appliance Inc.
* Author: Jason McMullan <mcmullan <at> netapp.com>
* Licensed under the GPL-2 or later.
* Jason McMullan <mcmullan@netapp.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include <console/console.h>
#include <stdlib.h>
#include <spi_flash.h>
#include <spi-generic.h>
#include <string.h>
#include <assert.h>
#include <delay.h>
#include <lib.h>

#include "spi_flash_internal.h"
#include "spi_winbond.h"

/* M25Pxx-specific commands */
#define CMD_W25_WREN 0x06 /* Write Enable */
#define CMD_W25_WRDI 0x04 /* Write Disable */
#define CMD_W25_RDSR 0x05 /* Read Status Register */
#define CMD_W25_WRSR 0x01 /* Write Status Register */
#define CMD_W25_RDSR2 0x35 /* Read Status2 Register */
#define CMD_W25_WRSR2 0x31 /* Write Status2 Register */
#define CMD_W25_READ 0x03 /* Read Data Bytes */
#define CMD_W25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */
#define CMD_W25_PP 0x02 /* Page Program */
#define CMD_W25_SE 0x20 /* Sector (4K) Erase */
#define CMD_W25_BE 0xd8 /* Block (64K) Erase */
#define CMD_W25_CE 0xc7 /* Chip Erase */
#define CMD_W25_DP 0xb9 /* Deep Power-down */
#define CMD_W25_RES 0xab /* Release from DP, and Read Signature */
#define CMD_W25_RD_SEC 0x48 /* Read security registers */
#define CMD_VOLATILE_SREG_WREN 0x50 /* Write Enable for Volatile SREG */

#define ADDR_W25_SEC1 0x10
#define ADDR_W25_SEC2 0x20
#define ADDR_W25_SEC3 0x30


/* tw: Maximum time to write a flash cell in milliseconds */
#define WINBOND_FLASH_TIMEOUT 30
struct winbond_spi_flash_params {
uint16_t id;
uint8_t l2_page_size_shift;
Expand Down
4 changes: 3 additions & 1 deletion src/drivers/xgi/common/vb_init.c
View file
Expand Up @@ -17,14 +17,16 @@
* GNU General Public License for more details.
*/

#include <delay.h>

#include "xgi_coreboot.h"
#include "vstruct.h"

#include "XGIfb.h"
#include "vb_def.h"
#include "vb_util.h"
#include "vb_setmode.h"
#include "vb_init.h"

static const unsigned short XGINew_DDRDRAM_TYPE340[4][2] = {
{ 16, 0x45},
{ 8, 0x35},
Expand Down
4 changes: 2 additions & 2 deletions src/drivers/xgi/common/vb_setmode.c
View file
Expand Up @@ -14,11 +14,11 @@
* GNU General Public License for more details.
*/

#include <delay.h>

#include "xgi_coreboot.h"
#include "vstruct.h"

#include "XGIfb.h"

#include "vb_def.h"
#include "vb_init.h"
#include "vb_util.h"
Expand Down
6 changes: 1 addition & 5 deletions src/drivers/xgi/common/xgi_coreboot.c
View file
Expand Up @@ -15,27 +15,23 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <delay.h>

#include <stdlib.h>
#include <vbe.h>

#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>

#include <pc80/vga.h>

#include "xgi_coreboot.h"
#include "vstruct.h"

#include "XGIfb.h"
#include "XGI_main.h"
#include "vb_init.h"
#include "vb_util.h"
#include "vb_setmode.h"

#include "XGI_main.c"

static int xgi_vbe_valid;
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/xgi/common/xgi_coreboot.h
View file
Expand Up @@ -19,12 +19,10 @@
#ifndef _XGI_COREBOOT_
#define _XGI_COREBOOT_

#include <delay.h>
#include <stdlib.h>
#include <stdint.h>
#include <arch/io.h>
#include <device/mmio.h>

#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
Expand Down
3 changes: 1 addition & 2 deletions src/drivers/xgi/z9s/z9s.c
View file
Expand Up @@ -12,9 +12,8 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <delay.h>
#include <stdlib.h>

#include <stdlib.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
Expand Down
2 changes: 1 addition & 1 deletion src/ec/google/chromeec/crosec_proto.c
View file
Expand Up @@ -14,9 +14,9 @@
*/

#include <console/console.h>
#include <delay.h>
#include <stdint.h>
#include <string.h>

#include "ec.h"
#include "ec_commands.h"
#include "ec_message.h"
Expand Down
1 change: 0 additions & 1 deletion src/ec/google/chromeec/ec_i2c.c
View file
Expand Up @@ -14,7 +14,6 @@
*/

#include <console/console.h>
#include <delay.h>
#include <device/i2c_simple.h>
#include <stdint.h>
#include <string.h>
Expand Down
6 changes: 3 additions & 3 deletions src/ec/google/wilco/Makefile.inc
View file
@@ -1,8 +1,8 @@
ifeq ($(CONFIG_EC_GOOGLE_WILCO),y)

bootblock-y += bootblock.c
romstage-y += commands.c mailbox.c romstage.c
ramstage-y += chip.c commands.c mailbox.c
smm-y += commands.c mailbox.c smihandler.c
romstage-y += commands.c mailbox.c romstage.c boardid.c
ramstage-y += chip.c commands.c mailbox.c boardid.c
smm-y += commands.c mailbox.c smihandler.c boardid.c

endif
32 changes: 32 additions & 0 deletions src/ec/google/wilco/boardid.c
View file
@@ -0,0 +1,32 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2019 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include <boardid.h>
#include "commands.h"

uint32_t board_id(void)
{
MAYBE_STATIC uint32_t id = BOARD_ID_INIT;

if (id == BOARD_ID_INIT) {
uint8_t ec_id;
if (wilco_ec_get_board_id(&ec_id) <= 0)
id = BOARD_ID_UNKNOWN;
else
id = ec_id;
}

return id;
}
7 changes: 7 additions & 0 deletions src/ec/google/wilco/chip.c
View file
Expand Up @@ -46,6 +46,13 @@ static void wilco_ec_post_video_init(void *unused)
BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT,
wilco_ec_post_video_init, NULL);

static void wilco_ec_post_logo_displayed(void *unused)
{
wilco_ec_send(KB_BIOS_PROGRESS, BIOS_PROGRESS_LOGO_DISPLAYED);
}
BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT,
wilco_ec_post_logo_displayed, NULL);

static void wilco_ec_resume(void *unused)
{
wilco_ec_send_noargs(KB_RESTORE);
Expand Down
6 changes: 6 additions & 0 deletions src/ec/google/wilco/commands.c
View file
Expand Up @@ -135,6 +135,12 @@ int wilco_ec_get_lid_state(void)
return !!(pm.state[0] & EC_PM1_LID_OPEN);
}

int wilco_ec_get_board_id(uint8_t *id)
{
return wilco_ec_mailbox(WILCO_EC_MSG_RAW, KB_BOARD_ID,
NULL, 0, id, sizeof(*id));
}

void wilco_ec_slp_en(void)
{
/* EC does not respond to this command */
Expand Down
13 changes: 13 additions & 0 deletions src/ec/google/wilco/commands.h
View file
Expand Up @@ -38,6 +38,8 @@ enum {
KB_EC_INFO = 0x38,
/* Set ACPI mode on or off */
KB_ACPI = 0x3a,
/* Board ID */
KB_BOARD_ID = 0x3d,
/* Change ACPI wake up source */
KB_ACPI_WAKEUP_CHANGE = 0x4a,
/* Manage the EC power button passthru to the host */
Expand Down Expand Up @@ -267,6 +269,17 @@ int wilco_ec_get_pm(struct ec_pm_event_state *pm, bool clear);
*/
int wilco_ec_get_lid_state(void);

/**
* wilco_ec_get_board_id
*
* Retrieve the board ID value from the EC.
* @id: Pointer to variable to store the ID read from the EC.
*
* Returns number of bytes transferred from the EC
* Returns -1 if the EC command failed
*/
int wilco_ec_get_board_id(uint8_t *id);

enum ec_wake_change {
WAKE_OFF = 0,
WAKE_ON
Expand Down
8 changes: 8 additions & 0 deletions src/ec/lenovo/h8/Kconfig
View file
Expand Up @@ -32,6 +32,14 @@ config H8_HAS_BAT_TRESHOLDS_IMPL
bool
default n

config H8_FN_KEY_AS_VBOOT_RECOVERY_SW
bool "Enable Fn-Key as VBOOT recovery switch"
depends on VBOOT
default n
help
If VBOOT is enabled, press Fn-Key at power on to force a recovery mode
boot instead of regular FW_MAIN_x boot.

endif

config H8_DOCK_EARLY_INIT
Expand Down
13 changes: 13 additions & 0 deletions src/ec/lenovo/h8/Makefile.inc
View file
@@ -1,5 +1,18 @@
ifeq ($(CONFIG_EC_LENOVO_H8),y)

ramstage-y += sense.c
verstage-y += sense.c
romstage-y += sense.c
bootblock-y += sense.c
postcar-y += sense.c
smm-y += sense.c

ramstage-$(CONFIG_VBOOT) += vboot.c
verstage-$(CONFIG_VBOOT) += vboot.c
romstage-$(CONFIG_VBOOT) += vboot.c
bootblock-$(CONFIG_VBOOT) += vboot.c
postcar-$(CONFIG_VBOOT) += vboot.c

ifneq ($(filter y,$(CONFIG_H8_BEEP_ON_DEATH) $(CONFIG_H8_FLASH_LEDS_ON_DEATH)),)
romstage-y += panic.c
ramstage-y += panic.c
Expand Down
5 changes: 5 additions & 0 deletions src/ec/lenovo/h8/h8.h
View file
Expand Up @@ -38,6 +38,9 @@ void h8_usb_always_on(void);

void h8_mainboard_init_dock (void);

int h8_get_fn_key(void);
int h8_get_sense_ready(void);

void h8_bluetooth_enable(int on);
bool h8_bluetooth_nv_enable(void);
bool h8_has_bdc(struct device *dev);
Expand Down Expand Up @@ -135,8 +138,10 @@ void h8_ssdt_generator(struct device *dev);
#define H8_EVENT_FN_PRESS 0x39

#define H8_STATUS0 0x46
#define H8_STATUS0_FN_KEY_DOWN 0x01
#define H8_STATUS1 0x47
#define H8_STATUS2 0x48
#define H8_STATUS3 0x49

#define H8_EVENT_BAT0 0x4a
#define H8_EVENT_BAT0_STATE 0x4b
Expand Down