| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,2 +1,8 @@ | ||
| config DRIVERS_GENESYSLOGIC_GL9763E | ||
| bool "Genesys Logic GL9763E" | ||
| default n | ||
|
|
||
| config DRIVERS_GENESYSLOGIC_GL9763E_L1_MAX | ||
| bool "Set L1 entry delay to MAX" | ||
| depends on DRIVERS_GENESYSLOGIC_GL9763E | ||
| default n |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,3 @@ | ||
| config DRIVERS_I2C_CS35L53 | ||
| bool | ||
| depends on HAVE_ACPI_TABLES |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1 @@ | ||
| ramstage-$(CONFIG_DRIVERS_I2C_CS35L53) += cs35l53.c |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,149 @@ | ||
| /* SPDX-License-Identifier: GPL-2.0-only */ | ||
|
|
||
| #include <acpi/acpi_device.h> | ||
|
|
||
| #define CS35L53_MAX_GPIOS 2 | ||
|
|
||
| enum cs35l53_boost_type { | ||
| INTERNAL_BOOST = 0, | ||
| EXTERNAL_BOOST = 1, | ||
| }; | ||
|
|
||
| enum cs35l53_boost_ind_nanohenrys { | ||
| BOOST_IND_1000_NH = 1000, | ||
| BOOST_IND_1200_NH = 1200, | ||
| BOOST_IND_1500_NH = 1500, | ||
| BOOST_IND_2200_NH = 2200, | ||
| }; | ||
|
|
||
| enum cs35l53_asp_sdout_hiz { | ||
| ASP_SDOUT_LOGIC0_UNUSED_LOGIC0_DISABLED = 0, | ||
| ASP_SDOUT_HIZ_UNUSED_LOGIC0_DISABLED = 1, | ||
| ASP_SDOUT_LOGIC0_UNUSED_HIZ_DISABLED = 2, | ||
| ASP_SDOUT_HIZ_UNUSED_HIZ_DISABLED = 3, | ||
| }; | ||
|
|
||
| enum cs35l53_gpio1_src { | ||
| GPIO1_SRC_HIGH_IMPEDANCE = 0, | ||
| GPIO1_SRC_GPIO = 1, | ||
| GPIO1_SRC_SYNC = 2, | ||
| GPIO1_SRC_MCLK_INPUT = 3, | ||
| }; | ||
|
|
||
| enum cs35l53_gpio2_src { | ||
| GPIO2_SRC_HIGH_IMPEDANCE = 0, | ||
| GPIO2_SRC_GPIO = 1, | ||
| GPIO2_SRC_OPEN_DRAIN = 2, | ||
| GPIO2_SRC_MCLK_INPUT = 3, | ||
| GPIO2_SRC_PUSH_PULL_INTB = 4, | ||
| GPIO2_SRC_PUSH_PULL_INT = 5, | ||
| }; | ||
|
|
||
| /* | ||
| * Cirrus Logic CS35L53 Audio Codec devicetree bindings | ||
| * linux/Documentation/devicetree/bindings/sound/cirrus,cs35l53.yaml | ||
| */ | ||
| struct drivers_i2c_cs35l53_config { | ||
| const char *name; /* ACPI Device Name */ | ||
|
|
||
| const char *sub; /* SUB ID to uniquely identify system */ | ||
|
|
||
| /* Interrupt configuration */ | ||
| struct acpi_irq irq; | ||
|
|
||
| /* Use GPIO based interrupt instead of PIRQ */ | ||
| struct acpi_gpio irq_gpio; | ||
|
|
||
| /* Use GPIO based reset gpio */ | ||
| struct acpi_gpio reset_gpio; | ||
|
|
||
| /* I2C Bus Frequency in Hertz (default 400kHz) */ | ||
| unsigned int bus_speed; | ||
|
|
||
| /* Define cs35l53 parameters */ | ||
| /* | ||
| * cirrus,boost-type : Configures the type of Boost being used. | ||
| * Internal boost requires boost-peak-milliamp, boost-ind-nanohenry and | ||
| * boost-cap-microfarad. | ||
| * External Boost must have GPIO1 as GPIO output. GPIO1 will be set high to | ||
| * enable boost voltage. | ||
| */ | ||
| enum cs35l53_boost_type boost_type; | ||
|
|
||
| /* | ||
| * cirrus,boost-peak-milliamp : Boost-converter peak current limit in mA. | ||
| * Configures the peak current by monitoring the current through the boost FET. | ||
| * Range starts at 1600 mA and goes to a maximum of 4500 mA with increments | ||
| * of 50 mA. See section 4.3.6 of the datasheet for details. | ||
| */ | ||
| unsigned int boost_peak_milliamp; | ||
|
|
||
| /* | ||
| * cirrus,boost-ind-nanohenry : Boost inductor value, expressed in nH. Valid | ||
| * values include 1000, 1200, 1500 and 2200. | ||
| */ | ||
| enum cs35l53_boost_ind_nanohenrys boost_ind_nanohenry; | ||
|
|
||
| /* | ||
| * cirrus,boost-cap-microfarad : Total equivalent boost capacitance on the VBST | ||
| * and VAMP pins, derated at 11 volts DC. The value must be rounded to the | ||
| * nearest integer and expressed in uF. | ||
| */ | ||
| unsigned int boost_cap_microfarad; | ||
|
|
||
| /* | ||
| * cirrus,asp-sdout-hiz : Audio serial port SDOUT Hi-Z control. Sets the Hi-Z | ||
| * configuration for SDOUT pin of amplifier. | ||
| * 0 = Logic 0 during unused slots, and while all transmit channels disabled | ||
| * 1 = Hi-Z during unused slots but logic 0 while all transmit channels disabled | ||
| * 2 = Logic 0 during unused slots, but Hi-Z while all transmit channels disabled | ||
| * 3 = Hi-Z during unused slots and while all transmit channels disabled | ||
| */ | ||
| enum cs35l53_asp_sdout_hiz asp_sdout_hiz; | ||
|
|
||
| /* | ||
| * cirrus,gpio1-polarity-invert : Boolean which specifies whether the GPIO1 | ||
| * level is inverted. | ||
| */ | ||
| bool gpio1_polarity_invert; | ||
|
|
||
| /* | ||
| * cirrus,gpio2-polarity-invert : Boolean which specifies whether the GPIO2 | ||
| * level is inverted. | ||
| */ | ||
| bool gpio2_polarity_invert; | ||
|
|
||
| /* | ||
| * cirrus,gpio1-output-enable : Boolean which specifies whether the GPIO1 pin | ||
| * is configured as an output. | ||
| */ | ||
| bool gpio1_output_enable; | ||
|
|
||
| /* | ||
| * cirrus,gpio2-output-enable : Boolean which specifies whether the GPIO2 pin | ||
| * is configured as an output. | ||
| */ | ||
| bool gpio2_output_enable; | ||
|
|
||
| /* | ||
| * cirrus,gpio1-src-select : Configures the function of the GPIO1 pin. | ||
| * GPIO1: | ||
| * 0 = High Impedance (Default) | ||
| * 1 = GPIO | ||
| * 2 = Sync | ||
| * 3 = MCLK input | ||
| */ | ||
| enum cs35l53_gpio1_src gpio1_src_select; | ||
|
|
||
| /* | ||
| * cirrus,gpio2-src-select : Configures the function of the GPIO2 pin. | ||
| * GPIO2: | ||
| * 0 = High Impedance (Default) | ||
| * 1 = GPIO | ||
| * 2 = Open Drain INTB | ||
| * 3 = MCLK input | ||
| * 4 = Push-pull INTB (active low) | ||
| * 5 = Push-pull INT (active high) | ||
| */ | ||
| enum cs35l53_gpio2_src gpio2_src_select; | ||
| }; |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,147 @@ | ||
| /* SPDX-License-Identifier: GPL-2.0-only */ | ||
|
|
||
| #include <acpi/acpi.h> | ||
| #include <acpi/acpi_device.h> | ||
| #include <acpi/acpigen.h> | ||
| #include <console/console.h> | ||
| #include <device/i2c_simple.h> | ||
| #include <device/device.h> | ||
| #include <device/path.h> | ||
|
|
||
| #include "chip.h" | ||
|
|
||
| #define CS35L53_ACPI_HID "CSC3541" | ||
|
|
||
| static void cs35l53_fill_ssdt(const struct device *dev) | ||
| { | ||
| struct drivers_i2c_cs35l53_config *config = dev->chip_info; | ||
| const char *scope = acpi_device_scope(dev); | ||
| const char *path = acpi_device_path(dev); | ||
| struct acpi_i2c i2c = { | ||
| .address = dev->path.i2c.device, | ||
| .mode_10bit = dev->path.i2c.mode_10bit, | ||
| .speed = config->bus_speed ? : I2C_SPEED_FAST, | ||
| .resource = scope, | ||
| }; | ||
| struct acpi_dp *dsd; | ||
| int gpio_index = 0; | ||
|
|
||
| if (!scope) | ||
| return; | ||
|
|
||
| /* Device */ | ||
| acpigen_write_scope(scope); | ||
| acpigen_write_device(acpi_device_name(dev)); | ||
| acpigen_write_name_string("_HID", CS35L53_ACPI_HID); | ||
| acpigen_write_name_integer("_UID", 0); | ||
| acpigen_write_name_string("_DDN", dev->chip_ops->name); | ||
| acpigen_write_name_string("_SUB", config->sub); | ||
| acpigen_write_STA(acpi_device_status(dev)); | ||
|
|
||
| /* Resources */ | ||
| acpigen_write_name("_CRS"); | ||
| acpigen_write_resourcetemplate_header(); | ||
| acpi_device_write_i2c(&i2c); | ||
| /* Use either Interrupt() or GpioInt() */ | ||
| if (config->irq_gpio.pin_count) | ||
| acpi_device_write_gpio(&config->irq_gpio); | ||
| else | ||
| acpi_device_write_interrupt(&config->irq); | ||
|
|
||
| /* for cs35l53 reset gpio */ | ||
| if (config->reset_gpio.pin_count) | ||
| acpi_device_write_gpio(&config->reset_gpio); | ||
|
|
||
| acpigen_write_resourcetemplate_footer(); | ||
|
|
||
| /* Add Child Device Properties */ | ||
| dsd = acpi_dp_new_table("_DSD"); | ||
| if (config->irq_gpio.pin_count) | ||
| acpi_dp_add_gpio(dsd, "irq-gpios", path, | ||
| gpio_index++, /* Index = 0 */ | ||
| 0, /* Pin = 0 (There is a single pin in the GPIO resource). */ | ||
| config->irq_gpio.active_low); | ||
| if (config->reset_gpio.pin_count) | ||
| acpi_dp_add_gpio(dsd, "reset-gpios", path, | ||
| gpio_index++, /* Index = 0 or 1 (if irq gpio is written). */ | ||
| 0, /* Pin = 0 (There is a single pin in the GPIO resource). */ | ||
| config->reset_gpio.active_low); | ||
|
|
||
| acpi_dp_add_integer(dsd, "cirrus,boost-type", config->boost_type); | ||
|
|
||
| switch (config->boost_type) { | ||
| case INTERNAL_BOOST: | ||
| if ((config->boost_peak_milliamp > 4500) || | ||
| (config->boost_peak_milliamp < 1600) || | ||
| (config->boost_peak_milliamp % 50)) { | ||
| printk(BIOS_ERR, | ||
| "%s: Incorrect boost_peak_milliamp(%d). Using default of 4500 mA\n", | ||
| __func__, config->boost_peak_milliamp); | ||
| config->boost_peak_milliamp = 4500; | ||
| } | ||
| acpi_dp_add_integer(dsd, "cirrus,boost-peak-milliamp", | ||
| config->boost_peak_milliamp); | ||
| acpi_dp_add_integer(dsd, "cirrus,boost-ind-nanohenry", | ||
| config->boost_ind_nanohenry); | ||
| acpi_dp_add_integer(dsd, "cirrus,boost-cap-microfarad", | ||
| config->boost_cap_microfarad); | ||
| break; | ||
| case EXTERNAL_BOOST: | ||
| config->gpio1_output_enable = true; | ||
| config->gpio1_src_select = GPIO1_SRC_GPIO; | ||
| break; | ||
| default: | ||
| break; | ||
| } | ||
|
|
||
| acpi_dp_add_integer(dsd, "cirrus,asp-sdout-hiz", config->asp_sdout_hiz); | ||
| acpi_dp_add_integer(dsd, "cirrus,gpio1-polarity-invert", | ||
| config->gpio1_polarity_invert); | ||
| acpi_dp_add_integer(dsd, "cirrus,gpio1-output-enable", | ||
| config->gpio1_output_enable); | ||
| acpi_dp_add_integer(dsd, "cirrus,gpio1-src-select", config->gpio1_src_select); | ||
| acpi_dp_add_integer(dsd, "cirrus,gpio2-polarity-invert", | ||
| config->gpio2_polarity_invert); | ||
| acpi_dp_add_integer(dsd, "cirrus,gpio2-output-enable", | ||
| config->gpio2_output_enable); | ||
| acpi_dp_add_integer(dsd, "cirrus,gpio2-src-select", config->gpio2_src_select); | ||
|
|
||
| /* Write Device Property Hierarchy */ | ||
| acpi_dp_write(dsd); | ||
|
|
||
| acpigen_pop_len(); /* Device */ | ||
| acpigen_pop_len(); /* Scope */ | ||
|
|
||
| printk(BIOS_INFO, "%s: %s address 0%xh irq %d\n", | ||
| acpi_device_path(dev), dev->chip_ops->name, | ||
| dev->path.i2c.device, config->irq.pin); | ||
| } | ||
|
|
||
| static const char *cs35l53_acpi_name(const struct device *dev) | ||
| { | ||
| struct drivers_i2c_cs35l53_config *config = dev->chip_info; | ||
| static char name[ACPI_NAME_BUFFER_SIZE]; | ||
|
|
||
| if (config->name) | ||
| return config->name; | ||
|
|
||
| snprintf(name, sizeof(name), "D%03.3X", dev->path.i2c.device); | ||
| return name; | ||
| } | ||
|
|
||
| static struct device_operations cs35l53_ops = { | ||
| .read_resources = noop_read_resources, | ||
| .set_resources = noop_set_resources, | ||
| .acpi_name = cs35l53_acpi_name, | ||
| .acpi_fill_ssdt = cs35l53_fill_ssdt, | ||
| }; | ||
|
|
||
| static void cs35l53_enable(struct device *dev) | ||
| { | ||
| dev->ops = &cs35l53_ops; | ||
| } | ||
|
|
||
| struct chip_operations drivers_i2c_cs35l53_ops = { | ||
| CHIP_NAME("Cirrus Logic CS35L53 Audio Codec") | ||
| .enable_dev = cs35l53_enable | ||
| }; |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,216 @@ | ||
| /* SPDX-License-Identifier: BSD-3-Clause */ | ||
|
|
||
| #include <drivers/spi/tpm/tpm.h> | ||
| #include <security/tpm/tis.h> | ||
| #include <string.h> | ||
| #include <types.h> | ||
|
|
||
| #define CR50_BOARD_CFG_LOCKBIT_MASK 0x80000000U | ||
| #define CR50_BOARD_CFG_FEATUREBITS_MASK 0x3FFFFFFFU | ||
|
|
||
| #define CR50_BOARD_CFG_100US_READY_PULSE 0x00000001U | ||
| #define CR50_BOARD_CFG_VALUE \ | ||
| (CONFIG(CR50_USE_LONG_INTERRUPT_PULSES) \ | ||
| ? CR50_BOARD_CFG_100US_READY_PULSE : 0) | ||
|
|
||
| enum cr50_register { | ||
| CR50_FW_VER_REG, | ||
| CR50_BOARD_CFG_REG, | ||
| }; | ||
|
|
||
| #define CR50_FW_VER_REG_SPI (TPM_LOCALITY_0_SPI_BASE + 0xf90) | ||
| #define CR50_BOARD_CFG_REG_SPI (TPM_LOCALITY_0_SPI_BASE + 0xfe0) | ||
|
|
||
| #define CR50_FW_VER_REG_I2C 0x0f | ||
| #define CR50_BOARD_CFG_REG_I2C 0x1c | ||
|
|
||
| /* Return register address, which depends on the bus type, or -1 for error. */ | ||
| static int get_reg_addr(enum cr50_register reg) | ||
| { | ||
| if (CONFIG(SPI_TPM)) { | ||
| switch (reg) { | ||
| case CR50_FW_VER_REG: | ||
| return CR50_FW_VER_REG_SPI; | ||
| case CR50_BOARD_CFG_REG: | ||
| return CR50_BOARD_CFG_REG_SPI; | ||
| default: | ||
| return -1; | ||
| } | ||
| } | ||
|
|
||
| if (CONFIG(I2C_TPM)) { | ||
| switch (reg) { | ||
| case CR50_FW_VER_REG: | ||
| return CR50_FW_VER_REG_I2C; | ||
| case CR50_BOARD_CFG_REG: | ||
| return CR50_BOARD_CFG_REG_I2C; | ||
| default: | ||
| return -1; | ||
| } | ||
| } | ||
|
|
||
| return -1; | ||
| } | ||
|
|
||
| static bool cr50_fw_supports_board_cfg(struct cr50_firmware_version *version) | ||
| { | ||
| /* Cr50 supports the CR50_BOARD_CFG register from version 0.5.5 / 0.6.5 | ||
| * and onwards. */ | ||
| if (version->epoch > 0 || version->major >= 7 | ||
| || (version->major >= 5 && version->minor >= 5)) | ||
| return true; | ||
|
|
||
| printk(BIOS_INFO, "Cr50 firmware does not support CR50_BOARD_CFG, version: %d.%d.%d\n", | ||
| version->epoch, version->major, version->minor); | ||
|
|
||
| return false; | ||
| } | ||
|
|
||
| /* | ||
| * Expose method to read the CR50_BOARD_CFG register, will return zero if | ||
| * register not supported by Cr50 firmware. | ||
| */ | ||
| static uint32_t cr50_get_board_cfg(void) | ||
| { | ||
| struct cr50_firmware_version ver; | ||
| uint32_t value; | ||
|
|
||
| if (cr50_get_firmware_version(&ver) != CB_SUCCESS) | ||
| return 0; | ||
|
|
||
| if (!cr50_fw_supports_board_cfg(&ver)) | ||
| return 0; | ||
|
|
||
| const enum cb_err ret = tis_vendor_read(get_reg_addr(CR50_BOARD_CFG_REG), &value, | ||
| sizeof(value)); | ||
| if (ret != CB_SUCCESS) { | ||
| printk(BIOS_INFO, "Error reading from cr50\n"); | ||
| return 0; | ||
| } | ||
|
|
||
| return value & CR50_BOARD_CFG_FEATUREBITS_MASK; | ||
| } | ||
|
|
||
| /** | ||
| * Set the BOARD_CFG register on the TPM chip to a particular compile-time constant value. | ||
| */ | ||
| enum cb_err cr50_set_board_cfg(void) | ||
| { | ||
| struct cr50_firmware_version ver; | ||
| enum cb_err ret; | ||
| uint32_t value; | ||
|
|
||
| if (cr50_get_firmware_version(&ver) != CB_SUCCESS) | ||
| return CB_ERR; | ||
|
|
||
| if (!cr50_fw_supports_board_cfg(&ver)) | ||
| return CB_ERR; | ||
|
|
||
| /* Set the CR50_BOARD_CFG register, for e.g. asking cr50 to use longer ready pulses. */ | ||
| ret = tis_vendor_read(get_reg_addr(CR50_BOARD_CFG_REG), &value, sizeof(value)); | ||
| if (ret != CB_SUCCESS) { | ||
| printk(BIOS_INFO, "Error reading from cr50\n"); | ||
| return CB_ERR; | ||
| } | ||
|
|
||
| if ((value & CR50_BOARD_CFG_FEATUREBITS_MASK) == CR50_BOARD_CFG_VALUE) { | ||
| printk(BIOS_INFO, "Current CR50_BOARD_CFG = 0x%08x, matches desired = 0x%08x\n", | ||
| value, CR50_BOARD_CFG_VALUE); | ||
| return CB_SUCCESS; | ||
| } | ||
|
|
||
| if (value & CR50_BOARD_CFG_LOCKBIT_MASK) { | ||
| /* The high bit is set, meaning that the Cr50 is already locked on a particular | ||
| * value for the register, but not the one we wanted. */ | ||
| printk(BIOS_ERR, "Current CR50_BOARD_CFG = 0x%08x, does not match" | ||
| "desired = 0x%08x\n", value, CR50_BOARD_CFG_VALUE); | ||
| return CB_ERR; | ||
| } | ||
|
|
||
| printk(BIOS_INFO, "Current CR50_BOARD_CFG = 0x%08x, setting to 0x%08x\n", | ||
| value, CR50_BOARD_CFG_VALUE); | ||
| value = CR50_BOARD_CFG_VALUE; | ||
|
|
||
| ret = tis_vendor_write(get_reg_addr(CR50_BOARD_CFG_REG), &value, sizeof(value)); | ||
| if (ret != CB_SUCCESS) { | ||
| printk(BIOS_ERR, "Error writing to cr50\n"); | ||
| return ret; | ||
| } | ||
|
|
||
| return CB_SUCCESS; | ||
| } | ||
|
|
||
| bool cr50_is_long_interrupt_pulse_enabled(void) | ||
| { | ||
| return !!(cr50_get_board_cfg() & CR50_BOARD_CFG_100US_READY_PULSE); | ||
| } | ||
|
|
||
| static enum cb_err cr50_parse_fw_version(const char *version_str, | ||
| struct cr50_firmware_version *ver) | ||
| { | ||
| int epoch, major, minor; | ||
|
|
||
| char *number = strstr(version_str, " RW_A:"); | ||
| if (!number) | ||
| number = strstr(version_str, " RW_B:"); | ||
| if (!number) | ||
| return CB_ERR_ARG; | ||
| number += 6; /* Skip past the colon. */ | ||
|
|
||
| epoch = skip_atoi(&number); | ||
| if (*number++ != '.') | ||
| return CB_ERR_ARG; | ||
| major = skip_atoi(&number); | ||
| if (*number++ != '.') | ||
| return CB_ERR_ARG; | ||
| minor = skip_atoi(&number); | ||
|
|
||
| ver->epoch = epoch; | ||
| ver->major = major; | ||
| ver->minor = minor; | ||
| return CB_SUCCESS; | ||
| } | ||
|
|
||
| enum cb_err cr50_get_firmware_version(struct cr50_firmware_version *version) | ||
| { | ||
| static struct cr50_firmware_version cr50_firmware_version; | ||
|
|
||
| if (cr50_firmware_version.epoch || cr50_firmware_version.major || | ||
| cr50_firmware_version.minor) | ||
| goto success; | ||
|
|
||
| int chunk_count = 0; | ||
| size_t chunk_size = 50; | ||
| char version_str[301]; | ||
| int addr = get_reg_addr(CR50_FW_VER_REG); | ||
|
|
||
| /* | ||
| * Does not really matter what's written, this just makes sure | ||
| * the version is reported from the beginning. | ||
| */ | ||
| tis_vendor_write(addr, &chunk_size, 1); | ||
|
|
||
| /* | ||
| * Read chunk_size bytes at a time, last chunk will be zero padded. | ||
| */ | ||
| do { | ||
| uint8_t *buf = (uint8_t *)version_str + chunk_count * chunk_size; | ||
| tis_vendor_read(addr, buf, chunk_size); | ||
| if (!version_str[++chunk_count * chunk_size - 1]) | ||
| /* Zero padding detected: end of string. */ | ||
| break; | ||
| /* Check if there is enough room for reading one more chunk. */ | ||
| } while (chunk_count * chunk_size < sizeof(version_str) - chunk_size); | ||
|
|
||
| version_str[chunk_count * chunk_size] = '\0'; | ||
| printk(BIOS_INFO, "Firmware version: %s\n", version_str); | ||
|
|
||
| if (cr50_parse_fw_version(version_str, &cr50_firmware_version) != CB_SUCCESS) { | ||
| printk(BIOS_ERR, "Did not recognize Cr50 version format\n"); | ||
| return CB_ERR; | ||
| } | ||
|
|
||
| success: | ||
| *version = cr50_firmware_version; | ||
| return CB_SUCCESS; | ||
| } |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,24 @@ | ||
| /* SPDX-License-Identifier: BSD-3-Clause */ | ||
|
|
||
| #ifndef __DRIVERS_TPM_CR50_H__ | ||
| #define __DRIVERS_TPM_CR50_H__ | ||
|
|
||
| #include <types.h> | ||
|
|
||
| /* Structure describing the elements of Cr50 firmware version. */ | ||
| struct cr50_firmware_version { | ||
| int epoch; | ||
| int major; | ||
| int minor; | ||
| }; | ||
|
|
||
| /* Indicates whether Cr50 ready pulses are guaranteed to be at least 100us. */ | ||
| bool cr50_is_long_interrupt_pulse_enabled(void); | ||
|
|
||
| /* Get the Cr50 firmware version information. */ | ||
| enum cb_err cr50_get_firmware_version(struct cr50_firmware_version *version); | ||
|
|
||
| /* Set the BOARD_CFG register depending on Cr50 Kconfigs */ | ||
| enum cb_err cr50_set_board_cfg(void); | ||
|
|
||
| #endif /* __DRIVERS_TPM_CR50_H__ */ |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,10 @@ | ||
| /* SPDX-License-Identifier: GPL-2.0-only */ | ||
|
|
||
| #include <device/device.h> | ||
|
|
||
| #ifndef _WIFI_GENERIC_WIFI_H_ | ||
| #define _WIFI_GENERIC_WIFI_H_ | ||
|
|
||
| bool wifi_generic_cnvi_ddr_rfim_enabled(const struct device *dev); | ||
|
|
||
| #endif /* _WIFI_GENERIC_WIFI_H_ */ |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,26 +1,137 @@ | ||
| /* SPDX-License-Identifier: GPL-2.0-only */ | ||
|
|
||
| Method (RPTS, 1, Serialized) | ||
| { | ||
|
|
||
| /* Store current EC settings in CMOS */ | ||
| Switch (ToInteger (\_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.TPLE)))) | ||
| { | ||
| // 0x00 == Enabled == 0x00 | ||
| // 0x11 == Re-enabled == 0x00 | ||
| // 0x22 == Disabled == 0x01 | ||
| Case (0x00) | ||
| { | ||
| \_SB.PCI0.LPCB.TPLC = 0x00 | ||
| } | ||
| Case (0x11) | ||
| { | ||
| \_SB.PCI0.LPCB.TPLC = 0x00 | ||
| } | ||
| Case (0x22) | ||
| { | ||
| \_SB.PCI0.LPCB.TPLC = 0x01 | ||
| } | ||
| } | ||
|
|
||
| \_SB.PCI0.LPCB.FLKC = | ||
| \_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.FLKE)) | ||
|
|
||
| Switch (ToInteger (\_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.KLSE)))) | ||
| { | ||
| // 0x00 == Disabled == 0x00 | ||
| // 0xdd == Enabled == 0x01 | ||
| Case (0x00) | ||
| { | ||
| \_SB.PCI0.LPCB.KLSC = 0x00 | ||
| } | ||
| Case (0xdd) | ||
| { | ||
| \_SB.PCI0.LPCB.KLSC = 0x01 | ||
| } | ||
| } | ||
|
|
||
| Switch (ToInteger (\_SB.PCI0.LPCB.EC.ECRD (RefOf (\_SB.PCI0.LPCB.EC.KLBE)))) | ||
| { | ||
| // 0xdd == On == 0x00 | ||
| // 0xcc == Off == 0x01 | ||
| // 0xbb == Low == 0x02 | ||
| // 0xaa == High == 0x03 | ||
| Case (0xdd) | ||
| { | ||
| \_SB.PCI0.LPCB.KLBC = 0x00 | ||
| } | ||
| Case (0xcc) | ||
| { | ||
| \_SB.PCI0.LPCB.KLBC = 0x01 | ||
| } | ||
| Case (0xbb) | ||
| { | ||
| \_SB.PCI0.LPCB.KLBC = 0x02 | ||
| } | ||
| Case (0xaa) | ||
| { | ||
| \_SB.PCI0.LPCB.KLBC = 0x03 | ||
| } | ||
| } | ||
|
|
||
| /* | ||
| * Disable ACPI support. | ||
| * This should always be the last action before entering S4 or S5. | ||
| */ | ||
| \_SB.PCI0.LPCB.EC.OSFG = 0x00 | ||
| } | ||
|
|
||
| Method (RWAK, 1, Serialized) | ||
| { | ||
| /* | ||
| * Enable ACPI support. | ||
| * This should always be the first action when exiting S4 or S5. | ||
| */ | ||
| \_SB.PCI0.LPCB.EC.OSFG = 0x01 | ||
|
|
||
| /* Restore EC settings from CMOS */ | ||
| Switch (ToInteger (\_SB.PCI0.LPCB.TPLC)) | ||
| { | ||
| // 0x00 == Enabled == 0x00 | ||
| // 0x00 == Re-enabled == 0x11 | ||
| // 0x01 == Disabled == 0x22 | ||
| Case (0x00) | ||
| { | ||
| \_SB.PCI0.LPCB.EC.ECWR (0x00, RefOf(\_SB.PCI0.LPCB.EC.TPLE)) | ||
| } | ||
| Case (0x01) | ||
| { | ||
| \_SB.PCI0.LPCB.EC.ECWR (0x22, RefOf(\_SB.PCI0.LPCB.EC.TPLE)) | ||
| } | ||
| } | ||
|
|
||
| \_SB.PCI0.LPCB.EC.ECWR (\_SB.PCI0.LPCB.FLKC, RefOf(\_SB.PCI0.LPCB.EC.FLKE)) | ||
|
|
||
| Switch (ToInteger (\_SB.PCI0.LPCB.KLSC)) | ||
| { | ||
| // 0x00 == Disabled == 0x00 | ||
| // 0x01 == Enabled == 0xdd | ||
| Case (0x00) | ||
| { | ||
| \_SB.PCI0.LPCB.EC.ECWR (0x00, RefOf(\_SB.PCI0.LPCB.EC.KLSE)) | ||
| } | ||
| Case (0x01) | ||
| { | ||
| \_SB.PCI0.LPCB.EC.ECWR (0xdd, RefOf(\_SB.PCI0.LPCB.EC.KLSE)) | ||
| } | ||
| } | ||
|
|
||
| Switch (ToInteger (\_SB.PCI0.LPCB.KLBC)) | ||
| { | ||
| // 0x00 == On == 0xdd | ||
| // 0x01 == Off == 0xcc | ||
| // 0x02 == Low == 0xbb | ||
| // 0x03 == High == 0xaa | ||
| Case (0x00) | ||
| { | ||
| \_SB.PCI0.LPCB.EC.ECWR (0xdd, RefOf(\_SB.PCI0.LPCB.EC.KLBE)) | ||
| } | ||
| Case (0x01) | ||
| { | ||
| \_SB.PCI0.LPCB.EC.ECWR (0xcc, RefOf(\_SB.PCI0.LPCB.EC.KLBE)) | ||
| } | ||
| Case (0x02) | ||
| { | ||
| \_SB.PCI0.LPCB.EC.ECWR (0xbb, RefOf(\_SB.PCI0.LPCB.EC.KLBE)) | ||
| } | ||
| Case (0x03) | ||
| { | ||
| \_SB.PCI0.LPCB.EC.ECWR (0xaa, RefOf(\_SB.PCI0.LPCB.EC.KLBE)) | ||
| } | ||
| } | ||
| } |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,9 @@ | ||
| config BOARD_DELL_OPTIPLEX_9010 | ||
| bool "OptiPlex 9010 SFF" | ||
| select BOARD_DELL_SNB_IVB_WORKSTATIONS | ||
| select SOUTHBRIDGE_INTEL_BD82X6X | ||
|
|
||
| config BOARD_DELL_PRECISION_T1650 | ||
| bool "Dell Precision T1650" | ||
| select BOARD_DELL_SNB_IVB_WORKSTATIONS | ||
| select SOUTHBRIDGE_INTEL_C216 |