34 changes: 21 additions & 13 deletions src/drivers/intel/fsp2_0/Kconfig
View file
Expand Up @@ -41,6 +41,7 @@ config HAVE_INTEL_FSP_REPO
config FSP_USE_REPO
bool "Use binaries of the Intel FSP repository on GitHub"
depends on HAVE_INTEL_FSP_REPO
select FSP_FULL_FD
default y
help
Select this option to use the default FSP headers and binaries
Expand All @@ -55,13 +56,6 @@ config FSP_HEADER_PATH
help
Include directory with the FSP ABI header files.

config FSP_FD_PATH
string
depends on FSP_USE_REPO
help
Path to the FSP FD file that contains the individual FSP-T, FSP-M
and FSP-S binaries.

config ADD_FSP_BINARIES
bool "Add Intel FSP 2.0 binaries to CBFS" if !FSP_USE_REPO
default y if FSP_USE_REPO
Expand All @@ -81,31 +75,45 @@ config FSP_M_CBFS
string "Name of FSP-M in CBFS"
default "fspm.bin"

config FSP_FULL_FD
bool "Use a combined FSP FD file" if !FSP_USE_REPO
depends on ADD_FSP_BINARIES
help
Use a combined FSP FD file instead of specifying individual, already split
binaries and split the file at build-time.

config FSP_FD_PATH
string "Location of FSP FD file" if FSP_FULL_FD && !FSP_USE_REPO
help
Path to the FSP FD file that contains the individual FSP-T, FSP-M
and FSP-S binaries. The file gets split at build-time.

config FSP_T_FILE
string "Intel FSP-T (temp RAM init) binary path and filename" if !FSP_USE_REPO
string "Intel FSP-T (temp RAM init) binary path and filename" if !FSP_FULL_FD
depends on ADD_FSP_BINARIES
depends on FSP_CAR
default "\$(obj)/Fsp_T.fd" if FSP_USE_REPO
default "\$(obj)/Fsp_T.fd" if FSP_FULL_FD
help
The path and filename of the Intel FSP-T binary for this platform.

config FSP_M_FILE
string "Intel FSP-M (memory init) binary path and filename" if !FSP_USE_REPO
string "Intel FSP-M (memory init) binary path and filename" if !FSP_FULL_FD
depends on ADD_FSP_BINARIES
default "\$(obj)/Fsp_M.fd" if FSP_USE_REPO
default "\$(obj)/Fsp_M.fd" if FSP_FULL_FD
help
The path and filename of the Intel FSP-M binary for this platform.

config FSP_S_FILE
string "Intel FSP-S (silicon init) binary path and filename" if !FSP_USE_REPO
string "Intel FSP-S (silicon init) binary path and filename" if !FSP_FULL_FD
depends on ADD_FSP_BINARIES
default "\$(obj)/Fsp_S.fd" if FSP_USE_REPO
default "\$(obj)/Fsp_S.fd" if FSP_FULL_FD
help
The path and filename of the Intel FSP-S binary for this platform.

config FSP_CAR
bool
default n
select NO_CBFS_MCACHE
help
Use FSP APIs to initialize & Tear Down the Cache-As-Ram

Expand Down
2 changes: 1 addition & 1 deletion src/drivers/intel/fsp2_0/Makefile.inc
View file
Expand Up @@ -72,7 +72,7 @@ ifeq ($(CONFIG_FSP_COMPRESS_FSP_S_LZ4),y)
$(FSP_S_CBFS)-compression := LZ4
endif

ifeq ($(CONFIG_FSP_USE_REPO),y)
ifeq ($(CONFIG_FSP_FULL_FD),y)
$(obj)/Fsp_M.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH))
python2 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)" -n "Fsp.fd"

Expand Down
87 changes: 34 additions & 53 deletions src/drivers/intel/fsp2_0/graphics.c
View file
Expand Up @@ -2,9 +2,11 @@

#include <boot/coreboot_tables.h>
#include <console/console.h>
#include <fsp/graphics.h>
#include <fsp/util.h>
#include <soc/intel/common/vbt.h>
#include <types.h>
#include <framebuffer_info.h>

enum pixel_format {
pixel_rgbx_8bpc = 0,
Expand Down Expand Up @@ -46,75 +48,54 @@ static const struct fsp_framebuffer {
[pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} },
};

enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer)

void fsp_report_framebuffer_info(const uintptr_t framebuffer_bar)
{
size_t size;
const struct hob_graphics_info *ginfo;
const struct fsp_framebuffer *fbinfo;

/*
* Pci enumeration happens after silicon init.
* After enumeration graphic framebuffer base may be relocated.
*/
if (!framebuffer_bar) {
printk(BIOS_ALERT, "Framebuffer BAR invalid\n");
return;
}

ginfo = fsp_find_extension_hob_by_guid(fsp_graphics_info_guid, &size);

if (!ginfo) {
printk(BIOS_ALERT, "Graphics hand-off block not found\n");
return CB_ERR;
return;
}

if (ginfo->pixel_format >= ARRAY_SIZE(fsp_framebuffer_format_map)) {
printk(BIOS_ALERT, "FSP set unknown framebuffer format: %d\n",
ginfo->pixel_format);
return CB_ERR;
return;
}

fbinfo = fsp_framebuffer_format_map + ginfo->pixel_format;

framebuffer->physical_address = ginfo->framebuffer_base;
framebuffer->x_resolution = ginfo->horizontal_resolution;
framebuffer->y_resolution = ginfo->vertical_resolution;
framebuffer->bytes_per_line = ginfo->pixels_per_scanline * 4;
framebuffer->bits_per_pixel = 32;
framebuffer->red_mask_pos = fbinfo->red.pos;
framebuffer->red_mask_size = fbinfo->red.size;
framebuffer->green_mask_pos = fbinfo->green.pos;
framebuffer->green_mask_size = fbinfo->green.size;
framebuffer->blue_mask_pos = fbinfo->blue.pos;
framebuffer->blue_mask_size = fbinfo->blue.size;
framebuffer->reserved_mask_pos = fbinfo->rsvd.pos;
framebuffer->reserved_mask_size = fbinfo->rsvd.pos;

return CB_SUCCESS;
}

int fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
{
enum cb_err ret;
uintptr_t framebuffer_bar;

/* Pci enumeration happens after silicon init.
* After enumeration graphic framebuffer base may be relocated.
* Get framebuffer base from soc.
*/
framebuffer_bar = fsp_soc_get_igd_bar();

if (!framebuffer_bar) {
printk(BIOS_ALERT, "Framebuffer BAR invalid\n");
return -1;
}

ret = fsp_fill_lb_framebuffer(framebuffer);
if (ret != CB_SUCCESS) {
printk(BIOS_ALERT, "FSP did not return a valid framebuffer\n");
return -1;
}

/* Resource allocator can move the BAR around after FSP configures it */
framebuffer->physical_address = framebuffer_bar;
printk(BIOS_DEBUG, "Graphics framebuffer located at 0x%llx\n",
framebuffer->physical_address);

return 0;
}

__weak uintptr_t fsp_soc_get_igd_bar(void)
{
return 0;
const struct lb_framebuffer fb = {
.physical_address = framebuffer_bar,
.x_resolution = ginfo->horizontal_resolution,
.y_resolution = ginfo->vertical_resolution,
.bytes_per_line = ginfo->pixels_per_scanline * 4,
.bits_per_pixel = fbinfo->rsvd.size + fbinfo->red.size +
fbinfo->green.size + fbinfo->blue.size,
.red_mask_pos = fbinfo->red.pos,
.red_mask_size = fbinfo->red.size,
.green_mask_pos = fbinfo->green.pos,
.green_mask_size = fbinfo->green.size,
.blue_mask_pos = fbinfo->blue.pos,
.blue_mask_size = fbinfo->blue.size,
.reserved_mask_pos = fbinfo->rsvd.pos,
.reserved_mask_size = fbinfo->rsvd.size,
.orientation = LB_FB_ORIENTATION_NORMAL,
};

fb_add_framebuffer_info_ex(&fb);
}
16 changes: 16 additions & 0 deletions src/drivers/intel/fsp2_0/include/fsp/graphics.h
View file
@@ -0,0 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */

#ifndef _FSP2_0_GRAPHICS_H_
#define _FSP2_0_GRAPHICS_H_

#include <types.h>

/*
* Report the fsp_graphics_info_guid HOB to framebuffer info.
*
* Must be called after PCI enumeration to make sure that the BAR
* doesn't change any more.
*/
void fsp_report_framebuffer_info(const uintptr_t framebuffer_bar);

#endif /* _FSP2_0_GRAPHICS_H_ */
4 changes: 0 additions & 4 deletions src/drivers/intel/fsp2_0/include/fsp/util.h
View file
Expand Up @@ -88,7 +88,6 @@ const void *fsp_get_hob_list(void);
void *fsp_get_hob_list_ptr(void);
const void *fsp_find_extension_hob_by_guid(const uint8_t *guid, size_t *size);
const void *fsp_find_nv_storage_data(size_t *size);
enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer);
int fsp_find_range_hob(struct range_entry *re, const uint8_t guid[16]);
void fsp_display_fvi_version_hob(void);
void fsp_find_reserved_memory(struct range_entry *re);
Expand Down Expand Up @@ -123,9 +122,6 @@ struct fsp_load_descriptor {
* header object will be validated and filled in on successful load. */
enum cb_err fsp_load_component(struct fsp_load_descriptor *fspld, struct fsp_header *hdr);

/* Get igd framebuffer bar from SoC */
uintptr_t fsp_soc_get_igd_bar(void);

/*
* Handle FSP reboot request status. Chipset/soc is expected to provide
* chipset_handle_reset() that deals with reset type codes specific to given
Expand Down
4 changes: 2 additions & 2 deletions src/drivers/intel/fsp2_0/logo.c
View file
Expand Up @@ -13,8 +13,8 @@ const struct cbmem_entry *fsp_load_logo(UINT32 *logo_ptr, UINT32 *logo_size)
if (logo_entry) {
logo_buffer = cbmem_entry_start(logo_entry);
if (logo_buffer) {
*logo_size = cbfs_boot_load_file("logo.bmp", (void *)logo_buffer,
1 * MiB, CBFS_TYPE_RAW);
*logo_size = cbfs_load("logo.bmp", (void *)logo_buffer,
1 * MiB);
if (*logo_size)
*logo_ptr = (UINT32)logo_buffer;
}
Expand Down
9 changes: 8 additions & 1 deletion src/drivers/intel/fsp2_0/memory_init.c
View file
Expand Up @@ -22,6 +22,7 @@
#include <security/tpm/tspi.h>
#include <vb2_api.h>
#include <types.h>
#include <mode_switch.h>

static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t));

Expand Down Expand Up @@ -296,7 +297,13 @@ static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake)

post_code(POST_FSP_MEMORY_INIT);
timestamp_add_now(TS_FSP_MEMORY_INIT_START);
status = fsp_raminit(&fspm_upd, fsp_get_hob_list_ptr());
if (ENV_X86_64)
status = protected_mode_call_2arg(fsp_raminit,
(uintptr_t)&fspm_upd,
(uintptr_t)fsp_get_hob_list_ptr());
else
status = fsp_raminit(&fspm_upd, fsp_get_hob_list_ptr());

post_code(POST_FSP_MEMORY_EXIT);
timestamp_add_now(TS_FSP_MEMORY_INIT_END);

Expand Down
8 changes: 6 additions & 2 deletions src/drivers/intel/fsp2_0/notify.c
View file
Expand Up @@ -5,6 +5,7 @@
#include <cpu/x86/mtrr.h>
#include <fsp/util.h>
#include <timestamp.h>
#include <mode_switch.h>

static void fsp_notify(enum fsp_notify_phase phase)
{
Expand All @@ -30,7 +31,10 @@ static void fsp_notify(enum fsp_notify_phase phase)
post_code(POST_FSP_NOTIFY_BEFORE_END_OF_FIRMWARE);
}

ret = fspnotify(&notify_params);
if (ENV_X86_64)
ret = protected_mode_call_1arg(fspnotify, (uintptr_t)&notify_params);
else
ret = fspnotify(&notify_params);

if (phase == AFTER_PCI_ENUM) {
timestamp_add_now(TS_FSP_AFTER_ENUMERATE);
Expand All @@ -57,7 +61,7 @@ static void fsp_notify(enum fsp_notify_phase phase)

static void fsp_notify_dummy(void *arg)
{
enum fsp_notify_phase phase = (uint32_t)arg;
enum fsp_notify_phase phase = (uint32_t)(uintptr_t)arg;

display_mtrrs();

Expand Down
10 changes: 9 additions & 1 deletion src/drivers/intel/fsp2_0/silicon_init.c
View file
Expand Up @@ -13,6 +13,7 @@
#include <string.h>
#include <timestamp.h>
#include <types.h>
#include <mode_switch.h>

struct fsp_header fsps_hdr;

Expand Down Expand Up @@ -117,7 +118,14 @@ static void do_silicon_init(struct fsp_header *hdr)

timestamp_add_now(TS_FSP_SILICON_INIT_START);
post_code(POST_FSP_SILICON_INIT);
status = silicon_init(upd);

if (ENV_X86_64)
status = protected_mode_call_1arg(silicon_init, (uintptr_t)upd);
else
status = silicon_init(upd);

printk(BIOS_ERR, "FSPS returned %x\n", status);

timestamp_add_now(TS_FSP_SILICON_INIT_END);
post_code(POST_FSP_SILICON_EXIT);

Expand Down
1 change: 0 additions & 1 deletion src/drivers/intel/fsp2_0/util.c
View file
Expand Up @@ -241,5 +241,4 @@ void lb_string_platform_blob_version(struct lb_header *header)

__weak void soc_validate_fsp_version(const struct fsp_header *hdr)
{
printk(BIOS_DEBUG, "%s not implemented.\n", __func__);
}
32 changes: 9 additions & 23 deletions src/drivers/intel/gma/gma-gfx_init.ads
View file
Expand Up @@ -13,28 +13,14 @@ is

----------------------------------------------------------------------------

type lb_framebuffer is record
tag : word32;
size : word32;

physical_address : word64;
x_resolution : word32;
y_resolution : word32;
bytes_per_line : word32;
bits_per_pixel : word8;
red_mask_pos : word8;
red_mask_size : word8;
green_mask_pos : word8;
green_mask_size : word8;
blue_mask_pos : word8;
blue_mask_size : word8;
reserved_mask_pos : word8;
reserved_mask_size : word8;
end record;

function fill_lb_framebuffer
(framebuffer : in out lb_framebuffer)
return Interfaces.C.int;
pragma Export (C, fill_lb_framebuffer, "fill_lb_framebuffer");
function c_fb_add_framebuffer_info
(fb_addr: Interfaces.C.size_t;
x_resolution : word32;
y_resolution : word32;
bytes_per_line : word32;
bits_per_pixel : word8)
return Interfaces.C.size_t;

pragma import (C, c_fb_add_framebuffer_info, "fb_add_framebuffer_info");

end GMA.GFX_Init;
59 changes: 20 additions & 39 deletions src/drivers/intel/gma/hires_fb/gma-gfx_init.adb
View file
Expand Up @@ -18,56 +18,29 @@ with GMA.Mainboard;
package body GMA.GFX_Init
is

fb_valid : boolean := false;

linear_fb_addr : word64;

fb : Framebuffer_Type;

function fill_lb_framebuffer
(framebuffer : in out lb_framebuffer)
return Interfaces.C.int
is
use type word32;
use type Interfaces.C.int;
begin
if fb_valid then
framebuffer :=
(tag => 0,
size => 0,
physical_address => linear_fb_addr,
x_resolution => word32 (fb.Width),
y_resolution => word32 (fb.Height),
bytes_per_line => 4 * word32 (fb.Stride),
bits_per_pixel => 32,
reserved_mask_pos => 24,
reserved_mask_size => 8,
red_mask_pos => 16,
red_mask_size => 8,
green_mask_pos => 8,
green_mask_size => 8,
blue_mask_pos => 0,
blue_mask_size => 8);
return 0;
else
return -1;
end if;
end fill_lb_framebuffer;

----------------------------------------------------------------------------

procedure gfxinit (lightup_ok : out Interfaces.C.int)
is
use type pos32;
use type word64;
use type word32;
use type Interfaces.C.size_t;

ports : Port_List;
configs : Pipe_Configs;

success : boolean;

linear_fb_addr : word64;

fb : Framebuffer_Type;

min_h : pos32 := Config.LINEAR_FRAMEBUFFER_MAX_WIDTH;
min_v : pos32 := Config.LINEAR_FRAMEBUFFER_MAX_HEIGHT;

fbinfo : Interfaces.C.size_t;

begin
lightup_ok := 0;

Expand Down Expand Up @@ -108,9 +81,17 @@ is
HW.GFX.GMA.Update_Outputs (configs);

HW.GFX.GMA.Map_Linear_FB (linear_fb_addr, fb);
fb_valid := linear_fb_addr /= 0;

lightup_ok := (if fb_valid then 1 else 0);
if linear_fb_addr /= 0 then
fbinfo := c_fb_add_framebuffer_info
(fb_addr => Interfaces.C.size_t (linear_fb_addr),
x_resolution => word32 (fb.Width),
y_resolution => word32 (fb.Height),
bytes_per_line => word32 (fb.Stride) * 4,
bits_per_pixel => 32);
if fbinfo /= 0 then
lightup_ok := 1;
end if;
end if;
end if;
end if;
end if;
Expand Down
3 changes: 1 addition & 2 deletions src/drivers/intel/gma/opregion.c
View file
Expand Up @@ -34,8 +34,7 @@ void *locate_vbt(size_t *vbt_size)

const char *filename = mainboard_vbt_filename();

size_t file_size = cbfs_boot_load_file(filename,
vbt_data, sizeof(vbt_data), CBFS_TYPE_RAW);
size_t file_size = cbfs_load(filename, vbt_data, sizeof(vbt_data));

if (file_size == 0)
return NULL;
Expand Down
11 changes: 0 additions & 11 deletions src/drivers/intel/gma/text_fb/gma-gfx_init.adb
View file
Expand Up @@ -13,17 +13,6 @@ with GMA.Mainboard;
package body GMA.GFX_Init
is

function fill_lb_framebuffer
(framebuffer : in out lb_framebuffer)
return Interfaces.C.int
is
use type Interfaces.C.int;
begin
return -1;
end fill_lb_framebuffer;

----------------------------------------------------------------------------

procedure gfxinit (lightup_ok : out Interfaces.C.int)
is
ports : Port_List;
Expand Down
8 changes: 4 additions & 4 deletions src/drivers/intel/i210/i210.c
View file
Expand Up @@ -206,17 +206,17 @@ static void init(struct device *dev)
return;
}

static void set_resources(struct device *dev)
static void enable_bus_master(struct device *dev)
{
pci_dev_set_resources(dev);
dev->command |= PCI_COMMAND_MASTER;
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
}

static struct device_operations i210_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = set_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = init,
.final = enable_bus_master,
};

static const unsigned short i210_device_ids[] = { 0x1537, 0x1538, 0x1533, 0 };
Expand Down
5 changes: 3 additions & 2 deletions src/drivers/intel/i210/i210.h
View file
Expand Up @@ -27,9 +27,10 @@
#define I210_CHECKSUM_ERROR 0x00000010
#define I210_FLASH_UPDATE_ERROR 0x00000020

#define MAC_ADDR_LEN 6

/* We need one function we can call to get a MAC address to use */
/* This function can be coded somewhere else but must exist. */
extern enum cb_err mainboard_get_mac_address(struct device *dev,
uint8_t mac[6]);
extern enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[MAC_ADDR_LEN]);

#endif /* _INTEL_I210_H_ */
56 changes: 27 additions & 29 deletions src/drivers/ipmi/ipmi_kcs_ops.c
View file
Expand Up @@ -76,20 +76,22 @@ static void ipmi_kcs_init(struct device *dev)
{
struct ipmi_devid_rsp rsp;
uint32_t man_id = 0, prod_id = 0;
struct drivers_ipmi_config *conf = NULL;
struct ipmi_selftest_rsp selftestrsp;
struct drivers_ipmi_config *conf = dev->chip_info;
struct ipmi_selftest_rsp selftestrsp = {0};
uint8_t retry_count;

if (!dev->enabled)
return;

printk(BIOS_DEBUG, "IPMI: PNP KCS 0x%x\n", dev->path.pnp.port);

if (dev->chip_info)
conf = dev->chip_info;
if (!conf) {
printk(BIOS_WARNING, "IPMI: chip_info is missing! Skip init.\n");
return;
}

/* Get IPMI version for ACPI and SMBIOS */
if (conf && conf->wait_for_bmc && conf->bmc_boot_timeout) {
if (conf->wait_for_bmc && conf->bmc_boot_timeout) {
struct stopwatch sw;
stopwatch_init_msecs_expire(&sw, conf->bmc_boot_timeout * 1000);
printk(BIOS_INFO, "IPMI: Waiting for BMC...\n");
Expand Down Expand Up @@ -174,7 +176,7 @@ static unsigned long
ipmi_write_acpi_tables(const struct device *dev, unsigned long current,
struct acpi_rsdp *rsdp)
{
struct drivers_ipmi_config *conf = NULL;
struct drivers_ipmi_config *conf = dev->chip_info;
struct acpi_spmi *spmi;
s8 gpe_interrupt = -1;
u32 apic_interrupt = 0;
Expand Down Expand Up @@ -204,42 +206,43 @@ ipmi_write_acpi_tables(const struct device *dev, unsigned long current,
printk(BIOS_DEBUG, "ACPI: * SPMI at %lx\n", current);
spmi = (struct acpi_spmi *)current;

if (dev->chip_info)
conf = dev->chip_info;

if (conf) {
if (conf->have_gpe)
gpe_interrupt = conf->gpe_interrupt;
if (conf->have_apic)
apic_interrupt = conf->apic_interrupt;
}

/* Use command to get UID from ipmi_ssdt */
acpi_create_ipmi(dev, spmi, (ipmi_revision_major << 8) |
(ipmi_revision_minor << 4), &addr,
IPMI_INTERFACE_KCS, gpe_interrupt, apic_interrupt,
conf->uid);
/* Use command to get UID from ipmi_ssdt */
acpi_create_ipmi(dev, spmi, (ipmi_revision_major << 8) |
(ipmi_revision_minor << 4), &addr,
IPMI_INTERFACE_KCS, gpe_interrupt, apic_interrupt,
conf->uid);

acpi_add_table(rsdp, spmi);
acpi_add_table(rsdp, spmi);

current += spmi->header.length;
current += spmi->header.length;
} else {
printk(BIOS_WARNING, "IPMI: chip_info is missing!\n");
}

return current;
}

static void ipmi_ssdt(const struct device *dev)
{
const char *scope = acpi_device_scope(dev);
struct drivers_ipmi_config *conf = NULL;
struct drivers_ipmi_config *conf = dev->chip_info;

if (!scope) {
printk(BIOS_ERR, "IPMI: Missing ACPI scope for %s\n",
dev_path(dev));
return;
}

if (dev->chip_info)
conf = dev->chip_info;
if (!conf) {
printk(BIOS_WARNING, "IPMI: chip_info is missing!\n");
return;
}

/* Use command to pass UID to ipmi_write_acpi_tables */
conf->uid = uid_cnt++;
Expand All @@ -257,11 +260,9 @@ static void ipmi_ssdt(const struct device *dev)
acpigen_write_io16(dev->path.pnp.port + CONFIG_IPMI_KCS_REGISTER_SPACING,
dev->path.pnp.port + CONFIG_IPMI_KCS_REGISTER_SPACING, 1, 1, 1);

if (conf) {
// FIXME: is that correct?
if (conf->have_apic)
acpigen_write_irq(1 << conf->apic_interrupt);
}
// FIXME: is that correct?
if (conf->have_apic)
acpigen_write_irq(1 << conf->apic_interrupt);

acpigen_write_resourcetemplate_footer();

Expand Down Expand Up @@ -295,16 +296,13 @@ void ipmi_bmc_version(uint8_t *ipmi_bmc_major_revision, uint8_t *ipmi_bmc_minor_
static int ipmi_smbios_data(struct device *dev, int *handle,
unsigned long *current)
{
struct drivers_ipmi_config *conf = NULL;
struct drivers_ipmi_config *conf = dev->chip_info;
u8 nv_storage = 0xff;
u8 i2c_address = 0;
u8 register_spacing;

int len = 0;

if (dev->chip_info)
conf = dev->chip_info;

if (conf) {
if (conf->have_nv_storage)
nv_storage = conf->nv_storage_device_address;
Expand Down
74 changes: 20 additions & 54 deletions src/drivers/pc80/rtc/option.c
View file
Expand Up @@ -49,53 +49,38 @@ static enum cb_err get_cmos_value(unsigned long bit, unsigned long length,
return CB_SUCCESS;
}

static enum cb_err locate_cmos_layout(struct region_device *rdev)
static struct cmos_option_table *get_cmos_layout(void)
{
uint32_t cbfs_type = CBFS_COMPONENT_CMOS_LAYOUT;
static struct cbfsf fh;
static struct cmos_option_table *ct = NULL;

/*
* In case VBOOT is enabled and this function is called from SMM,
* we have multiple CMOS layout files and to locate them we'd need to
* include VBOOT into SMM...
*
* Support only one CMOS layout in the 'COREBOOT' region for now.
* Support only one CMOS layout in the RO CBFS for now.
*/
if (!region_device_sz(&(fh.data))) {
if (cbfs_locate_file_in_region(&fh, "COREBOOT", "cmos_layout.bin",
&cbfs_type)) {
printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. "
"Options are disabled\n");
return CB_CMOS_LAYOUT_NOT_FOUND;
}
}

cbfs_file_data(rdev, &fh);

return CB_SUCCESS;
if (!ct)
ct = cbfs_ro_map("cmos_layout.bin", NULL);
if (!ct)
printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. "
"Options are disabled\n");
return ct;
}

enum cb_err cmos_get_option(void *dest, const char *name)
{
struct cmos_option_table *ct;
struct region_device rdev;
struct cmos_entries *ce;
size_t namelen;
int found = 0;

/* Figure out how long name is */
namelen = strnlen(name, CMOS_MAX_NAME_LENGTH);

if (locate_cmos_layout(&rdev) != CB_SUCCESS) {
ct = get_cmos_layout();
if (!ct)
return CB_CMOS_LAYOUT_NOT_FOUND;
}
ct = rdev_mmap_full(&rdev);
if (!ct) {
printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. "
"Options are disabled\n");

return CB_CMOS_LAYOUT_NOT_FOUND;
}

/* find the requested entry record */
ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length);
Expand All @@ -108,19 +93,15 @@ enum cb_err cmos_get_option(void *dest, const char *name)
}
if (!found) {
printk(BIOS_DEBUG, "No CMOS option '%s'.\n", name);
rdev_munmap(&rdev, ct);
return CB_CMOS_OPTION_NOT_FOUND;
}

if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) {
rdev_munmap(&rdev, ct);
if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC))
return CB_CMOS_CHECKSUM_INVALID;
}
if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) {
rdev_munmap(&rdev, ct);

if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS)
return CB_CMOS_ACCESS_ERROR;
}
rdev_munmap(&rdev, ct);

return CB_SUCCESS;
}

Expand Down Expand Up @@ -168,7 +149,6 @@ static enum cb_err set_cmos_value(unsigned long bit, unsigned long length,
enum cb_err cmos_set_option(const char *name, void *value)
{
struct cmos_option_table *ct;
struct region_device rdev;
struct cmos_entries *ce;
unsigned long length;
size_t namelen;
Expand All @@ -177,16 +157,9 @@ enum cb_err cmos_set_option(const char *name, void *value)
/* Figure out how long name is */
namelen = strnlen(name, CMOS_MAX_NAME_LENGTH);

if (locate_cmos_layout(&rdev) != CB_SUCCESS) {
ct = get_cmos_layout();
if (!ct)
return CB_CMOS_LAYOUT_NOT_FOUND;
}
ct = rdev_mmap_full(&rdev);
if (!ct) {
printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. "
"Options are disabled\n");

return CB_CMOS_LAYOUT_NOT_FOUND;
}

/* find the requested entry record */
ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length);
Expand All @@ -199,7 +172,6 @@ enum cb_err cmos_set_option(const char *name, void *value)
}
if (!found) {
printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name);
rdev_munmap(&rdev, ct);
return CB_CMOS_OPTION_NOT_FOUND;
}

Expand All @@ -208,18 +180,13 @@ enum cb_err cmos_set_option(const char *name, void *value)
length = MAX(strlen((const char *)value) * 8, ce->length - 8);
/* make sure the string is null terminated */
if (set_cmos_value(ce->bit + ce->length - 8, 8, &(u8[]){0})
!= CB_SUCCESS) {
rdev_munmap(&rdev, ct);
!= CB_SUCCESS)
return CB_CMOS_ACCESS_ERROR;
}
}

if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS) {
rdev_munmap(&rdev, ct);
if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS)
return CB_CMOS_ACCESS_ERROR;
}

rdev_munmap(&rdev, ct);
return CB_SUCCESS;
}

Expand All @@ -237,8 +204,7 @@ void sanitize_cmos(void)
size_t i;

if (CONFIG(TPM_MEASURED_BOOT) || cmos_need_reset) {
cmos_default = cbfs_boot_map_with_leak("cmos.default",
CBFS_COMPONENT_CMOS_DEFAULT, &length);
cmos_default = cbfs_map("cmos.default", &length);

if (!cmos_default || !cmos_need_reset)
return;
Expand Down
3 changes: 2 additions & 1 deletion src/drivers/spi/flashconsole.c
View file
Expand Up @@ -75,7 +75,8 @@ void flashconsole_tx_byte(unsigned char c)

size_t region_size = region_device_sz(rdev_ptr);

line_buffer[line_offset++] = c;
if (line_offset < LINE_BUFFER_SIZE)
line_buffer[line_offset++] = c;

if (line_offset >= LINE_BUFFER_SIZE ||
offset + line_offset >= region_size || c == '\n') {
Expand Down
8 changes: 8 additions & 0 deletions src/drivers/spi/spi_flash.c
View file
Expand Up @@ -669,6 +669,14 @@ void lb_spi_flash(struct lb_header *header)
flash->sector_size = 64 * KiB;
flash->erase_cmd = CMD_BLOCK_ERASE;
}

if (!CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) {
flash->mmap_count = 0;
} else {
struct flash_mmap_window *table = (struct flash_mmap_window *)(flash + 1);
flash->mmap_count = spi_flash_get_mmap_windows(table);
flash->size += flash->mmap_count * sizeof(*table);
}
}

int spi_flash_ctrlr_protect_region(const struct spi_flash *flash,
Expand Down
3 changes: 0 additions & 3 deletions src/drivers/uart/uart8250io.c
View file
Expand Up @@ -3,7 +3,6 @@
#include <arch/io.h>
#include <boot/coreboot_tables.h>
#include <console/uart.h>
#include <trace.h>
#include "uart8250reg.h"

#if CONFIG(BOARD_PCENGINES_APU1)
Expand Down Expand Up @@ -62,7 +61,6 @@ static unsigned char uart8250_rx_byte(unsigned int base_port)

static void uart8250_init(unsigned int base_port, unsigned int divisor)
{
DISABLE_TRACE;
/* Disable interrupts */
outb(0x0, base_port + UART8250_IER);
/* Enable FIFOs */
Expand All @@ -80,7 +78,6 @@ static void uart8250_init(unsigned int base_port, unsigned int divisor)

/* Set to 3 for 8N1 */
outb(CONFIG_TTYS0_LCS, base_port + UART8250_LCR);
ENABLE_TRACE;
}

static const unsigned int bases[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
Expand Down
3 changes: 1 addition & 2 deletions src/ec/compal/ene932/acpi/ec.asl
View file
Expand Up @@ -16,8 +16,7 @@ Device (EC0)
Field (ERAM, ByteAcc, Lock, Preserve)
{
// EC Name Space Configuration
Offset(0x00),
, 1, // Reserved ; 00h.0
, 1, // Reserved ; 00h.0
LCDS, 1, // 1= BACKLIGHT ON , 0= BACKLIGHT OFF ; 00h.1
, 6, // Reserved ; 00h.2 ~ 00h.6
HTBN, 8, // HOTKEY_BUTTON_NUMBER ; 01h For ABO Hot Key Function
Expand Down
3 changes: 1 addition & 2 deletions src/ec/google/chromeec/acpi/ec.asl
View file
Expand Up @@ -31,7 +31,6 @@ Device (EC0)
OperationRegion (ERAM, EmbeddedControl, 0x00, EC_ACPI_MEM_MAPPED_BEGIN)
Field (ERAM, ByteAcc, Lock, Preserve)
{
Offset (0x00),
RAMV, 8, // EC RAM Version
TSTB, 8, // Test Byte
TSTC, 8, // Complement of Test Byte
Expand Down Expand Up @@ -82,7 +81,7 @@ Device (EC0)
Offset (0x12),
BTID, 8, // Battery index that host wants to read
USPP, 8, // USB Port Power
}
}

#if CONFIG(EC_GOOGLE_CHROMEEC_ACPI_MEMMAP)
OperationRegion (EMEM, EmbeddedControl,
Expand Down
1 change: 0 additions & 1 deletion src/ec/google/chromeec/acpi/emem.asl
View file
Expand Up @@ -4,7 +4,6 @@
* EMEM data may be accessed through port 62/66 or through LPC at 900h.
*/

Offset (0x00),
TIN0, 8, // Temperature 0
TIN1, 8, // Temperature 1
TIN2, 8, // Temperature 2
Expand Down
2 changes: 1 addition & 1 deletion src/ec/quanta/it8518/acpi/ec.asl
View file
Expand Up @@ -16,7 +16,7 @@ Device (EC0)
OperationRegion(ERAM, EmbeddedControl, 0, 0xFF)
Field (ERAM, ByteAcc, NoLock, Preserve)
{
Offset(0x00), // [Configuration Space 0]
// [Configuration Space 0]
, 1, // Reserved bit[0]
ENGA, 1, // Enable Global attention
ENHY, 1, // Enable Hotkey function
Expand Down
1 change: 0 additions & 1 deletion src/ec/roda/it8518/acpi/ec.asl
View file
Expand Up @@ -14,7 +14,6 @@ Device (EC0)
OperationRegion(ERAM, EmbeddedControl, 0, 0xFF)
Field (ERAM, ByteAcc, NoLock, Preserve)
{
Offset(0x00), // [Configuration Space 0x0]
Offset(0x02), // [Configuration Space 0x2]
B0ST, 16, // Battery 0 State
B0FC, 16, // Battery 0 Last Full Charge Capacity
Expand Down
3 changes: 2 additions & 1 deletion src/include/boot_device.h
View file
Expand Up @@ -27,7 +27,8 @@ enum bootdev_prot_type {
* most likely not to work so don't rely on such semantics.
*/

/* Return the region_device for the read-only boot device. */
/* Return the region_device for the read-only boot device. This is the root
device for all CBFS boot devices. */
const struct region_device *boot_device_ro(void);

/* Return the region_device for the read-write boot device. */
Expand Down
45 changes: 35 additions & 10 deletions src/include/cbfs.h
View file
Expand Up @@ -7,6 +7,7 @@
#include <commonlib/cbfs.h>
#include <program_loading.h>
#include <types.h>
#include <vb2_sha.h>

/***********************************************
* Perform CBFS operations on the boot device. *
Expand All @@ -18,19 +19,28 @@ void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device);
void *cbfs_boot_map_optionrom_revision(uint16_t vendor, uint16_t device, uint8_t rev);
/* Locate file by name and optional type. Return 0 on success. < 0 on error. */
int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type);
/* Map file into memory leaking the mapping. Only should be used when
* leaking mappings are a no-op. Returns NULL on error, else returns
* the mapping and sets the size of the file. */
void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size);
/* Map file into memory, returning a pointer to the mapping or NULL on error.
If |size_out| is not NULL, it will pass out the size of the mapped file.
NOTE: Since this may return a direct pointer to memory-mapped hardware,
compressed files are NOT transparently decompressed (unlike cbfs_load()). */
void *cbfs_map(const char *name, size_t *size_out);
/* Like cbfs_map(), except that it will always read from the read-only CBFS
("COREBOOT" FMAP region), even when CONFIG(VBOOT) is enabled. */
void *cbfs_ro_map(const char *name, size_t *size_out);
/* Removes a previously allocated CBFS mapping. Should try to unmap mappings in
strict LIFO order where possible, since mapping backends often don't support
more complicated cases. */
int cbfs_unmap(void *mapping);
/* Locate file in a specific region of fmap. Return 0 on success. < 0 on error*/
int cbfs_locate_file_in_region(struct cbfsf *fh, const char *region_name,
const char *name, uint32_t *type);
/* Load an arbitrary type file from CBFS into a buffer. Returns amount of
* loaded bytes on success or 0 on error. File will get decompressed as
* necessary. Same decompression requirements as
* cbfs_load_and_decompress(). */
size_t cbfs_boot_load_file(const char *name, void *buf, size_t buf_size,
uint32_t type);
/* Load a file from CBFS into a buffer. Returns amount of loaded bytes on
success or 0 on error. File will get decompressed as necessary. Same
decompression requirements as cbfs_load_and_decompress(). */
size_t cbfs_load(const char *name, void *buf, size_t buf_size);
/* Like cbfs_load(), except that it will always read from the read-only CBFS
("COREBOOT" FMAP region), even when CONFIG(VBOOT) is enabled. */
size_t cbfs_ro_load(const char *name, void *buf, size_t buf_size);
/* Load |in_size| bytes from |rdev| at |offset| to the |buffer_size| bytes
* large |buffer|, decompressing it according to |compression| in the process.
* Returns the decompressed file size, or 0 on error.
Expand All @@ -42,6 +52,12 @@ size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset,
/* Load stage into memory filling in prog. Return 0 on success. < 0 on error. */
int cbfs_prog_stage_load(struct prog *prog);

/*
* Data structure that represents "a" CBFS boot device, with optional metadata
* cache. Generally we only have one of these, or two (RO and RW) when
* CONFIG(VBOOT) is set. The region device stored here must always be a
* subregion of boot_device_ro().
*/
struct cbfs_boot_device {
struct region_device rdev;
void *mcache;
Expand All @@ -59,4 +75,13 @@ void cbfs_boot_device_find_mcache(struct cbfs_boot_device *cbd, uint32_t id);
*/
const struct cbfs_boot_device *cbfs_get_boot_device(bool force_ro);

/*
* Builds the mcache (if |cbd->mcache| is set) and verifies |metadata_hash| (if
* it is not NULL). If CB_CBFS_CACHE_FULL is returned, the mcache is incomplete
* but still valid and the metadata hash was still verified. Should be called
* once per *boot* (not once per stage) before the first CBFS access.
*/
cb_err_t cbfs_init_boot_device(const struct cbfs_boot_device *cbd,
struct vb2_hash *metadata_hash);

#endif
15 changes: 13 additions & 2 deletions src/include/cbfs_glue.h
View file
Expand Up @@ -5,8 +5,19 @@

#include <commonlib/region.h>
#include <console/console.h>

#define CBFS_ENABLE_HASHING 0
#include <rules.h>

/*
* This flag prevents linking hashing functions into stages where they're not required. We don't
* need them at all if verification is disabled. If verification is enabled without TOCTOU
* safety, we only need to verify the metadata hash in the initial stage and can assume it stays
* valid in later stages. If TOCTOU safety is required, we may need them in every stage to
* reverify metadata that had to be reloaded from flash (e.g. because it didn't fit the mcache).
* Note that this only concerns metadata hashing -- file access functions may still link hashing
* routines independently for file data hashing.
*/
#define CBFS_ENABLE_HASHING (CONFIG(CBFS_VERIFICATION) && \
(CONFIG(TOCTOU_SAFETY) || ENV_INITIAL_STAGE))

#define ERROR(...) printk(BIOS_ERR, "CBFS ERROR: " __VA_ARGS__)
#define LOG(...) printk(BIOS_ERR, "CBFS: " __VA_ARGS__)
Expand Down
23 changes: 23 additions & 0 deletions src/include/cbfs_private.h
View file
@@ -0,0 +1,23 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#ifndef _CBFS_PRIVATE_H_
#define _CBFS_PRIVATE_H_

#include <commonlib/bsd/cbfs_private.h>
#include <commonlib/region.h>
#include <types.h>

/*
* This header contains low-level CBFS APIs that should only be used by code
* that really needs this level of access. Most code (particularly platform
* code) should use the higher-level CBFS APIs in <cbfs.h>. Code using these
* APIs needs to take special care to ensure CBFS file data is verified (in a
* TOCTOU-safe manner) before access (TODO: add details on how to do this once
* file verification code is in).
*/

/* Find by name, load metadata into |mdata| and chain file data to |rdev|. */
cb_err_t cbfs_boot_lookup(const char *name, bool force_ro,
union cbfs_mdata *mdata, struct region_device *rdev);

#endif
5 changes: 1 addition & 4 deletions src/include/cbmem.h
View file
Expand Up @@ -163,10 +163,7 @@ static inline int cbmem_online(void)
if (!cbmem_possibly_online())
return 0;

if (ENV_ROMSTAGE)
return cbmem_initialized;

return 1;
return cbmem_initialized;
}

#endif /* _CBMEM_H_ */
8 changes: 4 additions & 4 deletions src/include/cpu/x86/smm.h
View file
Expand Up @@ -150,10 +150,10 @@ struct smm_loader_params {

/* The following are only used by X86_SMM_LOADER_VERSION2 */
#if CONFIG(X86_SMM_LOADER_VERSION2)
unsigned int smm_entry;
unsigned int smm_main_entry_offset;
unsigned int smram_start;
unsigned int smram_end;
uintptr_t smm_entry;
uintptr_t smm_main_entry_offset;
uintptr_t smram_start;
uintptr_t smram_end;
#endif
};

Expand Down
4 changes: 4 additions & 0 deletions src/include/device/azalia_device.h
View file
Expand Up @@ -18,6 +18,10 @@
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)

int azalia_set_bits(void *port, u32 mask, u32 val);
int azalia_enter_reset(u8 *base);
int azalia_exit_reset(u8 *base);
u32 azalia_find_verb(const u32 *verb_table, u32 verb_table_bytes, u32 viddid, const u32 **verb);
void azalia_audio_init(struct device *dev);
extern struct device_operations default_azalia_audio_ops;

Expand Down
1 change: 1 addition & 0 deletions src/include/device/device.h
View file
Expand Up @@ -385,6 +385,7 @@ static inline DEVTREE_CONST void *config_of(const struct device *dev)
devtree_die();
}

/* config_of_soc() either returns a non-NULL pointer or dies in the config_of() call. */
static inline DEVTREE_CONST void *config_of_soc(void)
{
return config_of(pcidev_on_root(0, 0));
Expand Down
11 changes: 10 additions & 1 deletion src/include/device/pci_ids.h
View file
Expand Up @@ -2837,6 +2837,7 @@
#define PCI_DEVICE_ID_INTEL_LWB_C621A_SUPER 0xa24a
#define PCI_DEVICE_ID_INTEL_LWB_C627A_SUPER 0xa24b
#define PCI_DEVICE_ID_INTEL_LWB_C629A_SUPER 0xa24c
#define PCI_DEVICE_ID_INTEL_EMB_SUPER 0x1b81
#define PCI_DEVICE_ID_INTEL_KBP_H_H270 0xa2c4
#define PCI_DEVICE_ID_INTEL_KBP_H_Z270 0xa2c5
#define PCI_DEVICE_ID_INTEL_KBP_H_Q270 0xa2c6
Expand Down Expand Up @@ -3563,7 +3564,7 @@
#define PCI_DEVICE_ID_INTEL_TGP_SPI0 0xa0a4
#define PCI_DEVICE_ID_INTEL_TGP_GSPI0 0xa0aa
#define PCI_DEVICE_ID_INTEL_TGP_GSPI1 0xa0ab
#define PCI_DEVICE_ID_INTEL_TGP_GSPI2 0x34fb
#define PCI_DEVICE_ID_INTEL_TGP_GSPI2 0xa0fb
#define PCI_DEVICE_ID_INTEL_TGP_GSPI3 0xa0fd
#define PCI_DEVICE_ID_INTEL_TGP_GSPI4 0xa0fe
#define PCI_DEVICE_ID_INTEL_TGP_GSPI5 0xa0de
Expand Down Expand Up @@ -3871,6 +3872,7 @@
#define PCI_DEVICE_ID_INTEL_JSP_XHCI 0x4ded
#define PCI_DEVICE_ID_INTEL_ADP_P_XHCI 0x51ed
#define PCI_DEVICE_ID_INTEL_ADP_S_XHCI 0x7ae0
#define PCI_DEVICE_ID_INTEL_ADP_TCSS_XHCI 0x461e

/* Intel P2SB device Ids */
#define PCI_DEVICE_ID_INTEL_APL_P2SB 0x5a92
Expand Down Expand Up @@ -3984,6 +3986,7 @@
#define PCI_DEVICE_ID_INTEL_JSP_XDCI 0x4dee
#define PCI_DEVICE_ID_INTEL_ADP_P_XDCI 0x51ee
#define PCI_DEVICE_ID_INTEL_ADP_S_XDCI 0x7ae1
#define PCI_DEVICE_ID_INTEL_ADP_TCSS_XDCI 0x460e

/* Intel SD device Ids */
#define PCI_DEVICE_ID_INTEL_LPT_LP_SD 0x9c35
Expand All @@ -4008,8 +4011,14 @@
#define PCI_DEVICE_ID_INTEL_TGL_TBT_RP1 0x9a25
#define PCI_DEVICE_ID_INTEL_TGL_TBT_RP2 0x9a27
#define PCI_DEVICE_ID_INTEL_TGL_TBT_RP3 0x9a29
#define PCI_DEVICE_ID_INTEL_ADL_TBT_RP0 0x466e
#define PCI_DEVICE_ID_INTEL_ADL_TBT_RP1 0x463f
#define PCI_DEVICE_ID_INTEL_ADL_TBT_RP2 0x462f
#define PCI_DEVICE_ID_INTEL_ADL_TBT_RP3 0x461f
#define PCI_DEVICE_ID_INTEL_TGL_TBT_DMA0 0x9a1b
#define PCI_DEVICE_ID_INTEL_TGL_TBT_DMA1 0x9a1d
#define PCI_DEVICE_ID_INTEL_ADL_TBT_DMA0 0x463e
#define PCI_DEVICE_ID_INTEL_ADL_TBT_DMA1 0x466d

/* Intel WIFI Ids */
#define PCI_DEVICE_ID_1000_SERIES_WIFI 0x0084
Expand Down
3 changes: 1 addition & 2 deletions src/include/edid.h
View file
Expand Up @@ -4,6 +4,7 @@
#define EDID_H

#include <stdint.h>
#include <framebuffer_info.h>
#include "commonlib/coreboot_tables.h"

enum edid_modes {
Expand Down Expand Up @@ -95,8 +96,6 @@ enum edid_status {
int decode_edid(unsigned char *edid, int size, struct edid *out);
void edid_set_framebuffer_bits_per_pixel(struct edid *edid, int fb_bpp,
int row_byte_alignment);
void set_vbe_mode_info_valid(const struct edid *edid, uintptr_t fb_addr);
void set_vbe_framebuffer_orientation(enum lb_fb_orientation orientation);
int set_display_mode(struct edid *edid, enum edid_modes mode);

#endif /* EDID_H */
4 changes: 4 additions & 0 deletions src/include/elog.h
View file
Expand Up @@ -120,6 +120,10 @@
#define ELOG_WAKE_SOURCE_PME_PCIE23 0x2a
#define ELOG_WAKE_SOURCE_PME_PCIE24 0x2b
#define ELOG_WAKE_SOURCE_GPIO 0x2c
#define ELOG_WAKE_SOURCE_PME_TBT 0x2d
#define ELOG_WAKE_SOURCE_PME_TCSS_XHCI 0x2e
#define ELOG_WAKE_SOURCE_PME_TCSS_XDCI 0x2f
#define ELOG_WAKE_SOURCE_PME_TCSS_DMA 0x30

struct elog_event_data_wake {
u8 source;
Expand Down
26 changes: 26 additions & 0 deletions src/include/framebuffer_info.h
View file
@@ -0,0 +1,26 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */

#ifndef __FRAMEBUFFER_INFO_H_
#define __FRAMEBUFFER_INFO_H_

#include <stdint.h>
#include <stdbool.h>
#include <commonlib/coreboot_tables.h>

struct fb_info;

struct fb_info *
fb_add_framebuffer_info_ex(const struct lb_framebuffer *fb);

struct fb_info *fb_add_framebuffer_info(uintptr_t fb_addr, uint32_t x_resolution,
uint32_t y_resolution, uint32_t bytes_per_line,
uint8_t bits_per_pixel);

void fb_set_orientation(struct fb_info *info,
enum lb_fb_orientation orientation);

struct edid;
struct fb_info *fb_new_framebuffer_info_from_edid(const struct edid *edid,
uintptr_t fb_addr);

#endif /* __FRAMEBUFFER_INFO_H_ */
6 changes: 6 additions & 0 deletions src/include/fw_config.h
View file
Expand Up @@ -56,6 +56,12 @@ bool fw_config_probe(const struct fw_config *match);
*/
void fw_config_for_each_found(void (*cb)(const struct fw_config *config, void *arg), void *arg);

/**
* fw_config_is_provisioned() - Determine if FW_CONFIG has been provisioned.
* Return %true if FW_CONFIG has been provisioned, %false otherwise.
*/
bool fw_config_is_provisioned(void);

/**
* fw_config_get_found() - Return a pointer to the fw_config struct for a given field.
* @field_mask: A field mask from static.h, e.g., FW_CONFIG_FIELD_FEATURE_MASK
Expand Down
21 changes: 21 additions & 0 deletions src/include/metadata_hash.h
View file
@@ -0,0 +1,21 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#ifndef _METADATA_HASH_H_
#define _METADATA_HASH_H_

#include <commonlib/bsd/metadata_hash.h>

/* Verify the an FMAP data structure with the FMAP hash that is stored together with the CBFS
metadata hash in the bootblock's metadata hash anchor (when CBFS verification is enabled). */
vb2_error_t metadata_hash_verify_fmap(const void *fmap_base, size_t fmap_size);

#if CONFIG(CBFS_VERIFICATION)
/* Get the (RO) CBFS metadata hash for this CBFS image, which forms the root of trust for CBFS
verification. This function is only available in the bootblock. */
struct vb2_hash *metadata_hash_get(void);
#else
static inline struct vb2_hash *metadata_hash_get(void) { return NULL; }
#endif

#endif
2 changes: 1 addition & 1 deletion src/include/spd_cache.h
View file
Expand Up @@ -7,7 +7,7 @@
#include <stddef.h>
#include <stdint.h>

#define SPD_CACHE_FMAP_NAME "RW_SPD_CACHE"
#define SPD_CACHE_FMAP_NAME (CONFIG_SPD_CACHE_FMAP_NAME)
#define SC_SPD_NUMS (CONFIG_DIMM_MAX)
#define SC_SPD_OFFSET(n) (CONFIG_DIMM_SPD_SIZE * n)
#define SC_CRC_OFFSET (CONFIG_DIMM_MAX * CONFIG_DIMM_SPD_SIZE)
Expand Down
8 changes: 8 additions & 0 deletions src/include/spi_flash.h
View file
Expand Up @@ -230,4 +230,12 @@ int spi_flash_vector_helper(const struct spi_slave *slave,
int (*func)(const struct spi_slave *slave, const void *dout,
size_t bytesout, void *din, size_t bytesin));

/*
* Fill in the memory mapped windows used by the SPI flash device. This is useful for payloads
* to identify SPI flash to host space mapping.
*
* Returns number of windows added to the table.
*/
uint32_t spi_flash_get_mmap_windows(struct flash_mmap_window *table);

#endif /* _SPI_FLASH_H_ */
28 changes: 0 additions & 28 deletions src/include/trace.h
View file

This file was deleted.

26 changes: 17 additions & 9 deletions src/lib/Kconfig
View file
Expand Up @@ -5,14 +5,6 @@ config MISSING_BOARD_RESET
implementation. This activates a stub that logs the missing
board reset and halts execution.

config NO_EDID_FILL_FB
bool
default y if !MAINBOARD_DO_NATIVE_VGA_INIT
help
Don't include default fill_lb_framebuffer() implementation. Select
this if your drivers uses MAINBOARD_DO_NATIVE_VGA_INIT but provides
its own fill_lb_framebuffer() implementation.

config RAMSTAGE_ADA
bool
help
Expand Down Expand Up @@ -54,6 +46,23 @@ config DIMM_SPD_SIZE
config SPD_READ_BY_WORD
bool

config SPD_CACHE_IN_FMAP
bool
default n
help
Enables capability to cache DIMM SPDs in a dedicated FMAP region
to speed loading of SPD data. Currently requires board-level
romstage implementation to read/write/utilize cached SPD data.
When the default FMAP is used, will create a region named RW_SPD_CACHE
to store the cached SPD data.

config SPD_CACHE_FMAP_NAME
string
depends on SPD_CACHE_IN_FMAP
default "RW_SPD_CACHE"
help
Name of the FMAP region created in the default FMAP to cache SPD data.

if RAMSTAGE_LIBHWBASE

config HWBASE_DYNAMIC_MMIO
Expand Down Expand Up @@ -83,7 +92,6 @@ config ESPI_DEBUG

config NO_CBFS_MCACHE
bool
default y
help
Disables the CBFS metadata cache. This means that your platform does
not need to provide a CBFS_MCACHE section in memlayout and can save
Expand Down
58 changes: 58 additions & 0 deletions src/lib/Kconfig.cbfs_verification
View file
@@ -0,0 +1,58 @@
# SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
#
# This file is part of the coreboot project.
#
# This file is sourced from src/security/Kconfig for menuconfig convenience.

#menu "CBFS verification" # TODO: enable once it works

config CBFS_VERIFICATION
bool # TODO: make user selectable once it works
depends on !COMPRESS_BOOTBLOCK # TODO: figure out decompressor anchor
depends on !VBOOT_STARTS_BEFORE_BOOTBLOCK # this is gonna get tricky...
select VBOOT_LIB
help
Work in progress. Do not use (yet).

config TOCTOU_SAFETY
bool
depends on CBFS_VERIFICATION
depends on !NO_FMAP_CACHE
depends on !NO_CBFS_MCACHE
depends on !USE_OPTION_TABLE && !FSP_CAR # Known to access CBFS before CBMEM init
help
Work in progress. Not actually TOCTOU safe yet. Do not use.

Design idea here is that mcache overflows in this mode are only legal
for the RW CBFS, because it's relatively easy to retrieve the RW
metadata hash from persistent vboot context at any time, but the RO
metadata hash is lost after the bootblock is unloaded. This avoids the
need to carry yet another piece forward through the stages. Mcache
overflows are mostly a concern for RW updates (if an update adds more
files than originally planned for), for the RO section it should
always be possible to dimension the mcache correctly beforehand, so
this should be an acceptable limitation.

config CBFS_HASH_ALGO
int
default 1 if CBFS_HASH_SHA1
default 2 if CBFS_HASH_SHA256
default 3 if CBFS_HASH_SHA512

choice
prompt "--> hash type"
depends on CBFS_VERIFICATION
default CBFS_HASH_SHA256

config CBFS_HASH_SHA1
bool "SHA-1"

config CBFS_HASH_SHA256
bool "SHA-256"

config CBFS_HASH_SHA512
bool "SHA-512"

endchoice

#endmenu
7 changes: 2 additions & 5 deletions src/lib/Makefile.inc
View file
Expand Up @@ -47,6 +47,7 @@ bootblock-y += prog_ops.c
bootblock-y += cbfs.c
bootblock-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c
bootblock-y += libgcc.c
bootblock-$(CONFIG_CBFS_VERIFICATION) += metadata_hash.c
bootblock-$(CONFIG_GENERIC_UDELAY) += timer.c

bootblock-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
Expand Down Expand Up @@ -140,14 +141,10 @@ ramstage-y += wrdd.c
ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
ramstage-$(CONFIG_BOOTSPLASH) += bootsplash.c
ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c
ramstage-$(CONFIG_TRACE) += trace.c
postcar-$(CONFIG_TRACE) += trace.c
ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
ramstage-$(CONFIG_COVERAGE) += libgcov.c
ramstage-y += edid.c
ifneq ($(CONFIG_NO_EDID_FILL_FB),y)
ramstage-y += edid_fill_fb.c
endif
ramstage-y += memrange.c
ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c
ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c
Expand Down Expand Up @@ -376,4 +373,4 @@ endif

ramstage-y += uuid.c

romstage-$(CONFIG_ROMSTAGE_SPD_SMBUS) += spd_cache.c
romstage-$(CONFIG_SPD_CACHE_IN_FMAP) += spd_cache.c
4 changes: 2 additions & 2 deletions src/lib/bootsplash.c
View file
Expand Up @@ -16,8 +16,7 @@ void set_bootsplash(unsigned char *framebuffer, unsigned int x_resolution,
printk(BIOS_INFO, "Setting up bootsplash in %dx%d@%d\n", x_resolution, y_resolution,
fb_resolution);
struct jpeg_decdata *decdata;
unsigned char *jpeg =
cbfs_boot_map_with_leak("bootsplash.jpg", CBFS_TYPE_BOOTSPLASH, NULL);
unsigned char *jpeg = cbfs_map("bootsplash.jpg", NULL);
if (!jpeg) {
printk(BIOS_ERR, "Could not find bootsplash.jpg\n");
return;
Expand All @@ -31,6 +30,7 @@ void set_bootsplash(unsigned char *framebuffer, unsigned int x_resolution,
decdata = malloc(sizeof(*decdata));
int ret = jpeg_decode(jpeg, framebuffer, x_resolution, y_resolution, fb_resolution,
decdata);
cbfs_unmap(jpeg);
if (ret != 0) {
printk(BIOS_ERR, "Bootsplash could not be decoded. jpeg_decode returned %d.\n",
ret);
Expand Down
210 changes: 149 additions & 61 deletions src/lib/cbfs.c
View file
Expand Up @@ -3,84 +3,127 @@
#include <assert.h>
#include <boot_device.h>
#include <cbfs.h>
#include <cbfs_private.h>
#include <cbmem.h>
#include <commonlib/bsd/cbfs_private.h>
#include <commonlib/bsd/compression.h>
#include <commonlib/endian.h>
#include <console/console.h>
#include <fmap.h>
#include <lib.h>
#include <metadata_hash.h>
#include <security/tpm/tspi/crtm.h>
#include <security/vboot/vboot_common.h>
#include <stdlib.h>
#include <string.h>
#include <symbols.h>
#include <timestamp.h>

static cb_err_t cbfs_boot_lookup(const struct cbfs_boot_device *cbd,
const char *name, union cbfs_mdata *mdata, size_t *data_offset)
cb_err_t cbfs_boot_lookup(const char *name, bool force_ro,
union cbfs_mdata *mdata, struct region_device *rdev)
{
cb_err_t err = CB_CBFS_CACHE_FULL;
if (!CONFIG(NO_CBFS_MCACHE) && !ENV_SMM)
err = cbfs_mcache_lookup(cbd->mcache, cbd->mcache_size,
name, mdata, data_offset);
if (err == CB_CBFS_CACHE_FULL)
err = cbfs_lookup(&cbd->rdev, name, mdata, data_offset, NULL);
return err;
}

int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type)
{
const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false);
const struct cbfs_boot_device *cbd = cbfs_get_boot_device(force_ro);
if (!cbd)
return -1;
return CB_ERR;

size_t data_offset;
cb_err_t err = cbfs_boot_lookup(cbd, name, &fh->mdata, &data_offset);
cb_err_t err = CB_CBFS_CACHE_FULL;
if (!CONFIG(NO_CBFS_MCACHE) && !ENV_SMM && cbd->mcache_size)
err = cbfs_mcache_lookup(cbd->mcache, cbd->mcache_size,
name, mdata, &data_offset);
if (err == CB_CBFS_CACHE_FULL) {
struct vb2_hash *metadata_hash = NULL;
if (CONFIG(TOCTOU_SAFETY)) {
if (ENV_SMM) /* Cannot provide TOCTOU safety for SMM */
dead_code();
if (!cbd->mcache_size)
die("Cannot access CBFS TOCTOU-safely in " ENV_STRING " before CBMEM init!\n");
/* We can only reach this for the RW CBFS -- an mcache
overflow in the RO CBFS would have been caught when
building the mcache in cbfs_get_boot_device().
(Note that TOCTOU_SAFETY implies !NO_CBFS_MCACHE.) */
assert(cbd == vboot_get_cbfs_boot_device());
/* TODO: set metadata_hash to RW metadata hash here. */
}
err = cbfs_lookup(&cbd->rdev, name, mdata, &data_offset,
metadata_hash);
}

if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && err == CB_CBFS_NOT_FOUND) {
if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && !force_ro &&
err == CB_CBFS_NOT_FOUND) {
printk(BIOS_INFO, "CBFS: Fall back to RO region for %s\n",
name);
if (!(cbd = cbfs_get_boot_device(true)))
return -1;
err = cbfs_boot_lookup(cbd, name, &fh->mdata, &data_offset);
return cbfs_boot_lookup(name, true, mdata, rdev);
}
if (err) {
if (err == CB_CBFS_NOT_FOUND)
printk(BIOS_WARNING, "CBFS: '%s' not found.\n", name);
else if (err == CB_CBFS_HASH_MISMATCH)
printk(BIOS_ERR, "CBFS ERROR: metadata hash mismatch!\n");
else
printk(BIOS_ERR,
"CBFS ERROR: error %d when looking up '%s'\n",
err, name);
return err;
}
if (err)

if (rdev_chain(rdev, &cbd->rdev, data_offset, be32toh(mdata->h.len)))
return CB_ERR;

if (tspi_measure_cbfs_hook(rdev, name, be32toh(mdata->h.type)))
return CB_ERR;

return CB_SUCCESS;
}

int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type)
{
if (cbfs_boot_lookup(name, false, &fh->mdata, &fh->data))
return -1;

size_t msize = be32toh(fh->mdata.h.offset);
if (rdev_chain(&fh->metadata, &addrspace_32bit.rdev,
(uintptr_t)&fh->mdata, msize) ||
rdev_chain(&fh->data, &cbd->rdev, data_offset,
be32toh(fh->mdata.h.len)))
(uintptr_t)&fh->mdata, msize))
return -1;

if (type) {
if (!*type)
*type = be32toh(fh->mdata.h.type);
else if (*type != be32toh(fh->mdata.h.type))
return -1;
}

if (tspi_measure_cbfs_hook(fh, name))
return -1;

return 0;
}

void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size)
static void *_cbfs_map(const char *name, size_t *size_out, bool force_ro)
{
struct cbfsf fh;
size_t fsize;
struct region_device rdev;
union cbfs_mdata mdata;

if (cbfs_boot_locate(&fh, name, &type))
if (cbfs_boot_lookup(name, force_ro, &mdata, &rdev))
return NULL;

fsize = region_device_sz(&fh.data);
if (size_out != NULL)
*size_out = region_device_sz(&rdev);

if (size != NULL)
*size = fsize;
return rdev_mmap_full(&rdev);
}

return rdev_mmap(&fh.data, 0, fsize);
void *cbfs_map(const char *name, size_t *size_out)
{
return _cbfs_map(name, size_out, false);
}

void *cbfs_ro_map(const char *name, size_t *size_out)
{
return _cbfs_map(name, size_out, true);
}

int cbfs_unmap(void *mapping)
{
/* This works because munmap() only works on the root rdev and never
cares about which chained subregion something was mapped from. */
return rdev_munmap(boot_device_ro(), mapping);
}

int cbfs_locate_file_in_region(struct cbfsf *fh, const char *region_name,
Expand All @@ -94,9 +137,13 @@ int cbfs_locate_file_in_region(struct cbfsf *fh, const char *region_name,
return -1;
}

uint32_t dummy_type = 0;
if (!type)
type = &dummy_type;

ret = cbfs_locate(fh, &rdev, name, type);
if (!ret)
if (tspi_measure_cbfs_hook(fh, name))
if (tspi_measure_cbfs_hook(&rdev, name, *type))
return -1;
return ret;
}
Expand Down Expand Up @@ -255,7 +302,7 @@ void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device)
tohex16(vendor, name + 3);
tohex16(device, name + 8);

return cbfs_boot_map_with_leak(name, CBFS_TYPE_OPTIONROM, NULL);
return cbfs_map(name, NULL);
}

void *cbfs_boot_map_optionrom_revision(uint16_t vendor, uint16_t device, uint8_t rev)
Expand All @@ -266,27 +313,39 @@ void *cbfs_boot_map_optionrom_revision(uint16_t vendor, uint16_t device, uint8_t
tohex16(device, name + 8);
tohex8(rev, name + 13);

return cbfs_boot_map_with_leak(name, CBFS_TYPE_OPTIONROM, NULL);
return cbfs_map(name, NULL);
}

size_t cbfs_boot_load_file(const char *name, void *buf, size_t buf_size,
uint32_t type)
static size_t _cbfs_load(const char *name, void *buf, size_t buf_size,
bool force_ro)
{
struct cbfsf fh;
uint32_t compression_algo;
size_t decompressed_size;
struct region_device rdev;
union cbfs_mdata mdata;

if (cbfs_boot_locate(&fh, name, &type) < 0)
if (cbfs_boot_lookup(name, force_ro, &mdata, &rdev))
return 0;

if (cbfsf_decompression_info(&fh, &compression_algo,
&decompressed_size)
< 0
|| decompressed_size > buf_size)
return 0;
uint32_t compression = CBFS_COMPRESS_NONE;
const struct cbfs_file_attr_compression *attr = cbfs_find_attr(&mdata,
CBFS_FILE_ATTR_TAG_COMPRESSION, sizeof(*attr));
if (attr) {
compression = be32toh(attr->compression);
if (buf_size < be32toh(attr->decompressed_size))
return 0;
}

return cbfs_load_and_decompress(&rdev, 0, region_device_sz(&rdev),
buf, buf_size, compression);
}

size_t cbfs_load(const char *name, void *buf, size_t buf_size)
{
return _cbfs_load(name, buf, buf_size, false);
}

return cbfs_load_and_decompress(&fh.data, 0, region_device_sz(&fh.data),
buf, buf_size, compression_algo);
size_t cbfs_ro_load(const char *name, void *buf, size_t buf_size)
{
return _cbfs_load(name, buf, buf_size, true);
}

int cbfs_prog_stage_load(struct prog *pstage)
Expand Down Expand Up @@ -351,6 +410,9 @@ void cbfs_boot_device_find_mcache(struct cbfs_boot_device *cbd, uint32_t id)
if (CONFIG(NO_CBFS_MCACHE) || ENV_SMM)
return;

if (cbd->mcache_size)
return;

const struct cbmem_entry *entry;
if (cbmem_possibly_online() &&
(entry = cbmem_entry_find(id))) {
Expand All @@ -371,6 +433,26 @@ void cbfs_boot_device_find_mcache(struct cbfs_boot_device *cbd, uint32_t id)
}
}

cb_err_t cbfs_init_boot_device(const struct cbfs_boot_device *cbd,
struct vb2_hash *metadata_hash)
{
/* If we have an mcache, mcache_build() will also check mdata hash. */
if (!CONFIG(NO_CBFS_MCACHE) && !ENV_SMM && cbd->mcache_size > 0)
return cbfs_mcache_build(&cbd->rdev, cbd->mcache,
cbd->mcache_size, metadata_hash);

/* No mcache and no verification means we have nothing special to do. */
if (!CONFIG(CBFS_VERIFICATION) || !metadata_hash)
return CB_SUCCESS;

/* Verification only: use cbfs_walk() without a walker() function to
just run through the CBFS once, will return NOT_FOUND by default. */
cb_err_t err = cbfs_walk(&cbd->rdev, NULL, NULL, metadata_hash, 0);
if (err == CB_CBFS_NOT_FOUND)
err = CB_SUCCESS;
return err;
}

const struct cbfs_boot_device *cbfs_get_boot_device(bool force_ro)
{
static struct cbfs_boot_device ro;
Expand All @@ -388,19 +470,25 @@ const struct cbfs_boot_device *cbfs_get_boot_device(bool force_ro)
return rw;
}

/* In rare cases post-RAM stages may run this before cbmem_initialize(),
so we can't lock in the result of find_mcache() on the first try and
should keep trying every time until an mcache is found. */
cbfs_boot_device_find_mcache(&ro, CBMEM_ID_CBFS_RO_MCACHE);

if (region_device_sz(&ro.rdev))
return &ro;

if (fmap_locate_area_as_rdev("COREBOOT", &ro.rdev))
return NULL;

cbfs_boot_device_find_mcache(&ro, CBMEM_ID_CBFS_RO_MCACHE);

if (ENV_INITIAL_STAGE && !CONFIG(NO_CBFS_MCACHE)) {
cb_err_t err = cbfs_mcache_build(&ro.rdev, ro.mcache,
ro.mcache_size, NULL);
if (err && err != CB_CBFS_CACHE_FULL)
die("Failed to build RO mcache");
die("Cannot locate primary CBFS");

if (ENV_INITIAL_STAGE) {
cb_err_t err = cbfs_init_boot_device(&ro, metadata_hash_get());
if (err == CB_CBFS_HASH_MISMATCH)
die("RO CBFS metadata hash verification failure");
else if (CONFIG(TOCTOU_SAFETY) && err == CB_CBFS_CACHE_FULL)
die("RO mcache overflow breaks TOCTOU safety!\n");
else if (err && err != CB_CBFS_CACHE_FULL)
die("RO CBFS initialization error: %d", err);
}

return &ro;
Expand Down
3 changes: 1 addition & 2 deletions src/lib/coreboot_table.c
View file
Expand Up @@ -456,8 +456,7 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end)
#if CONFIG(USE_OPTION_TABLE)
{
struct cmos_option_table *option_table =
cbfs_boot_map_with_leak("cmos_layout.bin",
CBFS_COMPONENT_CMOS_LAYOUT, NULL);
cbfs_map("cmos_layout.bin", NULL);
if (option_table) {
struct lb_record *rec_dest = lb_new_record(head);
/* Copy the option config table, it's already a
Expand Down
196 changes: 146 additions & 50 deletions src/lib/edid_fill_fb.c
View file
Expand Up @@ -3,75 +3,171 @@
#include <console/console.h>
#include <edid.h>
#include <boot/coreboot_tables.h>
#include <framebuffer_info.h>
#include <string.h>
#include <stdlib.h>
#include <bootsplash.h>
#include <list.h>

static int fb_valid;
static struct lb_framebuffer edid_fb;
struct fb_info {
struct list_node node;
struct lb_framebuffer fb;
};
static struct list_node list;

/*
* Take an edid, and create a framebuffer. Set fb_valid to 1.
* Allocate a new framebuffer info struct on heap.
* Returns NULL on error.
*/
void set_vbe_mode_info_valid(const struct edid *edid, uintptr_t fb_addr)
static struct fb_info *fb_new_framebuffer_info(void)
{
edid_fb.physical_address = fb_addr;
edid_fb.x_resolution = edid->x_resolution;
edid_fb.y_resolution = edid->y_resolution;
edid_fb.bytes_per_line = edid->bytes_per_line;
/* In the case of (e.g.) 24 framebuffer bits per pixel, the convention
* nowadays seems to be to round it up to the nearest reasonable
* boundary, because otherwise the byte-packing is hideous.
* So, for example, in RGB with no alpha, the bytes are still
* packed into 32-bit words, the so-called 32bpp-no-alpha mode.
* Or, in 5:6:5 mode, the bytes are also packed into 32-bit words,
* and in 4:4:4 mode, they are packed into 16-bit words.
* Good call on the hardware guys part.
* It's not clear we're covering all cases here, but
* I'm not sure with grahpics you ever can.
*/
edid_fb.bits_per_pixel = edid->framebuffer_bits_per_pixel;
edid_fb.reserved_mask_pos = 0;
edid_fb.reserved_mask_size = 0;
switch (edid->framebuffer_bits_per_pixel) {
struct fb_info *ret;
ret = malloc(sizeof(struct fb_info));
if (ret)
memset(ret, 0, sizeof(struct fb_info));

return ret;
}

/*
* Fills a provided framebuffer info struct and adds it to the internal list if it's
* valid. Returns NULL on error.
*/
struct fb_info *
fb_add_framebuffer_info_ex(const struct lb_framebuffer *fb)
{
struct fb_info *info;
uint8_t bpp_mask;

/* Validate input */
if (!fb || !fb->x_resolution || !fb->y_resolution || !fb->bytes_per_line ||
!fb->bits_per_pixel) {
printk(BIOS_ERR, "%s: Invalid framebuffer data provided\n", __func__);
return NULL;
}

bpp_mask = fb->blue_mask_size + fb->green_mask_size + fb->red_mask_size +
fb->reserved_mask_size;
if (fb->bits_per_pixel != bpp_mask) {
printk(BIOS_ERR, "%s: BPP=%d and channel bit mask=%d doesn't match."
" This is a driver bug.\n", __func__, fb->bits_per_pixel, bpp_mask);
return NULL;
}

info = fb_new_framebuffer_info();
if (!info)
return NULL;

printk(BIOS_INFO, "framebuffer_info: bytes_per_line: %d, bits_per_pixel: %d\n "
" x_res x y_res: %d x %d, size: %d at 0x%llx\n",
fb->bytes_per_line, fb->bits_per_pixel, fb->x_resolution,
fb->y_resolution, (fb->bytes_per_line * fb->y_resolution),
fb->physical_address);

/* Update */
info->fb = *fb;

list_insert_after(&info->node, &list);

return info;
}

/*
* Allocates a new framebuffer info struct and fills it for 32/24/16bpp framebuffers.
* Intended for drivers that only support reporting the current information or have a single
* modeset invocation.
*
* Complex drivers should use fb_add_framebuffer_info_ex() instead.
*/
struct fb_info *
fb_add_framebuffer_info(uintptr_t fb_addr, uint32_t x_resolution,
uint32_t y_resolution, uint32_t bytes_per_line,
uint8_t bits_per_pixel)
{
struct fb_info *info = NULL;

switch (bits_per_pixel) {
case 32:
case 24:
case 24: {
/* FIXME: 24 BPP might be RGB8 or XRGB8 */
/* packed into 4-byte words */
edid_fb.reserved_mask_pos = 24;
edid_fb.reserved_mask_size = 8;
edid_fb.red_mask_pos = 16;
edid_fb.red_mask_size = 8;
edid_fb.green_mask_pos = 8;
edid_fb.green_mask_size = 8;
edid_fb.blue_mask_pos = 0;
edid_fb.blue_mask_size = 8;

const struct lb_framebuffer fb = {
.physical_address = fb_addr,
.x_resolution = x_resolution,
.y_resolution = y_resolution,
.bytes_per_line = bytes_per_line,
.bits_per_pixel = bits_per_pixel,
.red_mask_pos = 16,
.red_mask_size = 8,
.green_mask_pos = 8,
.green_mask_size = 8,
.blue_mask_pos = 0,
.blue_mask_size = 8,
.reserved_mask_pos = 24,
.reserved_mask_size = 8,
.orientation = LB_FB_ORIENTATION_NORMAL,
};

info = fb_add_framebuffer_info_ex(&fb);
break;
case 16:
}
case 16: {
/* packed into 2-byte words */
edid_fb.red_mask_pos = 11;
edid_fb.red_mask_size = 5;
edid_fb.green_mask_pos = 5;
edid_fb.green_mask_size = 6;
edid_fb.blue_mask_pos = 0;
edid_fb.blue_mask_size = 5;
const struct lb_framebuffer fb = {
.physical_address = fb_addr,
.x_resolution = x_resolution,
.y_resolution = y_resolution,
.bytes_per_line = bytes_per_line,
.bits_per_pixel = 16,
.red_mask_pos = 11,
.red_mask_size = 5,
.green_mask_pos = 5,
.green_mask_size = 6,
.blue_mask_pos = 0,
.blue_mask_size = 5,
.reserved_mask_pos = 0,
.reserved_mask_size = 0,
.orientation = LB_FB_ORIENTATION_NORMAL,
};
info = fb_add_framebuffer_info_ex(&fb);
break;
}
default:
printk(BIOS_SPEW, "%s: unsupported BPP %d\n", __func__,
edid->framebuffer_bits_per_pixel);
return;
printk(BIOS_ERR, "%s: unsupported BPP %d\n", __func__, bits_per_pixel);
}
if (!info)
printk(BIOS_ERR, "%s: failed to add framebuffer info\n", __func__);

fb_valid = 1;
return info;
}

void set_vbe_framebuffer_orientation(enum lb_fb_orientation orientation)
void fb_set_orientation(struct fb_info *info, enum lb_fb_orientation orientation)
{
edid_fb.orientation = orientation;
if (!info)
return;

info->fb.orientation = orientation;
}

int fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
/*
* Take an edid, and create a framebuffer.
*/
struct fb_info *fb_new_framebuffer_info_from_edid(const struct edid *edid,
uintptr_t fb_addr)
{
if (!fb_valid)
return -1;
return fb_add_framebuffer_info(fb_addr, edid->x_resolution, edid->y_resolution,
edid->bytes_per_line, edid->framebuffer_bits_per_pixel);
}

*framebuffer = edid_fb;
int fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
{
struct fb_info *i;

return 0;
list_for_each(i, list, node) {
//TODO: Add support for advertising all framebuffers in this list
*framebuffer = i->fb;
return 0;
}
return -1;
}
33 changes: 27 additions & 6 deletions src/lib/fmap.c
View file
Expand Up @@ -4,6 +4,7 @@
#include <cbmem.h>
#include <console/console.h>
#include <fmap.h>
#include <metadata_hash.h>
#include <stddef.h>
#include <string.h>
#include <symbols.h>
Expand All @@ -27,9 +28,20 @@ uint64_t get_fmap_flash_offset(void)
return FMAP_OFFSET;
}

static int check_signature(const struct fmap *fmap)
static int verify_fmap(const struct fmap *fmap)
{
return memcmp(fmap->signature, FMAP_SIGNATURE, sizeof(fmap->signature));
if (memcmp(fmap->signature, FMAP_SIGNATURE, sizeof(fmap->signature)))
return -1;

static bool done = false;
if (!CONFIG(CBFS_VERIFICATION) || !ENV_INITIAL_STAGE || done)
return 0; /* Only need to check hash in first stage. */

if (metadata_hash_verify_fmap(fmap, FMAP_SIZE) != VB2_SUCCESS)
return -1;

done = true;
return 0;
}

static void report(const struct fmap *fmap)
Expand Down Expand Up @@ -63,10 +75,12 @@ static void setup_preram_cache(struct mem_region_device *cache_mrdev)
if (!(ENV_INITIAL_STAGE)) {
/* NOTE: This assumes that the first stage will make
at least one FMAP access (usually from finding CBFS). */
if (!check_signature(fmap))
if (!verify_fmap(fmap))
goto register_cache;

printk(BIOS_ERR, "ERROR: FMAP cache corrupted?!\n");
if (CONFIG(TOCTOU_SAFETY))
die("TOCTOU safety relies on FMAP cache");
}

/* In case we fail below, make sure the cache is invalid. */
Expand All @@ -80,7 +94,7 @@ static void setup_preram_cache(struct mem_region_device *cache_mrdev)
/* memlayout statically guarantees that the FMAP_CACHE is big enough. */
if (rdev_readat(boot_rdev, fmap, FMAP_OFFSET, FMAP_SIZE) != FMAP_SIZE)
return;
if (check_signature(fmap))
if (verify_fmap(fmap))
return;
report(fmap);

Expand Down Expand Up @@ -111,8 +125,9 @@ static int find_fmap_directory(struct region_device *fmrd)
if (fmap == NULL)
return -1;

if (check_signature(fmap)) {
printk(BIOS_DEBUG, "No FMAP found at %zx offset.\n", offset);
if (verify_fmap(fmap)) {
printk(BIOS_ERR, "FMAP missing or corrupted at offset 0x%zx!\n",
offset);
rdev_munmap(boot, fmap);
return -1;
}
Expand Down Expand Up @@ -149,6 +164,9 @@ int fmap_locate_area(const char *name, struct region *ar)
struct region_device fmrd;
size_t offset;

if (name == NULL || ar == NULL)
return -1;

if (find_fmap_directory(&fmrd))
return -1;

Expand Down Expand Up @@ -191,6 +209,9 @@ int fmap_find_region_name(const struct region * const ar,
struct region_device fmrd;
size_t offset;

if (name == NULL || ar == NULL)
return -1;

if (find_fmap_directory(&fmrd))
return -1;

Expand Down
16 changes: 11 additions & 5 deletions src/lib/fw_config.c
View file
Expand Up @@ -24,12 +24,11 @@ uint64_t fw_config_get(void)

/* Look in CBFS to allow override of value. */
if (CONFIG(FW_CONFIG_SOURCE_CBFS)) {
if (cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/fw_config",
&fw_config_value, sizeof(fw_config_value),
CBFS_TYPE_RAW) != sizeof(fw_config_value)) {
if (cbfs_load(CONFIG_CBFS_PREFIX "/fw_config", &fw_config_value,
sizeof(fw_config_value)) != sizeof(fw_config_value)) {
printk(BIOS_WARNING, "%s: Could not get fw_config from CBFS\n",
__func__);
fw_config_value = 0;
fw_config_value = UNDEFINED_FW_CONFIG;
} else {
printk(BIOS_INFO, "FW_CONFIG value from CBFS is 0x%" PRIx64 "\n",
fw_config_value);
Expand All @@ -39,8 +38,10 @@ uint64_t fw_config_get(void)

/* Read the value from EC CBI. */
if (CONFIG(FW_CONFIG_SOURCE_CHROMEEC_CBI)) {
if (google_chromeec_cbi_get_fw_config(&fw_config_value))
if (google_chromeec_cbi_get_fw_config(&fw_config_value)) {
printk(BIOS_WARNING, "%s: Could not get fw_config from EC\n", __func__);
fw_config_value = UNDEFINED_FW_CONFIG;
}
}

printk(BIOS_INFO, "FW_CONFIG value is 0x%" PRIx64 "\n", fw_config_value);
Expand All @@ -64,6 +65,11 @@ bool fw_config_probe(const struct fw_config *match)
return false;
}

bool fw_config_is_provisioned(void)
{
return fw_config_get() != UNDEFINED_FW_CONFIG;
}

#if ENV_RAMSTAGE

/*
Expand Down
27 changes: 27 additions & 0 deletions src/lib/metadata_hash.c
View file
@@ -0,0 +1,27 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* This file is part of the coreboot project. */

#include <assert.h>
#include <cbmem.h>
#include <metadata_hash.h>
#include <symbols.h>

__attribute__((used, section(".metadata_hash_anchor")))
static struct metadata_hash_anchor metadata_hash_anchor = {
/* This is the only place in all of coreboot where we actually need to use this. */
.magic = DO_NOT_USE_METADATA_HASH_ANCHOR_MAGIC_DO_NOT_USE,
.cbfs_hash = { .algo = CONFIG_CBFS_HASH_ALGO }
};

struct vb2_hash *metadata_hash_get(void)
{
return &metadata_hash_anchor.cbfs_hash;
}

vb2_error_t metadata_hash_verify_fmap(const void *fmap_buffer, size_t fmap_size)
{
struct vb2_hash hash = { .algo = metadata_hash_anchor.cbfs_hash.algo };
memcpy(hash.raw, metadata_hash_anchor_fmap_hash(&metadata_hash_anchor),
vb2_digest_size(hash.algo));
return vb2_hash_verify(fmap_buffer, fmap_size, &hash);
}
4 changes: 1 addition & 3 deletions src/lib/program.ld
View file
Expand Up @@ -15,9 +15,7 @@
_text = .;
*(.text._start);
*(.text.stage_entry);
#if !ENV_X86 && (ENV_DECOMPRESSOR || ENV_BOOTBLOCK && !CONFIG(COMPRESS_BOOTBLOCK))
KEEP(*(.id));
#endif
KEEP(*(.metadata_hash_anchor));
*(.text);
*(.text.*);

Expand Down
12 changes: 6 additions & 6 deletions src/lib/reg_script.c
View file
Expand Up @@ -150,11 +150,11 @@ static uint32_t reg_script_read_mmio(struct reg_script_context *ctx)

switch (step->size) {
case REG_SCRIPT_SIZE_8:
return read8((u8 *)step->reg);
return read8((u8 *)(uintptr_t)step->reg);
case REG_SCRIPT_SIZE_16:
return read16((u16 *)step->reg);
return read16((u16 *)(uintptr_t)step->reg);
case REG_SCRIPT_SIZE_32:
return read32((u32 *)step->reg);
return read32((u32 *)(uintptr_t)step->reg);
}
return 0;
}
Expand All @@ -165,13 +165,13 @@ static void reg_script_write_mmio(struct reg_script_context *ctx)

switch (step->size) {
case REG_SCRIPT_SIZE_8:
write8((u8 *)step->reg, step->value);
write8((u8 *)(uintptr_t)step->reg, step->value);
break;
case REG_SCRIPT_SIZE_16:
write16((u16 *)step->reg, step->value);
write16((u16 *)(uintptr_t)step->reg, step->value);
break;
case REG_SCRIPT_SIZE_32:
write32((u32 *)step->reg, step->value);
write32((u32 *)(uintptr_t)step->reg, step->value);
break;
}
}
Expand Down
6 changes: 3 additions & 3 deletions src/lib/spd_bin.c
View file
Expand Up @@ -227,12 +227,11 @@ int read_ddr3_spd_from_cbfs(u8 *buf, int idx)
const int SPD_CRC_HI = 127;
const int SPD_CRC_LO = 126;

const char *spd_file;
char *spd_file;
size_t spd_file_len = 0;
size_t min_len = (idx + 1) * CONFIG_DIMM_SPD_SIZE;

spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
&spd_file_len);
spd_file = cbfs_map("spd.bin", &spd_file_len);
if (!spd_file)
printk(BIOS_EMERG, "file [spd.bin] not found in CBFS");
if (spd_file_len < min_len)
Expand All @@ -242,6 +241,7 @@ int read_ddr3_spd_from_cbfs(u8 *buf, int idx)

memcpy(buf, spd_file + (idx * CONFIG_DIMM_SPD_SIZE),
CONFIG_DIMM_SPD_SIZE);
cbfs_unmap(spd_file);

u16 crc = spd_ddr3_calc_crc(buf, CONFIG_DIMM_SPD_SIZE);

Expand Down
21 changes: 0 additions & 21 deletions src/lib/trace.c
View file

This file was deleted.

4 changes: 0 additions & 4 deletions src/mainboard/51nb/x210/devicetree.cb
View file
Expand Up @@ -32,7 +32,6 @@ chip soc/intel/skylake
register "dptf_enable" = "0"

# FSP Configuration
register "ProbelessTrace" = "0"
register "SataSalpSupport" = "1"
register "SataMode" = "0"

Expand All @@ -47,7 +46,6 @@ chip soc/intel/skylake
register "IoBufferOwnership" = "0"
register "SsicPortEnable" = "0"
register "ScsEmmcHs400Enabled" = "0"
register "PttSwitch" = "0"
register "SkipExtGfxScan" = "1"
register "HeciEnabled" = "1"
register "SaGv" = "SaGv_Enabled"
Expand All @@ -58,8 +56,6 @@ chip soc/intel/skylake

register "serirq_mode" = "SERIRQ_CONTINUOUS"

register "PmConfigPciClockRun" = "1"

# Enable Root Ports 3, 4 and 9
register "PcieRpEnable[2]" = "1" # Ethernet controller
register "PcieRpClkReqSupport[2]" = "1"
Expand Down
31 changes: 31 additions & 0 deletions src/mainboard/amd/majolica/Kconfig
View file
@@ -0,0 +1,31 @@
# SPDX-License-Identifier: GPL-2.0-only

if BOARD_AMD_MAJOLICA

config BOARD_SPECIFIC_OPTIONS
def_bool y
select SOC_AMD_CEZANNE

config FMDFILE
string
default "src/mainboard/amd/majolica/board.fmd"

config MAINBOARD_DIR
default "amd/majolica"

config MAINBOARD_PART_NUMBER
default "MAJOLICA"

config MAJOLICA_HAVE_MCHP_FW
bool "Have Microchip EC firmware?"
default n

config MAJOLICA_MCHP_FW_FILE
string
depends on MAJOLICA_HAVE_MCHP_FW
default "3rdparty/blobs/mainboard/amd/majolica/EC_majolica.bin"
help
The EC firmware blob is usually the first 128kByte of the stock
firmware image.

endif # BOARD_AMD_MAJOLICA
2 changes: 2 additions & 0 deletions src/mainboard/amd/majolica/Kconfig.name
View file
@@ -0,0 +1,2 @@
config BOARD_AMD_MAJOLICA
bool "Majolica"
18 changes: 18 additions & 0 deletions src/mainboard/amd/majolica/Makefile.inc
View file
@@ -0,0 +1,18 @@
# SPDX-License-Identifier: GPL-2.0-only

PHONY+=add_mchp_fw
INTERMEDIATE+=add_mchp_fw

ifeq ($(CONFIG_MAJOLICA_HAVE_MCHP_FW),y)
add_mchp_fw: $(obj)/coreboot.pre
$(CBFSTOOL) $(obj)/coreboot.pre write -r EC -f $(CONFIG_MAJOLICA_MCHP_FW_FILE) --fill-upward
else
files_added:: warn_no_mchp
endif # CONFIG_MAJOLICA_HAVE_MCHP_FW

PHONY+=warn_no_mchp
warn_no_mchp:
printf "\n\t** WARNING **\n"
printf "coreboot has been built without an the Microchip EC FW.\n"
printf "Do not flash this image. Your Majolica's power button\n"
printf "will not respond when you press it.\n\n"
8 changes: 8 additions & 0 deletions src/mainboard/amd/majolica/board.fmd
View file
@@ -0,0 +1,8 @@
FLASH@0xFF000000 16M {
BIOS {
EC 128K
RW_MRC_CACHE 64K
FMAP 4K
COREBOOT(CBFS)
}
}
1 change: 1 addition & 0 deletions src/mainboard/amd/majolica/board_info.txt
View file
@@ -0,0 +1 @@
Category: eval
8 changes: 8 additions & 0 deletions src/mainboard/amd/majolica/devicetree.cb
View file
@@ -0,0 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-only

chip soc/amd/cezanne

device domain 0 on
end

end
8 changes: 4 additions & 4 deletions src/mainboard/amd/mandolin/Kconfig
View file
Expand Up @@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS
select AZALIA_PLUGIN_SUPPORT
select HAVE_ACPI_RESUME
select DRIVERS_UART_ACPI
select PICASSO_CONSOLE_UART if !AMD_LPC_DEBUG_CARD
select AMD_SOC_CONSOLE_UART if !AMD_LPC_DEBUG_CARD

config FMDFILE
string
Expand All @@ -21,12 +21,12 @@ config FMDFILE
config AMD_LPC_DEBUG_CARD
bool "Enable LPC-Serial debug card on the debug header"
default n
select PICASSO_LPC_IOMUX
select MANDOLIN_LPC
select SUPERIO_SMSC_SIO1036
help
AMD's debug card contains an SMSC SIO1036 device which provides an
I/O-mapped UART in the system. This is mutually exclusive with
PICASSO_CONSOLE_UART which selects the SoC's integrated memory-mapped
AMD_SOC_CONSOLE_UART which selects the SoC's integrated memory-mapped
UART for coreboot console output.

choice
Expand Down Expand Up @@ -111,7 +111,7 @@ config MANDOLIN_IOMUX_USE_EMMC
endchoice
endif # !AMD_LPC_DEBUG_CARD

config PICASSO_LPC_IOMUX
config MANDOLIN_LPC
bool
default y if MANDOLIN_IOMUX_USE_LPC
help
Expand Down
3 changes: 1 addition & 2 deletions src/mainboard/amd/mandolin/Makefile.inc
View file
Expand Up @@ -6,7 +6,7 @@ bootblock-y += variants/$(VARIANT_DIR)/early_gpio.c
ramstage-y += variants/$(VARIANT_DIR)/gpio.c
ramstage-y += variants/$(VARIANT_DIR)/port_descriptors.c

ifneq ($(CONFIG_PICASSO_LPC_IOMUX),y)
ifneq ($(CONFIG_MANDOLIN_LPC),y)
ramstage-y += emmc_gpio.c
endif

Expand All @@ -21,7 +21,6 @@ INTERMEDIATE+=add_mchp_fw

ifeq ($(CONFIG_MANDOLIN_HAVE_MCHP_FW),y)

MANDOLIN_MICROCHIP_FW_OFFSET=0
add_mchp_fw: $(obj)/coreboot.pre
$(CBFSTOOL) $(obj)/coreboot.pre write -r EC -f $(CONFIG_MANDOLIN_MCHP_FW_FILE) --fill-upward

Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/amd/mandolin/emmc_gpio.c
View file
Expand Up @@ -6,7 +6,7 @@
/* eMMC controller driving either an SD card or eMMC device. */
static const struct soc_amd_gpio emmc_gpios[] = {
PAD_NF(GPIO_21, EMMC_CMD, PULL_UP),
PAD_NF(GPIO_22, EMMC_PRW_CTRL, PULL_UP),
PAD_NF(GPIO_22, EMMC_PWR_CTRL, PULL_UP),
PAD_NF(GPIO_68, EMMC_CD, PULL_UP),
PAD_NF(GPIO_70, EMMC_CLK, PULL_NONE),
PAD_NF(GPIO_104, EMMC_DATA0, PULL_UP),
Expand Down
4 changes: 2 additions & 2 deletions src/mainboard/amd/mandolin/mainboard.c
View file
Expand Up @@ -111,13 +111,13 @@ static void mainboard_init(void *chip_info)
{
struct soc_amd_picasso_config *cfg = config_of_soc();

if (!CONFIG(PICASSO_LPC_IOMUX))
if (!CONFIG(MANDOLIN_LPC))
cfg->emmc_config.timing = SD_EMMC_EMMC_HS400;

mainboard_program_gpios();

/* Re-muxing LPCCLK0 can hang the system if LPC is in use. */
if (CONFIG(PICASSO_LPC_IOMUX))
if (CONFIG(MANDOLIN_LPC))
printk(BIOS_INFO, "eMMC not available due to LPC requirement\n");
else
mainboard_program_emmc_gpios();
Expand Down
6 changes: 3 additions & 3 deletions src/mainboard/amd/mandolin/variants/cereme/board.fmd
View file
@@ -1,8 +1,8 @@
FLASH@0xFF000000 16M {
BIOS {
EC 0x20000
RW_MRC_CACHE 0x10000
FMAP 0x1000
EC 128K
RW_MRC_CACHE 64K
FMAP 4K
COREBOOT(CBFS)
}
}
4 changes: 2 additions & 2 deletions src/mainboard/amd/mandolin/variants/cereme/devicetree.cb
View file
Expand Up @@ -160,8 +160,8 @@ chip soc/amd/picasso
device pci 0.1 off end # integrated Ethernet MAC
device pci 0.2 off end # integrated Ethernet MAC
end
device pci 14.0 on end # SMBus
device pci 14.3 on # D14F3 bridge
device pci 14.0 on end # SMBus
device pci 14.3 on # D14F3 bridge
chip superio/smsc/sio1036 # optional debug card
end
end
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/amd/mandolin/variants/cereme/early_gpio.c
View file
Expand Up @@ -13,7 +13,7 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {
/* not USB_OC2_L */
PAD_GPI(GPIO_18, PULL_UP),
/* SDIO eMMC power control */
PAD_NF(GPIO_22, EMMC_PRW_CTRL, PULL_NONE),
PAD_NF(GPIO_22, EMMC_PWR_CTRL, PULL_NONE),
/* PCIe Reset 0 */
PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
/* PCIe Reset 1 */
Expand Down
4 changes: 2 additions & 2 deletions src/mainboard/amd/mandolin/variants/mandolin/board.fmd
View file
@@ -1,8 +1,8 @@
FLASH@0xFF800000 8M {
BIOS {
EC 0x20000
EC 128K
RW_MRC_CACHE 64K
FMAP 0x1000
FMAP 4K
COREBOOT(CBFS)
}
}
6 changes: 3 additions & 3 deletions src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb
View file
Expand Up @@ -148,7 +148,7 @@ chip soc/amd/picasso
device pci 8.1 on # Bridge to Bus A
device pci 0.0 on end # Internal GPU
device pci 0.1 on end # Display HDA
device pci 0.2 on end # Crypto Coprocesor
device pci 0.2 on end # Crypto Coprocessor
device pci 0.3 on end # USB 3.1
device pci 0.4 on end # USB 3.1
device pci 0.5 on end # Audio
Expand All @@ -160,8 +160,8 @@ chip soc/amd/picasso
device pci 0.1 off end # integrated Ethernet MAC
device pci 0.2 off end # integrated Ethernet MAC
end
device pci 14.0 on end # SM
device pci 14.3 on # - D14F3 bridge
device pci 14.0 on end # SMBus
device pci 14.3 on # D14F3 bridge
chip superio/smsc/sio1036 # optional debug card
end
end
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/amd/mandolin/variants/mandolin/early_gpio.c
View file
Expand Up @@ -17,7 +17,7 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {
/* not USB_OC2_L */
PAD_GPI(GPIO_18, PULL_UP),
/* SDIO eMMC power control */
PAD_NF(GPIO_22, EMMC_PRW_CTRL, PULL_NONE),
PAD_NF(GPIO_22, EMMC_PWR_CTRL, PULL_NONE),
/* PCIe SSD power enable */
PAD_GPO(GPIO_23, HIGH),
/* PCIe Reset to DP0, DP1, J2105, TP, FP */
Expand Down
3 changes: 1 addition & 2 deletions src/mainboard/apple/macbookair4_2/early_init.c
View file
Expand Up @@ -26,8 +26,7 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only)
{
void *spd_file;
size_t spd_file_len = 0;
spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
&spd_file_len);
spd_file = cbfs_map("spd.bin", &spd_file_len);
if (spd_file && spd_file_len >= 1024) {
int i;
for (i = 0; i < 4; i++)
Expand Down
1 change: 1 addition & 0 deletions src/mainboard/asus/p5gc-mx/Kconfig
View file
Expand Up @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS
select BOARD_ROMSIZE_KB_512
select MAINBOARD_HAS_NATIVE_VGA_INIT
select INTEL_GMA_HAVE_VBT
select NO_CBFS_MCACHE

config MAINBOARD_DIR
string
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/clevo/cml-u/Kconfig
View file
Expand Up @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_HAS_TPM2
select NO_UART_ON_SUPERIO
select SOC_INTEL_COMETLAKE_1
select SOC_INTEL_COMMON_BLOCK_HDA
select SOC_INTEL_COMMON_BLOCK_HDA_VERB
select SPD_READ_BY_WORD
select SYSTEM_TYPE_LAPTOP
Expand Down
4 changes: 2 additions & 2 deletions src/mainboard/clevo/cml-u/bootblock.c
View file
Expand Up @@ -2,9 +2,9 @@

#include <bootblock_common.h>
#include <gpio.h>
#include <mainboard/gpio.h>
#include <variant/gpio.h>

void bootblock_mainboard_init(void)
{
mainboard_configure_early_gpios();
variant_configure_early_gpios();
}
9 changes: 9 additions & 0 deletions src/mainboard/clevo/cml-u/include/variant/gpio.h
View file
@@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H

void variant_configure_early_gpios(void);
void variant_configure_gpios(void);

#endif
4 changes: 2 additions & 2 deletions src/mainboard/clevo/cml-u/ramstage.c
View file
@@ -1,11 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <device/device.h>
#include <mainboard/gpio.h>
#include <variant/gpio.h>

static void init_mainboard(void *chip_info)
{
mainboard_configure_gpios();
variant_configure_gpios();
}

struct chip_operations mainboard_ops = {
Expand Down
117 changes: 57 additions & 60 deletions src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
View file
Expand Up @@ -64,16 +64,16 @@ chip soc/intel/cannonlake

device domain 0 on
subsystemid 0x1558 0x1401 inherit
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on # SA Thermal device
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 on # SA Thermal device
register "Device4Enable" = "1"
end
device pci 12.0 on end # Thermal Subsystem
device pci 12.5 off end # UFS SCS
device pci 12.6 off end # GSPI #2
device pci 13.0 off end # Integrated Sensor Hub
device pci 14.0 on # USB xHCI
device pci 12.0 on end # Thermal Subsystem
device pci 12.5 off end # UFS SCS
device pci 12.6 off end # GSPI #2
device pci 13.0 off end # Integrated Sensor Hub
device pci 14.0 on # USB xHCI
# USB2
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 2
Expand All @@ -85,15 +85,15 @@ chip soc/intel/cannonlake
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 2
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 3
end
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.3 on
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.3 on # CNVi wifi
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
device generic 0 on end
end
end # CNVi wifi
device pci 14.5 off end # SDCard
device pci 15.0 on # I2C #0
end
device pci 14.5 off end # SDCard
device pci 15.0 on # I2C #0
chip drivers/i2c/hid
register "generic.hid" = ""ELAN040D""
register "generic.desc" = ""ELAN Touchpad""
Expand All @@ -103,17 +103,16 @@ chip soc/intel/cannonlake
device i2c 15 on end
end
end
device pci 15.1 off end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
device pci 16.0 off end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on # SATA
register "SataMode" = "Sata_AHCI"
device pci 15.1 off end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 off end # I2C #3
device pci 16.0 off end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT Redirection
device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on # SATA
register "SataSalpSupport" = "1"
# Port 2 (J_SSD2)
register "SataPortsEnable[1]" = "1"
Expand All @@ -122,26 +121,26 @@ chip soc/intel/cannonlake
register "SataPortsEnable[2]" = "1"
register "SataPortsDevSlp[2]" = "1"
end
device pci 19.0 off end # I2C #4
device pci 19.1 off end # I2C #5
device pci 19.2 on end # UART #2
device pci 1a.0 off end # eMMC
device pci 1c.0 off end # PCI Express Port 1
device pci 1c.1 off end # PCI Express Port 2
device pci 1c.2 off end # PCI Express Port 3
device pci 1c.3 off end # PCI Express Port 4
device pci 1c.4 off end # PCI Express Port 5
device pci 1c.5 on # PCI Express Port 6
device pci 19.0 off end # I2C #4
device pci 19.1 off end # I2C #5
device pci 19.2 on end # UART #2
device pci 1a.0 off end # eMMC
device pci 1c.0 off end # PCI Express Port 1
device pci 1c.1 off end # PCI Express Port 2
device pci 1c.2 off end # PCI Express Port 3
device pci 1c.3 off end # PCI Express Port 4
device pci 1c.4 off end # PCI Express Port 5
device pci 1c.5 on # PCI Express Port 6
device pci 00.0 on end # x1 Card reader
register "PcieRpEnable[5]" = "1"
register "PcieRpLtrEnable[5]" = "1"
register "PcieClkSrcUsage[3]" = "5"
register "PcieClkSrcClkReq[3]" = "3"
end
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 on # PCI Express Port 8
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 on # PCI Express Port 8
chip drivers/wifi/generic
device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1)
device pci 00.0 on end
end
register "PcieRpEnable[7]" = "1"
register "PcieRpLtrEnable[7]" = "1"
Expand All @@ -150,55 +149,53 @@ chip soc/intel/cannonlake
register "PcieRpSlotImplemented[7]" = "1"
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X"
end
device pci 1d.0 on # PCI Express Port 9
device pci 00.0 on end # x4 M.2/M 2280 (J_SSD2)
device pci 1d.0 on # PCI Express Port 9
register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[4]" = "8"
register "PcieClkSrcClkReq[4]" = "4"
register "PcieRpSlotImplemented[8]" = "1"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X"
end
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
device pci 1d.4 on # PCI Express Port 13
device pci 00.0 on end # x4 M.2/M 2280 (J_SSD1)
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
device pci 1d.4 on # PCI Express Port 13
register "PcieRpEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "1"
register "PcieClkSrcUsage[5]" = "12"
register "PcieClkSrcClkReq[5]" = "5"
register "PcieRpSlotImplemented[12]" = "1"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X"
end
device pci 1d.5 off end # PCI Express Port 14
device pci 1d.6 off end # PCI Express Port 15
device pci 1d.7 off end # PCI Express Port 16
device pci 1e.0 off end # UART #0
device pci 1e.1 off end # UART #1
device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1
device pci 1f.0 on # LPC Interface
device pci 1d.5 off end # PCI Express Port 14
device pci 1d.6 off end # PCI Express Port 15
device pci 1d.7 off end # PCI Express Port 16
device pci 1e.0 off end # UART #0
device pci 1e.1 off end # UART #1
device pci 1e.2 off end # GSPI #0
device pci 1e.3 off end # GSPI #1
device pci 1f.0 on # LPC Interface
# LPC configuration from lspci -s 1f.0 -xxx
# Address 0x84: Decode 0x80 - 0x8F (Port 80)
register "gen1_dec" = "0x000c0081"
# Address 0x88: Decode 0x68 - 0x6F (PMC)
register "gen2_dec" = "0x00040069"
# Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command)
register "gen3_dec" = "0x00fc0E01"
register "gen3_dec" = "0x00fc0e01"
# Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug)
register "gen4_dec" = "0x00fc0F01"
register "gen4_dec" = "0x00fc0f01"
chip drivers/pc80/tpm # TPM
device pnp 0c31.0 on end
end
end
device pci 1f.1 off end # P2SB
device pci 1f.2 off end # Power Management Controller
device pci 1f.3 on # Intel HDA
device pci 1f.1 hidden end # P2SB
device pci 1f.2 hidden end # Power Management Controller
device pci 1f.3 on # Intel HDA
register "PchHdaAudioLinkHda" = "1"
end
device pci 1f.4 on end # SMBus
device pci 1f.5 on end # PCH SPI
device pci 1f.6 off end # GbE
device pci 1f.4 on end # SMBus
device pci 1f.5 on end # PCH SPI
device pci 1f.6 off end # GbE
end
end
4 changes: 2 additions & 2 deletions src/mainboard/clevo/cml-u/variants/l140cu/gpio.c
View file
@@ -1,8 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <mainboard/gpio.h>
#include <soc/gpe.h>
#include <soc/gpio.h>
#include <variant/gpio.h>

/* Name format: <pad name> / <net/pin name in schematics> */
static const struct pad_config gpio_table[] = {
Expand Down Expand Up @@ -237,7 +237,7 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_H23, UP_20K),
};

void mainboard_configure_gpios(void)
void variant_configure_gpios(void)
{
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}
4 changes: 2 additions & 2 deletions src/mainboard/clevo/cml-u/variants/l140cu/gpio_early.c
View file
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <mainboard/gpio.h>
#include <soc/gpio.h>
#include <variant/gpio.h>

/* Name format: <pad name> / <net/pin name in schematics> */
static const struct pad_config early_gpio_table[] = {
Expand All @@ -11,7 +11,7 @@ static const struct pad_config early_gpio_table[] = {
PAD_NC(GPP_C23, UP_20K),
};

void mainboard_configure_early_gpios(void)
void variant_configure_early_gpios(void)
{
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}
4 changes: 2 additions & 2 deletions src/mainboard/clevo/kbl-u/bootblock.c
View file
@@ -1,9 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <bootblock_common.h>
#include <mainboard/gpio.h>
#include <variant/gpio.h>

void bootblock_mainboard_early_init(void)
{
mainboard_configure_gpios();
variant_configure_early_gpios();
}
8 changes: 0 additions & 8 deletions src/mainboard/clevo/kbl-u/include/mainboard/gpio.h
View file

This file was deleted.

9 changes: 9 additions & 0 deletions src/mainboard/clevo/kbl-u/include/variant/gpio.h
View file
@@ -0,0 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H

void variant_configure_early_gpios(void);
void variant_configure_gpios(void);

#endif
4 changes: 2 additions & 2 deletions src/mainboard/clevo/kbl-u/ramstage.c
View file
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <device/device.h>
#include <mainboard/gpio.h>
#include <variant/gpio.h>

/*
* TODO:
Expand All @@ -14,7 +14,7 @@

static void init_mainboard(void *chip_info)
{
mainboard_configure_gpios();
variant_configure_gpios();
}

struct chip_operations mainboard_ops = {
Expand Down
1 change: 0 additions & 1 deletion src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb
View file
Expand Up @@ -80,7 +80,6 @@ chip soc/intel/skylake
device pci 16.3 off end # Management Engine KT Redirection
device pci 16.4 off end # Management Engine Interface 3
device pci 17.0 on # SATA
register "SataMode" = "KBLFSP_SATA_MODE_AHCI"
register "SataSalpSupport" = "0"
# Ports
register "SataPortsEnable[0]" = "1"
Expand Down
4 changes: 2 additions & 2 deletions src/mainboard/clevo/kbl-u/variants/n13xwu/gpio.c
View file
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <mainboard/gpio.h>
#include <soc/gpio.h>
#include <variant/gpio.h>

static const struct pad_config gpio_table[] = {
// RCIN#
Expand Down Expand Up @@ -497,7 +497,7 @@ static const struct pad_config gpio_table[] = {
_PAD_CFG_STRUCT(GPP_G7, 0x44000702, 0x0)
};

void mainboard_configure_gpios(void)
void variant_configure_gpios(void)
{
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
}
4 changes: 2 additions & 2 deletions src/mainboard/clevo/kbl-u/variants/n13xwu/gpio_early.c
View file
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <mainboard/gpio.h>
#include <soc/gpio.h>
#include <variant/gpio.h>

static const struct pad_config early_gpio_table[] = {
// UART2_RXD
Expand All @@ -11,7 +11,7 @@ static const struct pad_config early_gpio_table[] = {
_PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0)
};

void mainboard_configure_gpios(void)
void variant_configure_early_gpios(void)
{
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}
3 changes: 1 addition & 2 deletions src/mainboard/dell/optiplex_9010/sch5545_ec.c
View file
Expand Up @@ -442,8 +442,7 @@ void sch5545_update_ec_firmware(uint16_t ec_version)
uint32_t *ec_fw_file;
size_t ec_fw_file_size;

ec_fw_file = cbfs_boot_map_with_leak("sch5545_ecfw.bin", CBFS_TYPE_RAW,
&ec_fw_file_size);
ec_fw_file = cbfs_map("sch5545_ecfw.bin", &ec_fw_file_size);

if (!ec_fw_file || ec_fw_file_size != 0x1750) {
printk(BIOS_ERR, "EC firmware file not found in CBFS!\n");
Expand Down
3 changes: 2 additions & 1 deletion src/mainboard/emulation/qemu-aarch64/memlayout.ld
View file
Expand Up @@ -19,7 +19,8 @@ SECTIONS
REGION(secram, 0xe000000, 0x1000000, 4096)
DRAM_START(0x40000000)
BOOTBLOCK(0x60010000, 64K)
STACK(0x60020000, 62K)
STACK(0x60020000, 54K)
CBFS_MCACHE(0x6002D800, 8K)
FMAP_CACHE(0x6002F800, 2K)
TIMESTAMP(0x60030000, 1K)
ROMSTAGE(0x60031000, 128K)
Expand Down
10 changes: 2 additions & 8 deletions src/mainboard/emulation/qemu-armv7/mainboard.c
View file
Expand Up @@ -4,15 +4,14 @@
#include <device/device.h>
#include <cbmem.h>
#include <halt.h>
#include <edid.h>
#include <device/mmio.h>
#include <ramdetect.h>
#include <symbols.h>
#include <framebuffer_info.h>

static void init_gfx(void)
{
uint32_t *pl111;
struct edid edid;
/* width is at most 4096 */
/* height is at most 1024 */
int width = 800, height = 600;
Expand All @@ -28,12 +27,7 @@ static void init_gfx(void)
write32(pl111 + 10, 0xff);
write32(pl111 + 6, (5 << 1) | 0x801);

edid.framebuffer_bits_per_pixel = 32;
edid.bytes_per_line = width * 4;
edid.x_resolution = width;
edid.y_resolution = height;

set_vbe_mode_info_valid(&edid, framebuffer);
fb_add_framebuffer_info(framebuffer, width, height, 4 * width, 32);
}

static void mainboard_enable(struct device *dev)
Expand Down
1 change: 1 addition & 0 deletions src/mainboard/emulation/qemu-armv7/memlayout.ld
View file
Expand Up @@ -35,6 +35,7 @@ SECTIONS
BOOTBLOCK(0x60010000, 128K)
FMAP_CACHE(0x60030000, 4K)
TIMESTAMP(0x60031000, 1K)
CBFS_MCACHE(0x60031400, 7K)
/* TODO: Implement MMU support and move TTB to a better location. */
TTB(0x60034000, 16K)
ROMSTAGE(0x60038000, 128K)
Expand Down
1 change: 1 addition & 0 deletions src/mainboard/emulation/qemu-i440fx/Kconfig
View file
Expand Up @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_HAS_NATIVE_VGA_INIT
select MAINBOARD_FORCE_NATIVE_VGA_INIT
select HAVE_ASAN_IN_ROMSTAGE
select NO_SMM

config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY
Expand Down
16 changes: 15 additions & 1 deletion src/mainboard/emulation/qemu-i440fx/northbridge.c
View file
Expand Up @@ -3,6 +3,7 @@
#include <console/console.h>
#include <cpu/cpu.h>
#include <cpu/x86/lapic_def.h>
#include <cpu/x86/mp.h>
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
Expand Down Expand Up @@ -244,9 +245,22 @@ static struct device_operations pci_domain_ops = {
#endif
};

static const struct mp_ops mp_ops_no_smm = {
.get_cpu_count = fw_cfg_max_cpus,
};

void mp_init_cpus(struct bus *cpu_bus)
{
if (mp_init_with_smm(cpu_bus, &mp_ops_no_smm))
printk(BIOS_ERR, "MP initialization failure.\n");
}

static void cpu_bus_init(struct device *dev)
{
initialize_cpus(dev->link_list);
if (CONFIG(PARALLEL_MP))
mp_cpu_bus_init(dev);
else
initialize_cpus(dev->link_list);
}

static void cpu_bus_scan(struct device *bus)
Expand Down
1 change: 1 addition & 0 deletions src/mainboard/emulation/qemu-power8/memlayout.ld
View file
Expand Up @@ -13,5 +13,6 @@ SECTIONS
STACK(0x40000, 0x3ff00)
PRERAM_CBMEM_CONSOLE(0x80000, 8K)
FMAP_CACHE(0x82000, 2K)
CBFS_MCACHE(0x82800, 8K)
RAMSTAGE(0x100000, 16M)
}
1 change: 1 addition & 0 deletions src/mainboard/emulation/qemu-riscv/memlayout.ld
View file
Expand Up @@ -25,6 +25,7 @@ SECTIONS
#endif
PRERAM_CBMEM_CONSOLE(STAGES_START + 128K, 8K)
FMAP_CACHE(STAGES_START + 136K, 2K)
CBFS_MCACHE(STAGES_START + 138K, 8K)
RAMSTAGE(STAGES_START + 200K, 16M)
STACK(STAGES_START + 200K + 16M, 4K)
}
3 changes: 2 additions & 1 deletion src/mainboard/emulation/spike-riscv/memlayout.ld
View file
Expand Up @@ -12,7 +12,8 @@ SECTIONS
BOOTBLOCK(START, 64K)
STACK(START + 8M, 4K)
FMAP_CACHE(START + 8M + 4K, 2K)
/* hole at (START + 8M + 6K, 58K) */
CBFS_MCACHE(START + 8M + 6K, 8K)
/* hole at (START + 8M + 14K, 50K) */
ROMSTAGE(START + 8M + 64K, 128K)
PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K)
RAMSTAGE(START + 8M + 200K, 256K)
Expand Down
2 changes: 1 addition & 1 deletion src/mainboard/facebook/fbg1701/board_mboot.h
View file
Expand Up @@ -6,7 +6,7 @@
const mboot_measure_item_t mb_log_list[] = {
{ "config", CBFS_TYPE_RAW, MBOOT_PCR_INDEX_0, EV_NO_ACTION, NULL },
{ "revision", CBFS_TYPE_RAW, MBOOT_PCR_INDEX_0, EV_NO_ACTION, NULL },
{ "cmos_layout.bin", CBFS_COMPONENT_CMOS_LAYOUT, MBOOT_PCR_INDEX_0,
{ "cmos_layout.bin", CBFS_TYPE_CMOS_LAYOUT, MBOOT_PCR_INDEX_0,
EV_NO_ACTION, NULL },
#if CONFIG(VENDORCODE_ELTAN_VBOOT)
{ "oemmanifest.bin", CBFS_TYPE_RAW, MBOOT_PCR_INDEX_7, EV_NO_ACTION,
Expand Down