diff --git a/src/device/resource_allocator_v4.c b/src/device/resource_allocator_v4.c
diff --git a/src/drivers/amd/agesa/def_callouts.c b/src/drivers/amd/agesa/def_callouts.c
@@ -42,28 +42,28 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINTN Data, VOID *ConfigPtr)
 	if (i >= BiosCalloutsLen)
 		return AGESA_UNSUPPORTED;
 
-	return BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr);
+	return BiosCallouts[i].CalloutPtr(Func, Data, ConfigPtr);
 }
 
-AGESA_STATUS agesa_NoopUnsupported (UINT32 Func, UINTN Data, VOID *ConfigPtr)
+AGESA_STATUS agesa_NoopUnsupported(UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
 	return AGESA_UNSUPPORTED;
 }
 
-AGESA_STATUS agesa_NoopSuccess (UINT32 Func, UINTN Data, VOID *ConfigPtr)
+AGESA_STATUS agesa_NoopSuccess(UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
 	return AGESA_SUCCESS;
 }
 
-AGESA_STATUS agesa_EmptyIdsInitData (UINT32 Func, UINTN Data, VOID *ConfigPtr)
+AGESA_STATUS agesa_EmptyIdsInitData(UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
 	IDS_NV_ITEM *IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr;
 	if (Data == IDS_CALLOUT_INIT)
 		IdsPtr[0].IdsNvValue = IdsPtr[0].IdsNvId = 0xffff;
 	return AGESA_SUCCESS;
 }
 
-AGESA_STATUS agesa_Reset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
+AGESA_STATUS agesa_Reset(UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
 	AGESA_STATUS        Status;
 	UINT8                 Value;
@@ -88,7 +88,7 @@ AGESA_STATUS agesa_Reset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
 	case WARM_RESET_IMMEDIATELY:
 	case COLD_RESET_IMMEDIATELY:
 		Value = 0x06;
-		LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader);
+		LibAmdIoWrite(AccessWidth8, 0xCf9, &Value, StdHeader);
 		break;
 
 	default:
@@ -99,7 +99,7 @@ AGESA_STATUS agesa_Reset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
 	return Status;
 }
 
-AGESA_STATUS agesa_RunFuncOnAp (UINT32 Func, UINTN Data, VOID *ConfigPtr)
+AGESA_STATUS agesa_RunFuncOnAp(UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
 	AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
 	AGESA_STATUS status;
@@ -127,12 +127,12 @@ AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINTN FchData, VOID *ConfigPrt)
 }
 #endif
 
-AGESA_STATUS agesa_ReadSpd (UINT32 Func, UINTN Data, VOID *ConfigPtr)
+AGESA_STATUS agesa_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
 	if (!ENV_RAMINIT)
 		return AGESA_UNSUPPORTED;
 
-	return AmdMemoryReadSPD (Func, Data, ConfigPtr);
+	return AmdMemoryReadSPD(Func, Data, ConfigPtr);
 }
 
 AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr)

diff --git a/src/drivers/amd/agesa/eventlog.c b/src/drivers/amd/agesa/eventlog.c
@@ -151,13 +151,13 @@ static const char *decodeAGESA_STATUS(AGESA_STATUS sret)
 
 static void show_event(EVENT_PARAMS *Event)
 {
-	printk(BIOS_DEBUG,"\nEventLog:  EventClass = %x, EventInfo = %x.\n",
+	printk(BIOS_DEBUG, "\nEventLog:  EventClass = %x, EventInfo = %x.\n",
 			(unsigned int)Event->EventClass,
 			(unsigned int)Event->EventInfo);
-	printk(BIOS_DEBUG,"  Param1 = %x, Param2 = %x.\n",
+	printk(BIOS_DEBUG, "  Param1 = %x, Param2 = %x.\n",
 			(unsigned int)Event->DataParam1,
 			(unsigned int)Event->DataParam2);
-	printk(BIOS_DEBUG,"  Param3 = %x, Param4 = %x.\n",
+	printk(BIOS_DEBUG, "  Param3 = %x, Param4 = %x.\n",
 			(unsigned int)Event->DataParam3,
 			(unsigned int)Event->DataParam4);
 }
@@ -194,7 +194,7 @@ void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader,
 	amd_flush_eventlog(&AmdEventParams);
 }
 
-AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus)
+AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus)
 {
 	EVENT_PARAMS AmdEventParams;
 

diff --git a/src/drivers/amd/agesa/heapmanager.c b/src/drivers/amd/agesa/heapmanager.c
@@ -42,7 +42,7 @@ void EmptyHeap(void)
 	memset(base, 0, BIOS_HEAP_SIZE);
 
 	printk(BIOS_DEBUG, "Wiped HEAP at [%08x - %08x]\n",
-		(unsigned int)(uintptr_t) base, (unsigned int)(uintptr_t) base + BIOS_HEAP_SIZE - 1);
+		(unsigned int)(uintptr_t)base, (unsigned int)(uintptr_t) base + BIOS_HEAP_SIZE - 1);
 }
 
 #if defined(HEAP_CALLOUT_RUNTIME) && ENV_RAMSTAGE
@@ -104,15 +104,15 @@ static AGESA_STATUS agesa_AllocateBuffer(BIOS_HEAP_MANAGER *BiosHeapBasePtr,
 	if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) {
 		/* First allocation */
 		CurrNodeOffset = sizeof(BIOS_HEAP_MANAGER);
-		CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+		CurrNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + CurrNodeOffset);
 		CurrNodePtr->BufferHandle = AllocParams->BufferHandle;
 		CurrNodePtr->BufferSize = AllocParams->BufferLength;
 		CurrNodePtr->NextNodeOffset = 0;
-		AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof(BIOS_BUFFER_NODE);
+		AllocParams->BufferPointer = (UINT8 *)CurrNodePtr + sizeof(BIOS_BUFFER_NODE);
 
 		/* Update the remaining free space */
 		FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof(BIOS_BUFFER_NODE);
-		FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+		FreedNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + FreedNodeOffset);
 		FreedNodePtr->BufferSize = AvailableHeapSize
 					- (FreedNodeOffset - CurrNodeOffset)
 					- sizeof(BIOS_BUFFER_NODE);
@@ -126,10 +126,10 @@ static AGESA_STATUS agesa_AllocateBuffer(BIOS_HEAP_MANAGER *BiosHeapBasePtr,
 		 * If it has, return AGESA_BOUNDS_CHK.
 		 */
 		CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
-		CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+		CurrNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + CurrNodeOffset);
 
 		while (CurrNodeOffset != 0) {
-			CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset);
+			CurrNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + CurrNodeOffset);
 			if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) {
 				return AGESA_BOUNDS_CHK;
 			}
@@ -144,15 +144,15 @@ static AGESA_STATUS agesa_AllocateBuffer(BIOS_HEAP_MANAGER *BiosHeapBasePtr,
 		BestFitNodeOffset = 0;
 		BestFitPrevNodeOffset = 0;
 		while (FreedNodeOffset != 0) {
-			FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+			FreedNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + FreedNodeOffset);
 			if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof(BIOS_BUFFER_NODE))) {
 				if (BestFitNodeOffset == 0) {
 					/* First node that fits the requested buffer size */
 					BestFitNodeOffset = FreedNodeOffset;
 					BestFitPrevNodeOffset = PrevNodeOffset;
 				} else {
 					/* Find out whether current node is a better fit than the previous nodes */
-					BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
+					BestFitNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + BestFitNodeOffset);
 					if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) {
 						BestFitNodeOffset = FreedNodeOffset;
 						BestFitPrevNodeOffset = PrevNodeOffset;
@@ -169,14 +169,14 @@ static AGESA_STATUS agesa_AllocateBuffer(BIOS_HEAP_MANAGER *BiosHeapBasePtr,
 			 */
 			return AGESA_BOUNDS_CHK;
 		} else {
-			BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset);
-			BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset);
+			BestFitNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + BestFitNodeOffset);
+			BestFitPrevNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + BestFitPrevNodeOffset);
 
 			/* If BestFitNode is larger than the requested buffer, fragment the node further */
 			if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof(BIOS_BUFFER_NODE))) {
 				NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof(BIOS_BUFFER_NODE);
 
-				NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset);
+				NextFreePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + NextFreeOffset);
 				NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof(BIOS_BUFFER_NODE));
 				NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset;
 			} else {
@@ -200,7 +200,7 @@ static AGESA_STATUS agesa_AllocateBuffer(BIOS_HEAP_MANAGER *BiosHeapBasePtr,
 			BestFitNodePtr->NextNodeOffset = 0;
 
 			/* Remove BestFitNode from list of Freed nodes */
-			AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof(BIOS_BUFFER_NODE);
+			AllocParams->BufferPointer = (UINT8 *)BestFitNodePtr + sizeof(BIOS_BUFFER_NODE);
 		}
 	}
 
@@ -225,7 +225,7 @@ static AGESA_STATUS agesa_DeallocateBuffer(BIOS_HEAP_MANAGER *BiosHeapBasePtr,
 	 * Return AGESA_BOUNDS_CHK if the BufferHandle is not found.
 	 */
 	AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
-	AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+	AllocNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + AllocNodeOffset);
 	PrevNodeOffset = AllocNodeOffset;
 
 	while (AllocNodePtr->BufferHandle !=  AllocParams->BufferHandle) {
@@ -234,20 +234,20 @@ static AGESA_STATUS agesa_DeallocateBuffer(BIOS_HEAP_MANAGER *BiosHeapBasePtr,
 		}
 		PrevNodeOffset = AllocNodeOffset;
 		AllocNodeOffset = AllocNodePtr->NextNodeOffset;
-		AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+		AllocNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + AllocNodeOffset);
 	}
 
 	/* Remove target node from list of allocated nodes */
-	PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
+	PrevNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + PrevNodeOffset);
 	PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset;
 
 	/* Zero out the buffer, and clear the BufferHandle */
-	LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof(BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader));
+	LibAmdMemFill((UINT8 *)AllocNodePtr + sizeof(BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader));
 	AllocNodePtr->BufferHandle = 0;
 
 	/* Add deallocated node in order to the list of freed nodes */
 	FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes;
-	FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset);
+	FreedNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + FreedNodeOffset);
 
 	EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize +
 						sizeof(BIOS_BUFFER_NODE);
@@ -284,14 +284,14 @@ static AGESA_STATUS agesa_DeallocateBuffer(BIOS_HEAP_MANAGER *BiosHeapBasePtr,
 				break;
 			}
 			NextNodeOffset = NextNodePtr->NextNodeOffset;
-			NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
+			NextNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + NextNodeOffset);
 		}
 
 		/* If deallocated node is adjacent to the next node,
 		 * concatenate both nodes.
 		 */
 		if (NextNodeOffset == EndNodeOffset) {
-			NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset);
+			NextNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + NextNodeOffset);
 			AllocNodePtr->BufferSize += NextNodePtr->BufferSize +
 						sizeof(BIOS_BUFFER_NODE);
 			AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset;
@@ -306,7 +306,7 @@ static AGESA_STATUS agesa_DeallocateBuffer(BIOS_HEAP_MANAGER *BiosHeapBasePtr,
 		/* If deallocated node is adjacent to the previous node,
 		 * concatenate both nodes.
 		 */
-		PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset);
+		PrevNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + PrevNodeOffset);
 		EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize +
 						sizeof(BIOS_BUFFER_NODE);
 		if (AllocNodeOffset == EndNodeOffset) {
@@ -332,7 +332,7 @@ static AGESA_STATUS agesa_LocateBuffer(BIOS_HEAP_MANAGER *BiosHeapBasePtr,
 	BIOS_BUFFER_NODE   *AllocNodePtr;
 
 	AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes;
-	AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+	AllocNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + AllocNodeOffset);
 
 	while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) {
 		if (AllocNodePtr->NextNodeOffset == 0) {
@@ -341,15 +341,14 @@ static AGESA_STATUS agesa_LocateBuffer(BIOS_HEAP_MANAGER *BiosHeapBasePtr,
 			return AGESA_BOUNDS_CHK;
 		} else {
 			AllocNodeOffset = AllocNodePtr->NextNodeOffset;
-			AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset);
+			AllocNodePtr = (BIOS_BUFFER_NODE *)(BiosHeapBaseAddr + AllocNodeOffset);
 		}
 	}
 
-	AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof(BIOS_BUFFER_NODE));
+	AllocParams->BufferPointer = (UINT8 *)((UINT8 *) AllocNodePtr + sizeof(BIOS_BUFFER_NODE));
 	AllocParams->BufferLength = AllocNodePtr->BufferSize;
 
 	return AGESA_SUCCESS;
-
 }
 
 AGESA_STATUS HeapManagerCallout(UINT32 Func, UINTN Data, VOID *ConfigPtr)

diff --git a/src/drivers/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c
@@ -45,7 +45,7 @@ void fixup_cbmem_to_UC(int s3resume)
 	 * writeback possible.
 	 */
 
-	uintptr_t top_of_ram = (uintptr_t) cbmem_top();
+	uintptr_t top_of_ram = (uintptr_t)cbmem_top();
 	top_of_ram = ALIGN_UP(top_of_ram, 4 * MiB);
 
 	set_range_uc(top_of_ram - 4 * MiB, 4 * MiB);
@@ -79,12 +79,12 @@ static void recover_postcar_frame(struct postcar_frame *pcf)
 	 * speed make them WB after CAR teardown.
 	 */
 	if (s3resume) {
-		uintptr_t top_of_ram = (uintptr_t) cbmem_top();
-		top_of_ram = ALIGN_DOWN(top_of_ram, 4*MiB);
+		uintptr_t top_of_ram = (uintptr_t)cbmem_top();
+		top_of_ram = ALIGN_DOWN(top_of_ram, 4 * MiB);
 
-		postcar_frame_add_mtrr(pcf, top_of_ram - 4*MiB, 4*MiB,
+		postcar_frame_add_mtrr(pcf, top_of_ram - 4 * MiB, 4 * MiB,
 			MTRR_TYPE_WRBACK);
-		postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 4*MiB,
+		postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 4 * MiB,
 			MTRR_TYPE_WRBACK);
 	}
 }

diff --git a/src/drivers/amd/agesa/oem_s3.c b/src/drivers/amd/agesa/oem_s3.c
@@ -37,7 +37,7 @@ AGESA_STATUS OemS3LateRestore(AMD_S3_PARAMS *dataBlock)
 		return AGESA_FATAL;
 
 	printk(BIOS_DEBUG, "Using resume HEAP at %08x\n",
-		(unsigned int)(uintptr_t) heap);
+		(unsigned int)(uintptr_t)heap);
 
 	/* Return allocated CBMEM size, we do not keep track of
 	 * how much was actually used.

diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c
@@ -76,7 +76,6 @@ void __noreturn romstage_main(void)
 
 	prepare_and_run_postcar();
 	/* We do not return. */
-	die("failed to load postcar\n");
 }
 
 static void ap_romstage_main(void)

diff --git a/src/drivers/amd/agesa/state_machine.c b/src/drivers/amd/agesa/state_machine.c
@@ -36,7 +36,7 @@ static void agesa_locate_image(AMD_CONFIG_PARAMS *StdHeader)
 
 	image = LibAmdLocateImage(agesa, agesa + file_size, 4096,
 		ModuleIdentifier);
-	StdHeader->ImageBasePtr = (void *) image;
+	StdHeader->ImageBasePtr = (void *)image;
 #endif
 }
 
@@ -159,7 +159,6 @@ static AGESA_STATUS romstage_dispatch(struct sysinfo *cb,
 		{
 			break;
 		}
-
 	}
 	return status;
 }
@@ -222,7 +221,6 @@ static AGESA_STATUS ramstage_dispatch(struct sysinfo *cb,
 		{
 			break;
 		}
-
 	}
 	return status;
 }
@@ -247,7 +245,7 @@ int agesa_execute_state(struct sysinfo *cb, AGESA_STRUCT_NAME func)
 
 	/* For these calls, heap is not available. */
 	if (func == AMD_INIT_RESET || func == AMD_S3LATE_RESTORE) {
-		buf = (void *) &agesa_params;
+		buf = (void *)&agesa_params;
 		len = sizeof(agesa_params);
 		memcpy(buf, &cb->StdHeader, sizeof(cb->StdHeader));
 	}

diff --git a/src/drivers/aspeed/ast2050/ast2050.c b/src/drivers/aspeed/ast2050/ast2050.c
@@ -14,7 +14,7 @@
 static void aspeed_ast2050_read_resources(struct device *dev)
 {
 	/* Reserve VGA regions */
-	mmio_resource(dev, 3, 0xa0000 >> 10, 0x1ffff >> 10);
+	mmio_resource_kb(dev, 3, 0xa0000 >> 10, 0x1ffff >> 10);
 
 	/* Run standard resource read routine */
 	pci_dev_read_resources(dev);

diff --git a/src/drivers/aspeed/common/ast_dp501.c b/src/drivers/aspeed/common/ast_dp501.c
@@ -146,7 +146,6 @@ static bool ast_launch_m68k(struct drm_device *dev)
 
 	data = ast_mindwm(ast, 0x1e6e2100) & 0x01;
 	if (!data) {
-
 		if (ast->dp501_fw_addr) {
 			fw_addr = ast->dp501_fw_addr;
 			len = 32*1024;

diff --git a/src/drivers/aspeed/common/ast_mode.c b/src/drivers/aspeed/common/ast_mode.c
@@ -26,7 +26,6 @@ static void ast_crtc_load_lut(struct drm_crtc *crtc)
 	/* FIXME: Gamma cor 2.6 ? */
 	for (int i = 0; i < 256; i++)
 		ast_load_palette_index(ast, i, i, i, i);
-
 }
 
 static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mode *mode,

diff --git a/src/drivers/aspeed/common/ast_post.c b/src/drivers/aspeed/common/ast_post.c
@@ -788,8 +788,8 @@ static void finetuneDQSI(struct ast_private *ast)
 	}
 	reg_mcr18 = reg_mcr18 | (g_dqidly << 16) | (g_dqsip << 23);
 	ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
-
 }
+
 static bool cbr_dll2(struct ast_private *ast, struct ast2300_dram_param *param)
 {
 	u32 dllmin[2], dllmax[2], dlli, data, passcnt, retry = 0;
@@ -1085,7 +1085,6 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
 		param->dram_config |= 0x0c;
 		break;
 	}
-
 }
 
 static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
@@ -1226,7 +1225,6 @@ static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
 	ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
 	ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
 #endif
-
 }
 
 static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *param)
@@ -1617,7 +1615,6 @@ static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param)
 	ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
 	ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
 #endif
-
 }
 
 static void ast_post_chip_2300(struct drm_device *dev)
@@ -1883,7 +1880,6 @@ static void reset_mmc_2500(struct ast_private *ast)
 
 static void ddr3_init_2500(struct ast_private *ast, const u32 *ddr_table)
 {
-
 	ast_moutdwm(ast, 0x1E6E0004, 0x00000303);
 	ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
 	ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);

diff --git a/src/drivers/camera/Kconfig b/src/drivers/camera/Kconfig
@@ -2,6 +2,6 @@ config CHROMEOS_CAMERA
 	bool
 	default n
 	help
-	  Camera with identifiers following Chrome OS Camera Info. The info is
+	  Camera with identifiers following ChromeOS Camera Info. The info is
 	  usually available on MIPI camera EEPROM for identifying correct
 	  drivers and config.
diff --git a/src/drivers/crb/tis.c b/src/drivers/crb/tis.c
@@ -5,6 +5,7 @@
 #include <acpi/acpigen.h>
 #include <device/device.h>
 #include <drivers/intel/ptt/ptt.h>
+#include <drivers/tpm/tpm_ppi.h>
 
 #include "tpm.h"
 #include "chip.h"
@@ -51,7 +52,6 @@ int tis_open(void)
 int tis_close(void)
 {
 	if (tpm_is_open) {
-
 		/*
 		 * Do we need to do something here, like waiting for a
 		 * transaction to stop?
@@ -115,6 +115,9 @@ static void crb_tpm_fill_ssdt(const struct device *dev)
 
 	acpigen_write_resourcetemplate_footer();
 
+	if (!CONFIG(CHROMEOS) && CONFIG(TPM_PPI))
+		tpm_ppi_acpi_fill_ssdt(dev);
+
 	acpigen_pop_len(); /* Device */
 }
 
@@ -123,7 +126,7 @@ static const char *crb_tpm_acpi_name(const struct device *dev)
 	return "TPM";
 }
 
-static struct device_operations __unused crb_ops = {
+static struct device_operations __maybe_unused crb_ops = {
 	.read_resources = noop_read_resources,
 	.set_resources = noop_set_resources,
 #if CONFIG(HAVE_ACPI_TABLES)

diff --git a/src/drivers/crb/tpm.c b/src/drivers/crb/tpm.c
@@ -110,7 +110,6 @@ static int crb_probe(void)
  */
 static uint8_t crb_activate_locality(void)
 {
-
 	uint8_t locality = (read8(CRB_REG(0, CRB_REG_LOC_STATE)) >> 2) & 0x07;
 	printk(BIOS_SPEW, "Active locality: %i\n", locality);
 
@@ -174,7 +173,6 @@ static int crb_switch_to_ready(void)
  */
 int tpm2_init(void)
 {
-
 	if (crb_probe()) {
 		printk(BIOS_ERR, "TPM: Probe failed.\n");
 		return -1;

diff --git a/src/drivers/generic/max98357a/chip.h b/src/drivers/generic/max98357a/chip.h
@@ -3,7 +3,6 @@
 #include <acpi/acpi_device.h>
 
 struct drivers_generic_max98357a_config {
-
 	/* ACPI _HID */
 	const char *hid;
 

diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c
@@ -346,7 +346,6 @@ static int recv_data(struct tpm_chip *chip, uint8_t *buf, size_t count)
 				  burstcnt);
 		if (rc == 0)
 			size += burstcnt;
-
 	}
 	return size;
 }

diff --git a/src/drivers/i2c/ww_ring/ww_ring.c b/src/drivers/i2c/ww_ring/ww_ring.c
@@ -375,7 +375,6 @@ static void ww_ring_init(unsigned int i2c_bus)
 	for (i = 0, ledc = lp55231s;
 	     i < WW_RING_NUM_LED_CONTROLLERS;
 	     i++, ledc++) {
-
 		ledc->i2c_bus = i2c_bus;
 		ledc->dev_addr = LP55231_I2C_BASE_ADDR + i;
 

diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c
@@ -406,7 +406,7 @@ static void write_create_tbat(const struct dptf_platform_info *platform_info)
 	acpigen_write_name("_HID");
 	if (platform_info->tbat_device_hid != NULL)
 		dptf_write_hid(platform_info->use_eisa_hids, platform_info->tbat_device_hid);
-	acpigen_write_name_string("_UID", "TBAT");
+	acpigen_write_name_string("_UID", "1");
 	acpigen_write_name_string("_STR", DEFAULT_BATTERY_STR);
 	acpigen_write_name_integer("PTYP", DPTF_GENERIC_PARTICIPANT_TYPE_BATTERY);
 	acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);

diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c
@@ -19,7 +19,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
 	 * with different TSEG size configurations. */
 	top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB);
 	postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK);
-
 }
 
 /* This is the romstage entry called from cpu/intel/car/romstage.c */

diff --git a/src/drivers/intel/fsp1_1/exit_car.S b/src/drivers/intel/fsp1_1/exit_car.S
@@ -7,7 +7,7 @@ chipset_teardown_car:
 
 	pop	%ebx
 	/* Move the stack pointer to real RAM */
-	movl	_estack, %esp
+	movl	$_estack, %esp
 	/* Align the stack 16 bytes */
 	andl	$0xfffffff0, %esp
 

diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c
@@ -134,7 +134,6 @@ struct hob_resource *find_resource_hob_by_guid(const struct hob_header *hob,
 
 	for (; hob->type != HOB_TYPE_END_OF_HOB_LIST;
 		hob = fsp_next_hob(hob)) {
-
 		if (hob->type != HOB_TYPE_RESOURCE_DESCRIPTOR)
 			continue;
 
@@ -198,7 +197,6 @@ const void *fsp_find_extension_hob_by_guid(const uint8_t *guid, size_t *size)
 
 	for (; hob->type != HOB_TYPE_END_OF_HOB_LIST;
 		hob = fsp_next_hob(hob)) {
-
 		if (hob->type != HOB_TYPE_GUID_EXTENSION)
 			continue;
 

diff --git a/src/drivers/intel/fsp2_0/header_display.c b/src/drivers/intel/fsp2_0/header_display.c
@@ -51,5 +51,4 @@ void fsp_print_header_info(const struct fsp_header *hdr)
 		printk(BIOS_SPEW, "\tNotify phase offset  0x%zx\n",
 		       (size_t)hdr->notify_phase_entry_offset);
 	}
-
 }
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
@@ -42,7 +42,7 @@ static void save_memory_training_data(bool s3wake, uint32_t fsp_version)
 
 	/*
 	 * Save MRC Data to CBMEM. By always saving the data this forces
-	 * a retrain after a trip through Chrome OS recovery path. The
+	 * a retrain after a trip through ChromeOS recovery path. The
 	 * code which saves the data to flash doesn't write if the latest
 	 * training data matches this one.
 	 */

diff --git a/src/drivers/intel/gma/opregion.c b/src/drivers/intel/gma/opregion.c
@@ -290,7 +290,6 @@ static inline bool uses_relative_vbt_addr(opregion_header_t *header)
 static void opregion_add_ext_vbt(igd_opregion_t *opregion, uint8_t *ext_vbt,
 				optionrom_vbt_t *vbt)
 {
-
 	opregion_header_t *header = &opregion->header;
 	/* Copy VBT into extended VBT region (at offset 8 KiB) */
 	memcpy(ext_vbt, vbt, vbt->hdr_vbt_size);

diff --git a/src/drivers/intel/i210/i210.c b/src/drivers/intel/i210/i210.c
@@ -203,7 +203,6 @@ static void init(struct device *dev)
 	} else {
 		printk(BIOS_INFO, "I210: MAC address is up to date.\n");
 	}
-	return;
 }
 
 static void enable_bus_master(struct device *dev)

diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c
@@ -139,7 +139,9 @@ static void camera_fill_cio2(const struct device *dev)
 		if (CONFIG(ACPI_ADL_IPU_ES_SUPPORT)) {
 			u32 cpu_id = cpu_get_cpuid();
 			if (cpu_id == CPUID_ALDERLAKE_J0 || cpu_id == CPUID_ALDERLAKE_Q0 ||
-				cpu_id == CPUID_ALDERLAKE_N_A0 || cpu_id == CPUID_RAPTORLAKE_P_J0)
+				cpu_id == CPUID_ALDERLAKE_N_A0 ||
+				cpu_id == CPUID_RAPTORLAKE_P_J0 ||
+				cpu_id == CPUID_RAPTORLAKE_P_Q0)
 				acpi_dp_add_integer(dsd, "is_es", 1);
 			else
 				acpi_dp_add_integer(dsd, "is_es", 0);

diff --git a/src/drivers/intel/usb4/retimer/retimer.c b/src/drivers/intel/usb4/retimer/retimer.c
@@ -386,7 +386,6 @@ static void usb4_retimer_fill_ssdt(const struct device *dev)
 	acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);
 
 	for (dfp_port = 0; dfp_port < DFP_NUM_MAX; dfp_port++) {
-
 		if (!config->dfp[dfp_port].power_gpio.pin_count) {
 			printk(BIOS_WARNING, "%s: No DFP%1d power GPIO for %s\n",
 				__func__, dfp_port, dev_path(dev));

diff --git a/src/drivers/ipmi/ipmi_fru.c b/src/drivers/ipmi/ipmi_fru.c
@@ -571,5 +571,4 @@ void print_fru_areas(struct fru_info_str *fru_info_str)
 			printk(BIOS_DEBUG, "chassis custom data %i: %s\n", count,
 				*(chassis_info.chassis_custom + count));
 	}
-
 }
diff --git a/src/drivers/mrc_cache/Kconfig b/src/drivers/mrc_cache/Kconfig
@@ -46,7 +46,7 @@ config MRC_STASH_TO_CBMEM
 
 config MRC_SAVE_HASH_IN_TPM
 	bool "Save a hash of the MRC_CACHE data in TPM NVRAM"
-	depends on VBOOT_STARTS_IN_BOOTBLOCK && TPM2 && !TPM1
+	depends on VBOOT_STARTS_IN_BOOTBLOCK && TPM2 && !TPM1 && !VBOOT_MOCK_SECDATA
 	default y
 	help
 	  Store a hash of the MRC_CACHE training data in a TPM NVRAM

diff --git a/src/drivers/net/ne2k.c b/src/drivers/net/ne2k.c
@@ -124,7 +124,6 @@ static void str2mac(const char *str, unsigned char *mac)
 	int acc = 0;
 
 	do {
-
 		c = str[i];
 		if ((c >= '0') && (c <= '9')) {
 			acc *= 16;

diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c
@@ -267,7 +267,6 @@ void set_boot_successful(void)
 		/* If we are in normal mode set the boot count to 0 */
 		if (byte & RTC_BOOT_NORMAL)
 			byte &= 0x0f;
-
 	}
 
 	outb(byte, RTC_PORT(1));

diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c
@@ -749,7 +749,7 @@ static int tis_setup_interrupt(int vector, int polarity)
 static void lpc_tpm_read_resources(struct device *dev)
 {
 	/* Static 5K memory region specified in Kconfig */
-	mmio_resource(dev, 0, CONFIG_TPM_TIS_BASE_ADDRESS >> 10, 0x5000 >> 10);
+	mmio_resource_kb(dev, 0, CONFIG_TPM_TIS_BASE_ADDRESS >> 10, 0x5000 >> 10);
 }
 
 static void lpc_tpm_set_resources(struct device *dev)

diff --git a/src/drivers/pcie/generic/chip.h b/src/drivers/pcie/generic/chip.h
@@ -6,15 +6,9 @@
 #include <types.h>
 
 struct drivers_pcie_generic_config {
-	bool is_untrusted;
-	/*
-	 * This needs to be pointed to the device instance in the device tree when
-	 * there is already a device with the root port so that the ACPI code to be
-	 * generated will be added to that existing device.
-	 * By default, an ACPI device named 'DEV0' is created under the root port if
-	 * this does not reference to a device.
-	 */
-	DEVTREE_CONST struct device *companion_dev;
+	const char *name;
+	unsigned int wake_gpe;
+	unsigned int wake_deepest;
 };
 
 #endif /* _PCIE_GENERIC_H_ */
diff --git a/src/drivers/pcie/generic/generic.c b/src/drivers/pcie/generic/generic.c
@@ -11,44 +11,39 @@ static const char *pcie_generic_acpi_name(const struct device *dev)
 {
 	struct drivers_pcie_generic_config *config = dev->chip_info;
 
-	if (config->companion_dev)
-		return acpi_device_name(config->companion_dev);
-	return "DEV0";
+	if (!config || !config->name)
+		return "DEV0";
+
+	return config->name;
 }
 
 static void pcie_generic_fill_ssdt(const struct device *dev)
 {
 	struct drivers_pcie_generic_config *config;
-	struct acpi_dp *dsd;
 
 	if (!is_dev_enabled(dev))
 		return;
 
 	pci_rom_ssdt(dev);
 
 	config = dev->chip_info;
-	if (!config || !config->is_untrusted || !dev->bus || !dev->bus->dev)
+	if (!config || !dev->bus || !dev->bus->dev)
 		return;
 
 	const char *scope;
 	const char *name;
 
-	/* Code will be generated under companion device instead if present. */
-	if (config->companion_dev)
-		scope = acpi_device_path(config->companion_dev);
-	else
-		scope = acpi_device_path(dev->bus->dev);
+	scope = acpi_device_path(dev->bus->dev);
 	name = acpi_device_name(dev);
+
 	acpigen_write_scope(scope);
-	if (!config->companion_dev) {
-		acpigen_write_device(name);
-		acpigen_write_ADR_pci_device(dev);
-	}
-	dsd = acpi_dp_new_table("_DSD");
-	acpi_dp_add_integer(dsd, "DmaProperty", 1);
-	acpi_dp_write(dsd);
-	if (!config->companion_dev)
-		acpigen_write_device_end();
+	acpigen_write_device(name);
+	acpigen_write_ADR_pci_device(dev);
+
+	if (config->wake_gpe)
+		acpigen_write_PRW(config->wake_gpe, config->wake_deepest);
+
+	acpigen_write_device_end();
 	acpigen_write_scope_end();
 
 	printk(BIOS_INFO, "%s.%s: Enable ACPI properties for %s (%s)\n", scope, name,

diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c
@@ -169,7 +169,6 @@ static enum cb_err scan_end(struct region_device *store)
 		return CB_ERR;
 
 	return CB_SUCCESS;
-
 }
 /*
  * Append data to region

diff --git a/src/drivers/spi/spi_sdcard.c b/src/drivers/spi/spi_sdcard.c
@@ -210,7 +210,7 @@ static int lookup_response_length(int response_type)
 static int response_resolve(int response_type, uint8_t *response,
 	uint32_t *out_register)
 {
-	__unused static const char * const sd_err[] = {
+	__maybe_unused static const char * const sd_err[] = {
 		"Card is locked",
 		"wp erase skip | lock/unlok cmd failed",
 		"error",

diff --git a/src/drivers/spi/tpm/tis.c b/src/drivers/spi/tpm/tis.c
@@ -40,7 +40,6 @@ int tis_open(void)
 int tis_close(void)
 {
 	if (tpm_is_open) {
-
 		/*
 		 * Do we need to do something here, like waiting for a
 		 * transaction to stop?

diff --git a/src/drivers/tpm/ppi.c b/src/drivers/tpm/ppi.c
@@ -581,7 +581,6 @@ void tpm_ppi_acpi_fill_ssdt(const struct device *dev)
 				found = true;
 		}
 	} else {
-
 		for (size_t i = 0; i < ARRAY_SIZE(tpm2_funcs); i++) {
 			ppib->func[tpm2_funcs[i]] = 1;
 			if (ppib->pprq == tpm2_funcs[i])

diff --git a/src/drivers/usb/ehci.h b/src/drivers/usb/ehci.h
@@ -42,7 +42,6 @@ struct ehci_caps {
 
 /* Section 2.3 Host Controller Operational Registers */
 struct ehci_regs {
-
 	/* USBCMD: offset 0x00 */
 	u32		command;
 

diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c
@@ -41,14 +41,6 @@ __weak int get_wifi_sar_limits(union wifi_sar_limits *sar_limits)
 	return -1;
 }
 
-/*
- * Generate ACPI AML code for _DSM method.
- * This function takes as input uuid for the device, set of callbacks and
- * argument to pass into the callbacks. Callbacks should ensure that Local0 and
- * Local1 are left untouched. Use of Local2-Local7 is permitted in callbacks.
- */
-void wifi_emit_dsm(struct dsm_profile *dsm);
-
 /*
  * Function 1: Allow PC OEMs to set ETSI 5.8GHz SRD in Passive/Disabled ESTI SRD
  * Channels: 149, 153, 157, 161, 165
@@ -180,21 +172,6 @@ static void (*wifi_dsm2_callbacks[])(void *) = {
 	wifi_dsm_ddrrfim_func3_cb,	/* Function 3 */
 };
 
-void wifi_emit_dsm(struct dsm_profile *dsm)
-{
-	int i;
-	size_t count = ARRAY_SIZE(wifi_dsm_callbacks);
-
-	if (dsm == NULL)
-		return;
-
-	for (i = 1; i < count; i++)
-		if (!(dsm->supported_functions & (1 << i)))
-			wifi_dsm_callbacks[i] = NULL;
-
-	acpigen_write_dsm(ACPI_DSM_OEM_WIFI_UUID, wifi_dsm_callbacks, count, dsm);
-}
-
 static const uint8_t *sar_fetch_set(const struct sar_profile *sar, size_t set_num)
 {
 	const uint8_t *sar_table = &sar->sar_table[0];

diff --git a/src/ec/acpi/ec.c b/src/ec/acpi/ec.c
@@ -47,7 +47,7 @@ int send_ec_command_timeout(u8 command, int timeout_us)
 	if (!ec_ready_send(timeout_us)) {
 		printk(BIOS_DEBUG, "Timeout while sending command 0x%02x to EC!\n",
 				command);
-		// return -1;
+		return -1;
 	}
 
 	outb(command, ec_cmd_reg);
@@ -65,26 +65,26 @@ int send_ec_data_timeout(u8 data, int timeout_us)
 	if (!ec_ready_send(timeout_us)) {
 		printk(BIOS_DEBUG, "Timeout while sending data 0x%02x to EC!\n",
 				data);
-		// return -1;
+		return -1;
 	}
 
 	outb(data, ec_data_reg);
 
 	return 0;
 }
 
-u8 recv_ec_data(void)
+int recv_ec_data(void)
 {
 	return recv_ec_data_timeout(EC_RECV_TIMEOUT_US);
 }
 
-u8 recv_ec_data_timeout(int timeout_us)
+int recv_ec_data_timeout(int timeout_us)
 {
 	u8 data;
 
 	if (!ec_ready_recv(timeout_us)) {
 		printk(BIOS_DEBUG, "Timeout while receiving data from EC!\n");
-		// return -1;
+		return -1;
 	}
 
 	data = inb(ec_data_reg);

diff --git a/src/ec/acpi/ec.h b/src/ec/acpi/ec.h
@@ -29,8 +29,8 @@ int send_ec_command(u8 command);
 int send_ec_command_timeout(u8 command, int timeout);
 int send_ec_data(u8 data);
 int send_ec_data_timeout(u8 data, int timeout);
-u8 recv_ec_data(void);
-u8 recv_ec_data_timeout(int timeout);
+int recv_ec_data(void);
+int recv_ec_data_timeout(int timeout);
 void ec_clear_out_queue(void);
 u8 ec_status(void);
 u8 ec_query(void);

diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig
@@ -125,9 +125,9 @@ config EC_GOOGLE_CHROMEEC_PD_BOARDNAME
 
 config EC_GOOGLE_CHROMEEC_RTC
 	depends on EC_GOOGLE_CHROMEEC
-	bool "Enable Chrome OS EC RTC"
+	bool "Enable ChromeOS EC RTC"
 	help
-	  Enable support for the real-time clock on the Chrome OS EC. This
+	  Enable support for the real-time clock on the ChromeOS EC. This
 	  uses the EC_CMD_RTC_GET_VALUE command to read the current time.
 
 choice
@@ -194,7 +194,7 @@ config EC_GOOGLE_CHROMEEC_SWITCHES
 	depends on EC_GOOGLE_CHROMEEC && VBOOT
 	bool
 	help
-	  Enable support for Chrome OS mode switches provided by the Chrome OS
+	  Enable support for ChromeOS mode switches provided by the ChromeOS
 	  EC.
 
 config EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG

diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl
@@ -169,7 +169,6 @@ Device (EC0)
 			\_SB.DPTC()
 		}
 #endif
-
 	}
 
 	/* Read requested temperature and check against EC error values */
@@ -301,12 +300,6 @@ Device (EC0)
 		Notify (\_TZ, 0x80)
 	}
 
-	// USB Charger
-	Method (_Q0C, 0, NotSerialized)
-	{
-		Printf ("EC: USB CHARGER")
-	}
-
 	// Key Pressed
 	Method (_Q0D, 0, NotSerialized)
 	{

diff --git a/src/ec/google/chromeec/acpi/emem.asl b/src/ec/google/chromeec/acpi/emem.asl
@@ -47,3 +47,5 @@ BSER, 64,	// Battery Serial String
 BTYP, 64,	// Battery Type String
 Offset (0x80),
 ALS0, 16,	// ALS reading 0 in lux
+Offset (0xa6),
+GPUD, 8,	// GPU Data
diff --git a/src/ec/google/chromeec/acpi/superio.asl b/src/ec/google/chromeec/acpi/superio.asl
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 /*
- * Chrome OS Embedded Controller interface
+ * ChromeOS Embedded Controller interface
  *
  * Constants that should be defined:
  *

diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
@@ -219,7 +219,7 @@ static int google_chromeec_clear_mask(uint8_t type, uint64_t mask)
 						EC_HOST_EVENT_CLEAR, &mask);
 }
 
-static int __unused google_chromeec_set_mask(uint8_t type, uint64_t mask)
+static int google_chromeec_set_mask(uint8_t type, uint64_t mask)
 {
 	if (google_chromeec_is_uhepi_supported())
 		return google_chromeec_uhepi_cmd(type,
@@ -949,45 +949,6 @@ uint32_t google_chromeec_get_sku_id(void)
 	return resp.sku_id;
 }
 
-int google_chromeec_vbnv_context(int is_read, uint8_t *data, int len)
-{
-	struct ec_params_vbnvcontext params = {
-		.op = is_read ? EC_VBNV_CONTEXT_OP_READ :
-				EC_VBNV_CONTEXT_OP_WRITE,
-	};
-	struct ec_response_vbnvcontext resp = {};
-	struct chromeec_command cmd = {
-		.cmd_code = EC_CMD_VBNV_CONTEXT,
-		.cmd_version = EC_VER_VBNV_CONTEXT,
-		.cmd_data_in = &params,
-		.cmd_data_out = &resp,
-		.cmd_size_in = sizeof(params),
-		.cmd_size_out = is_read ? sizeof(resp) : 0,
-		.cmd_dev_index = 0,
-	};
-	int retries = 3;
-
-	if (len != EC_VBNV_BLOCK_SIZE)
-		return -1;
-
-	if (!is_read)
-		memcpy(&params.block, data, EC_VBNV_BLOCK_SIZE);
-retry:
-
-	if (google_chromeec_command(&cmd)) {
-		printk(BIOS_ERR, "failed to %s vbnv_ec context: %d\n",
-			is_read ? "read" : "write", (int)cmd.cmd_code);
-		mdelay(10);	/* just in case */
-		if (--retries)
-			goto retry;
-	}
-
-	if (is_read)
-		memcpy(data, &resp.block, EC_VBNV_BLOCK_SIZE);
-
-	return cmd.cmd_code;
-}
-
 static uint16_t google_chromeec_get_uptime_info(
 	struct ec_response_uptime_info *resp)
 {

diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
@@ -77,7 +77,6 @@ uint64_t  google_chromeec_get_events_b(void);
 int google_chromeec_clear_events_b(uint64_t mask);
 int google_chromeec_kbbacklight(int percent);
 void google_chromeec_post(uint8_t postcode);
-int google_chromeec_vbnv_context(int is_read, uint8_t *data, int len);
 uint8_t google_chromeec_get_switches(void);
 bool google_chromeec_get_ap_watchdog_flag(void);
 

diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h
@@ -103,10 +103,14 @@ extern "C" {
 /*
  * The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff
  * and they tell the kernel that so we have to think of it as two parts.
+ *
+ * Other BIOSes report only the I/O port region spanned by the Microchip
+ * MEC series EC; an attempt to address a larger region may fail.
  */
-#define EC_HOST_CMD_REGION0    0x800
-#define EC_HOST_CMD_REGION1    0x880
-#define EC_HOST_CMD_REGION_SIZE 0x80
+#define EC_HOST_CMD_REGION0       0x800
+#define EC_HOST_CMD_REGION1       0x880
+#define EC_HOST_CMD_REGION_SIZE    0x80
+#define EC_HOST_CMD_MEC_REGION_SIZE 0x8
 
 /* EC command register bit functions */
 #define EC_LPC_CMDR_DATA	BIT(0)  /* Data ready for host to read */
@@ -822,11 +826,15 @@ struct ec_lpc_host_args {
 #define EC_SPI_PAST_END       0xed
 
 /*
- * EC is ready to receive, and has ignored the byte sent by the AP.  EC expects
+ * EC is ready to receive, and has ignored the byte sent by the AP. EC expects
  * that the AP will send a valid packet header (starting with
  * EC_COMMAND_PROTOCOL_3) in the next 32 bytes.
+ *
+ * NOTE: Some SPI configurations place the Most Significant Bit on SDO when
+ *	 CS goes low. This macro has the Most Significant Bit set to zero,
+ *	 so SDO will not be driven high when CS goes low.
  */
-#define EC_SPI_RX_READY       0xf8
+#define EC_SPI_RX_READY       0x78
 
 /*
  * EC has started receiving the request from the AP, but hasn't started
@@ -1507,6 +1515,10 @@ enum ec_feature_code {
 	 * The EC supports entering and residing in S4.
 	 */
 	EC_FEATURE_S4_RESIDENCY = 44,
+	/*
+	 * The EC supports the AP directing mux sets for the board.
+	 */
+	EC_FEATURE_TYPEC_AP_MUX_SET = 45,
 };
 
 #define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32)
@@ -1854,34 +1866,6 @@ struct ec_response_flash_region_info {
 	uint32_t size;
 } __ec_align4;
 
-/*
- * Read/write VbNvContext
- *
- * Deprecated as of February 2021.  No current devices use VBNV in EC
- * BBRAM anymore, so this is guaranteed to fail.
- *
- * TODO(b/178689388): remove from this header once no external
- * dependencies reference these constants.
- */
-#define EC_CMD_VBNV_CONTEXT 0x0017
-#define EC_VER_VBNV_CONTEXT 1
-#define EC_VBNV_BLOCK_SIZE 16
-
-enum ec_vbnvcontext_op {
-	EC_VBNV_CONTEXT_OP_READ,
-	EC_VBNV_CONTEXT_OP_WRITE,
-};
-
-struct ec_params_vbnvcontext {
-	uint32_t op;
-	uint8_t block[EC_VBNV_BLOCK_SIZE];
-} __ec_align4;
-
-struct ec_response_vbnvcontext {
-	uint8_t block[EC_VBNV_BLOCK_SIZE];
-} __ec_align4;
-
-
 /* Get SPI flash information */
 #define EC_CMD_FLASH_SPI_INFO 0x0018
 
@@ -4713,6 +4697,39 @@ struct ec_params_dedicated_charger_limit {
 	uint16_t voltage_lim; /* in mV */
 } __ec_align2;
 
+/*
+ * Get and set charging splashscreen variables
+ */
+#define EC_CMD_CHARGESPLASH 0x00A5
+
+enum ec_chargesplash_cmd {
+	/* Get the current state variables */
+	EC_CHARGESPLASH_GET_STATE = 0,
+
+	/* Indicate initialization of the display loop */
+	EC_CHARGESPLASH_DISPLAY_READY,
+
+	/* Manually put the EC into the requested state */
+	EC_CHARGESPLASH_REQUEST,
+
+	/* Reset all state variables */
+	EC_CHARGESPLASH_RESET,
+
+	/* Manually trigger a lockout */
+	EC_CHARGESPLASH_LOCKOUT,
+};
+
+struct __ec_align1 ec_params_chargesplash {
+	/* enum ec_chargesplash_cmd */
+	uint8_t cmd;
+};
+
+struct __ec_align1 ec_response_chargesplash {
+	uint8_t requested;
+	uint8_t display_initialized;
+	uint8_t locked_out;
+};
+
 /*****************************************************************************/
 /* Hibernate/Deep Sleep Commands */
 
@@ -5664,6 +5681,15 @@ struct ec_response_charge_port_count {
 	uint8_t port_count;
 } __ec_align1;
 
+/*
+ * This command enable/disable dynamic PDO selection.
+ */
+#define EC_CMD_USB_PD_DPS_CONTROL 0x0106
+
+struct ec_params_usb_pd_dps_control {
+	uint8_t enable;
+} __ec_align1;
+
 /* Write USB-PD device FW */
 #define EC_CMD_USB_PD_FW_UPDATE 0x0110
 
@@ -6634,6 +6660,7 @@ enum typec_control_command {
 	TYPEC_CONTROL_COMMAND_CLEAR_EVENTS,
 	TYPEC_CONTROL_COMMAND_ENTER_MODE,
 	TYPEC_CONTROL_COMMAND_TBT_UFP_REPLY,
+	TYPEC_CONTROL_COMMAND_USB_MUX_SET,
 };
 
 /* Modes (USB or alternate) that a type-C port may enter. */
@@ -6649,6 +6676,11 @@ enum typec_tbt_ufp_reply {
 	TYPEC_TBT_UFP_REPLY_ACK,
 };
 
+struct typec_usb_mux_set {
+	uint8_t mux_index;	/* Index of the mux to set in the chain */
+	uint8_t mux_flags;	/* USB_PD_MUX_*-encoded USB mux state to set */
+} __ec_align1;
+
 struct ec_params_typec_control {
 	uint8_t port;
 	uint8_t command;	/* enum typec_control_command */
@@ -6666,6 +6698,8 @@ struct ec_params_typec_control {
 		uint8_t mode_to_enter;
 		/* Used for TBT_UFP_REPLY - enum typec_tbt_ufp_reply */
 		uint8_t tbt_ufp_reply;
+		/* Used for USB_MUX_SET */
+		struct typec_usb_mux_set mux_params;
 		uint8_t placeholder[128];
 	};
 } __ec_align1;
@@ -6753,6 +6787,8 @@ enum tcpc_cc_polarity {
 #define PD_STATUS_EVENT_SOP_PRIME_DISC_DONE	BIT(1)
 #define PD_STATUS_EVENT_HARD_RESET		BIT(2)
 #define PD_STATUS_EVENT_DISCONNECTED		BIT(3)
+#define PD_STATUS_EVENT_MUX_0_SET_DONE		BIT(4)
+#define PD_STATUS_EVENT_MUX_1_SET_DONE		BIT(5)
 
 /*
  * Encode and decode for BCD revision response
@@ -6913,7 +6949,20 @@ struct ec_response_pchg {
 	/* Fields added in version 1 */
 	uint32_t fw_version;
 	uint32_t dropped_event_count;
-} __ec_align2;
+} __ec_align4;
+
+struct ec_response_pchg_v2 {
+	uint32_t error;			/* enum pchg_error */
+	uint8_t state;			/* enum pchg_state state */
+	uint8_t battery_percentage;
+	uint8_t unused0;
+	uint8_t unused1;
+	/* Fields added in version 1 */
+	uint32_t fw_version;
+	uint32_t dropped_event_count;
+	/* Fields added in version 2 */
+	uint32_t dropped_host_event_count;
+} __ec_align4;
 
 enum pchg_state {
 	/* Charger is reset and not initialized. */
@@ -6959,7 +7008,7 @@ enum pchg_state {
 #define EC_MKBP_PCHG_PORT_SHIFT		28
 /* Utility macros for converting MKBP event <-> port number. */
 #define EC_MKBP_PCHG_EVENT_TO_PORT(e)	(((e) >> EC_MKBP_PCHG_PORT_SHIFT) & 0xf)
-#define EC_MKBP_PCHG_PORT_TO_EVENT(p)	(BIT((p) + EC_MKBP_PCHG_PORT_SHIFT))
+#define EC_MKBP_PCHG_PORT_TO_EVENT(p)	((p) << EC_MKBP_PCHG_PORT_SHIFT)
 /* Utility macro for extracting event bits. */
 #define EC_MKBP_PCHG_EVENT_MASK(e)	((e) \
 					& GENMASK(EC_MKBP_PCHG_PORT_SHIFT-1, 0))
@@ -7058,6 +7107,66 @@ struct ec_response_i2c_control {
 	} cmd_response;
 } __ec_align_size1;
 
+#define EC_CMD_RGBKBD_SET_COLOR	0x013A
+#define EC_CMD_RGBKBD		0x013B
+
+#define EC_RGBKBD_MAX_KEY_COUNT		128
+#define EC_RGBKBD_MAX_RGB_COLOR		0xFFFFFF
+#define EC_RGBKBD_MAX_SCALE		0xFF
+
+enum rgbkbd_state {
+	/* RGB keyboard is reset and not initialized. */
+	RGBKBD_STATE_RESET = 0,
+	/* RGB keyboard is initialized but not enabled. */
+	RGBKBD_STATE_INITIALIZED,
+	/* RGB keyboard is disabled. */
+	RGBKBD_STATE_DISABLED,
+	/* RGB keyboard is enabled and ready to receive a command. */
+	RGBKBD_STATE_ENABLED,
+
+	/* Put no more entry below */
+	RGBKBD_STATE_COUNT,
+};
+
+enum ec_rgbkbd_subcmd {
+	EC_RGBKBD_SUBCMD_CLEAR = 1,
+	EC_RGBKBD_SUBCMD_DEMO = 2,
+	EC_RGBKBD_SUBCMD_SET_SCALE = 3,
+	EC_RGBKBD_SUBCMD_COUNT
+};
+
+enum ec_rgbkbd_demo {
+	EC_RGBKBD_DEMO_OFF = 0,
+	EC_RGBKBD_DEMO_FLOW = 1,
+	EC_RGBKBD_DEMO_DOT = 2,
+	EC_RGBKBD_DEMO_COUNT,
+};
+
+BUILD_ASSERT(EC_RGBKBD_DEMO_COUNT <= 255);
+
+struct ec_rgbkbd_set_scale {
+	uint8_t key;
+	struct rgb_s scale;
+};
+
+struct ec_params_rgbkbd {
+	uint8_t subcmd;         /* Sub-command (enum ec_rgbkbd_subcmd) */
+	union {
+		struct rgb_s color;	/* EC_RGBKBD_SUBCMD_CLEAR */
+		uint8_t demo;		/* EC_RGBKBD_SUBCMD_DEMO */
+		struct ec_rgbkbd_set_scale set_scale;
+	};
+} __ec_align1;
+
+struct ec_params_rgbkbd_set_color {
+	/* Specifies the starting key ID whose color is being changed. */
+	uint8_t start_key;
+	/* Specifies # of elements in <color>. */
+	uint8_t length;
+	/* RGB color data array of length up to MAX_KEY_COUNT. */
+	struct rgb_s color[];
+} __ec_align1;
+
 /*****************************************************************************/
 /* The command range 0x200-0x2FF is reserved for Rotor. */
 
@@ -7120,22 +7229,28 @@ struct ec_params_fp_passthru {
 /* Capture types defined in bits [30..28] */
 #define FP_MODE_CAPTURE_TYPE_SHIFT 28
 #define FP_MODE_CAPTURE_TYPE_MASK  (0x7 << FP_MODE_CAPTURE_TYPE_SHIFT)
-/*
- * This enum must remain ordered, if you add new values you must ensure that
- * FP_CAPTURE_TYPE_MAX is still the last one.
+/**
+ * enum fp_capture_type - Specifies the "mode" when capturing images.
+ *
+ * @FP_CAPTURE_VENDOR_FORMAT: Capture 1-3 images and choose the best quality
+ * image (produces 'frame_size' bytes)
+ * @FP_CAPTURE_SIMPLE_IMAGE: Simple raw image capture (produces width x height x
+ * bpp bits)
+ * @FP_CAPTURE_PATTERN0: Self test pattern (e.g. checkerboard)
+ * @FP_CAPTURE_PATTERN1: Self test pattern (e.g. inverted checkerboard)
+ * @FP_CAPTURE_QUALITY_TEST: Capture for Quality test with fixed contrast
+ * @FP_CAPTURE_RESET_TEST: Capture for pixel reset value test
+ * @FP_CAPTURE_TYPE_MAX: End of enum
+ *
+ * @note This enum must remain ordered, if you add new values you must ensure
+ * that FP_CAPTURE_TYPE_MAX is still the last one.
  */
 enum fp_capture_type {
-	/* Full blown vendor-defined capture (produces 'frame_size' bytes) */
 	FP_CAPTURE_VENDOR_FORMAT = 0,
-	/* Simple raw image capture (produces width x height x bpp bits) */
 	FP_CAPTURE_SIMPLE_IMAGE = 1,
-	/* Self test pattern (e.g. checkerboard) */
 	FP_CAPTURE_PATTERN0 = 2,
-	/* Self test pattern (e.g. inverted checkerboard) */
 	FP_CAPTURE_PATTERN1 = 3,
-	/* Capture for Quality test with fixed contrast */
 	FP_CAPTURE_QUALITY_TEST = 4,
-	/* Capture for pixel reset value test */
 	FP_CAPTURE_RESET_TEST = 5,
 	FP_CAPTURE_TYPE_MAX,
 };

diff --git a/src/ec/google/chromeec/ec_message.h b/src/ec/google/chromeec/ec_message.h
@@ -1,5 +1,5 @@
 /*
- * Chromium OS Matrix Keyboard Message Protocol definitions
+ * ChromiumOS Matrix Keyboard Message Protocol definitions
  */
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
@@ -9,7 +9,7 @@
 /*
  * Command interface between EC and AP, for LPC, I2C and SPI interfaces.
  *
- * This is copied from the Chromium OS Open Source Embedded Controller code.
+ * This is copied from the ChromiumOS Open Source Embedded Controller code.
  */
 enum {
 	/* The header byte, which follows the preamble */

diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c
@@ -161,9 +161,9 @@ static void wilco_ec_resource(struct device *dev, int index,
 			      size_t base, size_t size)
 {
 	struct resource *res = new_resource(dev, index);
-	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 	res->base = base;
 	res->size = size;
+	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
 static void wilco_ec_read_resources(struct device *dev)

diff --git a/src/ec/kontron/kempld/kempld.c b/src/ec/kontron/kempld/kempld.c
@@ -12,12 +12,9 @@ static void kempld_uart_read_resources(struct device *dev)
 	static const unsigned int io_addr[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
 
 	const struct ec_kontron_kempld_config *const config = dev->chip_info;
-
-	struct resource *const res_io = new_resource(dev, 0);
-	struct resource *const res_irq = new_resource(dev, 1);
 	const unsigned int uart = dev->path.generic.subid;
 
-	if (!config || !res_io || !res_irq || uart >= KEMPLD_NUM_UARTS)
+	if (!config || uart >= KEMPLD_NUM_UARTS)
 		return;
 
 	const enum kempld_uart_io io = config->uart[uart].io;
@@ -34,13 +31,16 @@ static void kempld_uart_read_resources(struct device *dev)
 		return;
 	}
 
+	struct resource *res_io = new_resource(dev, 0);
 	res_io->base = io_addr[io];
 	res_io->size = 8;
 	res_io->flags = IORESOURCE_IO | IORESOURCE_FIXED |
 			IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+	struct resource *res_irq = new_resource(dev, 1);
 	res_irq->base = irq;
 	res_irq->size = 1;
-	res_irq->flags = IORESOURCE_IO | IORESOURCE_FIXED |
+	res_irq->flags = IORESOURCE_IRQ | IORESOURCE_FIXED |
 			 IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 
 	if (kempld_get_mutex(100) < 0)

diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c
@@ -107,11 +107,11 @@ static void enable_dev(struct device *dev)
 	struct resource *resource;
 
 	resource = new_resource(dev, EC_LENOVO_PMH7_INDEX);
-	resource->flags = IORESOURCE_IO | IORESOURCE_FIXED;
 	resource->base = EC_LENOVO_PMH7_BASE;
 	resource->size = 16;
 	resource->align = 5;
 	resource->gran = 5;
+	resource->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_ASSIGNED;
 
 	pmh7_backlight_enable(conf->backlight_enable);
 	pmh7_dock_event_enable(conf->dock_event_enable);

diff --git a/src/ec/system76/ec/Kconfig b/src/ec/system76/ec/Kconfig
@@ -6,7 +6,7 @@ config EC_SYSTEM76_EC
 config EC_SYSTEM76_EC_BAT_THRESHOLDS
 	depends on EC_SYSTEM76_EC
 	bool
-	default n
+	default y
 
 config EC_SYSTEM76_EC_COLOR_KEYBOARD
 	depends on EC_SYSTEM76_EC

diff --git a/src/ec/system76/ec/acpi/s76.asl b/src/ec/system76/ec/acpi/s76.asl
@@ -10,6 +10,8 @@
 Device (S76D) {
 	Name (_HID, "17761776")
 	Name (_UID, 0)
+	// Hide the device so that Windows does not warn about a missing driver.
+	Name (_STA, 0xB)
 
 	Method (RSET, 0, Serialized) {
 		Debug = "S76D: RSET"

diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h
@@ -210,6 +210,72 @@ enum region_space {
 	REGION_SPACE_MAX,
 };
 
+enum acpi_resource_type {
+	RSRC_TYPE_MEM = 0,
+	RSRC_TYPE_IO = 1,
+	RSRC_TYPE_BUS = 2
+};
+
+enum acpi_decode_type {
+	DECODE_10,
+	DECODE_16
+};
+
+enum acpi_read_write_type {
+	READ_ONLY,
+	READ_WRITE
+};
+
+enum acpi_cacheable_type {
+	NON_CACHEABLE,
+	CACHEABLE
+};
+
+enum acpi_resource_subtype {
+	DWORD_IO,
+	DWORD_MEMORY,
+	IO,
+	MEMORY_32_FIXED,
+	QWORD_MEMORY,
+	WORD_BUS_NUMBER
+};
+
+/* macros for ACPI Table 6.49 Memory Resource Flag (Resource Type = 0) */
+#define MEM_RSRC_FLAG_TRNSL_TYPE_STATIC		0x0
+#define MEM_RSRC_FLAG_TRNSL_TYPE_TRANSLATION	(0x1 << 5)
+#define MEM_RSRC_FLAG_ADDR_RNG_MEM		0x0
+#define MEM_RSRC_FLAG_ADDR_RNG_RSV		(0x1 << 3)
+#define MEM_RSRC_FLAG_ADDR_RNG_ACPI		(0x2 << 3)
+#define MEM_RSRC_FLAG_ADDR_RNG_NVA		(0x3 << 3)
+#define MEM_RSRC_FLAG_MEM_ATTR_NON_CACHE	0x0
+#define MEM_RSRC_FLAG_MEM_ATTR_CACHE		(0x1 << 1)
+#define MEM_RSRC_FLAG_MEM_ATTR_CACHE_WRT	(0x2 << 1)
+#define MEM_RSRC_FLAG_MEM_ATTR_CACHE_PREFETCH	(0x3 << 1)
+#define MEM_RSRC_FLAG_MEM_READ_ONLY		0x0
+#define MEM_RSRC_FLAG_MEM_READ_WRITE		0x1
+
+/* macros for ACPI Table 6.50 I/O Resource Flag (Resource Type = 1) */
+#define IO_RSRC_FLAG_ENTIRE_RANGE		0x3
+#define IO_RSRC_FLAG_ISA_ONLY			0x2
+#define IO_RSRC_FLAG_NON_ISA_ONLY		0x1
+#define IO_RSRC_FLAG_TRASL_TYPE_STATIC		0x0
+#define IO_RSRC_FLAG_TRNSL_TYPE_TRANSLATION	(0x1 << 4)
+#define IO_RSRC_FLAG_SPRS_TRASL_DENSE		0x0
+#define IO_RSRC_FLAG_SPRS_TRNSL_SPARSE		(0x1 << 5)
+
+/* macro for ACPI Table 6.51 Bus Number Range Resource Flag (Resource Type = 2) */
+#define BUS_NUM_RANGE_RESOURCE_FLAG		0x0 // reserved
+
+/* General Flags for WORD Address Space Descriptor Definition  (ACPI Table 6.47, byte 4)*/
+#define ADDR_SPACE_GENERAL_FLAG_MAX_FIXED	(0x1 << 3)
+#define ADDR_SPACE_GENERAL_FLAG_MAX_NOT_FIXED	0x0
+#define ADDR_SPACE_GENERAL_FLAG_MIN_FIXED	(0x1 << 2)
+#define ADDR_SPACE_GENERAL_FLAG_MIN_NOT_FIXED	0x0
+#define ADDR_SPACE_GENERAL_FLAG_DEC_SUB		(0x1 << 1)
+#define ADDR_SPACE_GENERAL_FLAG_DEC_POS		0x0
+#define ADDR_SPACE_GENERAL_FLAG_CONSUMER	0x10
+#define ADDR_SPACE_GENERAL_FLAG_PRODUCER	0x0
+
 struct opregion {
 	const char *name;
 	enum region_space regionspace;

diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h
@@ -64,5 +64,6 @@
 #define CPUID_METEORLAKE_A0_1		0xa06a0
 #define CPUID_METEORLAKE_A0_2		0xa06a1
 #define CPUID_RAPTORLAKE_P_J0		0xb06a2
+#define CPUID_RAPTORLAKE_P_Q0		0xb06a3
 
 #endif /* CPU_INTEL_CPU_IDS_H */
diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h
@@ -4,6 +4,10 @@
 
 #include <stdint.h>
 
+/* Find the microcode and reload the microcode if SoC has RELOAD_MICROCODE_PATCH
+ * config selected. */
+void intel_reload_microcode(void);
+
 void intel_update_microcode_from_cbfs(void);
 /* Find a microcode that matches the revision and platform family returning
  * NULL if none found. The found microcode is cached for faster access on

diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h
@@ -176,6 +176,7 @@ void stop_this_cpu(void);
 #endif
 
 void enable_lapic(void);
+void enable_lapic_mode(bool try_set_x2apic);
 void disable_lapic(void);
 void setup_lapic_interrupts(void);
 

diff --git a/src/include/device/device.h b/src/include/device/device.h
@@ -74,7 +74,6 @@ static inline void noop_read_resources(struct device *dev) {}
 static inline void noop_set_resources(struct device *dev) {}
 
 struct bus {
-
 	DEVTREE_CONST struct device *dev;	/* This bridge device */
 	DEVTREE_CONST struct device *children;	/* devices behind this bridge */
 	DEVTREE_CONST struct bus *next;    /* The next bridge on this device */
@@ -265,23 +264,6 @@ void show_one_resource(int debug_level, struct device *dev,
 void show_all_devs_resources(int debug_level, const char *msg);
 
 /* Debug macros */
-#if CONFIG(DEBUG_RESOURCES)
-#include <console/console.h>
-#define LOG_MEM_RESOURCE(type, dev, index, base_kb, size_kb) \
-	printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, " \
-		"end: 0x%llx, size_kb: 0x%llx\n", \
-		__func__, __LINE__, type, dev_path(dev), index, (base_kb << 10), \
-		(base_kb << 10) + (size_kb << 10) - 1, size_kb)
-
-#define LOG_IO_RESOURCE(type, dev, index, base, size) \
-	printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, " \
-		"end: 0x%llx, size: 0x%llx\n", \
-		__func__, __LINE__, type, dev_path(dev), index, base, base + size - 1, size)
-#else /* DEBUG_RESOURCES*/
-#define LOG_MEM_RESOURCE(type, dev, index, base_kb, size_kb)
-#define LOG_IO_RESOURCE(type, dev, index, base, size)
-#endif /* DEBUG_RESOURCES*/
-
 #if CONFIG(DEBUG_FUNC)
 #include <console/console.h>
 #define DEV_FUNC_ENTER(dev) \
@@ -307,35 +289,139 @@ void pci_domain_read_resources(struct device *dev);
 void pci_domain_set_resources(struct device *dev);
 void pci_domain_scan_bus(struct device *dev);
 
-void fixed_io_resource(struct device *dev, unsigned long index,
-		unsigned long base, unsigned long size);
+void mmconf_resource(struct device *dev, unsigned long index);
 
-void fixed_mem_resource(struct device *dev, unsigned long index,
-		  unsigned long basek, unsigned long sizek, unsigned long type);
+/* These are temporary resource constructors to get us through the
+   migration away from open-coding all the IORESOURCE_FLAGS. */
 
-void mmconf_resource(struct device *dev, unsigned long index);
+const struct resource *fixed_resource_range_idx(struct device *dev, unsigned long index,
+					    uint64_t base, uint64_t size,
+					    unsigned long flags);
+
+static inline
+const struct resource *fixed_mem_range_flags(struct device *dev, unsigned long index,
+					    uint64_t base, uint64_t size,
+					    unsigned long flags)
+{
+	return fixed_resource_range_idx(dev, index, base, size, IORESOURCE_MEM | flags);
+}
+
+static inline
+const struct resource *fixed_mem_from_to_flags(struct device *dev, unsigned long index,
+					uint64_t base, uint64_t end, unsigned long flags)
+{
+	if (end <= base)
+		return NULL;
+	return fixed_mem_range_flags(dev, index, base, end - base, flags);
+}
+
+static inline
+const struct resource *ram_range(struct device *dev, unsigned long index, uint64_t base,
+				      uint64_t size)
+{
+	return fixed_mem_range_flags(dev, index, base, size, IORESOURCE_CACHEABLE | IORESOURCE_STORED);
+}
+
+static inline
+const struct resource *ram_from_to(struct device *dev, unsigned long index, uint64_t base,
+				 uint64_t end)
+{
+	if (end <= base)
+		return NULL;
+	return ram_range(dev, index, base, end - base);
+}
+
+static inline
+const struct resource *reserved_ram_range(struct device *dev, unsigned long index,
+					       uint64_t base, uint64_t size)
+{
+	return fixed_mem_range_flags(dev, index, base, size, IORESOURCE_CACHEABLE |
+				    IORESOURCE_RESERVE | IORESOURCE_STORED);
+}
+
+static inline
+const struct resource *reserved_ram_from_to(struct device *dev, unsigned long index,
+					  uint64_t base, uint64_t end)
+{
+	if (end <= base)
+		return NULL;
+	return reserved_ram_range(dev, index, base, end - base);
+}
 
-/* It is the caller's responsibility to adjust regions such that ram_resource()
- * and mmio_resource() do not overlap.
+static inline
+const struct resource *mmio_range(struct device *dev, unsigned long index, uint64_t base,
+				       uint64_t size)
+{
+	return fixed_mem_range_flags(dev, index, base, size, IORESOURCE_RESERVE | IORESOURCE_STORED);
+}
+
+static inline
+const struct resource *mmio_from_to(struct device *dev, unsigned long index, uint64_t base,
+				  uint64_t end)
+{
+	if (end <= base)
+		return NULL;
+	return mmio_range(dev, index, base, end - base);
+}
+
+const struct resource *lower_ram_end(struct device *dev, unsigned long index, uint64_t end);
+const struct resource *upper_ram_end(struct device *dev, unsigned long index, uint64_t end);
+
+#define bad_ram_range(...)	reserved_ram_range(__VA_ARGS__)
+#define uma_range(...)		mmio_range(__VA_ARGS__)
+#define uma_from_to(...)	mmio_from_to(__VA_ARGS__)
+
+static inline
+const struct resource *fixed_io_range_flags(struct device *dev, unsigned long index,
+			uint16_t base, uint16_t size, unsigned long flags)
+{
+	return fixed_resource_range_idx(dev, index, base, size, IORESOURCE_IO | flags);
+}
+
+static inline
+const struct resource *fixed_io_from_to_flags(struct device *dev, unsigned long index,
+				      uint16_t base, uint16_t end, unsigned long flags)
+{
+	if (end <= base)
+		return NULL;
+	return fixed_io_range_flags(dev, index, base, end - base, flags);
+}
+
+static inline
+const struct resource *fixed_io_range_reserved(struct device *dev, unsigned long index,
+				      uint16_t base, uint16_t size)
+{
+	return fixed_io_range_flags(dev, index, base, size, IORESOURCE_RESERVE);
+}
+
+/* Compatibility code */
+
+static inline void fixed_mem_resource_kb(struct device *dev, unsigned long index,
+			unsigned long basek, unsigned long sizek,
+			unsigned long flags)
+{
+	fixed_mem_range_flags(dev, index, ((uint64_t)basek) << 10,
+		((uint64_t)sizek) << 10, IORESOURCE_STORED | flags);
+}
+
+/* It is the caller's responsibility to adjust regions such that ram_resource_kb()
+ * and mmio_resource_kb() do not overlap.
  */
-#define ram_resource(dev, idx, basek, sizek) \
-	fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE)
+#define ram_resource_kb(dev, idx, basek, sizek) \
+	fixed_mem_resource_kb(dev, idx, basek, sizek, IORESOURCE_CACHEABLE)
 
-#define reserved_ram_resource(dev, idx, basek, sizek) \
-	fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE \
+#define reserved_ram_resource_kb(dev, idx, basek, sizek) \
+	fixed_mem_resource_kb(dev, idx, basek, sizek, IORESOURCE_CACHEABLE \
 		| IORESOURCE_RESERVE)
 
-#define bad_ram_resource(dev, idx, basek, sizek) \
-	reserved_ram_resource((dev), (idx), (basek), (sizek))
-
-#define uma_resource(dev, idx, basek, sizek) \
-	fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE)
+#define bad_ram_resource_kb(dev, idx, basek, sizek) \
+	reserved_ram_resource_kb((dev), (idx), (basek), (sizek))
 
-#define mmio_resource(dev, idx, basek, sizek) \
-	fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE)
+#define uma_resource_kb(dev, idx, basek, sizek) \
+	fixed_mem_resource_kb(dev, idx, basek, sizek, IORESOURCE_RESERVE)
 
-#define io_resource(dev, idx, base, size) \
-	fixed_io_resource(dev, idx, base, size)
+#define mmio_resource_kb(dev, idx, basek, sizek) \
+	fixed_mem_resource_kb(dev, idx, basek, sizek, IORESOURCE_RESERVE)
 
 void tolm_test(void *gp, struct device *dev, struct resource *new);
 u32 find_pci_tolm(struct bus *bus);

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
@@ -4009,11 +4009,14 @@
 #define PCI_DID_INTEL_ADL_N_GT3				0x46D2
 #define PCI_DID_INTEL_MTL_M_GT2				0x7d40
 #define PCI_DID_INTEL_MTL_P_GT2_1			0x7d50
-#define PCI_DID_INTEL_MTL_P_GT2_2			0x7d60
+#define PCI_DID_INTEL_MTL_P_GT2_2			0x7d55
+#define PCI_DID_INTEL_MTL_P_GT2_3			0x7d60
 #define PCI_DID_INTEL_RPL_P_GT1				0xa720
 #define PCI_DID_INTEL_RPL_P_GT2				0xa7a8
 #define PCI_DID_INTEL_RPL_P_GT3				0xa7a0
-
+#define PCI_DID_INTEL_RPL_P_GT4				0xa7a9
+#define PCI_DID_INTEL_RPL_P_GT5				0xa7a1
+#define PCI_DID_INTEL_RPL_P_GT6				0xa721
 
 /* Intel Northbridge Ids */
 #define PCI_DID_INTEL_APL_NB			0x5af0
@@ -4133,8 +4136,10 @@
 #define PCI_DID_INTEL_MTL_M_ID			0x7D00
 #define PCI_DID_INTEL_MTL_P_ID_1		0x7D01
 #define PCI_DID_INTEL_MTL_P_ID_2		0x7D02
+#define PCI_DID_INTEL_MTL_P_ID_3		0x7d14
 #define PCI_DID_INTEL_RPL_P_ID_1		0xa706
 #define PCI_DID_INTEL_RPL_P_ID_2		0xa707
+#define PCI_DID_INTEL_RPL_P_ID_3		0xa708
 
 /* Intel SMBUS device Ids */
 #define PCI_DID_INTEL_LPT_H_SMBUS			0x8c22

diff --git a/src/include/program_loading.h b/src/include/program_loading.h
@@ -152,7 +152,7 @@ enum cb_err legacy_romstage_select_and_load(struct prog *romstage);
  */
 void preload_ramstage(void);
 /* Run ramstage from romstage. */
-void run_ramstage(void);
+void __noreturn run_ramstage(void);
 
 /***********************
  *   PAYLOAD LOADING   *

diff --git a/src/lib/fit.c b/src/lib/fit.c
@@ -287,35 +287,12 @@ struct mem_map {
 static bool walk_memory_table(const struct range_entry *r, void *arg)
 {
 	struct mem_map *arg_map = arg;
+	struct memranges *ranges;
+	enum bootmem_type tag;
 
-	/*
-	 * Kernel likes its available memory areas at least 1MB
-	 * aligned, let's trim the regions such that unaligned padding
-	 * is added to reserved memory.
-	 */
-	if (range_entry_tag(r) == BM_MEM_RAM) {
-		uint64_t new_start = ALIGN_UP(range_entry_base(r), 1 * MiB);
-		uint64_t new_end = ALIGN_DOWN(range_entry_end(r), 1 * MiB);
-
-		if (new_start != range_entry_base(r))
-			memranges_insert(&arg_map->reserved,
-					 range_entry_base(r),
-					 new_start - range_entry_base(r),
-					 BM_MEM_RESERVED);
-
-		if (new_start != new_end)
-			memranges_insert(&arg_map->mem, new_start,
-					 new_end - new_start, BM_MEM_RAM);
-
-		if (new_end != range_entry_end(r))
-			memranges_insert(&arg_map->reserved, new_end,
-					 range_entry_end(r) - new_end,
-					 BM_MEM_RESERVED);
-	} else
-		memranges_insert(&arg_map->reserved, range_entry_base(r),
-				 range_entry_size(r),
-				 BM_MEM_RESERVED);
-
+	ranges = range_entry_tag(r) == BM_MEM_RAM ? &arg_map->mem : &arg_map->reserved;
+	tag = range_entry_tag(r) == BM_MEM_RAM ? BM_MEM_RAM : BM_MEM_RESERVED;
+	memranges_insert(ranges, range_entry_base(r), range_entry_size(r), tag);
 	return true;
 }
 

diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c
@@ -82,7 +82,7 @@ void preload_ramstage(void)
 
 	cbfs_preload(CONFIG_CBFS_PREFIX "/ramstage");
 }
-void run_ramstage(void)
+void __noreturn run_ramstage(void)
 {
 	struct prog ramstage =
 		PROG_INIT(PROG_RAMSTAGE, CONFIG_CBFS_PREFIX "/ramstage");

diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb
@@ -6,7 +6,6 @@ chip soc/intel/skylake
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |
 	#+-------------------+---------------------------+
-	#| chipset_lockdown  | CHIPSET_LOCKDOWN_COREBOOT |
 	#| I2C0              | Touchscreen               |
 	#| I2C1              | Touchpad                  |
 	#+-------------------+---------------------------+

diff --git a/src/mainboard/amd/bilby/board.fmd b/src/mainboard/amd/bilby/board.fmd
@@ -1,7 +1,9 @@
 FLASH@0xFF000000 16M {
 	BIOS {
 		RW_MRC_CACHE 64K
-		FMAP 4K
 		COREBOOT(CBFS)
+		PSP_NVRAM(PRESERVE) 128K
+		PSP_RPMC_NVRAM(PRESERVE) 64K
+		FMAP 4K
 	}
 }
diff --git a/src/mainboard/amd/gardenia/irq_tables.c b/src/mainboard/amd/gardenia/irq_tables.c
@@ -43,7 +43,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
 
 	pirq = (void *)(addr);
-	v = (u8 *) (addr);
+	v = (u8 *)(addr);
 
 	pirq->signature = PIRQ_SIGNATURE;
 	pirq->version = PIRQ_VERSION;

diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c
@@ -7,8 +7,8 @@
 #include <SB800.h>
 #include <southbridge/amd/cimx/sb800/gpio_oem.h>
 
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
-static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr);
+static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data, VOID *ConfigPtr);
+static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr);
 
 const BIOS_CALLOUT_STRUCT BiosCallouts[] =
 {
@@ -25,7 +25,7 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
 const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
 
 /*  Call the host environment interface to provide a user hook opportunity. */
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
+static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
 	AGESA_STATUS      Status;
 	MEM_DATA_STRUCT   *MemData;
@@ -38,65 +38,65 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
 	Status  = AGESA_SUCCESS;
 	GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
 
-	Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+	Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
 	Data8 &= ~BIT5;
-	TempData8  = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+	TempData8  = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
 	TempData8 &= 0x03;
 	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
+	Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, TempData8);
 
-	Data8 |= BIT2+BIT3;
+	Data8 |= BIT2 | BIT3;
 	Data8 &= ~BIT4;
-	TempData8  = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+	TempData8  = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
 	TempData8 &= 0x23;
 	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
+	Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, TempData8);
 
-	Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+	Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
 	Data8 &= ~BIT5;
-	TempData8  = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+	TempData8  = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
 	TempData8 &= 0x03;
 	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
+	Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, TempData8);
 
-	Data8 |= BIT2+BIT3;
+	Data8 |= BIT2 | BIT3;
 	Data8 &= ~BIT4;
-	TempData8  = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+	TempData8  = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
 	TempData8 &= 0x23;
 	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
+	Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, TempData8);
 
 	switch (MemData->ParameterListPtr->DDR3Voltage) {
 	case VOLT1_35:
-		Data8 =  Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+		Data8 =  Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
 		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-		Data8 =  Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+		Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
+		Data8 =  Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
 		Data8 |= (UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+		Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
 		break;
 	case VOLT1_25:
-		Data8 =  Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+		Data8 =  Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
 		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-		Data8 =  Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+		Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
+		Data8 =  Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
 		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+		Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
 		break;
 	case VOLT1_5:
 	default:
-		Data8 =  Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+		Data8 =  Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
 		Data8 |= (UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-		Data8 =  Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+		Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
+		Data8 =  Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
 		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+		Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
 	}
 	return Status;
 }
 
 /* PCIE slot reset control */
-static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
+static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
 	AGESA_STATUS Status;
 	PCIe_SLOT_RESET_INFO  *ResetInfo;
@@ -111,53 +111,53 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
 	case 4:
 		switch (ResetInfo->ResetControl) {
 		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
+			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG21);
 			Data8 &= ~(UINT8)BIT6;
 			/* MXM_GPIO0. GPIO21 */
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
+			Write64Mem8(GpioMmioAddr + SB_GPIO_REG21, Data8);
 			Status = AGESA_SUCCESS;
 			break;
 		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
+			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG21);
 			Data8 |= BIT6;
 			/* MXM_GPIO0. GPIO21 */
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
+			Write64Mem8(GpioMmioAddr + SB_GPIO_REG21, Data8);
 			Status = AGESA_SUCCESS;
 			break;
 		}
 		break;
 	case 6:
 		switch (ResetInfo->ResetControl) {
 		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG25);
 			Data8 &= ~(UINT8)BIT6;
 			/* PCIE_RST#_LAN, GPIO25 */
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
+			Write64Mem8(GpioMmioAddr + SB_GPIO_REG25, Data8);
 			Status = AGESA_SUCCESS;
 			break;
 		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG25);
 			Data8 |= BIT6;
 			/* PCIE_RST#_LAN, GPIO25 */
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
+			Write64Mem8(GpioMmioAddr + SB_GPIO_REG25, Data8);
 			Status = AGESA_SUCCESS;
 			break;
 		}
 		break;
 	case 7:
 		switch (ResetInfo->ResetControl) {
 		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
+			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG02);
 			Data8 &= ~(UINT8)BIT6;
 			/* MPCIE_RST0, GPIO02 */
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
+			Write64Mem8(GpioMmioAddr + SB_GPIO_REG02, Data8);
 			Status = AGESA_SUCCESS;
 			break;
 		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
+			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG02);
 			Data8 |= BIT6;
 			/* MPCIE_RST0, GPIO02 */
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
+			Write64Mem8(GpioMmioAddr + SB_GPIO_REG02, Data8);
 			Status = AGESA_SUCCESS;
 			break;
 		}

diff --git a/src/mainboard/amd/inagua/irq_tables.c b/src/mainboard/amd/inagua/irq_tables.c
@@ -43,7 +43,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
 
 	pirq = (void *)(addr);
-	v = (u8 *) (addr);
+	v = (u8 *)(addr);
 
 	pirq->signature = PIRQ_SIGNATURE;
 	pirq->version = PIRQ_VERSION;

diff --git a/src/mainboard/amd/olivehill/irq_tables.c b/src/mainboard/amd/olivehill/irq_tables.c
@@ -43,7 +43,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
 
 	pirq = (void *)(addr);
-	v = (u8 *) (addr);
+	v = (u8 *)(addr);
 
 	pirq->signature = PIRQ_SIGNATURE;
 	pirq->version = PIRQ_VERSION;

diff --git a/src/mainboard/amd/parmer/irq_tables.c b/src/mainboard/amd/parmer/irq_tables.c
@@ -43,7 +43,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
 
 	pirq = (void *)(addr);
-	v = (u8 *) (addr);
+	v = (u8 *)(addr);
 
 	pirq->signature = PIRQ_SIGNATURE;
 	pirq->version = PIRQ_VERSION;

diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c
@@ -6,8 +6,8 @@
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 #include <SB800.h>
 
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
-static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr);
+static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data, VOID *ConfigPtr);
+static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr);
 
 const BIOS_CALLOUT_STRUCT BiosCallouts[] =
 {
@@ -24,7 +24,7 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
 const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
 
 /*	Call the host environment interface to provide a user hook opportunity. */
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
+static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
 	// Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage.
 	// Make sure the right speed settings are selected.
@@ -33,7 +33,7 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
 }
 
 /* PCIE slot reset control */
-static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
+static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
 	AGESA_STATUS Status;
 	PCIe_SLOT_RESET_INFO	*ResetInfo;
@@ -49,15 +49,15 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
 	case 46:	// GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot
 		switch (ResetInfo->ResetControl) {
 		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50);
+			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG50);
 			Data8 &= ~(UINT8)BIT6;
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8);
+			Write64Mem8(GpioMmioAddr + SB_GPIO_REG50, Data8);
 			Status = AGESA_SUCCESS;
 			break;
 		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50);
+			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG50);
 			Data8 |= BIT6;
-			Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8);
+			Write64Mem8(GpioMmioAddr + SB_GPIO_REG50, Data8);
 			Status = AGESA_SUCCESS;
 			break;
 		}

diff --git a/src/mainboard/amd/persimmon/irq_tables.c b/src/mainboard/amd/persimmon/irq_tables.c
@@ -43,7 +43,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
 
 	pirq = (void *)(addr);
-	v = (u8 *) (addr);
+	v = (u8 *)(addr);
 
 	pirq->signature = PIRQ_SIGNATURE;
 	pirq->version = PIRQ_VERSION;

diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c
@@ -25,36 +25,36 @@
  */
 static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
 	/* INTA# - INTH# */
-	[0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
+	[0x00] = 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B,
 	/* Misc-nil,0,1,2, INT from Serial irq */
-	[0x08] = 0x00,0xF0,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+	[0x08] = 0x00, 0xF0, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
 	/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon */
-	[0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F,
+	[0x10] = 0x1F, 0x1F, 0x1F, 0x0A, 0x1F, 0x1F, 0x1F,
 	/* IMC INT0 - 5 */
-	[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
+	[0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
 	/* USB Devs 18/19/20/22 INTA-C */
-	[0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,
+	[0x30] = 0x0A, 0x0B, 0x0A, 0x0B, 0x0A, 0x0B, 0x0A,
 	/* IDE, SATA */
-	[0x40] = 0x0B,0x0B,
+	[0x40] = 0x0B, 0x0B,
 	/* GPPInt0 - 3 */
-	[0x50] = 0x0A,0x0B,0x0A,0x0B
+	[0x50] = 0x0A, 0x0B, 0x0A, 0x0B
 };
 
 static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
 	/* INTA# - INTH# */
-	[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
+	[0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
 	/* Misc-nil,0,1,2, INT from Serial irq */
-	[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+	[0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
 	/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon */
-	[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,
+	[0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F,
 	/* IMC INT0 - 5 */
-	[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
+	[0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
 	/* USB Devs 18/19/22/20 INTA-C */
-	[0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,
+	[0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12,
 	/* IDE, SATA */
-	[0x40] = 0x11,0x13,
+	[0x40] = 0x11, 0x13,
 	/* GPPInt0 - 3 */
-	[0x50] = 0x10,0x11,0x12,0x13
+	[0x50] = 0x10, 0x11, 0x12, 0x13
 };
 
 /*

diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c
@@ -7,8 +7,8 @@
 #include <SB800.h>
 #include <southbridge/amd/cimx/sb800/gpio_oem.h>
 
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
-static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr);
+static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data, VOID *ConfigPtr);
+static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr);
 
 const BIOS_CALLOUT_STRUCT BiosCallouts[] =
 {
@@ -25,7 +25,7 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
 const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
 
 /* Call the host environment interface to provide a user hook opportunity. */
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
+static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
 	AGESA_STATUS      Status;
 	MEM_DATA_STRUCT   *MemData;
@@ -38,65 +38,65 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
 	Status = AGESA_SUCCESS;
 	GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
 
-	Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+	Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
 	Data8 &= ~BIT5;
-	TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+	TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
 	TempData8 &= 0x03;
 	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
+	Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, TempData8);
 
-	Data8 |= BIT2+BIT3;
+	Data8 |= BIT2 | BIT3;
 	Data8 &= ~BIT4;
-	TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+	TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
 	TempData8 &= 0x23;
 	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
+	Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, TempData8);
 
-	Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+	Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
 	Data8 &= ~BIT5;
-	TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+	TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
 	TempData8 &= 0x03;
 	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
+	Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, TempData8);
 
-	Data8 |= BIT2+BIT3;
+	Data8 |= BIT2 | BIT3;
 	Data8 &= ~BIT4;
-	TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+	TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
 	TempData8 &= 0x23;
 	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
+	Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, TempData8);
 
 	switch (MemData->ParameterListPtr->DDR3Voltage) {
 	case VOLT1_35:
-		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
 		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+		Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
+		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
 		Data8 |= (UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+		Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
 		break;
 	case VOLT1_25:
-		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
 		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+		Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
+		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
 		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+		Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
 		break;
 	case VOLT1_5:
 	default:
-		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
 		Data8 |= (UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+		Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
+		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
 		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+		Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
 	}
 	return Status;
 }
 
 /* PCIE slot reset control */
-static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
+static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
 	AGESA_STATUS           Status;
 	PCIe_SLOT_RESET_INFO   *ResetInfo;
@@ -111,53 +111,53 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
 	case 4:
 		switch (ResetInfo->ResetControl) {
 		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
+			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG21);
 			Data8 &= ~(UINT8)BIT6;
 			/* MXM_GPIO0. GPIO21 */
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
+			Write64Mem8(GpioMmioAddr + SB_GPIO_REG21, Data8);
 			Status = AGESA_SUCCESS;
 			break;
 		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
+			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG21);
 			Data8 |= BIT6;
 			/* MXM_GPIO0. GPIO21 */
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
+			Write64Mem8(GpioMmioAddr + SB_GPIO_REG21, Data8);
 			Status = AGESA_SUCCESS;
 			break;
 		}
 		break;
 	case 6:
 		switch (ResetInfo->ResetControl) {
 		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG25);
 			Data8 &= ~(UINT8)BIT6;
 			/* PCIE_RST#_LAN, GPIO25 */
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
+			Write64Mem8(GpioMmioAddr + SB_GPIO_REG25, Data8);
 			Status = AGESA_SUCCESS;
 			break;
 		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG25);
 			Data8 |= BIT6;
 			/* PCIE_RST#_LAN, GPIO25 */
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
+			Write64Mem8(GpioMmioAddr + SB_GPIO_REG25, Data8);
 			Status = AGESA_SUCCESS;
 			break;
 		}
 		break;
 	case 7:
 		switch (ResetInfo->ResetControl) {
 		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
+			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG02);
 			Data8 &= ~(UINT8)BIT6;
 			/* MPCIE_RST0, GPIO02 */
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
+			Write64Mem8(GpioMmioAddr + SB_GPIO_REG02, Data8);
 			Status = AGESA_SUCCESS;
 			break;
 		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
+			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG02);
 			Data8 |= BIT6;
 			/* MPCIE_RST0, GPIO02 */
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
+			Write64Mem8(GpioMmioAddr + SB_GPIO_REG02, Data8);
 			Status = AGESA_SUCCESS;
 			break;
 		}

diff --git a/src/mainboard/amd/south_station/irq_tables.c b/src/mainboard/amd/south_station/irq_tables.c
@@ -43,7 +43,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
 
 	pirq = (void *)(addr);
-	v = (u8 *) (addr);
+	v = (u8 *)(addr);
 
 	pirq->signature = PIRQ_SIGNATURE;
 	pirq->version = PIRQ_VERSION;

diff --git a/src/mainboard/amd/thatcher/irq_tables.c b/src/mainboard/amd/thatcher/irq_tables.c
@@ -43,7 +43,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
 
 	pirq = (void *)(addr);
-	v = (u8 *) (addr);
+	v = (u8 *)(addr);
 
 	pirq->signature = PIRQ_SIGNATURE;
 	pirq->version = PIRQ_VERSION;

diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c
@@ -7,8 +7,8 @@
 #include <SB800.h>
 #include <southbridge/amd/cimx/sb800/gpio_oem.h>
 
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
-static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr);
+static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data, VOID *ConfigPtr);
+static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr);
 
 const BIOS_CALLOUT_STRUCT BiosCallouts[] =
 {
@@ -25,7 +25,7 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
 const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
 
 /* Call the host environment interface to provide a user hook opportunity. */
-static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
+static AGESA_STATUS board_BeforeDramInit(UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
 	AGESA_STATUS       Status;
 	MEM_DATA_STRUCT    *MemData;
@@ -38,65 +38,65 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigP
 	Status = AGESA_SUCCESS;
 	GpioMmioAddr = (uintptr_t)acpimmio_gpio_100;
 
-	Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+	Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
 	Data8 &= ~BIT5;
-	TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+	TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
 	TempData8 &= 0x03;
 	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
+	Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, TempData8);
 
-	Data8 |= BIT2+BIT3;
+	Data8 |= BIT2 | BIT3;
 	Data8 &= ~BIT4;
-	TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+	TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
 	TempData8 &= 0x23;
 	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
+	Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, TempData8);
 
-	Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+	Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
 	Data8 &= ~BIT5;
-	TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+	TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
 	TempData8 &= 0x03;
 	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
+	Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, TempData8);
 
-	Data8 |= BIT2+BIT3;
+	Data8 |= BIT2 | BIT3;
 	Data8 &= ~BIT4;
-	TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+	TempData8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
 	TempData8 &= 0x23;
 	TempData8 |= Data8;
-	Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8);
+	Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, TempData8);
 
 	switch (MemData->ParameterListPtr->DDR3Voltage) {
 	case VOLT1_35:
-		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
 		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+		Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
+		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
 		Data8 |= (UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+		Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
 		break;
 	case VOLT1_25:
-		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
 		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+		Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
+		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
 		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+		Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
 		break;
 	case VOLT1_5:
 	default:
-		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178);
+		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG178);
 		Data8 |= (UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
-		Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179);
+		Write64Mem8(GpioMmioAddr + SB_GPIO_REG178, Data8);
+		Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG179);
 		Data8 &= ~(UINT8)BIT6;
-		Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
+		Write64Mem8(GpioMmioAddr + SB_GPIO_REG179, Data8);
 	}
 	return Status;
 }
 
 /* PCIE slot reset control */
-static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
+static AGESA_STATUS board_GnbPcieSlotReset(UINT32 Func, UINTN Data, VOID *ConfigPtr)
 {
 	AGESA_STATUS            Status;
 	PCIe_SLOT_RESET_INFO    *ResetInfo;
@@ -111,53 +111,53 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *Confi
 	case 4:
 		switch (ResetInfo->ResetControl) {
 		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
+			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG21);
 			Data8 &= ~(UINT8)BIT6;
 			/* MXM_GPIO0. GPIO21 */
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
+			Write64Mem8(GpioMmioAddr + SB_GPIO_REG21, Data8);
 			Status = AGESA_SUCCESS;
 			break;
 		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
+			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG21);
 			Data8 |= BIT6;
 			/* MXM_GPIO0. GPIO21 */
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8);
+			Write64Mem8(GpioMmioAddr + SB_GPIO_REG21, Data8);
 			Status = AGESA_SUCCESS;
 			break;
 		}
 		break;
 	case 6:
 		switch (ResetInfo->ResetControl) {
 		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG25);
 			Data8 &= ~(UINT8)BIT6;
 			/* PCIE_RST#_LAN, GPIO25 */
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
+			Write64Mem8(GpioMmioAddr + SB_GPIO_REG25, Data8);
 			Status = AGESA_SUCCESS;
 			break;
 		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
+			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG25);
 			Data8 |= BIT6;
 			/* PCIE_RST#_LAN, GPIO25 */
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8);
+			Write64Mem8(GpioMmioAddr + SB_GPIO_REG25, Data8);
 			Status = AGESA_SUCCESS;
 			break;
 		}
 		break;
 	case 7:
 		switch (ResetInfo->ResetControl) {
 		case AssertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
+			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG02);
 			Data8 &= ~(UINT8)BIT6;
 			/* MPCIE_RST0, GPIO02 */
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
+			Write64Mem8(GpioMmioAddr + SB_GPIO_REG02, Data8);
 			Status = AGESA_SUCCESS;
 			break;
 		case DeassertSlotReset:
-			Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02);
+			Data8 = Read64Mem8(GpioMmioAddr + SB_GPIO_REG02);
 			Data8 |= BIT6;
 			/* MPCIE_RST0, GPIO02 */
-			Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8);
+			Write64Mem8(GpioMmioAddr + SB_GPIO_REG02, Data8);
 			Status = AGESA_SUCCESS;
 			break;
 		}

diff --git a/src/mainboard/amd/union_station/irq_tables.c b/src/mainboard/amd/union_station/irq_tables.c
@@ -43,7 +43,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
 	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
 
 	pirq = (void *)(addr);
-	v = (u8 *) (addr);
+	v = (u8 *)(addr);
 
 	pirq->signature = PIRQ_SIGNATURE;
 	pirq->version = PIRQ_VERSION;

diff --git a/src/mainboard/clevo/cml-u/Kconfig b/src/mainboard/clevo/cml-u/Kconfig
@@ -49,10 +49,6 @@ config UART_FOR_CONSOLE
 	int
 	default 2
 
-config MAX_CPUS
-	int
-	default 8 if BOARD_CLEVO_L140CU_BASE
-
 config DIMM_MAX
 	default 2 if BOARD_CLEVO_L140CU_BASE
 
@@ -76,4 +72,7 @@ config SEABIOS_PS2_TIMEOUT
 	depends on PAYLOAD_SEABIOS
 	default 500
 
+config EC_SYSTEM76_EC_BAT_THRESHOLDS
+	default n if BOARD_CLEVO_L140CU_BASE
+
 endif
diff --git a/src/mainboard/emulation/qemu-aarch64/mainboard.c b/src/mainboard/emulation/qemu-aarch64/mainboard.c
@@ -13,7 +13,7 @@ void bootmem_platform_add_ranges(void)
 static void mainboard_enable(struct device *dev)
 {
 	int ram_size_mb = probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB);
-	ram_resource(dev, 0, (uintptr_t)_dram / KiB, ram_size_mb * KiB);
+	ram_resource_kb(dev, 0, (uintptr_t)_dram / KiB, ram_size_mb * KiB);
 }
 
 struct chip_operations mainboard_ops = {

diff --git a/src/mainboard/emulation/qemu-armv7/mainboard.c b/src/mainboard/emulation/qemu-armv7/mainboard.c
@@ -39,7 +39,7 @@ static void mainboard_enable(struct device *dev)
 
 	discovered = probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB);
 	printk(BIOS_DEBUG, "%d MiB of RAM discovered\n", discovered);
-	ram_resource(dev, 0, 0x60000000 >> 10, discovered << 10);
+	ram_range(dev, 0, 0x60000000, discovered * MiB);
 	init_gfx();
 }
 

diff --git a/src/mainboard/emulation/qemu-armv7/romstage.c b/src/mainboard/emulation/qemu-armv7/romstage.c
@@ -3,12 +3,16 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <program_loading.h>
+#include <romstage_common.h>
 
 void main(void)
 {
 	console_init();
+	romstage_main();
+}
 
+void __noreturn romstage_main(void)
+{
 	cbmem_initialize_empty();
-
 	run_ramstage();
 }
diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c
@@ -37,8 +37,7 @@ static void qemu_nb_read_resources(struct device *dev)
 
 	if (CONFIG(ARCH_RAMSTAGE_X86_64)) {
 		/* Reserve page tables in DRAM. FIXME: Remove once x86_64 page tables reside in CBMEM */
-		reserved_ram_resource(dev, 0, CONFIG_ARCH_X86_64_PGTBL_LOC / KiB,
-			(6 * 0x1000) / KiB);
+		reserved_ram_range(dev, 0, CONFIG_ARCH_X86_64_PGTBL_LOC, 6 * 0x1000);
 	}
 }
 

diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c
@@ -47,7 +47,7 @@ static void cpu_pci_domain_read_resources(struct device *dev)
 	int i440fx = (nbid == 0x1237);
 	int q35    = (nbid == 0x29c0);
 	struct resource *res;
-	unsigned long tomk = 0, high;
+	uint64_t tomk = 0;
 	int idx = 10;
 	FWCfgFile f;
 
@@ -65,12 +65,10 @@ static void cpu_pci_domain_read_resources(struct device *dev)
 				       list[i].address, list[i].length);
 				if (list[i].address == 0) {
 					tomk = list[i].length / 1024;
-					ram_resource(dev, idx++, 0, 640);
-					ram_resource(dev, idx++, 768, tomk - 768);
+					ram_from_to(dev, idx++, 0, 0xa0000);
+					ram_from_to(dev, idx++, 0xc0000, tomk * KiB);
 				} else {
-					ram_resource(dev, idx++,
-						     list[i].address / 1024,
-						     list[i].length / 1024);
+					ram_range(dev, idx++, list[i].address, list[i].length);
 				}
 				break;
 			case 2: /* reserved */
@@ -94,15 +92,16 @@ static void cpu_pci_domain_read_resources(struct device *dev)
 	if (!tomk) {
 		/* qemu older than 1.7, or reading etc/e820 failed. Fallback to cmos. */
 		tomk = qemu_get_memory_size();
-		high = qemu_get_high_memory_size();
-		printk(BIOS_DEBUG, "QEMU: cmos: %lu MiB RAM below 4G.\n", tomk / 1024);
-		printk(BIOS_DEBUG, "QEMU: cmos: %lu MiB RAM above 4G.\n", high / 1024);
+		uint64_t high = qemu_get_high_memory_size();
+		printk(BIOS_DEBUG, "QEMU: cmos: %llu MiB RAM below 4G.\n", tomk / 1024);
+		printk(BIOS_DEBUG, "QEMU: cmos: %llu MiB RAM above 4G.\n", high / 1024);
 
 		/* Report the memory regions. */
-		ram_resource(dev, idx++, 0, 640);
-		ram_resource(dev, idx++, 768, tomk - 768);
+		ram_from_to(dev, idx++, 0, 0xa0000);
+		ram_from_to(dev, idx++, 0xc0000, tomk * KiB);
+
 		if (high)
-			ram_resource(dev, idx++, 4 * 1024 * 1024, high);
+			upper_ram_end(dev, idx++, 4ull * GiB + high * KiB);
 	}
 
 	/* Reserve I/O ports used by QEMU */
@@ -119,10 +118,10 @@ static void cpu_pci_domain_read_resources(struct device *dev)
 	}
 
 	/* A segment is legacy VGA region */
-	mmio_resource(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
+	mmio_from_to(dev, idx++, 0xa0000, 0xc0000);
 
 	/* C segment to 1MB is reserved RAM (low tables) */
-	reserved_ram_resource(dev, idx++, 0xc0000 / KiB, (1 * MiB - 0xc0000) / KiB);
+	reserved_ram_from_to(dev, idx++, 0xc0000, 1 * MiB);
 
 	if (q35 && ((tomk * 1024) < 0xb0000000)) {
 		/*

diff --git a/src/mainboard/emulation/qemu-power8/mainboard.c b/src/mainboard/emulation/qemu-power8/mainboard.c
@@ -11,7 +11,7 @@ static void mainboard_enable(struct device *dev)
 	}
 
 	/* Where does RAM live? */
-	ram_resource(dev, 0, 2048, 32768);
+	ram_range(dev, 0, 2 * MiB, 32 * MiB);
 }
 
 struct chip_operations mainboard_ops = {

diff --git a/src/mainboard/emulation/qemu-power9/mainboard.c b/src/mainboard/emulation/qemu-power9/mainboard.c
@@ -8,7 +8,7 @@ static void mainboard_enable(struct device *dev)
 {
 	if (!dev)
 		die("No dev0; die\n");
-	ram_resource(dev, 0, 0, (unsigned long)cbmem_top() / KiB);
+	ram_resource_kb(dev, 0, 0, (unsigned long)cbmem_top() / KiB);
 }
 
 struct chip_operations mainboard_ops = {

diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c
@@ -55,12 +55,11 @@ static void qemu_nb_read_resources(struct device *dev)
 
 	if (CONFIG(ARCH_RAMSTAGE_X86_64)) {
 		/* Reserve page tables in DRAM. FIXME: Remove once x86_64 page tables reside in CBMEM */
-		reserved_ram_resource(dev, 0, CONFIG_ARCH_X86_64_PGTBL_LOC / KiB,
-			(6 * 0x1000) / KiB);
+		reserved_ram_range(dev, 0, CONFIG_ARCH_X86_64_PGTBL_LOC, 6 * 0x1000);
 	}
 
 	smm_region(&tseg_base, &tseg_size);
-	reserved_ram_resource(dev, ESMRAMC, tseg_base / 1024, tseg_size / 1024);
+	reserved_ram_range(dev, ESMRAMC, tseg_base, tseg_size);
 }
 
 

diff --git a/src/mainboard/emulation/qemu-riscv/mainboard.c b/src/mainboard/emulation/qemu-riscv/mainboard.c
@@ -14,7 +14,7 @@ static void mainboard_enable(struct device *dev)
 	}
 
 	dram_mb_detected = probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB);
-	ram_resource(dev, 0, (uintptr_t)_dram / KiB, dram_mb_detected * MiB / KiB);
+	ram_resource_kb(dev, 0, (uintptr_t)_dram / KiB, dram_mb_detected * MiB / KiB);
 }
 
 struct chip_operations mainboard_ops = {

diff --git a/src/mainboard/emulation/spike-riscv/mainboard.c b/src/mainboard/emulation/spike-riscv/mainboard.c
@@ -17,7 +17,7 @@ static void mainboard_enable(struct device *dev)
 		die("No dev0; die\n");
 	}
 
-	ram_resource(dev, 0, 0x80000000/KiB, ram_size/KiB);
+	ram_resource_kb(dev, 0, 0x80000000/KiB, ram_size/KiB);
 }
 
 struct chip_operations mainboard_ops = {

diff --git a/src/mainboard/google/asurada/chromeos.fmd b/src/mainboard/google/asurada/chromeos.fmd
@@ -1,4 +1,4 @@
-# Firmware Layout Description for Chrome OS.
+# Firmware Layout Description for ChromeOS.
 #
 # The size and address of every section must be aligned to at least 4K, except:
 # RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections.

diff --git a/src/mainboard/google/asurada/regulator.c b/src/mainboard/google/asurada/regulator.c
@@ -38,8 +38,7 @@ static int get_mt6359p_regulator_id(enum mtk_regulator regulator)
 	return -1;
 }
 
-void mainboard_set_regulator_vol(enum mtk_regulator regulator,
-				 uint32_t voltage_uv)
+void mainboard_set_regulator_voltage(enum mtk_regulator regulator, uint32_t voltage_uv)
 {
 	/*
 	 * Handle the regulator that does not have a regulator ID
@@ -68,7 +67,7 @@ void mainboard_set_regulator_vol(enum mtk_regulator regulator,
 	printk(BIOS_WARNING, "Invalid regulator ID: %d\n", regulator);
 }
 
-uint32_t mainboard_get_regulator_vol(enum mtk_regulator regulator)
+uint32_t mainboard_get_regulator_voltage(enum mtk_regulator regulator)
 {
 	/*
 	 * Handle the regulator that does not have a regulator ID
@@ -95,7 +94,7 @@ uint32_t mainboard_get_regulator_vol(enum mtk_regulator regulator)
 	return 0;
 }
 
-int mainboard_enable_regulator(enum mtk_regulator regulator, uint8_t enable)
+int mainboard_enable_regulator(enum mtk_regulator regulator, bool enable)
 {
 	/* Return 0 if the regulator is already enabled or disabled. */
 	if (mainboard_regulator_is_enabled(regulator) == enable)
@@ -112,24 +111,24 @@ int mainboard_enable_regulator(enum mtk_regulator regulator, uint8_t enable)
 	return google_chromeec_regulator_enable(id, enable);
 }
 
-uint8_t mainboard_regulator_is_enabled(enum mtk_regulator regulator)
+bool mainboard_regulator_is_enabled(enum mtk_regulator regulator)
 {
 	int id;
 
 	id = get_mt6360_regulator_id(regulator);
 	if (id < 0) {
 		printk(BIOS_WARNING, "Invalid regulator ID: %d\n; assuming disabled",
 		       regulator);
-		return 0;
+		return false;
 	}
 
 	uint8_t enabled;
 	if (google_chromeec_regulator_is_enabled(id, &enabled) < 0) {
 		printk(BIOS_WARNING,
 		       "Failed to query regulator ID: %d\n; assuming disabled",
 		       regulator);
-		return 0;
+		return false;
 	}
 
-	return enabled;
+	return !!enabled;
 }
diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig
@@ -8,7 +8,6 @@ config BOARD_GOOGLE_BASEBOARD_AURON
 	select HAVE_OPTION_TABLE
 	select INTEL_GMA_HAVE_VBT
 	select INTEL_INT15
-	select MAINBOARD_HAS_CHROMEOS
 	select MAINBOARD_HAS_LIBGFXINIT
 	select MEMORY_MAPPED_TPM
 	select MAINBOARD_HAS_TPM1
@@ -44,11 +43,6 @@ config BOARD_GOOGLE_SAMUS
 
 if BOARD_GOOGLE_BASEBOARD_AURON
 
-config VBOOT
-	select EC_GOOGLE_CHROMEEC_SWITCHES
-	select VBOOT_LID_SWITCH
-	select VBOOT_VBNV_CMOS
-
 config MAINBOARD_DIR
 	default "google/auron"
 

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
@@ -60,6 +60,11 @@ config BOARD_GOOGLE_BASEBOARD_BRASK
 	select SOC_INTEL_ALDERLAKE_PCH_P
 	select TPM_GOOGLE_CR50
 
+config BOARD_GOOGLE_BASEBOARD_GHOST
+	def_bool n
+	select BOARD_GOOGLE_BASEBOARD_BRYA if BOARD_GOOGLE_GHOST4ADL
+	select BOARD_GOOGLE_BASEBOARD_SKOLAS if !BOARD_GOOGLE_GHOST4ADL
+
 config BOARD_GOOGLE_BASEBOARD_NISSA
 	def_bool n
 	select BOARD_GOOGLE_BRYA_COMMON
@@ -68,18 +73,20 @@ config BOARD_GOOGLE_BASEBOARD_NISSA
 	select MEMORY_SOLDERDOWN
 	select SOC_INTEL_ALDERLAKE_PCH_N
 	select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW
+	select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE
 	select SYSTEM_TYPE_LAPTOP
 	select TI50_FIRMWARE_VERSION_NOT_SUPPORTED
 	select TPM_GOOGLE_TI50
 	select SOC_INTEL_COMMON_MMC_OVERRIDE
 
 config BOARD_GOOGLE_BASEBOARD_SKOLAS
 	def_bool n
-	select SOC_INTEL_RAPTORLAKE
 	select BOARD_GOOGLE_BRYA_COMMON
+	select BOARD_ROMSIZE_KB_32768
 	select HAVE_SLP_S0_GATE
 	select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_BANSHEE
 	select SOC_INTEL_ALDERLAKE_PCH_P
+	select SOC_INTEL_RAPTORLAKE
 	select SYSTEM_TYPE_LAPTOP
 	select TPM_GOOGLE_CR50
 
@@ -97,7 +104,7 @@ config CHROMEOS
 	select HAS_RECOVERY_MRC_CACHE
 
 config CHROMEOS_WIFI_SAR
-	bool "Enable SAR options for Chrome OS build"
+	bool "Enable SAR options for ChromeOS build"
 	depends on CHROMEOS
 	select DSAR_ENABLE
 	select GEO_SAR_ENABLE
@@ -114,7 +121,7 @@ config DRIVER_TPM_I2C_BUS
 	default 0x1 if BOARD_GOOGLE_BRASK
 	default 0x1 if BOARD_GOOGLE_PRIMUS
 	default 0x3 if BOARD_GOOGLE_PRIMUS4ES
-	default 0x1 if BOARD_GOOGLE_GHOST4ADL
+	default 0x1 if BOARD_GOOGLE_BASEBOARD_GHOST
 	default 0x1 if BOARD_GOOGLE_GIMBLE
 	default 0x3 if BOARD_GOOGLE_GIMBLE4ES
 	default 0x1 if BOARD_GOOGLE_REDRIX
@@ -139,16 +146,18 @@ config DRIVER_TPM_I2C_BUS
 	default 0x1 if BOARD_GOOGLE_OSIRIS
 	default 0x1 if BOARD_GOOGLE_MITHRAX
 	default 0x1 if BOARD_GOOGLE_KULDAX
-	default 0x3 if BOARD_GOOGLE_SKOLAS4ES
+	default 0x1 if BOARD_GOOGLE_SKOLAS4ES
 	default 0x0 if BOARD_GOOGLE_JOXER
 	default 0x0 if BOARD_GOOGLE_PUJJO
+	default 0x0 if BOARD_GOOGLE_XIVU
 
 config DRIVER_TPM_I2C_ADDR
 	hex
 	default 0x50
 
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-serger.fmd" if BOARD_GOOGLE_BRASK
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-nissa-16MiB-debugfsp.fmd" if BOARD_GOOGLE_BASEBOARD_NISSA && BOARD_ROMSIZE_KB_16384 && BUILDING_WITH_DEBUG_FSP
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-nissa-16MiB.fmd" if BOARD_GOOGLE_BASEBOARD_NISSA && BOARD_ROMSIZE_KB_16384
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-nissa-32MiB.fmd" if BOARD_GOOGLE_BASEBOARD_NISSA && BOARD_ROMSIZE_KB_32768
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd"
@@ -176,7 +185,9 @@ config MAINBOARD_PART_NUMBER
 	default "Brask" if BOARD_GOOGLE_BRASK
 	default "Primus" if BOARD_GOOGLE_PRIMUS
 	default "Primus4ES" if BOARD_GOOGLE_PRIMUS4ES
+	default "Ghost" if BOARD_GOOGLE_GHOST
 	default "Ghost4ADL" if BOARD_GOOGLE_GHOST4ADL
+	default "Ghost4ES" if BOARD_GOOGLE_GHOST4ES
 	default "Gimble" if BOARD_GOOGLE_GIMBLE
 	default "Gimble4ES" if BOARD_GOOGLE_GIMBLE4ES
 	default "Redrix" if BOARD_GOOGLE_REDRIX
@@ -204,14 +215,15 @@ config MAINBOARD_PART_NUMBER
 	default "Skolas4ES" if BOARD_GOOGLE_SKOLAS4ES
 	default "Joxer" if BOARD_GOOGLE_JOXER
 	default "Pujjo" if BOARD_GOOGLE_PUJJO
+	default "Xivu" if BOARD_GOOGLE_XIVU
 
 config VARIANT_DIR
 	default "brya0" if BOARD_GOOGLE_BRYA0
 	default "brya4es" if BOARD_GOOGLE_BRYA4ES
 	default "brask" if BOARD_GOOGLE_BRASK
 	default "primus" if BOARD_GOOGLE_PRIMUS
 	default "primus4es" if BOARD_GOOGLE_PRIMUS4ES
-	default "ghost4adl" if BOARD_GOOGLE_GHOST4ADL
+	default "ghost" if BOARD_GOOGLE_BASEBOARD_GHOST
 	default "gimble" if BOARD_GOOGLE_GIMBLE
 	default "gimble4es" if BOARD_GOOGLE_GIMBLE4ES
 	default "redrix" if BOARD_GOOGLE_REDRIX
@@ -239,6 +251,7 @@ config VARIANT_DIR
 	default "skolas4es" if BOARD_GOOGLE_SKOLAS4ES
 	default "joxer" if BOARD_GOOGLE_JOXER
 	default "pujjo" if BOARD_GOOGLE_PUJJO
+	default "xivu" if BOARD_GOOGLE_XIVU
 
 config VBOOT
 	select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA
@@ -273,7 +286,7 @@ config USE_PM_ACPI_TIMER
 
 choice
 	prompt "Cache as RAM (CAR) setup configuration to use"
-	default USE_ADL_NEM if BOARD_GOOGLE_BRYA4ES || BOARD_GOOGLE_PRIMUS4ES || BOARD_GOOGLE_GIMBLE4ES || BOARD_GOOGLE_REDRIX4ES || BOARD_GOOGLE_TAEKO4ES || BOARD_GOOGLE_ANAHERA4ES || BOARD_GOOGLE_TANIKS || BOARD_GOOGLE_NIVVIKS || BOARD_GOOGLE_NEREID || BOARD_GOOGLE_CRAASK || BOARD_GOOGLE_SKOLAS4ES || BOARD_GOOGLE_JOXER || BOARD_GOOGLE_PUJJO
+	default USE_ADL_NEM if BOARD_GOOGLE_BRYA4ES || BOARD_GOOGLE_PRIMUS4ES || BOARD_GOOGLE_GIMBLE4ES || BOARD_GOOGLE_REDRIX4ES || BOARD_GOOGLE_TAEKO4ES || BOARD_GOOGLE_ANAHERA4ES || BOARD_GOOGLE_TANIKS || BOARD_GOOGLE_NIVVIKS || BOARD_GOOGLE_NEREID || BOARD_GOOGLE_CRAASK || BOARD_GOOGLE_SKOLAS4ES || BOARD_GOOGLE_JOXER || BOARD_GOOGLE_PUJJO || BOARD_GOOGLE_XIVU
 	default USE_ADL_ENEM
 
 config USE_ADL_ENEM

diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
@@ -57,9 +57,18 @@ config BOARD_GOOGLE_FELWINTER
 	select DRIVERS_GENERIC_GPIO_KEYS
 	select DRIVERS_GENESYSLOGIC_GL9755
 
+config BOARD_GOOGLE_GHOST
+	bool "->  Ghost"
+	select BOARD_GOOGLE_BASEBOARD_GHOST
+
 config BOARD_GOOGLE_GHOST4ADL
 	bool "->  Ghost4ADL"
-	select BOARD_GOOGLE_BASEBOARD_BRYA
+	select BOARD_GOOGLE_BASEBOARD_GHOST
+	select ENABLE_TCSS_DISPLAY_DETECTION if RUN_FSP_GOP
+
+config BOARD_GOOGLE_GHOST4ES
+	bool "->  Ghost4ES"
+	select BOARD_GOOGLE_BASEBOARD_GHOST
 
 config BOARD_GOOGLE_GIMBLE
 	bool "->  Gimble"
@@ -205,6 +214,7 @@ config BOARD_GOOGLE_CROTA
 	select CHROMEOS_WIFI_SAR if CHROMEOS
 	select DRIVERS_GENESYSLOGIC_GL9750
 	select DRIVERS_I2C_CS42L42
+	select VPD
 
 config BOARD_GOOGLE_MOLI
 	bool "->  Moli"
@@ -217,7 +227,6 @@ config BOARD_GOOGLE_KINOX
 config BOARD_GOOGLE_CRAASK
 	bool "->  Craask"
 	select BOARD_GOOGLE_BASEBOARD_NISSA
-	select BOARD_ROMSIZE_KB_32768
 	select DRIVERS_GENERIC_GPIO_KEYS
 	select DRIVERS_GENESYSLOGIC_GL9750
 	select DRIVERS_INTEL_MIPI_CAMERA
@@ -226,6 +235,8 @@ config BOARD_GOOGLE_CRAASK
 config BOARD_GOOGLE_OSIRIS
 	bool "->  Osiris"
 	select BOARD_GOOGLE_BASEBOARD_BRYA
+	select CHROMEOS_WIFI_SAR if CHROMEOS
+	select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
 	select RT8168_GEN_ACPI_POWER_RESOURCE
 	select RT8168_GET_MAC_FROM_VPD
 	select RT8168_SET_LED_MODE
@@ -243,8 +254,20 @@ config BOARD_GOOGLE_KULDAX
 
 config BOARD_GOOGLE_JOXER
 	bool "->  Joxer"
+	select ALDERLAKE_CONFIGURE_DESCRIPTOR
 	select BOARD_GOOGLE_BASEBOARD_NISSA
+	select DRIVERS_GENESYSLOGIC_GL9750
 
 config BOARD_GOOGLE_PUJJO
 	bool "->  Pujjo"
 	select BOARD_GOOGLE_BASEBOARD_NISSA
+	select DRIVERS_GENERIC_GPIO_KEYS
+	select DRIVERS_GENESYSLOGIC_GL9750
+	select HAVE_WWAN_POWER_SEQUENCE
+
+config BOARD_GOOGLE_XIVU
+	bool "->  Xivu"
+	select BOARD_GOOGLE_BASEBOARD_NISSA
+	select DRIVERS_GENERIC_GPIO_KEYS
+	select DRIVERS_GENESYSLOGIC_GL9750
+	select DRIVERS_INTEL_MIPI_CAMERA
diff --git a/src/mainboard/google/brya/acpi/gpu_defines.h b/src/mainboard/google/brya/acpi/gpu_defines.h
@@ -46,3 +46,15 @@
 #define REVISION_MIN_NBCI	0x102
 #define REVISION_MIN_NVPCF	0x200
 #define REVISION_MIN_GPS	0x200
+
+#define D1_EC	0
+#define D2_EC	1
+#define D3_EC	2
+#define D4_EC	3
+#define D5_EC	4
+
+#define D1_GPU	0xD1
+#define D2_GPU	0xD2
+#define D3_GPU	0xD3
+#define D4_GPU	0xD4
+#define D5_GPU	0xD5
diff --git a/src/mainboard/google/brya/acpi/gpu_ec.asl b/src/mainboard/google/brya/acpi/gpu_ec.asl
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define EC_D_NOTIFY_MASK	0x7
+
+Scope (\_SB.PCI0.LPCB.EC0)
+{
+	/* EC has data for GPU in memmap */
+	Method (_Q0C, 0, Serialized)
+	{
+		Local0 = ToInteger(GPUD) & EC_D_NOTIFY_MASK
+		\_SB.PCI0.PEG0.PEGP.DNOT (Local0)
+	}
+}
diff --git a/src/mainboard/google/brya/acpi/gpu_top.asl b/src/mainboard/google/brya/acpi/gpu_top.asl
@@ -25,6 +25,33 @@ Scope (\_SB.PCI0.PEG0)
 		#include "nbci.asl"
 		#include "nvpcf.asl"
 		#include "gps.asl"
+		#include "gpu_ec.asl"
+
+		/* Convert D Notify from EC to GPU */
+		Method (CNVD, 1, NotSerialized)
+		{
+			Switch (ToInteger(Arg0)) {
+				Case (D1_EC) { Return (D1_GPU) }
+				Case (D2_EC) { Return (D2_GPU) }
+				Case (D3_EC) { Return (D3_GPU) }
+				Case (D4_EC) { Return (D4_GPU) }
+				Case (D5_EC) { Return (D5_GPU) }
+				Default { Return (D5_GPU) }
+			}
+		}
+
+		/* Current D Notify Value, defaults to D1 */
+		Name (CDNV, D1_EC)
+		Method (DNOT, 1, Serialized)
+		{
+			Printf ("EC: GPU D-Notify, %o", Arg0)
+			If (Arg0 != CDNV)
+			{
+				CDNV = Arg0
+				Local0 = CNVD (Arg0)
+				Notify (\_SB.PCI0.PEG0.PEGP, Local0)
+			}
+		}
 
 		Method (_DSM, 4, Serialized)
 		{
-Original file line number
+Diff line change
@@ Expand Up / @@ -51,5 +51,4 @@ void fsp_print_header_info(const struct fsp_header *hdr) @@
     		printk(BIOS_SPEW, "\tNotify phase offset  0x%zx\n",
     		       (size_t)hdr->notify_phase_entry_offset);
     	}
     }