diff --git a/src/arch/x86/id.S b/src/arch/x86/id.S
@@ -12,11 +12,11 @@ part:
 	.asciz CONFIG_MAINBOARD_PART_NUMBER
 
 #if ENV_X86_64
-.long 	0xffffffff - ver + 1		/* Reverse offset to the version */
+.long	0xffffffff - ver + 1		/* Reverse offset to the version */
 .long	0xffffffff - vendor + 1		/* Reverse offset to the vendor id */
 .long	0xffffffff - part + 1		/* Reverse offset to the part number */
 #else
-.long 	- ver		/* Reverse offset to the version */
+.long	- ver		/* Reverse offset to the version */
 .long	- vendor	/* Reverse offset to the vendor id */
 .long	- part		/* Reverse offset to the part number */
 #endif

diff --git a/src/arch/x86/include/arch/bert_storage.h b/src/arch/x86/include/arch/bert_storage.h
@@ -41,6 +41,9 @@
  * +--------------------------------------------------------------------+
  */
 
+#define CRASHLOG_RECORD_TYPE	0x2
+#define CRASHLOG_FW_ERR_REV	0x2
+
 /* Get implementation-specific reserved area for generating BERT info */
 void bert_reserved_region(void **start, size_t *size);
 
@@ -120,6 +123,9 @@ acpi_hest_generic_data_v300_t *bert_append_genproc(
 acpi_hest_generic_data_v300_t *bert_append_ia32x64(
 					acpi_generic_error_status_t *status);
 
+void *new_cper_fw_error_crashlog(acpi_generic_error_status_t *status, size_t cl_size);
+acpi_hest_generic_data_v300_t *bert_append_fw_err(acpi_generic_error_status_t *status);
+
 /* Add a new event to the BERT region.  An event consists of an ACPI Error
  * Status Block, a Generic Error Data Entry, and an associated CPER Error
  * Section.

diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
@@ -217,7 +217,6 @@ struct cpu_device_id {
 struct cpu_driver {
 	struct device_operations *ops;
 	const struct cpu_device_id *id_table;
-	struct acpi_cstate *cstates;
 };
 
 struct cpu_driver *find_cpu_driver(struct device *cpu);
@@ -306,7 +305,7 @@ uint32_t cpu_get_feature_flags_edx(void);
  * function will always getting called from coreboot context
  * (ESP stack pointer will always refer to coreboot).
  *
- * But with FSP_USES_MP_SERVICES_PPI implementation in coreboot this
+ * But with MP_SERVICES_PPI implementation in coreboot this
  * assumption might not be true, where FSP context (stack pointer refers
  * to FSP) will request to get cpu_index().
  *

diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
@@ -28,8 +28,6 @@ SECTIONS
 
 	#include "car.ld"
 #elif ENV_BOOTBLOCK
-	BOOTBLOCK(0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1,
-			CONFIG_C_ENV_BOOTBLOCK_SIZE)
 
 	#include "car.ld"
 

diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c
@@ -9,7 +9,6 @@
 #include <program_loading.h>
 #include <reset.h>
 #include <rmodule.h>
-#include <romstage_handoff.h>
 #include <stage_cache.h>
 #include <timestamp.h>
 #include <security/vboot/vboot_common.h>
@@ -183,8 +182,7 @@ void run_postcar_phase(struct postcar_frame *pcf)
 
 	postcar_commit_mtrrs(pcf);
 
-	if (!CONFIG(NO_STAGE_CACHE) &&
-				romstage_handoff_is_resume()) {
+	if (resume_from_stage_cache()) {
 		stage_cache_load_stage(STAGE_POSTCAR, &prog);
 		/* This is here to allow platforms to pass different stack
 		   parameters between S3 resume and normal boot. On the

diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
@@ -5,6 +5,7 @@
 #include <console/console.h>
 #include <version.h>
 #include <device/device.h>
+#include <device/dram/spd.h>
 #include <arch/cpu.h>
 #include <cpu/x86/name.h>
 #include <elog.h>
@@ -154,44 +155,10 @@ static int smbios_processor_name(u8 *start)
 	return smbios_add_string(start, str);
 }
 
-static const char *get_dimm_manufacturer_name(const uint16_t mod_id)
-{
-	switch (mod_id) {
-	case 0x9b85:
-		return "Crucial";
-	case 0x4304:
-		return "Ramaxel";
-	case 0x4f01:
-		return "Transcend";
-	case 0x9801:
-		return "Kingston";
-	case 0x987f:
-		return "Hynix";
-	case 0x9e02:
-		return "Corsair";
-	case 0xb004:
-		return "OCZ";
-	case 0xad80:
-		return "Hynix/Hyundai";
-	case 0x3486:
-		return "Super Talent";
-	case 0xcd04:
-		return "GSkill";
-	case 0xce80:
-		return "Samsung";
-	case 0xfe02:
-		return "Elpida";
-	case 0x2c80:
-		return "Micron";
-	default:
-		return NULL;
-	}
-}
-
 /* this function will fill the corresponding manufacturer */
 void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id, struct smbios_type17 *t)
 {
-	const char *const manufacturer = get_dimm_manufacturer_name(mod_id);
+	const char *const manufacturer = spd_manufacturer_name(mod_id);
 
 	if (manufacturer) {
 		t->manufacturer = smbios_add_string(t->eos, manufacturer);
@@ -422,7 +389,7 @@ static int smbios_write_type0(unsigned long *current, int handle)
 	t->vendor = smbios_add_string(t->eos, "coreboot");
 	t->bios_release_date = smbios_add_string(t->eos, coreboot_dmi_date);
 
-	if (CONFIG(CHROMEOS)) {
+	if (CONFIG(CHROMEOS) && CONFIG(HAVE_ACPI_TABLES)) {
 		uintptr_t version_address = (uintptr_t)t->eos;
 		/* SMBIOS offsets start at 1 rather than 0 */
 		version_address += (u32)smbios_string_table_len(t->eos) - 1;
@@ -609,6 +576,7 @@ static int smbios_write_type3(unsigned long *current, int handle)
 	t->thermal_state = SMBIOS_STATE_SAFE;
 	t->_type = smbios_mainboard_enclosure_type();
 	t->security_status = SMBIOS_STATE_SAFE;
+	t->number_of_power_cords = smbios_chassis_power_cords();
 	t->asset_tag_number = smbios_add_string(t->eos, smbios_mainboard_asset_tag());
 	t->version = smbios_add_string(t->eos, smbios_chassis_version());
 	t->serial_number = smbios_add_string(t->eos, smbios_chassis_serial_number());
@@ -685,15 +653,16 @@ static int smbios_write_type4(unsigned long *current, int handle)
 	t->processor_upgrade = get_socket_type();
 	len = t->length + smbios_string_table_len(t->eos);
 	if (cpu_have_cpuid() && cpuid_get_max_func() >= 0x16) {
-		t->max_speed = cpuid_ebx(0x16);
 		t->current_speed = cpuid_eax(0x16); /* base frequency */
 		t->external_clock = cpuid_ecx(0x16);
 	} else {
-		t->max_speed = smbios_cpu_get_max_speed_mhz();
 		t->current_speed = smbios_cpu_get_current_speed_mhz();
 		t->external_clock = smbios_processor_external_clock();
 	}
 
+	/* This field identifies a capability for the system, not the processor itself. */
+	t->max_speed = smbios_cpu_get_max_speed_mhz();
+
 	if (cpu_have_cpuid()) {
 		res = cpuid(1);
 
@@ -1028,6 +997,7 @@ static int smbios_write_type16(unsigned long *current, int *handle)
 
 	int len;
 	int i;
+	uint64_t max_capacity;
 
 	struct memory_info *meminfo;
 	meminfo = cbmem_find(CBMEM_ID_MEMINFO);
@@ -1057,7 +1027,13 @@ static int smbios_write_type16(unsigned long *current, int *handle)
 
 	/* no error information handle available */
 	t->memory_error_information_handle = 0xFFFE;
-	t->maximum_capacity = meminfo->max_capacity_mib * (MiB / KiB);
+	max_capacity = meminfo->max_capacity_mib;
+	if (max_capacity * (MiB / KiB) < SMBIOS_USE_EXTENDED_MAX_CAPACITY)
+		t->maximum_capacity = max_capacity * (MiB / KiB);
+	else {
+		t->maximum_capacity = SMBIOS_USE_EXTENDED_MAX_CAPACITY;
+		t->extended_maximum_capacity = max_capacity * MiB;
+	}
 	t->number_of_memory_devices = meminfo->number_of_devices;
 
 	len += smbios_string_table_len(t->eos);

diff --git a/src/arch/x86/smbios_defaults.c b/src/arch/x86/smbios_defaults.c
@@ -143,3 +143,8 @@ __weak const char *smbios_processor_serial_number(void)
 {
 	return "";
 }
+
+__weak u8 smbios_chassis_power_cords(void)
+{
+	return 1;
+}
diff --git a/src/commonlib/bsd/cbfs_private.c b/src/commonlib/bsd/cbfs_private.c
@@ -173,13 +173,13 @@ const void *cbfs_find_attr(const union cbfs_mdata *mdata, uint32_t attr_tag, siz
 		const uint32_t len = be32toh(attr->len);
 
 		if (offset + len > end) {
-			ERROR("Attribute %s[%u] overflows end of metadata\n",
+			ERROR("Attribute %s[%x] overflows end of metadata\n",
 			      mdata->h.filename, tag);
 			return NULL;
 		}
 		if (tag == attr_tag) {
 			if (size_check && len != size_check) {
-				ERROR("Attribute %s[%u] size mismatch: %u != %zu\n",
+				ERROR("Attribute %s[%x] size mismatch: %u != %zu\n",
 				      mdata->h.filename, tag, len, size_check);
 				return NULL;
 			}

diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h
@@ -6,7 +6,7 @@
 
 #include <commonlib/bsd/cb_err.h>
 #include <commonlib/bsd/cbfs_serialized.h>
-#include <endian.h>
+#include <commonlib/bsd/sysincludes.h>
 #include <stdbool.h>
 #include <stdint.h>
 #include <vb2_sha.h>

diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h
@@ -114,6 +114,9 @@ struct cbfs_file_attribute {
 	uint8_t data[0];
 } __packed;
 
+/* All attribute sizes must be divisible by this! */
+#define CBFS_ATTRIBUTE_ALIGN 4
+
 /* Depending on how the header was initialized, it may be backed with 0x00 or
  * 0xff. Support both. */
 enum cbfs_file_attr_tag {

diff --git a/src/commonlib/cbfs.c b/src/commonlib/cbfs.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <console/console.h>
 #include <commonlib/cbfs.h>
 #include <commonlib/endian.h>
 #include <commonlib/helpers.h>

diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h
@@ -4,6 +4,7 @@
 #define _CBMEM_ID_H_
 
 #define CBMEM_ID_ACPI		0x41435049
+#define CBMEM_ID_ACPI_BERT      0x42455254
 #define CBMEM_ID_ACPI_GNVS	0x474e5653
 #define CBMEM_ID_ACPI_UCSI	0x55435349
 #define CBMEM_ID_AFTER_CAR	0xc4787a93
@@ -14,6 +15,7 @@
 #define CBMEM_ID_CBTABLE_FWD	0x43425443
 #define CBMEM_ID_CB_EARLY_DRAM	0x4544524D
 #define CBMEM_ID_CONSOLE	0x434f4e53
+#define CBMEM_ID_CPU_CRASHLOG	0x4350555f
 #define CBMEM_ID_COVERAGE	0x47434f56
 #define CBMEM_ID_DRTM_LOG	0x444c4f47
 #define CBMEM_ID_EHCI_DEBUG	0xe4c1deb9
@@ -32,6 +34,7 @@
 #define CBMEM_ID_MMC_STATUS	0x4d4d4353
 #define CBMEM_ID_MPTABLE	0x534d5054
 #define CBMEM_ID_MRCDATA	0x4d524344
+#define CBMEM_ID_PMC_CRASHLOG	0x504d435f
 #define CBMEM_ID_VAR_MRCDATA	0x4d524345
 #define CBMEM_ID_MTC		0xcb31d31c
 #define CBMEM_ID_NONE		0x00000000
@@ -77,6 +80,7 @@
 
 #define CBMEM_ID_TO_NAME_TABLE				 \
 	{ CBMEM_ID_ACPI,		"ACPI       " }, \
+	{ CBMEM_ID_ACPI_BERT,		"ACPI BERT  " }, \
 	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
 	{ CBMEM_ID_ACPI_UCSI,		"ACPI UCSI  " }, \
 	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
@@ -89,6 +93,7 @@
 	{ CBMEM_ID_CONSOLE,		"CONSOLE    " }, \
 	{ CBMEM_ID_COVERAGE,		"COVERAGE   " }, \
 	{ CBMEM_ID_DRTM_LOG,		"DRTM TPMLOG" }, \
+	{ CBMEM_ID_CPU_CRASHLOG,	"CPU CRASHLOG"}, \
 	{ CBMEM_ID_EHCI_DEBUG,		"USBDEBUG   " }, \
 	{ CBMEM_ID_ELOG,		"ELOG       " }, \
 	{ CBMEM_ID_FREESPACE,		"FREE SPACE " }, \
@@ -103,6 +108,7 @@
 	{ CBMEM_ID_MMC_STATUS,		"MMC STATUS " }, \
 	{ CBMEM_ID_MPTABLE,		"SMP TABLE  " }, \
 	{ CBMEM_ID_MRCDATA,		"MRC DATA   " }, \
+	{ CBMEM_ID_PMC_CRASHLOG,	"PMC CRASHLOG"}, \
 	{ CBMEM_ID_VAR_MRCDATA,		"VARMRC DATA" }, \
 	{ CBMEM_ID_MTC,			"MTC        " }, \
 	{ CBMEM_ID_PIRQ,		"IRQ TABLE  " }, \

diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c
@@ -7,7 +7,7 @@
 #include <console/vtxprintf.h>
 #include <ctype.h>
 #include <string.h>
-#include <stdint.h>
+#include <types.h>
 
 #define call_tx(x) tx_byte(x, data)
 

diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
@@ -111,7 +111,6 @@ config CPU_MICROCODE_CBFS_DEFAULT_BINS
 config CPU_MICROCODE_CBFS_EXTERNAL_BINS
 	bool "Include external microcode binary"
 	select USE_CPU_MICROCODE_CBFS_BINS
-	depends on !CPU_MICROCODE_MULTIPLE_FILES
 	help
 	  Select this option if you want to include external binary files
 	  in the CPUs native format. They will be included as a separate
@@ -128,7 +127,6 @@ config CPU_MICROCODE_CBFS_EXTERNAL_BINS
 
 config CPU_MICROCODE_CBFS_EXTERNAL_HEADER
 	bool "Include external microcode header files"
-	depends on !CPU_MICROCODE_MULTIPLE_FILES
 	help
 	  Select this option if you want to include external c header files
 	  containing the CPU microcode. This will be included as a separate
@@ -183,12 +181,6 @@ config AGESA_UCODE_EXPERIMENTAL
 
 endchoice
 
-config CPU_MICROCODE_MULTIPLE_FILES
-	bool
-	help
-	  Select this option to install separate microcode container files into
-	  CBFS instead of using the traditional monolithic microcode file format.
-
 config CPU_MICROCODE_HEADER_FILES
 	string "List of space separated microcode header files with the path"
 	depends on CPU_MICROCODE_CBFS_EXTERNAL_HEADER

diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
@@ -13,9 +13,7 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32))
 ## Rules for building the microcode blob in CBFS
 ################################################################################
 
-ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y)
 cbfs-files-$(CONFIG_USE_CPU_MICROCODE_CBFS_BINS) += cpu_microcode_blob.bin
-endif
 
 ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
 cbfs-files-y  += cpu_microcode_blob.bin

diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
@@ -37,10 +37,6 @@ config DCACHE_BSP_STACK_SIZE
 	hex
 	default 0x4000
 
-config C_ENV_BOOTBLOCK_SIZE
-	hex
-	default 0x8000
-
 config ENABLE_MRC_CACHE
 	bool "Use cached memory configuration"
 	default n

diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c
@@ -15,37 +15,37 @@ void amd_initcpuio(void)
 	AMD_CONFIG_PARAMS             StdHeader;
 
 	/* Enable legacy video routing: D18F1xF4 VGA Enable */
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);
 	PciData = 1;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
 	/* The platform BIOS needs to ensure the memory ranges of Hudson legacy
 	 * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
 	 * set to non-posted regions.
 	 */
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
 	PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
 	PciData |= 1 << 7;    /* set NP (non-posted) bit */
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
 	PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
 	/* Map the remaining PCI hole as posted MMIO */
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
 	PciData = 0x00FECF00; /* last address before non-posted range */
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 	LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
 	MsrReg = (MsrReg >> 8) | 3;
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
 	PciData = (UINT32)MsrReg;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
 	/* Send all IO (0000-FFFF) to southbridge. */
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
 	PciData = 0x0000F000;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
 	PciData = 0x00000003;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 }
diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig
@@ -36,10 +36,6 @@ config DCACHE_BSP_STACK_SIZE
 	hex
 	default 0x4000
 
-config C_ENV_BOOTBLOCK_SIZE
-	hex
-	default 0x8000
-
 endif # CPU_AMD_PI
 
 source "src/cpu/amd/pi/00630F01/Kconfig"

diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c
@@ -44,8 +44,10 @@ static int get_fsb_tsc(int *fsb, int *ratio)
 		case 0x2a: /* SandyBridge BCLK fixed at 100MHz */
 		case 0x3a: /* IvyBridge BCLK fixed at 100MHz */
 		case 0x3c: /* Haswell BCLK fixed at 100MHz */
+		case 0x3d: /* Broadwell-ULT BCLK fixed at 100MHz */
 		case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */
 		case 0x46: /* Haswell-GT3e BCLK fixed at 100MHz */
+		case 0x47: /* Broadwell BCLK fixed at 100MHz */
 			*fsb = 100;
 			*ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff;
 			break;
@@ -101,7 +103,6 @@ static void resolve_timebase(void)
 	/* Set some semi-ridiculous defaults. */
 	timer_fsb = 500;
 	timer_tsc = 5000;
-	return;
 }
 
 u32 get_timer_fsb(void)

diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c
@@ -14,38 +14,101 @@
 
 #include <southbridge/intel/lynxpoint/pch.h>
 
-static int cstate_set_s0ix[3] = {
+#define MWAIT_RES(state, sub_state)                         \
+	{                                                   \
+		.addrl = (((state) << 4) | (sub_state)),    \
+		.space_id = ACPI_ADDRESS_SPACE_FIXED,       \
+		.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,    \
+		.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,    \
+		.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \
+	}
+
+static acpi_cstate_t cstate_map[NUM_C_STATES] = {
+	[C_STATE_C0] = { },
+	[C_STATE_C1] = {
+		.latency = 0,
+		.power = 1000,
+		.resource = MWAIT_RES(0, 0),
+	},
+	[C_STATE_C1E] = {
+		.latency = 0,
+		.power = 1000,
+		.resource = MWAIT_RES(0, 1),
+	},
+	[C_STATE_C3] = {
+		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+		.power = 900,
+		.resource = MWAIT_RES(1, 0),
+	},
+	[C_STATE_C6_SHORT_LAT] = {
+		.latency = C_STATE_LATENCY_FROM_LAT_REG(1),
+		.power = 800,
+		.resource = MWAIT_RES(2, 0),
+	},
+	[C_STATE_C6_LONG_LAT] = {
+		.latency = C_STATE_LATENCY_FROM_LAT_REG(2),
+		.power = 800,
+		.resource = MWAIT_RES(2, 1),
+	},
+	[C_STATE_C7_SHORT_LAT] = {
+		.latency = C_STATE_LATENCY_FROM_LAT_REG(1),
+		.power = 700,
+		.resource = MWAIT_RES(3, 0),
+	},
+	[C_STATE_C7_LONG_LAT] = {
+		.latency = C_STATE_LATENCY_FROM_LAT_REG(2),
+		.power = 700,
+		.resource = MWAIT_RES(3, 1),
+	},
+	[C_STATE_C7S_SHORT_LAT] = {
+		.latency = C_STATE_LATENCY_FROM_LAT_REG(1),
+		.power = 700,
+		.resource = MWAIT_RES(3, 2),
+	},
+	[C_STATE_C7S_LONG_LAT] = {
+		.latency = C_STATE_LATENCY_FROM_LAT_REG(2),
+		.power = 700,
+		.resource = MWAIT_RES(3, 3),
+	},
+	[C_STATE_C8] = {
+		.latency = C_STATE_LATENCY_FROM_LAT_REG(3),
+		.power = 600,
+		.resource = MWAIT_RES(4, 0),
+	},
+	[C_STATE_C9] = {
+		.latency = C_STATE_LATENCY_FROM_LAT_REG(4),
+		.power = 500,
+		.resource = MWAIT_RES(5, 0),
+	},
+	[C_STATE_C10] = {
+		.latency = C_STATE_LATENCY_FROM_LAT_REG(5),
+		.power = 400,
+		.resource = MWAIT_RES(6, 0),
+	},
+};
+
+static const int cstate_set_s0ix[3] = {
 	C_STATE_C1E,
 	C_STATE_C7S_LONG_LAT,
 	C_STATE_C10,
 };
 
-static int cstate_set_lp[3] = {
+static const int cstate_set_lp[3] = {
 	C_STATE_C1E,
 	C_STATE_C3,
 	C_STATE_C7S_LONG_LAT,
 };
 
-static int cstate_set_trad[3] = {
+static const int cstate_set_trad[3] = {
 	C_STATE_C1,
 	C_STATE_C3,
 	C_STATE_C6_LONG_LAT,
 };
 
-static int get_cores_per_package(void)
+static int get_logical_cores_per_package(void)
 {
-	struct cpuinfo_x86 c;
-	struct cpuid_result result;
-	int cores = 1;
-
-	get_fms(&c, cpuid_eax(1));
-	if (c.x86 != 6)
-		return 1;
-
-	result = cpuid_ext(0xb, 1);
-	cores = result.ebx & 0xff;
-
-	return cores;
+	msr_t msr = rdmsr(MSR_CORE_THREAD_COUNT);
+	return msr.lo & 0xffff;
 }
 
 static acpi_tstate_t tss_table_fine[] = {
@@ -117,35 +180,28 @@ static bool is_s0ix_enabled(void)
 
 static void generate_C_state_entries(void)
 {
-	acpi_cstate_t map[3];
-	int *set;
-	int i;
-
-	struct cpu_info *info;
-	struct cpu_driver *cpu;
+	acpi_cstate_t acpi_cstate_map[3] = {0};
 
-	/* Find CPU map of supported C-states */
-	info = cpu_info();
-	if (!info)
-		return;
-	cpu = find_cpu_driver(info->cpu);
-	if (!cpu || !cpu->cstates)
-		return;
+	const int *acpi_cstates;
 
 	if (is_s0ix_enabled())
-		set = cstate_set_s0ix;
+		acpi_cstates = cstate_set_s0ix;
 	else if (haswell_is_ult())
-		set = cstate_set_lp;
+		acpi_cstates = cstate_set_lp;
 	else
-		set = cstate_set_trad;
+		acpi_cstates = cstate_set_trad;
 
-	for (i = 0; i < ARRAY_SIZE(map); i++) {
-		map[i] = cpu->cstates[set[i]];
-		map[i].ctype = i + 1;
-	}
+	/* Count number of active C-states */
+	int count = 0;
 
-	/* Generate C-state tables */
-	acpigen_write_CST_package(map, ARRAY_SIZE(map));
+	for (int i = 0; i < ARRAY_SIZE(acpi_cstate_map); i++) {
+		if (acpi_cstates[i] > 0 && acpi_cstates[i] < ARRAY_SIZE(cstate_map)) {
+			acpi_cstate_map[count] = cstate_map[acpi_cstates[i]];
+			acpi_cstate_map[count].ctype = i + 1;
+			count++;
+		}
+	}
+	acpigen_write_CST_package(acpi_cstate_map, count);
 }
 
 static int calculate_power(int tdp, int p1_ratio, int ratio)
@@ -279,7 +335,7 @@ void generate_cpu_entries(const struct device *device)
 {
 	int coreID, cpuID, pcontrol_blk = get_pmbase(), plen = 6;
 	int totalcores = dev_count_cpu();
-	int cores_per_package = get_cores_per_package();
+	int cores_per_package = get_logical_cores_per_package();
 	int numcpus = totalcores/cores_per_package;
 
 	printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",

diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <types.h>
-#include <arch/cpu.h>
 #include <cpu/x86/msr.h>
+
 #include "haswell.h"
 
 void intel_cpu_haswell_finalize_smm(void)

diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
@@ -20,79 +20,6 @@
 #include "haswell.h"
 #include "chip.h"
 
-#define MWAIT_RES(state, sub_state)                         \
-	{                                                   \
-		.addrl = (((state) << 4) | (sub_state)),    \
-		.space_id = ACPI_ADDRESS_SPACE_FIXED,       \
-		.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,    \
-		.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,    \
-		.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \
-	}
-
-static acpi_cstate_t cstate_map[NUM_C_STATES] = {
-	[C_STATE_C0] = { },
-	[C_STATE_C1] = {
-		.latency = 0,
-		.power = 1000,
-		.resource = MWAIT_RES(0, 0),
-	},
-	[C_STATE_C1E] = {
-		.latency = 0,
-		.power = 1000,
-		.resource = MWAIT_RES(0, 1),
-	},
-	[C_STATE_C3] = {
-		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
-		.power = 900,
-		.resource = MWAIT_RES(1, 0),
-	},
-	[C_STATE_C6_SHORT_LAT] = {
-		.latency = C_STATE_LATENCY_FROM_LAT_REG(1),
-		.power = 800,
-		.resource = MWAIT_RES(2, 0),
-	},
-	[C_STATE_C6_LONG_LAT] = {
-		.latency = C_STATE_LATENCY_FROM_LAT_REG(2),
-		.power = 800,
-		.resource = MWAIT_RES(2, 1),
-	},
-	[C_STATE_C7_SHORT_LAT] = {
-		.latency = C_STATE_LATENCY_FROM_LAT_REG(1),
-		.power = 700,
-		.resource = MWAIT_RES(3, 0),
-	},
-	[C_STATE_C7_LONG_LAT] = {
-		.latency = C_STATE_LATENCY_FROM_LAT_REG(2),
-		.power = 700,
-		.resource = MWAIT_RES(3, 1),
-	},
-	[C_STATE_C7S_SHORT_LAT] = {
-		.latency = C_STATE_LATENCY_FROM_LAT_REG(1),
-		.power = 700,
-		.resource = MWAIT_RES(3, 2),
-	},
-	[C_STATE_C7S_LONG_LAT] = {
-		.latency = C_STATE_LATENCY_FROM_LAT_REG(2),
-		.power = 700,
-		.resource = MWAIT_RES(3, 3),
-	},
-	[C_STATE_C8] = {
-		.latency = C_STATE_LATENCY_FROM_LAT_REG(3),
-		.power = 600,
-		.resource = MWAIT_RES(4, 0),
-	},
-	[C_STATE_C9] = {
-		.latency = C_STATE_LATENCY_FROM_LAT_REG(4),
-		.power = 500,
-		.resource = MWAIT_RES(5, 0),
-	},
-	[C_STATE_C10] = {
-		.latency = C_STATE_LATENCY_FROM_LAT_REG(5),
-		.power = 400,
-		.resource = MWAIT_RES(6, 0),
-	},
-};
-
 /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
 static const u8 power_limit_time_sec_to_msr[] = {
 	[0]   = 0x00,
@@ -738,5 +665,4 @@ static const struct cpu_device_id cpu_table[] = {
 static const struct cpu_driver driver __cpu_driver = {
 	.ops      = &cpu_dev_ops,
 	.id_table = cpu_table,
-	.cstates  = cstate_map,
 };
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/cpu.h>
 #include <console/console.h>
 #include <cpu/intel/haswell/haswell.h>
 #include <cpu/x86/msr.h>

diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
@@ -119,30 +119,27 @@ uint32_t get_microcode_checksum(const void *microcode)
 
 const void *intel_microcode_find(void)
 {
-	const struct microcode *ucode_updates;
+	static const struct microcode *ucode_updates;
 	size_t microcode_len;
 	u32 eax;
 	u32 pf, rev, sig, update_size;
-	unsigned int x86_model, x86_family;
 	msr_t msr;
+	struct cpuinfo_x86 c;
+
+	if (ucode_updates)
+		return ucode_updates;
 
 	ucode_updates = cbfs_map(MICROCODE_CBFS_FILE, &microcode_len);
 	if (ucode_updates == NULL)
 		return NULL;
 
-	/* CPUID sets MSR 0x8B if a microcode update has been loaded. */
-	msr.lo = 0;
-	msr.hi = 0;
-	wrmsr(IA32_BIOS_SIGN_ID, msr);
+	rev = read_microcode_rev();
 	eax = cpuid_eax(1);
-	msr = rdmsr(IA32_BIOS_SIGN_ID);
-	rev = msr.hi;
-	x86_model = (eax >> 4) & 0x0f;
-	x86_family = (eax >> 8) & 0x0f;
+	get_fms(&c, eax);
 	sig = eax;
 
 	pf = 0;
-	if ((x86_model >= 5) || (x86_family > 6)) {
+	if ((c.x86_model >= 5) || (c.x86 > 6)) {
 		msr = rdmsr(IA32_PLATFORM_ID);
 		pf = 1 << ((msr.hi >> 18) & 7);
 	}
@@ -173,6 +170,8 @@ const void *intel_microcode_find(void)
 		microcode_len -= update_size;
 	}
 
+	ucode_updates = NULL;
+
 	return NULL;
 }
 
@@ -188,7 +187,7 @@ void intel_update_microcode_from_cbfs(void)
 }
 
 #if ENV_RAMSTAGE
-__weak int soc_skip_ucode_update(u32 currrent_patch_id,
+__weak int soc_skip_ucode_update(u32 current_patch_id,
 	u32 new_patch_id)
 {
 	return 0;

diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
@@ -9,11 +9,10 @@
 #include <device/device.h>
 
 /* Parallel MP initialization support. */
-static const void *microcode_patch;
-
 static void pre_mp_init(void)
 {
-	intel_microcode_load_unlocked(microcode_patch);
+	const void *patch = intel_microcode_find();
+	intel_microcode_load_unlocked(patch);
 
 	/* Setup MTRRs based on physical address size. */
 	x86_setup_mtrrs_with_detect();
@@ -32,7 +31,7 @@ static int get_cpu_count(void)
 
 static void get_microcode_info(const void **microcode, int *parallel)
 {
-	*microcode = microcode_patch;
+	*microcode = intel_microcode_find();
 	*parallel = !intel_ht_supported();
 }
 
@@ -98,8 +97,6 @@ static const struct mp_ops mp_ops = {
 
 void mp_init_cpus(struct bus *cpu_bus)
 {
-	microcode_patch = intel_microcode_find();
-
 	if (mp_init_with_smm(cpu_bus, &mp_ops))
 		printk(BIOS_ERR, "MP initialization failure.\n");
 }
diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c
@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <types.h>
-#include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <cpu/intel/speedstep.h>
+
 #include "model_2065x.h"
 
 /* MSR Documentation based on

diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c
@@ -123,8 +123,6 @@ static void model_2065x_init(struct device *cpu)
 }
 
 /* MP initialization support. */
-static const void *microcode_patch;
-
 static void pre_mp_init(void)
 {
 	/* Setup MTRRs based on physical address size. */
@@ -149,8 +147,7 @@ static int get_cpu_count(void)
 
 static void get_microcode_info(const void **microcode, int *parallel)
 {
-	microcode_patch = intel_microcode_find();
-	*microcode = microcode_patch;
+	*microcode = intel_microcode_find();
 	*parallel = !intel_ht_supported();
 }
 
@@ -160,6 +157,7 @@ static void per_cpu_smm_trigger(void)
 	smm_relocate();
 
 	/* After SMM relocation a 2nd microcode load is required. */
+	const void *microcode_patch = intel_microcode_find();
 	intel_microcode_load_unlocked(microcode_patch);
 }
 

diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c
@@ -13,49 +13,90 @@
 #include "model_206ax.h"
 #include "chip.h"
 
+/*
+ * List of supported C-states in this processor
+ *
+ * Latencies are typical worst-case package exit time in uS
+ * taken from the SandyBridge BIOS specification.
+ */
+static const acpi_cstate_t cstate_map[] = {
+	{	/* 0: C0 */
+	}, {	/* 1: C1 */
+		.latency = 1,
+		.power = 1000,
+		.resource = {
+			.addrl = 0x00,	/* MWAIT State 0 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 2: C1E */
+		.latency = 1,
+		.power = 1000,
+		.resource = {
+			.addrl = 0x01,	/* MWAIT State 0 Sub-state 1 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 3: C3 */
+		.latency = 63,
+		.power = 500,
+		.resource = {
+			.addrl = 0x10,	/* MWAIT State 1 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 4: C6 */
+		.latency = 87,
+		.power = 350,
+		.resource = {
+			.addrl = 0x20,	/* MWAIT State 2 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 5: C7 */
+		.latency = 90,
+		.power = 200,
+		.resource = {
+			.addrl = 0x30,	/* MWAIT State 3 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 6: C7S */
+		.latency = 90,
+		.power = 200,
+		.resource = {
+			.addrl = 0x31,	/* MWAIT State 3 Sub-state 1 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+};
+
 static int get_logical_cores_per_package(void)
 {
 	msr_t msr = rdmsr(MSR_CORE_THREAD_COUNT);
 	return msr.lo & 0xffff;
 }
 
-static void generate_cstate_entries(acpi_cstate_t *cstates,
-				    int c1, int c2, int c3)
-{
-	int cstate_count = 0;
-
-	/* Count number of active C-states */
-	if (c1 > 0)
-		++cstate_count;
-	if (c2 > 0)
-		++cstate_count;
-	if (c3 > 0)
-		++cstate_count;
-
-	acpigen_write_package(cstate_count + 1);
-	acpigen_write_byte(cstate_count);
-
-	/* Add an entry if the level is enabled */
-	if (c1 > 0) {
-		cstates[c1].ctype = 1;
-		acpigen_write_CST_package_entry(&cstates[c1]);
-	}
-	if (c2 > 0) {
-		cstates[c2].ctype = 2;
-		acpigen_write_CST_package_entry(&cstates[c2]);
-	}
-	if (c3 > 0) {
-		cstates[c3].ctype = 3;
-		acpigen_write_CST_package_entry(&cstates[c3]);
-	}
-
-	acpigen_pop_len();
-}
-
 static void generate_C_state_entries(void)
 {
-	struct cpu_info *info;
-	struct cpu_driver *cpu;
 	struct device *lapic;
 	struct cpu_intel_model_206ax_config *conf = NULL;
 
@@ -67,18 +108,21 @@ static void generate_C_state_entries(void)
 	if (!conf)
 		return;
 
-	/* Find CPU map of supported C-states */
-	info = cpu_info();
-	if (!info)
-		return;
-	cpu = find_cpu_driver(info->cpu);
-	if (!cpu || !cpu->cstates)
-		return;
+	const int acpi_cstates[3] = { conf->acpi_c1, conf->acpi_c2, conf->acpi_c3 };
 
-	acpigen_write_method("_CST", 0);
-	acpigen_emit_byte(RETURN_OP);
-	generate_cstate_entries(cpu->cstates, conf->acpi_c1, conf->acpi_c2, conf->acpi_c3);
-	acpigen_pop_len();
+	acpi_cstate_t acpi_cstate_map[ARRAY_SIZE(acpi_cstates)] = { 0 };
+
+	/* Count number of active C-states */
+	int count = 0;
+
+	for (int i = 0; i < ARRAY_SIZE(acpi_cstates); i++) {
+		if (acpi_cstates[i] > 0 && acpi_cstates[i] < ARRAY_SIZE(cstate_map)) {
+			acpi_cstate_map[count] = cstate_map[acpi_cstates[i]];
+			acpi_cstate_map[count].ctype = i + 1;
+			count++;
+		}
+	}
+	acpigen_write_CST_package(acpi_cstate_map, count);
 }
 
 static acpi_tstate_t tss_table_fine[] = {

diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <types.h>
-#include <arch/cpu.h>
 #include <cpu/x86/msr.h>
+
 #include "model_206ax.h"
 
 /* MSR Documentation based on

diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -20,83 +20,6 @@
 #include <cpu/intel/common/common.h>
 #include <smbios.h>
 
-/*
- * List of supported C-states in this processor
- *
- * Latencies are typical worst-case package exit time in uS
- * taken from the SandyBridge BIOS specification.
- */
-static acpi_cstate_t cstate_map[] = {
-	{	/* 0: C0 */
-	}, {	/* 1: C1 */
-		.latency = 1,
-		.power = 1000,
-		.resource = {
-			.addrl = 0x00,	/* MWAIT State 0 */
-			.space_id = ACPI_ADDRESS_SPACE_FIXED,
-			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
-			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
-			.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
-		}
-	},
-	{	/* 2: C1E */
-		.latency = 1,
-		.power = 1000,
-		.resource = {
-			.addrl = 0x01,	/* MWAIT State 0 Sub-state 1 */
-			.space_id = ACPI_ADDRESS_SPACE_FIXED,
-			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
-			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
-			.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
-		}
-	},
-	{	/* 3: C3 */
-		.latency = 63,
-		.power = 500,
-		.resource = {
-			.addrl = 0x10,	/* MWAIT State 1 */
-			.space_id = ACPI_ADDRESS_SPACE_FIXED,
-			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
-			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
-			.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
-		}
-	},
-	{	/* 4: C6 */
-		.latency = 87,
-		.power = 350,
-		.resource = {
-			.addrl = 0x20,	/* MWAIT State 2 */
-			.space_id = ACPI_ADDRESS_SPACE_FIXED,
-			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
-			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
-			.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
-		}
-	},
-	{	/* 5: C7 */
-		.latency = 90,
-		.power = 200,
-		.resource = {
-			.addrl = 0x30,	/* MWAIT State 3 */
-			.space_id = ACPI_ADDRESS_SPACE_FIXED,
-			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
-			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
-			.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
-		}
-	},
-	{	/* 6: C7S */
-		.latency = 90,
-		.power = 200,
-		.resource = {
-			.addrl = 0x31,	/* MWAIT State 3 Sub-state 1 */
-			.space_id = ACPI_ADDRESS_SPACE_FIXED,
-			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
-			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
-			.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,
-		}
-	},
-	{ 0 }
-};
-
 /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
 static const u8 power_limit_time_sec_to_msr[] = {
 	[0]   = 0x00,
@@ -466,8 +389,6 @@ static void model_206ax_init(struct device *cpu)
 }
 
 /* MP initialization support. */
-static const void *microcode_patch;
-
 static void pre_mp_init(void)
 {
 	/* Setup MTRRs based on physical address size. */
@@ -492,8 +413,7 @@ static int get_cpu_count(void)
 
 static void get_microcode_info(const void **microcode, int *parallel)
 {
-	microcode_patch = intel_microcode_find();
-	*microcode = microcode_patch;
+	*microcode = intel_microcode_find();
 	*parallel = !intel_ht_supported();
 }
 
@@ -503,6 +423,7 @@ static void per_cpu_smm_trigger(void)
 	smm_relocate();
 
 	/* After SMM relocation a 2nd microcode load is required. */
+	const void *microcode_patch = intel_microcode_find();
 	intel_microcode_load_unlocked(microcode_patch);
 }
 
@@ -554,5 +475,4 @@ static const struct cpu_device_id cpu_table[] = {
 static const struct cpu_driver driver __cpu_driver = {
 	.ops      = &cpu_dev_ops,
 	.id_table = cpu_table,
-	.cstates  = cstate_map,
 };
diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig
@@ -5,7 +5,7 @@ config CPU_INTEL_SLOT_1
 
 if CPU_INTEL_SLOT_1
 
-config SLOT_SPECIFIC_OPTIONS # dummy
+config SLOT_SPECIFIC_OPTIONS
 	def_bool y
 	select CPU_INTEL_MODEL_65X
 	select CPU_INTEL_MODEL_67X
@@ -32,7 +32,6 @@ config DCACHE_BSP_STACK_SIZE
 
 config C_ENV_BOOTBLOCK_SIZE
 	hex
-	default 0x4000 if BOOTBLOCK_CONSOLE
-	default 0x2000
+	default 0x10000
 
 endif
diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig
@@ -3,17 +3,13 @@ config CPU_INTEL_SOCKET_441
 
 if CPU_INTEL_SOCKET_441
 
-config SOCKET_SPECIFIC_OPTIONS # dummy
+config SOCKET_SPECIFIC_OPTIONS
 	def_bool y
 	select CPU_INTEL_MODEL_106CX
 	select MMX
 	select SSE
 	select SETUP_XIP_CACHE
 
-config C_ENV_BOOTBLOCK_SIZE
-	hex
-	default 0x8000
-
 config DCACHE_RAM_BASE
 	hex
 	default 0xfefc0000

diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig
@@ -3,7 +3,7 @@ config CPU_INTEL_SOCKET_LGA775
 
 if CPU_INTEL_SOCKET_LGA775
 
-config SOCKET_SPECIFIC_OPTIONS # dummy
+config SOCKET_SPECIFIC_OPTIONS
 	def_bool y
 	select CPU_INTEL_MODEL_6FX
 	select CPU_INTEL_MODEL_F3X
@@ -25,6 +25,6 @@ config DCACHE_BSP_STACK_SIZE
 
 config DCACHE_RAM_BASE
 	hex
-	default 0xfeffc000 # 4GB - 16MB - DCACHE_RAM_SIZE
+	default 0xfeff8000 # 4GB - 16MB - DCACHE_RAM_SIZE
 
 endif # CPU_INTEL_SOCKET_LGA775
diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig
@@ -3,7 +3,7 @@ config CPU_INTEL_SOCKET_M
 
 if CPU_INTEL_SOCKET_M
 
-config SOCKET_SPECIFIC_OPTIONS # dummy
+config SOCKET_SPECIFIC_OPTIONS
 	def_bool y
 	select CPU_INTEL_MODEL_6EX
 	select CPU_INTEL_MODEL_6FX
@@ -22,8 +22,4 @@ config DCACHE_BSP_STACK_SIZE
 	hex
 	default 0x2000
 
-config C_ENV_BOOTBLOCK_SIZE
-	hex
-	default 0x8000
-
 endif
diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig
@@ -3,7 +3,7 @@ config CPU_INTEL_SOCKET_MPGA604
 
 if CPU_INTEL_SOCKET_MPGA604
 
-config SOCKET_SPECIFIC_OPTIONS # dummy
+config SOCKET_SPECIFIC_OPTIONS
 	def_bool y
 	select CPU_INTEL_MODEL_F2X
 	select MMX

diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
@@ -133,4 +133,8 @@ void generate_cpu_entries(const struct device *device)
 	acpigen_write_processor_package("PPKG", 0, cores_per_package);
 
 	acpigen_write_processor_cnot(cores_per_package);
+
+	acpigen_write_scope("\\");
+	acpigen_write_name_integer("MPEN", numcpus > 1);
+	acpigen_pop_len();
 }
diff --git a/src/cpu/intel/speedstep/acpi/cpu.asl b/src/cpu/intel/speedstep/acpi/cpu.asl
@@ -5,6 +5,7 @@ External (\_SB.CNOT, MethodObj)
 External (\_SB_.CP00, DeviceObj)
 External (\_SB_.CP00._PPC)
 External (\_SB_.CP01._PPC)
+External (\MPEN, IntObj)
 
 Method (PNOT)
 {

diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig
@@ -44,8 +44,8 @@ endchoice
 
 config MAX_CPUS
 	int
-	default 4 if SMM_ASEG
-	default 32
+	default 32 if SMM_TSEG
+	default 4
 
 config CPU_QEMU_X86_64
 	bool "Experimental 64bit support"

diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc
diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc
@@ -8,6 +8,10 @@ ramstage-y += backup_default_smm.c
 
 subdirs-$(CONFIG_CPU_INTEL_COMMON_SMM) += ../intel/smm
 
+bootblock-y += entry32.S
+bootblock-y += entry16.S
+bootblock-y += reset16.S
+
 additional-dirs += $(obj)/cpu/x86
 
 SIPI_ELF=$(obj)/cpu/x86/sipi_vector.elf

diff --git a/src/cpu/x86/16bit/entry16.inc → src/cpu/x86/entry16.S b/src/cpu/x86/16bit/entry16.inc → src/cpu/x86/entry16.S
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
 /*
  * This software and ancillary information (herein called SOFTWARE)
  * called LinuxBIOS is made available under the terms described here.
@@ -28,10 +30,11 @@
 #include <arch/rom_segs.h>
 #include <cpu/x86/post_code.h>
 
-/* Symbol _start16bit must be aligned to 4kB to start AP CPUs with
- * Startup IPI message without RAM.
+.section .init._start, "ax", @progbits
+
+/* Symbol _start16bit must reachable from the reset vector, and be aligned to
+ * 4kB to start AP CPUs with Startup IPI message without RAM.
  */
-.align 4096
 .code16
 .globl _start16bit
 .type _start16bit, @function
@@ -121,7 +124,7 @@ _start16bit:
 	movl	%ebp, %eax
 
 	/* Now that we are in protected mode jump to a 32 bit code segment. */
-	ljmpl	$ROM_CODE_SEG, $__protected_start
+	ljmpl	$ROM_CODE_SEG, $bootblock_protected_mode_entry
 
 	/**
 	 * The gdt is defined in gdt_init.S, it has a 4 Gb code segment

diff --git a/src/arch/x86/bootblock_crt0.S → src/cpu/x86/entry32.S b/src/arch/x86/bootblock_crt0.S → src/cpu/x86/entry32.S
@@ -1,4 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/* For starting coreboot in protected mode */
+
 /*
  * This is the modern bootblock. It prepares the system for C environment runtime
  * setup. The actual setup is done by hardware-specific code.
@@ -8,17 +11,39 @@
  *
  */
 
+#include <arch/rom_segs.h>
 #include <cpu/x86/cr.h>
+#include <cpu/x86/post_code.h>
 
-.section .init._start, "ax", @progbits
+.section .init, "ax", @progbits
 
+	.code32
 /*
- * Include the old code for reset vector and protected mode entry. That code has
- * withstood the test of time.
+ *	When we come here we are in protected mode.
+ *	NOTE aligned to 4 so that we are sure that the prefetch
+ *	cache will be reloaded.
  */
-#include <cpu/x86/16bit/entry16.inc>
-#include <cpu/x86/16bit/reset16.inc>
-#include <cpu/x86/32bit/entry32.inc>
+	.align	4
+
+.globl bootblock_protected_mode_entry
+bootblock_protected_mode_entry:
+
+	/* Save the BIST value */
+	movl	%eax, %ebp
+
+#if !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES)
+	post_code(POST_ENTER_PROTECTED_MODE)
+#endif
+
+	movw	$ROM_DATA_SEG, %ax
+	movw	%ax, %ds
+	movw	%ax, %es
+	movw	%ax, %ss
+	movw	%ax, %fs
+	movw	%ax, %gs
+
+	/* Restore the BIST value to %eax */
+	movl	%ebp, %eax
 
 #if CONFIG(BOOTBLOCK_DEBUG_SPINLOOP)
 
@@ -30,14 +55,14 @@ debug_spinloop:
 	jz	debug_spinloop
 #endif
 
-bootblock_protected_mode_entry:
-
 #if !CONFIG(USE_MARCH_586)
 	/* MMX registers required here */
 
 	/* BIST result in eax */
 	movd	%eax, %mm0
 
+__timestamp:
+
 	/* Get an early timestamp */
 	rdtsc
 	movd	%eax, %mm1

diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
@@ -196,8 +196,12 @@ static void asmlinkage ap_init(unsigned int cpu)
 	/* Fix up APIC id with reality. */
 	info->cpu->path.apic.apic_id = lapicid();
 
-	printk(BIOS_INFO, "AP: slot %d apic_id %x.\n", cpu,
-		info->cpu->path.apic.apic_id);
+	if (cpu_is_intel())
+		printk(BIOS_INFO, "AP: slot %d apic_id %x, MCU rev: 0x%08x\n", cpu,
+		       info->cpu->path.apic.apic_id, get_current_microcode_rev());
+	else
+		printk(BIOS_INFO, "AP: slot %d apic_id %x\n", cpu,
+		       info->cpu->path.apic.apic_id);
 
 	/* Walk the flight plan */
 	ap_do_flight_plan();

diff --git a/src/cpu/x86/name/name.c b/src/cpu/x86/name/name.c
@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <string.h>
 #include <arch/cpu.h>
-#include <device/device.h>
 #include <cpu/x86/name.h>
+#include <stdint.h>
+#include <string.h>
 
 void fill_processor_name(char *processor_name)
 {

diff --git a/src/cpu/x86/16bit/reset16.inc → src/cpu/x86/reset16.S b/src/cpu/x86/16bit/reset16.inc → src/cpu/x86/reset16.S
@@ -12,4 +12,3 @@ _start:
 	 * instead of the weird 16 bit relocations that binutils does not
 	 * handle consistently between versions because they are used so rarely.
 	 */
-	.previous
diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc
@@ -33,6 +33,7 @@ ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual
 endif
 
 smm-y += save_state.c
+smm-y += smi_trigger.c
 
 ifeq ($(CONFIG_SMM_TSEG),y)
 

diff --git a/src/cpu/x86/smm/smi_trigger.c b/src/cpu/x86/smm/smi_trigger.c
@@ -4,24 +4,17 @@
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 
-int apm_control(u8 cmd)
+static void apmc_log(const char *fn, u8 cmd)
 {
-	if (!CONFIG(HAVE_SMI_HANDLER))
-		return -1;
-
 	switch (cmd) {
-	case APM_CNT_CST_CONTROL:
-		break;
-	case APM_CNT_PST_CONTROL:
-		break;
 	case APM_CNT_ACPI_DISABLE:
-		printk(BIOS_DEBUG, "Disabling ACPI via APMC.\n");
+		printk(BIOS_DEBUG, "%s: Disabling ACPI.\n", fn);
 		break;
 	case APM_CNT_ACPI_ENABLE:
-		printk(BIOS_DEBUG, "Enabling ACPI via APMC.\n");
+		printk(BIOS_DEBUG, "%s: Enabling ACPI.\n", fn);
 		break;
 	case APM_CNT_FINALIZE:
-		printk(BIOS_DEBUG, "Finalizing SMM.\n");
+		printk(BIOS_DEBUG, "%s: Finalizing SMM.\n", fn);
 		break;
 	case APM_CNT_ELOG_GSMI:
 		break;
@@ -30,12 +23,31 @@ int apm_control(u8 cmd)
 	case APM_CNT_SMMINFO:
 		break;
 	default:
+		printk(BIOS_DEBUG, "%s: Unknown APMC 0x%02x.\n", fn, cmd);
 		break;
 	}
+}
+
+int apm_control(u8 cmd)
+{
+	/* Never proceed inside SMI handler or without one. */
+	if (ENV_SMM || !CONFIG(HAVE_SMI_HANDLER))
+		return -1;
+
+	apmc_log(__func__, cmd);
 
 	/* Now raise the SMI. */
 	outb(cmd, APM_CNT);
 
 	printk(BIOS_DEBUG, "APMC done.\n");
 	return 0;
 }
+
+u8 apm_get_apmc(void)
+{
+	/* Emulate B2 register as the FADT / Linux expects it */
+	u8 cmd = inb(APM_CNT);
+
+	apmc_log("SMI#", cmd);
+	return cmd;
+}
diff --git a/src/cpu/x86/smm/smm_module_loaderv2.c b/src/cpu/x86/smm/smm_module_loaderv2.c
@@ -129,7 +129,7 @@ static int smm_create_map(uintptr_t smbase, unsigned int num_cpus,
 		return 0;
 	}
 
-	if (sizeof(cpus) / sizeof(struct cpu_smm_info) < num_cpus) {
+	if (ARRAY_SIZE(cpus) < num_cpus) {
 		printk(BIOS_ERR,
 			"%s: increase MAX_CPUS in Kconfig\n", __func__);
 		return 0;

diff --git a/src/device/Kconfig b/src/device/Kconfig
@@ -117,6 +117,16 @@ config NO_GFX_INIT
 
 endchoice
 
+config PRE_GRAPHICS_DELAY_MS
+	int "Graphics initialization delay in ms"
+	default 0
+	depends on VGA_ROM_RUN
+	help
+	  On some systems, coreboot boots so fast that connected monitors
+	  (mostly TVs) won't be able to wake up fast enough to talk to the
+	  VBIOS. On those systems we need to wait for a bit before executing
+	  the VBIOS.
+
 config ONBOARD_VGA_IS_PRIMARY
 	bool "Use onboard VGA as primary video device"
 	default n
@@ -513,6 +523,22 @@ config PCIEXP_PLUGIN_SUPPORT
 	bool
 	default y
 
+config MMCONF_BASE_ADDRESS
+	hex
+	depends on MMCONF_SUPPORT
+
+config MMCONF_BUS_NUMBER
+	int
+	depends on MMCONF_SUPPORT
+
+config MMCONF_LENGTH
+	hex
+	depends on MMCONF_SUPPORT
+	default 0x04000000 if MMCONF_BUS_NUMBER = 64
+	default 0x08000000 if MMCONF_BUS_NUMBER = 128
+	default 0x10000000 if MMCONF_BUS_NUMBER = 256
+	default 0x0
+
 config PCI_ALLOW_BUS_MASTER
 	bool "Allow coreboot to set optional PCI bus master bits"
 	default y

diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c
@@ -174,9 +174,9 @@ static int wait_for_valid(u8 *base)
 	reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID;
 	write32(base + HDA_ICII_REG, reg32);
 
-	while (timeout--) {
+	while (timeout--)
 		udelay(1);
-	}
+
 	timeout = 50;
 	while (timeout--) {
 		reg32 = read32(base + HDA_ICII_REG);
@@ -188,12 +188,37 @@ static int wait_for_valid(u8 *base)
 	return -1;
 }
 
+static int azalia_write_verb(u8 *base, u32 verb)
+{
+	if (wait_for_ready(base) < 0)
+		return -1;
+
+	write32(base + HDA_IC_REG, verb);
+
+	return wait_for_valid(base);
+}
+
+int azalia_program_verb_table(u8 *base, const u32 *verbs, u32 verb_size)
+{
+	if (!verbs)
+		return 0;
+
+	for (u32 i = 0; i < verb_size; i++) {
+		if (azalia_write_verb(base, verbs[i]) < 0)
+			return -1;
+	}
+	return 0;
+}
+
+__weak void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid)
+{
+}
+
 static void codec_init(struct device *dev, u8 *base, int addr)
 {
 	u32 reg32;
 	const u32 *verb;
 	u32 verb_size;
-	int i;
 
 	printk(BIOS_DEBUG, "azalia_audio: Initializing codec #%d\n", addr);
 
@@ -220,19 +245,13 @@ static void codec_init(struct device *dev, u8 *base, int addr)
 		printk(BIOS_DEBUG, "azalia_audio: No verb!\n");
 		return;
 	}
-	printk(BIOS_DEBUG, "azalia_audio: verb_size: %d\n", verb_size);
+	printk(BIOS_DEBUG, "azalia_audio: verb_size: %u\n", verb_size);
 
 	/* 3 */
-	for (i = 0; i < verb_size; i++) {
-		if (wait_for_ready(base) < 0)
-			return;
-
-		write32(base + HDA_IC_REG, verb[i]);
-
-		if (wait_for_valid(base) < 0)
-			return;
-	}
+	azalia_program_verb_table(base, verb, verb_size);
 	printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n");
+
+	mainboard_azalia_program_runtime_verbs(base, reg32);
 }
 
 static void codecs_init(struct device *dev, u8 *base, u32 codec_mask)

diff --git a/src/device/device.c b/src/device/device.c
@@ -166,8 +166,8 @@ static void read_resources(struct bus *bus)
 
 		if (!curdev->ops || !curdev->ops->read_resources) {
 			if (curdev->path.type != DEVICE_PATH_APIC)
-				printk(BIOS_ERR, "%s missing read_resources\n",
-				       dev_path(curdev));
+				printk(BIOS_ERR, "%s missing %s\n",
+				       dev_path(curdev), __func__);
 			continue;
 		}
 		post_log_path(curdev);
@@ -178,8 +178,8 @@ static void read_resources(struct bus *bus)
 			read_resources(link);
 	}
 	post_log_clear();
-	printk(BIOS_SPEW, "%s read_resources bus %d link: %d done\n",
-	       dev_path(bus->dev), bus->secondary, bus->link_num);
+	printk(BIOS_SPEW, "%s %s bus %d link: %d done\n",
+	       dev_path(bus->dev), __func__, bus->secondary, bus->link_num);
 }
 
 struct device *vga_pri = NULL;
@@ -210,11 +210,10 @@ static void set_vga_bridge_bits(void)
 				"A bridge on the path doesn't support 16-bit VGA decoding!");
 		}
 
-		if (dev->on_mainboard) {
+		if (dev->on_mainboard)
 			vga_onboard = dev;
-		} else {
+		else
 			vga = dev;
-		}
 
 		/* It isn't safe to enable all VGA cards. */
 		dev->command &= ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
@@ -269,8 +268,8 @@ void assign_resources(struct bus *bus)
 {
 	struct device *curdev;
 
-	printk(BIOS_SPEW, "%s assign_resources, bus %d link: %d\n",
-	       dev_path(bus->dev), bus->secondary, bus->link_num);
+	printk(BIOS_SPEW, "%s %s, bus %d link: %d\n",
+	       dev_path(bus->dev), __func__, bus->secondary, bus->link_num);
 
 	for (curdev = bus->children; curdev; curdev = curdev->sibling) {
 		if (!curdev->enabled || !curdev->resource_list)
@@ -285,8 +284,8 @@ void assign_resources(struct bus *bus)
 		curdev->ops->set_resources(curdev);
 	}
 	post_log_clear();
-	printk(BIOS_SPEW, "%s assign_resources, bus %d link: %d\n",
-	       dev_path(bus->dev), bus->secondary, bus->link_num);
+	printk(BIOS_SPEW, "%s %s, bus %d link: %d done\n",
+	       dev_path(bus->dev), __func__, bus->secondary, bus->link_num);
 }
 
 /**

diff --git a/src/device/device_const.c b/src/device/device_const.c
@@ -9,7 +9,7 @@
 #include <device/resource.h>
 
 /** Linked list of ALL devices */
-DEVTREE_CONST struct device * DEVTREE_CONST all_devices = &dev_root;
+DEVTREE_CONST struct device *DEVTREE_CONST all_devices = &dev_root;
 
 /**
  * Given a PCI bus and a devfn number, find the device structure.

diff --git a/src/device/device_util.c b/src/device/device_util.c
@@ -370,7 +370,8 @@ struct resource *new_resource(struct device *dev, unsigned int index)
 		resource->next = NULL;
 		tail = dev->resource_list;
 		if (tail) {
-			while (tail->next) tail = tail->next;
+			while (tail->next)
+				tail = tail->next;
 			tail->next = resource;
 		} else {
 			dev->resource_list = resource;
@@ -555,7 +556,7 @@ void search_bus_resources(struct bus *bus, unsigned long type_mask,
 
 			/* If it is a subtractive resource recurse. */
 			if (res->flags & IORESOURCE_SUBTRACTIVE) {
-				struct bus * subbus;
+				struct bus *subbus;
 				for (subbus = curdev->link_list; subbus;
 				     subbus = subbus->next)
 					if (subbus->link_num
@@ -604,11 +605,10 @@ void dev_set_enabled(struct device *dev, int enable)
 		return;
 
 	dev->enabled = enable;
-	if (dev->ops && dev->ops->enable) {
+	if (dev->ops && dev->ops->enable)
 		dev->ops->enable(dev);
-	} else if (dev->chip_ops && dev->chip_ops->enable_dev) {
+	else if (dev->chip_ops && dev->chip_ops->enable_dev)
 		dev->chip_ops->enable_dev(dev);
-	}
 }
 
 void disable_children(struct bus *bus)
@@ -814,7 +814,7 @@ void show_one_resource(int debug_level, struct device *dev,
 		  buf, resource_type(resource), comment);
 }
 
-void show_all_devs_resources(int debug_level, const char* msg)
+void show_all_devs_resources(int debug_level, const char *msg)
 {
 	struct device *dev;
 
@@ -862,11 +862,11 @@ void fixed_io_resource(struct device *dev, unsigned long index,
 		 IORESOURCE_RESERVE;
 }
 
-void mmconf_resource_init(struct resource *resource, resource_t base,
-	int buses)
+void mmconf_resource(struct device *dev, unsigned long index)
 {
-	resource->base = base;
-	resource->size = buses * MiB;
+	struct resource *resource = new_resource(dev, index);
+	resource->base = CONFIG_MMCONF_BASE_ADDRESS;
+	resource->size = CONFIG_MMCONF_LENGTH;
 	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
 		IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 
@@ -875,13 +875,6 @@ void mmconf_resource_init(struct resource *resource, resource_t base,
 			(unsigned long)(resource->base + resource->size));
 }
 
-void mmconf_resource(struct device *dev, unsigned long index)
-{
-	struct resource *resource = new_resource(dev, index);
-	mmconf_resource_init(resource, CONFIG_MMCONF_BASE_ADDRESS,
-		CONFIG_MMCONF_BUS_NUMBER);
-}
-
 void tolm_test(void *gp, struct device *dev, struct resource *new)
 {
 	struct resource **best_p = gp;

diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc
@@ -1,2 +1,3 @@
 romstage-y += ddr4.c ddr3.c ddr2.c ddr_common.c
-ramstage-y += ddr4.c ddr3.c ddr2.c ddr_common.c
+
+ramstage-y += ddr4.c ddr3.c ddr2.c ddr_common.c spd.c
diff --git a/src/device/dram/spd.c b/src/device/dram/spd.c
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/dram/spd.h>
+
+const char *spd_manufacturer_name(const uint16_t mod_id)
+{
+	switch (mod_id) {
+	case 0x9b85:
+		return "Crucial";
+	case 0x4304:
+		return "Ramaxel";
+	case 0x4f01:
+		return "Transcend";
+	case 0x9801:
+		return "Kingston";
+	case 0x987f:
+		return "Hynix";
+	case 0x9e02:
+		return "Corsair";
+	case 0xb004:
+		return "OCZ";
+	case 0xad80:
+		return "Hynix/Hyundai";
+	case 0x3486:
+		return "Super Talent";
+	case 0xcd04:
+		return "GSkill";
+	case 0xce80:
+		return "Samsung";
+	case 0xfe02:
+		return "Elpida";
+	case 0x2c80:
+		return "Micron";
+	default:
+		return NULL;
+	}
+}
diff --git a/src/device/i2c_bus.c b/src/device/i2c_bus.c
@@ -48,19 +48,17 @@ int i2c_dev_readb(struct device *const dev)
 			.len	= sizeof(val),
 		};
 
-		const int ret = busdev->ops->ops_i2c_bus->
-			transfer(busdev, &msg, 1);
+		const int ret = busdev->ops->ops_i2c_bus->transfer(busdev, &msg, 1);
 		if (ret)
 			return ret;
 		else
 			return val;
 	} else if (busdev->ops->ops_smbus_bus->recv_byte) {
 		return busdev->ops->ops_smbus_bus->recv_byte(dev);
-	} else {
-		printk(BIOS_ERR, "%s Missing ops_smbus_bus->recv_byte",
-		       dev_path(busdev));
-		return -1;
 	}
+
+	printk(BIOS_ERR, "%s Missing ops_smbus_bus->recv_byte", dev_path(busdev));
+	return -1;
 }
 
 int i2c_dev_writeb(struct device *const dev, uint8_t val)
@@ -79,11 +77,11 @@ int i2c_dev_writeb(struct device *const dev, uint8_t val)
 		return busdev->ops->ops_i2c_bus->transfer(busdev, &msg, 1);
 	} else if (busdev->ops->ops_smbus_bus->send_byte) {
 		return busdev->ops->ops_smbus_bus->send_byte(dev, val);
-	} else {
-		printk(BIOS_ERR, "%s Missing ops_smbus_bus->send_byte",
-		       dev_path(busdev));
-		return -1;
 	}
+
+	printk(BIOS_ERR, "%s Missing ops_smbus_bus->send_byte",
+	       dev_path(busdev));
+	return -1;
 }
 
 int i2c_dev_readb_at(struct device *const dev, uint8_t off)
@@ -109,23 +107,21 @@ int i2c_dev_readb_at(struct device *const dev, uint8_t off)
 			},
 		};
 
-		const int ret = busdev->ops->ops_i2c_bus->
-			transfer(busdev, msg, ARRAY_SIZE(msg));
+		const int ret = busdev->ops->ops_i2c_bus->transfer(busdev, msg,
+								   ARRAY_SIZE(msg));
 		if (ret)
 			return ret;
 		else
 			return val;
 	} else if (busdev->ops->ops_smbus_bus->read_byte) {
 		return busdev->ops->ops_smbus_bus->read_byte(dev, off);
-	} else {
-		printk(BIOS_ERR, "%s Missing ops_smbus_bus->read_byte",
-		       dev_path(busdev));
-		return -1;
 	}
+
+	printk(BIOS_ERR, "%s Missing ops_smbus_bus->read_byte", dev_path(busdev));
+	return -1;
 }
 
-int i2c_dev_writeb_at(struct device *const dev,
-			const uint8_t off, const uint8_t val)
+int i2c_dev_writeb_at(struct device *const dev, const uint8_t off, const uint8_t val)
 {
 	struct device *const busdev = i2c_busdev(dev);
 	if (!busdev)
@@ -142,15 +138,15 @@ int i2c_dev_writeb_at(struct device *const dev,
 		return busdev->ops->ops_i2c_bus->transfer(busdev, &msg, 1);
 	} else if (busdev->ops->ops_smbus_bus->write_byte) {
 		return busdev->ops->ops_smbus_bus->write_byte(dev, off, val);
-	} else {
-		printk(BIOS_ERR, "%s Missing ops_smbus_bus->write_byte",
-		       dev_path(busdev));
-		return -1;
 	}
+
+	printk(BIOS_ERR, "%s Missing ops_smbus_bus->write_byte",
+	       dev_path(busdev));
+	return -1;
 }
 
-int i2c_dev_read_at16(struct device *const dev,
-		      uint8_t *const buf, const size_t len, uint16_t off)
+int i2c_dev_read_at16(struct device *const dev, uint8_t *const buf, const size_t len,
+		      uint16_t off)
 {
 	struct device *const busdev = i2c_busdev(dev);
 	if (!busdev)
@@ -173,8 +169,8 @@ int i2c_dev_read_at16(struct device *const dev,
 		};
 
 		write_be16(&off, off);
-		const int ret = busdev->ops->ops_i2c_bus->transfer(
-					busdev, msg, ARRAY_SIZE(msg));
+		const int ret = busdev->ops->ops_i2c_bus->transfer(busdev, msg,
+								   ARRAY_SIZE(msg));
 		if (ret)
 			return ret;
 		else

diff --git a/src/device/oprom/include/x86emu/fpu_regs.h b/src/device/oprom/include/x86emu/fpu_regs.h
@@ -1,8 +1,8 @@
 /****************************************************************************
 *
-*						Realmode X86 Emulator Library
+*		Realmode X86 Emulator Library
 *
-*            	Copyright (C) 1996-1999 SciTech Software, Inc.
+*			Copyright (C) 1996-1999 SciTech Software, Inc.
 * 				     Copyright (C) David Mosberger-Tang
 * 					   Copyright (C) 1999 Egbert Eich
 *
@@ -103,13 +103,13 @@ struct x86_fpu_registers {
 #endif /* X86_FPU_SUPPORT */
 
 #if CONFIG(X86EMU_DEBUG)
-# define DECODE_PRINTINSTR32(t,mod,rh,rl)     	\
-	DECODE_PRINTF(t[(mod<<3)+(rh)]);
-# define DECODE_PRINTINSTR256(t,mod,rh,rl)    	\
-	DECODE_PRINTF(t[(mod<<6)+(rh<<3)+(rl)]);
+# define DECODE_PRINTINSTR32(t, mod, rh, rl)	\
+	DECODE_PRINTF(t[(mod<<3)+(rh)])
+# define DECODE_PRINTINSTR256(t, mod, rh, rl)	\
+	DECODE_PRINTF(t[(mod<<6)+(rh<<3)+(rl)])
 #else
-# define DECODE_PRINTINSTR32(t,mod,rh,rl)
-# define DECODE_PRINTINSTR256(t,mod,rh,rl)
+# define DECODE_PRINTINSTR32(t, mod, rh, rl)
+# define DECODE_PRINTINSTR256(t, mod, rh, rl)
 #endif
 
 #endif /* __X86EMU_FPU_REGS_H */
diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c
@@ -218,17 +218,20 @@ const vbe_mode_info_t *vbe_mode_info(void)
 
 static int vbe_check_for_failure(int ah);
 
-static void vbe_get_ctrl_info(vbe_info_block *info)
+static u8 vbe_get_ctrl_info(vbe_info_block *info)
 {
 	char *buffer = PTR_TO_REAL_MODE(__realmode_buffer);
 	u16 buffer_seg = (((unsigned long)buffer) >> 4) & 0xff00;
 	u16 buffer_adr = ((unsigned long)buffer) & 0xffff;
 	X86_EAX = realmode_interrupt(0x10, VESA_GET_INFO, 0x0000, 0x0000,
 			0x0000, buffer_seg, buffer_adr);
 	/* If the VBE function completed successfully, 0x0 is returned in AH */
-	if (X86_AH)
-		die("\nError: In %s function\n", __func__);
+	if (X86_AH) {
+		printk(BIOS_WARNING, "Warning: Error from VGA BIOS in %s\n", __func__);
+		return 1;
+	}
 	memcpy(info, buffer, sizeof(vbe_info_block));
+	return 0;
 }
 
 static void vbe_oprom_list_supported_mode(uint16_t *video_mode_ptr)
@@ -242,17 +245,19 @@ static void vbe_oprom_list_supported_mode(uint16_t *video_mode_ptr)
 	} while (mode != 0xffff);
 }
 
-static void vbe_oprom_supported_mode_list(void)
+static u8 vbe_oprom_supported_mode_list(void)
 {
 	uint16_t segment, offset;
 	vbe_info_block info;
 
-	vbe_get_ctrl_info(&info);
+	if (vbe_get_ctrl_info(&info))
+		return 1;
 
 	offset = info.video_mode_ptr;
 	segment = info.video_mode_ptr >> 16;
 
 	vbe_oprom_list_supported_mode((uint16_t *)((segment << 4) + offset));
+	return 0;
 }
 /*
  * EAX register is used to indicate the completion status upon return from
@@ -288,7 +293,8 @@ static int vbe_check_for_failure(int ah)
 	default:
 		printk(BIOS_DEBUG, "VBE: Unsupported video mode %x!\n",
 			CONFIG_FRAMEBUFFER_VESA_MODE);
-		vbe_oprom_supported_mode_list();
+		if (vbe_oprom_supported_mode_list())
+			printk(BIOS_WARNING, "VBE Warning: Could not get VBE mode list.\n");
 		status = -1;
 		break;
 	}
@@ -304,8 +310,10 @@ static u8 vbe_get_mode_info(vbe_mode_info_t * mi)
 	u16 buffer_adr = ((unsigned long)buffer) & 0xffff;
 	X86_EAX = realmode_interrupt(0x10, VESA_GET_MODE_INFO, 0x0000,
 			mi->video_mode, 0x0000, buffer_seg, buffer_adr);
-	if (vbe_check_for_failure(X86_AH))
-		die("\nError: In %s function\n", __func__);
+	if (vbe_check_for_failure(X86_AH)) {
+		printk(BIOS_WARNING, "VBE Warning: Error from VGA BIOS in %s\n", __func__);
+		return 1;
+	}
 	memcpy(mi->mode_info_block, buffer, sizeof(mi->mode_info_block));
 	mode_info_valid = 1;
 	return 0;
@@ -320,8 +328,10 @@ static u8 vbe_set_mode(vbe_mode_info_t * mi)
 	mi->video_mode &= ~(1 << 15);
 	X86_EAX = realmode_interrupt(0x10, VESA_SET_MODE, mi->video_mode,
 			0x0000, 0x0000, 0x0000, 0x0000);
-	if (vbe_check_for_failure(X86_AH))
-		die("\nError: In %s function\n", __func__);
+	if (vbe_check_for_failure(X86_AH)) {
+		printk(BIOS_WARNING, "VBE Warning: Error from VGA BIOS in %s\n", __func__);
+		return 1;
+	}
 	return 0;
 }
 
@@ -331,7 +341,10 @@ static u8 vbe_set_mode(vbe_mode_info_t * mi)
 void vbe_set_graphics(void)
 {
 	mode_info.video_mode = (1 << 14) | CONFIG_FRAMEBUFFER_VESA_MODE;
-	vbe_get_mode_info(&mode_info);
+	if (vbe_get_mode_info(&mode_info)) {
+		printk(BIOS_WARNING, "VBE Warning: Could not get VBE graphics mode info.\n");
+		return;
+	}
 	unsigned char *framebuffer =
 		(unsigned char *)mode_info.vesa.phys_base_ptr;
 	printk(BIOS_DEBUG, "VBE: resolution:  %dx%d@%d\n",
@@ -346,7 +359,10 @@ void vbe_set_graphics(void)
 		return;
 	}
 
-	vbe_set_mode(&mode_info);
+	if (vbe_set_mode(&mode_info)) {
+		printk(BIOS_WARNING, "VBE Warning: Could not set VBE graphics mode.\n");
+		return;
+	}
 	const struct lb_framebuffer fb = {
 		.physical_address    = mode_info.vesa.phys_base_ptr,
 		.x_resolution        = le16_to_cpu(mode_info.vesa.x_resolution),
@@ -369,11 +385,17 @@ void vbe_set_graphics(void)
 
 void vbe_textmode_console(void)
 {
-	delay(2);
-	X86_EAX = realmode_interrupt(0x10, 0x0003, 0x0000, 0x0000,
-				0x0000, 0x0000, 0x0000);
-	if (vbe_check_for_failure(X86_AH))
-		die("\nError: In %s function\n", __func__);
+	u8 retval = 1;
+	if (mode_info.vesa.phys_base_ptr) {
+		delay(2);
+		X86_EAX = realmode_interrupt(0x10, 0x0003, 0x0000, 0x0000,
+					0x0000, 0x0000, 0x0000);
+		if (!vbe_check_for_failure(X86_AH))
+			retval = 0;
+	}
+
+	if (retval)
+		printk(BIOS_WARNING, "VBE Warning: Could not set VBE text mode.\n");
 }
 
 #endif

diff --git a/src/device/pci_device.c b/src/device/pci_device.c
@@ -732,6 +732,12 @@ static int should_load_oprom(struct device *dev)
 	return 0;
 }
 
+static void oprom_pre_graphics_stall(void)
+{
+	if (CONFIG_PRE_GRAPHICS_DELAY_MS)
+		mdelay(CONFIG_PRE_GRAPHICS_DELAY_MS);
+}
+
 /** Default handler: only runs the relevant PCI BIOS. */
 void pci_dev_init(struct device *dev)
 {
@@ -760,6 +766,9 @@ void pci_dev_init(struct device *dev)
 	if (!should_run_oprom(dev, rom))
 		return;
 
+	/* Wait for any configured pre-graphics delay */
+	oprom_pre_graphics_stall();
+
 	run_bios(dev, (unsigned long)ram);
 
 	gfx_set_init_done(1);
@@ -1211,14 +1220,13 @@ void pci_scan_bus(struct bus *bus, unsigned int min_devfn,
 	struct device *dev, **prev;
 	int once = 0;
 
-	printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %02x\n", bus->secondary);
+	printk(BIOS_DEBUG, "PCI: %s for bus %02x\n", __func__, bus->secondary);
 
 	/* Maximum sane devfn is 0xFF. */
 	if (max_devfn > 0xff) {
-		printk(BIOS_ERR, "PCI: pci_scan_bus limits devfn %x - "
-		       "devfn %x\n", min_devfn, max_devfn);
-		printk(BIOS_ERR, "PCI: pci_scan_bus upper limit too big. "
-		       "Using 0xff.\n");
+		printk(BIOS_ERR, "PCI: %s limits devfn %x - devfn %x\n",
+		       __func__, min_devfn, max_devfn);
+		printk(BIOS_ERR, "PCI: %s upper limit too big. Using 0xff.\n", __func__);
 		max_devfn=0xff;
 	}
 

diff --git a/src/device/resource_allocator_common.c b/src/device/resource_allocator_common.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <console/console.h>
 #include <device/device.h>
 
 struct pick_largest_state {

diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S
@@ -26,7 +26,7 @@ _cache_as_ram_setup:
 /*
  * on entry:
  *   mm0: BIST (ignored)
- *   mm2_mm1: timestamp at bootblock_protected_mode_entry
+ *   mm2_mm1: timestamp
  */
 bootblock_pre_c_entry:
 

diff --git a/src/drivers/aspeed/common/ast_main.c b/src/drivers/aspeed/common/ast_main.c
@@ -393,7 +393,7 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags)
 	ast->dev = dev;
 
 	/* PCI BAR 1 */
-	res = find_resource(dev->pdev, PCI_BASE_ADDRESS_1);
+	res = probe_resource(dev->pdev, PCI_BASE_ADDRESS_1);
 	if (!res) {
 		dev_err(dev->pdev, "BAR1 resource not found.\n");
 		ret = -EIO;
@@ -407,19 +407,16 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags)
 
 	/* PCI BAR 2 */
 	ast->io_space_uses_mmap = false;
-	res = find_resource(dev->pdev, PCI_BASE_ADDRESS_2);
-	if (!res) {
+	res = probe_resource(dev->pdev, PCI_BASE_ADDRESS_2);
+	if (!res)
 		dev_err(dev->pdev, "BAR2 resource not found.\n");
-		ret = -EIO;
-		goto out_free;
-	}
 
 	/*
 	 * If we don't have IO space at all, use MMIO now and
 	 * assume the chip has MMIO enabled by default (rev 0x20
 	 * and higher).
 	 */
-	if (!(res->flags & IORESOURCE_IO)) {
+	if (!res || !(res->flags & IORESOURCE_IO)) {
 		DRM_INFO("platform has no IO space, trying MMIO\n");
 		ast->ioregs = ast->regs + AST_IO_MM_OFFSET;
 		ast->io_space_uses_mmap = true;
@@ -432,8 +429,6 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags)
 			ret = -EIO;
 			goto out_free;
 		}
-		/* Adjust the I/O space location to match expectations (the code expects offset 0x0 to be I/O location 0x380) */
-		ast->ioregs = (void *)AST_IO_MM_OFFSET;
 	}
 
 	ast_detect_chip(dev, &need_post);

diff --git a/src/drivers/elog/boot_count.c b/src/drivers/elog/boot_count.c
@@ -37,7 +37,7 @@ static int boot_count_cmos_read(struct boot_count *bc)
 	u8 i, *p;
 	u16 csum;
 
-	for (p = (u8*)bc, i = 0; i < sizeof(*bc); i++, p++)
+	for (p = (u8 *)bc, i = 0; i < sizeof(*bc); i++, p++)
 		*p = cmos_read(BOOT_COUNT_CMOS_OFFSET + i);
 
 	/* Verify signature */
@@ -66,7 +66,7 @@ static void boot_count_cmos_write(struct boot_count *bc)
 	bc->checksum = compute_ip_checksum(
 		bc, offsetof(struct boot_count, checksum));
 
-	for (p = (u8*)bc, i = 0; i < sizeof(*bc); i++, p++)
+	for (p = (u8 *)bc, i = 0; i < sizeof(*bc); i++, p++)
 		cmos_write(*p, BOOT_COUNT_CMOS_OFFSET + i);
 }
 

diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c
@@ -183,7 +183,7 @@ static void elog_debug_dump_buffer(const char *msg)
  */
 static void elog_update_checksum(struct event_header *event, u8 checksum)
 {
-	u8 *event_data = (u8*)event;
+	u8 *event_data = (u8 *)event;
 	event_data[event->length - 1] = checksum;
 }
 
@@ -193,7 +193,7 @@ static void elog_update_checksum(struct event_header *event, u8 checksum)
 static u8 elog_checksum_event(struct event_header *event)
 {
 	u8 index, checksum = 0;
-	u8 *data = (u8*)event;
+	u8 *data = (u8 *)event;
 
 	for (index = 0; index < event->length; index++)
 		checksum += data[index];

diff --git a/src/drivers/generic/bayhub/bh720.c b/src/drivers/generic/bayhub/bh720.c
@@ -4,15 +4,54 @@
 
 #include <console/console.h>
 #include <device/device.h>
+#include <device/mmio.h>
 #include <device/path.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include "chip.h"
 #include "bh720.h"
 
-__attribute__((weak)) void board_bh720(struct device *dev)
+static u32 bh720_read_pcr(u32 sdbar, u32 addr)
 {
+	write32((void *)(sdbar + BH720_MEM_RW_ADR), BH720_MEM_RW_READ | addr);
+	return read32((void *)(sdbar + BH720_MEM_RW_DATA));
+}
+
+static void bh720_write_pcr(u32 sdbar, u32 addr, u32 data)
+{
+	write32((void *)(sdbar + BH720_MEM_RW_DATA), data);
+	write32((void *)(sdbar + BH720_MEM_RW_ADR), BH720_MEM_RW_WRITE | addr);
+}
+
+static void bh720_rmw_pcr(u32 sdbar, u32 addr, u32 clear, u32 set)
+{
+	u32 data = bh720_read_pcr(sdbar, addr);
+	data &= ~clear;
+	data |= set;
+	bh720_write_pcr(sdbar, addr, data);
+}
+
+static void bh720_program_hs200_mode(struct device *dev)
+{
+	u32 sdbar = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
+
+	/* Enable Memory Access Function */
+	write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x40000000);
+	bh720_write_pcr(sdbar, 0xd0, 0x80000000);
+
+	/* Set EMMC VCCQ 1.8V PCR 0x308[4] */
+	bh720_rmw_pcr(sdbar, BH720_PCR_EMMC_SETTING, 0, BH720_PCR_EMMC_SETTING_1_8V);
+
+	/* Set Base clock to 200MHz(PCR 0x304[31:16] = 0x2510) */
+	bh720_rmw_pcr(sdbar, BH720_PCR_DrvStrength_PLL, 0xffff << 16, 0x2510 << 16);
+
+	/* Use PLL Base clock PCR 0x3E4[22] = 1 */
+	bh720_rmw_pcr(sdbar, BH720_PCR_CSR, 0, BH720_PCR_CSR_EMMC_MODE_SEL);
+
+	/* Disable Memory Access */
+	bh720_write_pcr(sdbar, 0xd0, 0x80000001);
+	write32((void *)(sdbar + BH720_MEM_ACCESS_EN), 0x80000000);
 }
 
 static void bh720_init(struct device *dev)
@@ -43,7 +82,8 @@ static void bh720_init(struct device *dev)
 		       pci_read_config32(dev, BH720_LINK_CTRL));
 	}
 
-	board_bh720(dev);
+	if (config && !config->disable_hs200_mode)
+		bh720_program_hs200_mode(dev);
 
 	if (config && config->vih_tuning_value) {
 		/* Tune VIH */

diff --git a/src/drivers/generic/bayhub/bh720.h b/src/drivers/generic/bayhub/bh720.h
@@ -39,5 +39,3 @@ enum {
 	BH720_PCR_CSR			= 0x3e4,
 	BH720_PCR_CSR_EMMC_MODE_SEL	= BIT(22),
 };
-
-void board_bh720(struct device *dev);
diff --git a/src/drivers/generic/bayhub/chip.h b/src/drivers/generic/bayhub/chip.h
@@ -9,6 +9,9 @@ struct drivers_generic_bayhub_config {
 	/* 1 to enable power-saving mode, 0 to disable */
 	int power_saving;
 
+	/* When set, disables programming HS200 mode */
+	bool disable_hs200_mode;
+
 	/* CLK and DAT tuning values */
 	uint8_t vih_tuning_value;
 };
diff --git a/src/drivers/generic/bayhub_lv2/Kconfig b/src/drivers/generic/bayhub_lv2/Kconfig
@@ -0,0 +1,2 @@
+config DRIVERS_GENERIC_BAYHUB_LV2
+	bool
diff --git a/src/drivers/generic/bayhub_lv2/Makefile.inc b/src/drivers/generic/bayhub_lv2/Makefile.inc
@@ -0,0 +1 @@
+ramstage-$(CONFIG_DRIVERS_GENERIC_BAYHUB_LV2) += lv2.c
diff --git a/src/drivers/generic/bayhub_lv2/chip.h b/src/drivers/generic/bayhub_lv2/chip.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdbool.h>
+
+/* Bayhub LV2 PCIe to SD bridge */
+struct drivers_generic_bayhub_lv2_config {
+	bool enable_power_saving;
+};
diff --git a/src/drivers/generic/bayhub_lv2/lv2.c b/src/drivers/generic/bayhub_lv2/lv2.c
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Driver for BayHub Technology LV2 PCI to SD bridge */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/path.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include "chip.h"
+#include "lv2.h"
+
+static void lv2_enable(struct device *dev)
+{
+	struct drivers_generic_bayhub_lv2_config *config = dev->chip_info;
+	pci_dev_init(dev);
+
+	if (!config || !config->enable_power_saving)
+		return;
+	/*
+	 * This procedure for enabling power-saving mode is from the
+	 * BayHub BIOS Implementation Guideline document.
+	 */
+	pci_write_config32(dev, LV2_PROTECT, LV2_PROTECT_OFF | LV2_PROTECT_LOCK_OFF);
+	pci_or_config32(dev, LV2_PCR_HEX_FC, LV2_PCIE_PHY_P1_ENABLE);
+	pci_update_config32(dev, LV2_PCR_HEX_E0, LV2_PCI_PM_L1_TIMER_MASK, LV2_PCI_PM_L1_TIMER);
+	pci_update_config32(dev, LV2_PCR_HEX_FC, LV2_ASPM_L1_TIMER_MASK, LV2_ASPM_L1_TIMER);
+	pci_or_config32(dev, LV2_PCR_HEX_A8, LV2_LTR_ENABLE);
+	pci_write_config32(dev, LV2_PCR_HEX_234, LV2_MAX_LATENCY_SETTING);
+	pci_update_config32(dev, LV2_PCR_HEX_3F4, LV2_L1_SUBSTATE_OPTIMISE_MASK,
+			    LV2_L1_SUBSTATE_OPTIMISE);
+	pci_update_config32(dev, LV2_PCR_HEX_300, LV2_TUNING_WINDOW_MASK, LV2_TUNING_WINDOW);
+	pci_update_config32(dev, LV2_PCR_HEX_304, LV2_DRIVER_STRENGTH_MASK,
+			    LV2_DRIVER_STRENGTH);
+	pci_update_config32(dev, LV2_PCR_HEX_308, LV2_RESET_DMA_DISABLE_MASK,
+			    LV2_RESET_DMA_DISABLE);
+	pci_write_config32(dev, LV2_PROTECT, LV2_PROTECT_ON | LV2_PROTECT_LOCK_ON);
+	printk(BIOS_INFO, "BayHub LV2: Power-saving enabled\n");
+}
+
+static struct device_operations lv2_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.ops_pci		= &pci_dev_ops_pci,
+	.enable			= lv2_enable,
+};
+
+static const unsigned short pci_device_ids[] = {
+	PCI_DEVICE_ID_O2_LV2,
+	0
+};
+
+static const struct pci_driver bayhub_lv2 __pci_driver = {
+	.ops		= &lv2_ops,
+	.vendor		= PCI_VENDOR_ID_O2,
+	.devices	= pci_device_ids,
+};
+
+struct chip_operations drivers_generic_bayhub_lv2_ops = {
+	CHIP_NAME("BayHub Technology LV2 PCIe to SD bridge")
+};
diff --git a/src/drivers/generic/bayhub_lv2/lv2.h b/src/drivers/generic/bayhub_lv2/lv2.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* Driver for BayHub Technology LV2 PCIe to SD bridge */
+
+#include <types.h>
+
+enum {
+	LV2_PROTECT			= 0xD0,
+	LV2_PROTECT_LOCK_OFF		= 0,
+	LV2_PROTECT_LOCK_ON		= BIT(0),
+	LV2_PROTECT_OFF			= 0,
+	LV2_PROTECT_ON			= BIT(31),
+	LV2_PCR_HEX_FC			= 0xFC,
+	LV2_PCIE_PHY_P1_ENABLE		= BIT(25),
+	LV2_ASPM_L1_TIMER		= 0x000E0000,
+	LV2_ASPM_L1_TIMER_MASK		= 0xFFF0FFFF,
+	LV2_PCR_HEX_A8			= 0xA8,
+	LV2_LTR_ENABLE			= BIT(10),
+	LV2_PCR_HEX_E0			= 0xE0,
+	LV2_PCI_PM_L1_TIMER		= 0x30000000,
+	LV2_PCI_PM_L1_TIMER_MASK	= 0x0FFFFFFF,
+	LV2_PCR_HEX_234			= 0x234,
+	LV2_MAX_LATENCY_SETTING		= 0x10011001,
+	LV2_PCR_HEX_3F4			= 0x3F4,
+	LV2_L1_SUBSTATE_OPTIMISE	= 0x0000000A,
+	LV2_L1_SUBSTATE_OPTIMISE_MASK	= 0xFFFFFFF0,
+	LV2_PCR_HEX_300			= 0x300,
+	LV2_TUNING_WINDOW		= 0x00006055,
+	LV2_TUNING_WINDOW_MASK		= 0xFFFF0F00,
+	LV2_PCR_HEX_304			= 0x304,
+	LV2_DRIVER_STRENGTH		= 0x0000224B,
+	LV2_DRIVER_STRENGTH_MASK	= 0xFFFF0000,
+	LV2_PCR_HEX_308			= 0x308,
+	LV2_RESET_DMA_DISABLE		= 0x00C00000,
+	LV2_RESET_DMA_DISABLE_MASK	= 0xFF3FFFFF,
+};
diff --git a/src/drivers/gfx/generic/generic.c b/src/drivers/gfx/generic/generic.c
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <acpi/acpigen.h>
-#include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>

diff --git a/src/drivers/i2c/hid/hid.c b/src/drivers/i2c/hid/hid.c
@@ -1,6 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <acpi/acpigen_dsm.h>
+#include <acpi/acpi_device.h>
+#include <assert.h>
 #include <device/device.h>
 #include <string.h>
 #include "chip.h"
@@ -68,6 +70,18 @@ static void i2c_hid_enable(struct device *dev)
 		}
 	}
 
+	/*
+	 * Ensure that I2C HID devices use level triggered interrupts as per ACPI
+	 * I2C HID requirement. Check interrupt and GPIO interrupt.
+	 */
+	if ((!config->generic.irq_gpio.pin_count &&
+	      config->generic.irq.mode != ACPI_IRQ_LEVEL_TRIGGERED) ||
+	    (config->generic.irq_gpio.pin_count &&
+	     config->generic.irq_gpio.irq.mode != ACPI_IRQ_LEVEL_TRIGGERED)) {
+		printk(BIOS_ERR, "%s IRQ is not level triggered.\n", config->generic.hid);
+		BUG();
+	}
+
 	dev->ops = &i2c_hid_ops;
 
 	if (config && config->generic.desc) {

diff --git a/src/drivers/intel/dptf/chip.h b/src/drivers/intel/dptf/chip.h
@@ -4,7 +4,7 @@
 #define _DRIVERS_INTEL_DPTF_CHIP_H_
 
 #include <acpi/acpigen_dptf.h>
-#include <timer.h> /* for MSECS_PER_SEC */
+#include <timer.h>
 
 #define DPTF_PASSIVE(src, tgt, tmp, prd) \
 	{.source = DPTF_##src, .target = DPTF_##tgt, .temp = (tmp), .period = (prd)}

diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig
@@ -78,7 +78,7 @@ config SKIP_FSP_CAR
 	help
 	  Selected by platforms that implement their own CAR setup.
 
-config FSP1_1_DISPLAY_LOGO
+config BMP_LOGO
 	bool "Enable logo"
 	default n
 	help
@@ -87,7 +87,7 @@ config FSP1_1_DISPLAY_LOGO
 
 config FSP1_1_LOGO_FILE_NAME
 	string "Logo file"
-	depends on FSP1_1_DISPLAY_LOGO
+	depends on BMP_LOGO
 	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/logo.bmp"
 
 endif #PLATFORM_USES_FSP1_1
diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc
@@ -21,7 +21,6 @@ romstage-$(CONFIG_MMA) += mma_core.c
 ramstage-y += fsp_relocate.c
 ramstage-y += fsp_util.c
 ramstage-y += hob.c
-ramstage-$(CONFIG_FSP1_1_DISPLAY_LOGO) += logo.c
 ramstage-y += ramstage.c
 ramstage-$(CONFIG_INTEL_GMA_ADD_VBT) += vbt.c
 ramstage-$(CONFIG_MMA) += mma_core.c
@@ -44,7 +43,7 @@ fsp.bin-COREBOOT-position := $(CONFIG_FSP_LOC)
 endif
 
 # Add logo to the cbfs image
-cbfs-files-$(CONFIG_FSP1_1_DISPLAY_LOGO) += logo.bmp
+cbfs-files-$(CONFIG_BMP_LOGO) += logo.bmp
 logo.bmp-file := $(call strip_quotes,$(CONFIG_FSP1_1_LOGO_FILE_NAME))
 logo.bmp-type := raw
 logo.bmp-compression := LZMA

diff --git a/src/drivers/intel/fsp1_1/include/fsp/ramstage.h b/src/drivers/intel/fsp1_1/include/fsp/ramstage.h
@@ -6,24 +6,15 @@
 #include <fsp/util.h>
 #include <stdint.h>
 
-/*
- * Load FSP from stage cache or CBFS. This allows SoCs to load FSP separately
- * from calling silicon init. It might be required in cases where stage cache is
- * no longer available by the point SoC calls into silicon init.
- */
-void fsp_load(void);
 /* Perform Intel silicon init. */
 void intel_silicon_init(void);
-void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup);
-const struct cbmem_entry *fsp_load_logo(UINT32 *logo_ptr, UINT32 *logo_size);
 /* Called after the silicon init code has run. */
 void soc_after_silicon_init(void);
 /* Initialize UPD data before SiliconInit call. */
 void soc_silicon_init_params(SILICON_INIT_UPD *params);
 void mainboard_silicon_init_params(SILICON_INIT_UPD *params);
 void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
 	SILICON_INIT_UPD *new);
-const struct cbmem_entry *soc_load_logo(SILICON_INIT_UPD *params);
-void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params);
+void load_vbt(SILICON_INIT_UPD *params);
 
 #endif /* _INTEL_COMMON_RAMSTAGE_H_ */
diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
@@ -9,7 +9,7 @@
 #include <fsp/car.h>
 #include <fsp/util.h>
 #include <soc/intel/common/mma.h>
-#include <soc/pm.h>		/* chip_power_state */
+#include <soc/pm.h>
 
 struct romstage_params {
 	uint32_t fsp_version;

diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h
@@ -3,7 +3,6 @@
 #ifndef FSP1_1_UTIL_H
 #define FSP1_1_UTIL_H
 
-#include <rules.h>
 #include <arch/cpu.h>
 #include <fsp/api.h>
 /* Current users expect to get the SoC's FSP definitions by including util.h. */

diff --git a/src/drivers/intel/fsp1_1/logo.c b/src/drivers/intel/fsp1_1/logo.c
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
@@ -8,7 +8,7 @@
 #include <cpu/x86/smm.h>
 #include <fsp/romstage.h>
 #include <fsp/util.h>
-#include <lib.h> /* hexdump */
+#include <lib.h>
 #include <string.h>
 #include <timestamp.h>
 

diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <bootmode.h>
+#include <bootsplash.h>
 #include <acpi/acpi.h>
 #include <console/console.h>
 #include <fsp/ramstage.h>
@@ -50,15 +51,14 @@ static void display_hob_info(FSP_INFO_HEADER *fsp_info_header)
 	}
 }
 
-void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
+static void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header)
 {
 	FSP_SILICON_INIT fsp_silicon_init;
 	SILICON_INIT_UPD *original_params;
 	SILICON_INIT_UPD silicon_init_params;
 	EFI_STATUS status;
 	UPD_DATA_REGION *upd_ptr;
 	VPD_DATA_REGION *vpd_ptr;
-	const struct cbmem_entry *logo_entry = NULL;
 
 	/* Display the FSP header */
 	if (fsp_info_header == NULL) {
@@ -82,11 +82,12 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
 
 	/* Locate VBT and pass to FSP GOP */
 	if (CONFIG(RUN_FSP_GOP))
-		load_vbt(is_s3_wakeup, &silicon_init_params);
+		load_vbt(&silicon_init_params);
 	mainboard_silicon_init_params(&silicon_init_params);
 
-	if (CONFIG(FSP1_1_DISPLAY_LOGO) && !is_s3_wakeup)
-		logo_entry = soc_load_logo(&silicon_init_params);
+	if (CONFIG(BMP_LOGO))
+		bmp_load_logo(&silicon_init_params.PcdLogoPtr,
+			      &silicon_init_params.PcdLogoSize);
 
 	/* Display the UPD data */
 	if (CONFIG(DISPLAY_UPD_DATA))
@@ -106,8 +107,8 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
 	printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status);
 
 	/* The logo_entry can be freed up now as it is not required any longer */
-	if (logo_entry && !is_s3_wakeup)
-		cbmem_entry_remove(logo_entry);
+	if (CONFIG(BMP_LOGO))
+		bmp_release_logo();
 
 	/* Mark graphics init done after SiliconInit if VBT was provided */
 #if CONFIG(RUN_FSP_GOP)
@@ -143,21 +144,6 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
 	soc_after_silicon_init();
 }
 
-static void fsp_cache_save(struct prog *fsp)
-{
-	if (CONFIG(NO_STAGE_CACHE))
-		return;
-
-	printk(BIOS_DEBUG, "FSP: Saving binary in cache\n");
-
-	if (prog_entry(fsp) == NULL) {
-		printk(BIOS_ERR, "ERROR: No FSP to save in cache.\n");
-		return;
-	}
-
-	stage_cache_add(STAGE_REFCODE, fsp);
-}
-
 static int fsp_find_and_relocate(struct prog *fsp)
 {
 	if (prog_locate(fsp)) {
@@ -173,33 +159,27 @@ static int fsp_find_and_relocate(struct prog *fsp)
 	return 0;
 }
 
-void fsp_load(void)
+static void fsp_load(void)
 {
-	static int load_done;
 	struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin");
-	int is_s3_wakeup = acpi_is_wakeup_s3();
-
-	if (load_done)
-		return;
 
-	if (is_s3_wakeup && !CONFIG(NO_STAGE_CACHE)) {
-		printk(BIOS_DEBUG, "FSP: Loading binary from cache\n");
+	if (resume_from_stage_cache()) {
 		stage_cache_load_stage(STAGE_REFCODE, &fsp);
 	} else {
 		fsp_find_and_relocate(&fsp);
-		fsp_cache_save(&fsp);
+
+		if (prog_entry(&fsp))
+			stage_cache_add(STAGE_REFCODE, &fsp);
 	}
 
 	/* FSP_INFO_HEADER is set as the program entry. */
 	fsp_update_fih(prog_entry(&fsp));
-
-	load_done = 1;
 }
 
 void intel_silicon_init(void)
 {
 	fsp_load();
-	fsp_run_silicon_init(fsp_get_fih(), acpi_is_wakeup_s3());
+	fsp_run_silicon_init(fsp_get_fih());
 }
 
 /* Initialize the UPD parameters for SiliconInit */

diff --git a/src/drivers/intel/fsp1_1/vbt.c b/src/drivers/intel/fsp1_1/vbt.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <acpi/acpi.h>
 #include <bootmode.h>
 #include <console/console.h>
 #include <drivers/intel/gma/opregion.h>
@@ -8,13 +9,13 @@
 #include <lib.h>
 
 /* Locate VBT and pass it to FSP GOP */
-void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params)
+void load_vbt(SILICON_INIT_UPD *params)
 {
 	const optionrom_vbt_t *vbt_data = NULL;
 	size_t vbt_len;
 
 	/* Check boot mode - for S3 resume path VBT loading is not needed */
-	if (s3_resume) {
+	if (acpi_is_wakeup_s3()) {
 		printk(BIOS_DEBUG, "S3 resume do not pass VBT to GOP\n");
 	} else if (display_init_required()) {
 		/* Get VBT data */

diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
@@ -31,6 +31,13 @@ config PLATFORM_USES_FSP2_2
 
 if PLATFORM_USES_FSP2_0
 
+config PLATFORM_USES_FSP2_X86_32
+	bool
+	default y
+	help
+	  The FSP 2.0 runs in x86_32 protected mode.
+	  Once there's a x86_64 FSP this needs to default to n.
+
 config HAVE_INTEL_FSP_REPO
 	bool
 	help
@@ -113,7 +120,7 @@ config FSP_S_FILE
 config FSP_CAR
 	bool
 	default n
-	select NO_CBFS_MCACHE
+	select NO_CBFS_MCACHE if !NO_FSP_TEMP_RAM_EXIT
 	help
 	  Use FSP APIs to initialize & Tear Down the Cache-As-Ram
 
@@ -126,6 +133,13 @@ config FSP_T_RESERVED_SIZE
 	  defined in the FSP specification but in the SOC integration
 	  guides.
 
+config NO_FSP_TEMP_RAM_EXIT
+	bool
+	depends on FSP_CAR
+	help
+	  Select this on a platform where you want to use FSP-T but use
+	  coreboot code to tear down CAR.
+
 config FSP_M_XIP
 	bool
 	default n
@@ -166,21 +180,11 @@ config FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
 	  This allows deployed systems to bump their version number
 	  with the same FSP which will trigger a retrain of the memory.
 
-config FSP_PEIM_TO_PEIM_INTERFACE
-	bool
-	select FSP_USES_MP_SERVICES_PPI
-	help
-	  This option allows SOC user to create specific PPI for Intel FSP
-	  usage, coreboot will provide required PPI structure definitions
-	  along with all APIs as per EFI specification. So far this feature
-	  is limited till EFI_PEI_MP_SERVICE_PPI and this option might be
-	  useful to add further PPI if required.
-
 config HAVE_FSP_LOGO_SUPPORT
 	bool
 	default n
 
-config FSP2_0_DISPLAY_LOGO
+config BMP_LOGO
 	bool "Enable logo"
 	default n
 	depends on HAVE_FSP_LOGO_SUPPORT
@@ -191,7 +195,7 @@ config FSP2_0_DISPLAY_LOGO
 
 config FSP2_0_LOGO_FILE_NAME
 	string "Logo file"
-	depends on FSP2_0_DISPLAY_LOGO
+	depends on BMP_LOGO
 	default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/logo.bmp"
 
 config FSP_COMPRESS_FSP_S_LZMA
@@ -264,9 +268,4 @@ config SOC_INTEL_COMMON_FSP_RESET
 	  Common code block to handle platform reset request raised by FSP. The FSP
 	  will use the FSP EAS v2.0 section 12.2.2 (OEM Status Code) to indicate that
 	  a reset is required.
-
-if FSP_PEIM_TO_PEIM_INTERFACE
-source "src/drivers/intel/fsp2_0/ppi/Kconfig"
-endif
-
 endif
diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc
@@ -22,14 +22,15 @@ ramstage-y += hand_off_block.c
 ramstage-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c
 ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
 ramstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c
-ramstage-$(CONFIG_FSP2_0_DISPLAY_LOGO) += logo.c
 ramstage-y += notify.c
 ramstage-y += silicon_init.c
 ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
 ramstage-y += util.c
 ramstage-$(CONFIG_MMA) += mma_core.c
 
+ifneq ($(CONFIG_NO_FSP_TEMP_RAM_EXIT),y)
 postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c
+endif
 postcar-$(CONFIG_FSP_CAR) += util.c
 postcar-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c
 postcar-y += hand_off_block.c
@@ -84,7 +85,7 @@ $(obj)/Fsp_T.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(obj)/Fsp_M.fd
 endif
 
 # Add logo to the cbfs image
-cbfs-files-$(CONFIG_FSP2_0_DISPLAY_LOGO) += logo.bmp
+cbfs-files-$(CONFIG_BMP_LOGO) += logo.bmp
 logo.bmp-file := $(call strip_quotes,$(CONFIG_FSP2_0_LOGO_FILE_NAME))
 logo.bmp-type := raw
 logo.bmp-compression := LZMA
@@ -93,7 +94,6 @@ ifneq ($(call strip_quotes,$(CONFIG_FSP_HEADER_PATH)),)
 CPPFLAGS_common+=-I$(CONFIG_FSP_HEADER_PATH)
 endif
 
-# Include PPI directory of CONFIG_FSP_PEIM_TO_PEIM_INTERFACE is enable
-subdirs-$(CONFIG_FSP_PEIM_TO_PEIM_INTERFACE) += ppi
+subdirs-y += ppi
 
 endif
diff --git a/src/drivers/intel/fsp2_0/header_display.c b/src/drivers/intel/fsp2_0/header_display.c
@@ -19,24 +19,24 @@ void fsp_print_header_info(const struct fsp_header *hdr)
 	printk(BIOS_SPEW, "Type: %s/%s\n",
 			(hdr->component_attribute & 1) ? "release" : "debug",
 			(hdr->component_attribute & 2) ? "official" : "test");
-	printk(BIOS_SPEW, "image ID: %s, base 0x%lx + 0x%zx\n",
-		hdr->image_id, hdr->image_base, hdr->image_size);
+	printk(BIOS_SPEW, "image ID: %s, base 0x%zx + 0x%zx\n",
+		hdr->image_id, (size_t)hdr->image_base, (size_t)hdr->image_size);
 	printk(BIOS_SPEW, "\tConfig region        0x%zx + 0x%zx\n",
-		hdr->cfg_region_offset, hdr->cfg_region_size);
+		(size_t)hdr->cfg_region_offset, (size_t)hdr->cfg_region_size);
 
 	if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPM) {
 		printk(BIOS_SPEW, "\tMemory init offset   0x%zx\n",
-						hdr->memory_init_entry_offset);
+		       (size_t)hdr->memory_init_entry_offset);
 	}
 
 	if ((hdr->component_attribute >> 12) == FSP_HDR_ATTRIB_FSPS) {
 		printk(BIOS_SPEW, "\tSilicon init offset  0x%zx\n",
-						hdr->silicon_init_entry_offset);
+		       (size_t)hdr->silicon_init_entry_offset);
 		if (CONFIG(PLATFORM_USES_FSP2_2))
 			printk(BIOS_SPEW, "\tMultiPhaseSiInit offset  0x%zx\n",
-						hdr->multi_phase_si_init_entry_offset);
+			       (size_t)hdr->multi_phase_si_init_entry_offset);
 		printk(BIOS_SPEW, "\tNotify phase offset  0x%zx\n",
-						hdr->notify_phase_entry_offset);
+		       (size_t)hdr->notify_phase_entry_offset);
 	}
 
 }
diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -33,15 +33,15 @@ enum fsp_notify_phase {
 
 /* Main FSP stages */
 void fsp_memory_init(bool s3wake);
-void fsp_silicon_init(bool s3wake);
+void fsp_silicon_init(void);
 void fsp_temp_ram_exit(void);
 
 /*
  * Load FSP-S from stage cache or CBFS. This allows SoCs to load FSPS-S
  * separately from calling silicon init. It might be required in cases where
  * stage cache is no longer available by the point SoC calls into silicon init.
  */
-void fsps_load(bool s3wake);
+void fsps_load(void);
 
 /* Callbacks for updating stage-specific parameters */
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version);
@@ -59,16 +59,13 @@ int soc_fsp_multi_phase_init_is_enable(void);
 uint8_t fsp_memory_mainboard_version(void);
 uint8_t fsp_memory_soc_version(void);
 
-/* Load logo to be displayed by FSP */
-const struct cbmem_entry *fsp_load_logo(UINT32 *logo_ptr, UINT32 *logo_size);
-
 /* Callback after processing FSP notify */
 void platform_fsp_notify_status(enum fsp_notify_phase phase);
 
 /* Initialize memory margin analysis settings. */
 void setup_mma(FSP_M_CONFIG *memory_cfg);
 /* Update the SOC specific logo param and load the logo. */
-const struct cbmem_entry *soc_load_logo(FSPS_UPD *supd);
+void soc_load_logo(FSPS_UPD *supd);
 /* Update the SOC specific memory config param for mma. */
 void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg,
 	struct mma_config_param *mma_cfg);

diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h
@@ -16,24 +16,29 @@
 #define FSP_HDR_ATTRIB_FSPM		2
 #define FSP_HDR_ATTRIB_FSPS		3
 
+#if CONFIG(PLATFORM_USES_FSP2_X86_32)
 struct fsp_header {
 	uint32_t fsp_revision;
-	size_t image_size;
-	uintptr_t image_base;
+	uint32_t image_size;
+	uint32_t image_base;
 	uint16_t image_attribute;
 	uint8_t spec_version;
 	uint16_t component_attribute;
-	size_t cfg_region_offset;
-	size_t cfg_region_size;
-	size_t temp_ram_init_entry;
-	size_t temp_ram_exit_entry;
-	size_t notify_phase_entry_offset;
-	size_t memory_init_entry_offset;
-	size_t silicon_init_entry_offset;
-	size_t multi_phase_si_init_entry_offset;
+	uint32_t cfg_region_offset;
+	uint32_t cfg_region_size;
+	uint32_t temp_ram_init_entry;
+	uint32_t temp_ram_exit_entry;
+	uint32_t notify_phase_entry_offset;
+	uint32_t memory_init_entry_offset;
+	uint32_t silicon_init_entry_offset;
+	uint32_t multi_phase_si_init_entry_offset;
 	char image_id[sizeof(uint64_t) + 1];
 	uint8_t revision;
-};
+} __packed;
+#else
+#error You need to implement this struct for x86_64 FSP
+#endif
+
 
 enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob);
 

diff --git a/src/drivers/intel/fsp2_0/include/fsp/ppi/mp_service_ppi.h b/src/drivers/intel/fsp2_0/include/fsp/ppi/mp_service_ppi.h
@@ -11,10 +11,36 @@
 #include <efi/efi_datatype.h>
 #include <fsp/soc_binding.h>
 
-/*
- * SOC must call this function to get required EFI_PEI_MP_SERVICES_PPI
- * structure.
- */
-efi_pei_mp_services_ppi *mp_fill_ppi_services_data(void);
+/* SOC must call this function to get required EFI_PEI_MP_SERVICES_PPI structure */
+void *mp_fill_ppi_services_data(void);
+
+/* get the number of logical processors in the platform */
+efi_return_status_t mp_get_number_of_processors(efi_uintn_t *number_of_processors,
+	efi_uintn_t *number_of_enabled_processors);
+
+/* get processor info such as id, status */
+efi_return_status_t mp_get_processor_info(efi_uintn_t processor_number,
+	efi_processor_information *processor_info_buffer);
+
+/* executes a caller provided function on all enabled APs */
+efi_return_status_t mp_startup_all_aps(efi_ap_procedure procedure,
+	efi_uintn_t timeout_usec, void *argument);
+
+/* executes a caller provided function on all enabled APs + BSP */
+efi_return_status_t mp_startup_all_cpus(efi_ap_procedure procedure,
+	efi_uintn_t timeout_usec, void *argument);
+
+/* executes a caller provided function on specific AP */
+efi_return_status_t mp_startup_this_ap(efi_ap_procedure procedure,
+	efi_uintn_t processor_number, efi_uintn_t timeout_usec, void *argument);
+
+/* get the processor instance */
+efi_return_status_t mp_identify_processor(efi_uintn_t *processor_number);
+
+/* for the APIs that are not supported/required */
+static inline efi_return_status_t mp_api_unsupported(void)
+{
+	return FSP_UNSUPPORTED;
+}
 
 #endif	/* MP_SERVICE_PPI_H */
diff --git a/src/drivers/intel/fsp2_0/include/fsp/upd.h b/src/drivers/intel/fsp2_0/include/fsp/upd.h
@@ -21,6 +21,7 @@ struct FSP_UPD_HEADER {
 	uint8_t                       Reserved[23];
 } __packed;
 
+#if CONFIG(PLATFORM_USES_FSP2_X86_32)
 struct FSPM_ARCH_UPD {
 	///
 	/// Revision of the structure. For FSP v2.0 value is 1.
@@ -31,12 +32,12 @@ struct FSPM_ARCH_UPD {
 	/// Pointer to the non-volatile storage (NVS) data buffer.
 	/// If it is NULL it indicates the NVS data is not available.
 	///
-	void                        *NvsBufferPtr;
+	uint32_t                      NvsBufferPtr;
 	///
 	/// Pointer to the temporary stack base address to be
 	/// consumed inside FspMemoryInit() API.
 	///
-	void                        *StackBase;
+	uint32_t                      StackBase;
 	///
 	/// Temporary stack size to be consumed inside
 	/// FspMemoryInit() API.
@@ -53,7 +54,11 @@ struct FSPM_ARCH_UPD {
 	uint32_t                      BootMode;
 	uint8_t                       Reserved1[8];
 } __packed;
+#else
+#error You need to implement this struct for x86_64 FSP
+#endif
 
+#endif
 struct FSPS_ARCH_UPD {
 	///
 	/// Revision of the structure. For FSP v2.2 value is 1.

diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h
@@ -97,6 +97,8 @@ const struct hob_header *fsp_next_hob(const struct hob_header *parent);
 bool fsp_guid_compare(const uint8_t guid1[16], const uint8_t guid2[16]);
 void fsp_find_bootloader_tolum(struct range_entry *re);
 void fsp_get_version(char *buf);
+/* fsp_verify_upd_header_signature calls die() on signature mismatch */
+void fsp_verify_upd_header_signature(uint64_t upd_signature, uint64_t expected_signature);
 void lb_string_platform_blob_version(struct lb_header *header);
 void report_fspt_output(void);
 void soc_validate_fsp_version(const struct fsp_header *hdr);

diff --git a/src/drivers/intel/fsp2_0/logo.c b/src/drivers/intel/fsp2_0/logo.c
-Original file line number
+Diff line change
@@ Expand Up / @@ -33,6 +33,7 @@ ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual @@
     endif
     smm-y += save_state.c
+    smm-y += smi_trigger.c
     ifeq ($(CONFIG_SMM_TSEG),y)
@@ Expand Down @@
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1 @@
		ramstage-$(CONFIG_DRIVERS_GENERIC_BAYHUB_LV2) += lv2.c