4 changes: 2 additions & 2 deletions src/arch/x86/include/arch/early_variables.h
View file
Expand Up @@ -19,7 +19,7 @@
#include <arch/symbols.h>
#include <stdlib.h>

#if ENV_CACHE_AS_RAM && !IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION)
#if ENV_CACHE_AS_RAM && !CONFIG(NO_CAR_GLOBAL_MIGRATION)
asm(".section .car.global_data,\"w\",@nobits");
asm(".previous");
#ifdef __clang__
Expand Down Expand Up @@ -100,6 +100,6 @@ static inline int car_active(void) { return 0; }
#define car_get_var(var) (var)
#define car_sync_var(var) (var)
#define car_set_var(var, val) (var) = (val)
#endif /* ENV_CACHE_AS_RAM && !IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION) */
#endif /* ENV_CACHE_AS_RAM && !CONFIG(NO_CAR_GLOBAL_MIGRATION) */

#endif /* ARCH_EARLY_VARIABLES_H */
2 changes: 1 addition & 1 deletion src/arch/x86/include/arch/exception.h
View file
Expand Up @@ -32,7 +32,7 @@

#include <arch/cpu.h>

#if IS_ENABLED(CONFIG_IDT_IN_EVERY_STAGE) || ENV_RAMSTAGE
#if CONFIG(IDT_IN_EVERY_STAGE) || ENV_RAMSTAGE
asmlinkage void exception_init(void);
#else
static inline void exception_init(void) { /* not implemented */ }
Expand Down
4 changes: 2 additions & 2 deletions src/arch/x86/include/arch/interrupt.h
View file
Expand Up @@ -21,9 +21,9 @@
#include "registers.h"

/* setup interrupt handlers for mainboard */
#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_REALMODE)
#if CONFIG(PCI_OPTION_ROM_RUN_REALMODE)
extern void mainboard_interrupt_handlers(int intXX, int (*intXX_func)(void));
#elif IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL)
#elif CONFIG(PCI_OPTION_ROM_RUN_YABEL)
#include <device/oprom/yabel/biosemu.h>
#else
static inline void mainboard_interrupt_handlers(int intXX,
Expand Down
87 changes: 45 additions & 42 deletions src/arch/x86/include/arch/pci_io_cfg.h
View file
Expand Up @@ -19,105 +19,108 @@
#include <device/pci_type.h>

static __always_inline
unsigned int pci_io_encode_addr(pci_devfn_t dev, unsigned int where)
uint32_t pci_io_encode_addr(pci_devfn_t dev, uint16_t reg)
{
if (IS_ENABLED(CONFIG_PCI_IO_CFG_EXT)) {
// seg == 0
return dev >> 4 | (where & 0xff) | ((where & 0xf00) << 16);
} else {
return dev >> 4 | where;
}
uint32_t addr = 1 << 31;

addr |= dev >> 4;
addr |= reg & 0xfc;

if (CONFIG(PCI_IO_CFG_EXT))
addr |= (reg & 0xf00) << 16;

return addr;
}

static __always_inline
uint8_t pci_io_read_config8(pci_devfn_t dev, unsigned int where)
uint8_t pci_io_read_config8(pci_devfn_t dev, uint16_t reg)
{
unsigned int addr = pci_io_encode_addr(dev, where);
outl(0x80000000 | (addr & ~3), 0xCF8);
return inb(0xCFC + (addr & 3));
uint32_t addr = pci_io_encode_addr(dev, reg);
outl(addr, 0xCF8);
return inb(0xCFC + (reg & 3));
}

static __always_inline
uint16_t pci_io_read_config16(pci_devfn_t dev, unsigned int where)
uint16_t pci_io_read_config16(pci_devfn_t dev, uint16_t reg)
{
unsigned int addr = pci_io_encode_addr(dev, where);
outl(0x80000000 | (addr & ~3), 0xCF8);
return inw(0xCFC + (addr & 2));
uint32_t addr = pci_io_encode_addr(dev, reg);
outl(addr, 0xCF8);
return inw(0xCFC + (reg & 2));
}

static __always_inline
uint32_t pci_io_read_config32(pci_devfn_t dev, unsigned int where)
uint32_t pci_io_read_config32(pci_devfn_t dev, uint16_t reg)
{
unsigned int addr = pci_io_encode_addr(dev, where);
outl(0x80000000 | (addr & ~3), 0xCF8);
uint32_t addr = pci_io_encode_addr(dev, reg);
outl(addr, 0xCF8);
return inl(0xCFC);
}

static __always_inline
void pci_io_write_config8(pci_devfn_t dev, unsigned int where, uint8_t value)
void pci_io_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value)
{
unsigned int addr = pci_io_encode_addr(dev, where);
outl(0x80000000 | (addr & ~3), 0xCF8);
outb(value, 0xCFC + (addr & 3));
uint32_t addr = pci_io_encode_addr(dev, reg);
outl(addr, 0xCF8);
outb(value, 0xCFC + (reg & 3));
}

static __always_inline
void pci_io_write_config16(pci_devfn_t dev, unsigned int where, uint16_t value)
void pci_io_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value)
{
unsigned int addr = pci_io_encode_addr(dev, where);
outl(0x80000000 | (addr & ~3), 0xCF8);
outw(value, 0xCFC + (addr & 2));
uint32_t addr = pci_io_encode_addr(dev, reg);
outl(addr, 0xCF8);
outw(value, 0xCFC + (reg & 2));
}

static __always_inline
void pci_io_write_config32(pci_devfn_t dev, unsigned int where, uint32_t value)
void pci_io_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value)
{
unsigned int addr = pci_io_encode_addr(dev, where);
outl(0x80000000 | (addr & ~3), 0xCF8);
uint32_t addr = pci_io_encode_addr(dev, reg);
outl(addr, 0xCF8);
outl(value, 0xCFC);
}

#if !IS_ENABLED(CONFIG_MMCONF_SUPPORT)
#if !CONFIG(MMCONF_SUPPORT)

/* Avoid name collisions as different stages have different signature
* for these functions. The _s_ stands for simple, fundamental IO or
* MMIO variant.
*/

static __always_inline
uint8_t pci_s_read_config8(pci_devfn_t dev, unsigned int where)
uint8_t pci_s_read_config8(pci_devfn_t dev, uint16_t reg)
{
return pci_io_read_config8(dev, where);
return pci_io_read_config8(dev, reg);
}

static __always_inline
uint16_t pci_s_read_config16(pci_devfn_t dev, unsigned int where)
uint16_t pci_s_read_config16(pci_devfn_t dev, uint16_t reg)
{
return pci_io_read_config16(dev, where);
return pci_io_read_config16(dev, reg);
}

static __always_inline
uint32_t pci_s_read_config32(pci_devfn_t dev, unsigned int where)
uint32_t pci_s_read_config32(pci_devfn_t dev, uint16_t reg)
{
return pci_io_read_config32(dev, where);
return pci_io_read_config32(dev, reg);
}

static __always_inline
void pci_s_write_config8(pci_devfn_t dev, unsigned int where, uint8_t value)
void pci_s_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value)
{
pci_io_write_config8(dev, where, value);
pci_io_write_config8(dev, reg, value);
}

static __always_inline
void pci_s_write_config16(pci_devfn_t dev, unsigned int where, uint16_t value)
void pci_s_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value)
{
pci_io_write_config16(dev, where, value);
pci_io_write_config16(dev, reg, value);
}

static __always_inline
void pci_s_write_config32(pci_devfn_t dev, unsigned int where, uint32_t value)
void pci_s_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value)
{
pci_io_write_config32(dev, where, value);
pci_io_write_config32(dev, reg, value);
}

#endif
Expand Down
6 changes: 0 additions & 6 deletions src/arch/x86/include/arch/pci_ops.h
View file
Expand Up @@ -17,10 +17,4 @@
#include <arch/pci_io_cfg.h>
#include <device/pci_mmio_cfg.h>

#ifndef __SIMPLE_DEVICE__

extern const struct pci_bus_operations pci_cf8_conf1;

#endif

#endif /* ARCH_I386_PCI_OPS_H */
2 changes: 1 addition & 1 deletion src/arch/x86/include/arch/registers.h
View file
Expand Up @@ -60,7 +60,7 @@ struct eregs {
};
#endif // !ASSEMBLER

#if IS_ENABLED(CONFIG_COMPILER_LLVM_CLANG)
#if CONFIG(COMPILER_LLVM_CLANG)
#define ADDR32(opcode) opcode
#else
#define ADDR32(opcode) addr32 opcode
Expand Down
6 changes: 3 additions & 3 deletions src/arch/x86/include/arch/smp/spinlock.h
View file
Expand Up @@ -15,9 +15,9 @@
#define ARCH_SMP_SPINLOCK_H

#if !defined(__PRE_RAM__) \
|| IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) \
|| IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) \
|| IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
|| CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK) \
|| CONFIG(HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK) \
|| CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)

/*
* Your basic SMP spinlocks, allowing only a single CPU anywhere
Expand Down
2 changes: 1 addition & 1 deletion src/arch/x86/include/cf9_reset.h
View file
Expand Up @@ -27,7 +27,7 @@ void do_system_reset(void);
void do_full_reset(void);

/* Called by functions below before reset. */
#if IS_ENABLED(CONFIG_HAVE_CF9_RESET_PREPARE)
#if CONFIG(HAVE_CF9_RESET_PREPARE)
void cf9_reset_prepare(void);
#else
static inline void cf9_reset_prepare(void) {}
Expand Down
4 changes: 2 additions & 2 deletions src/arch/x86/ioapic.c
View file
Expand Up @@ -103,15 +103,15 @@ static void load_vectors(void *ioapic_base)

ioapic_interrupts = ioapic_interrupt_count(ioapic_base);

if (IS_ENABLED(CONFIG_IOAPIC_INTERRUPTS_ON_FSB)) {
if (CONFIG(IOAPIC_INTERRUPTS_ON_FSB)) {
/*
* For the Pentium 4 and above APICs deliver their interrupts
* on the front side bus, enable that.
*/
printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n");
io_apic_write(ioapic_base, 0x03,
io_apic_read(ioapic_base, 0x03) | (1 << 0));
} else if (IS_ENABLED(CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS)) {
} else if (CONFIG(IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS)) {
printk(BIOS_DEBUG,
"IOAPIC: Enabling interrupts on APIC serial bus\n");
io_apic_write(ioapic_base, 0x03, 0);
Expand Down
4 changes: 2 additions & 2 deletions src/arch/x86/memlayout.ld
View file
Expand Up @@ -26,7 +26,7 @@ SECTIONS
* conditionalize with macros.
*/
#if ENV_RAMSTAGE
RAMSTAGE(CONFIG_RAMBASE, (CONFIG_RELOCATABLE_RAMSTAGE ? 8M :
RAMSTAGE(CONFIG_RAMBASE, (CONFIG(RELOCATABLE_RAMSTAGE) ? 8M :
CONFIG_RAMTOP - CONFIG_RAMBASE))

#elif ENV_ROMSTAGE
Expand Down Expand Up @@ -62,7 +62,7 @@ SECTIONS
#include <cpu/x86/16bit/entry16.ld>
#include <cpu/x86/16bit/reset16.ld>
#include <arch/x86/id.ld>
#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
#if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
#include <cpu/intel/fit/fit.ld>
#endif
#endif /* ENV_BOOTBLOCK */
1 change: 0 additions & 1 deletion src/arch/x86/mmap_boot.c
View file
Expand Up @@ -14,7 +14,6 @@
*/

#include <boot_device.h>
#include <cbfs.h>
#include <endian.h>
#include <stdlib.h>

Expand Down
78 changes: 0 additions & 78 deletions src/arch/x86/pci_ops_conf1.c
View file

This file was deleted.

4 changes: 2 additions & 2 deletions src/arch/x86/pirq_routing.c
View file
Expand Up @@ -198,9 +198,9 @@ unsigned long copy_pirq_routing_table(unsigned long addr,
addr);
memcpy((void *)addr, routing_table, routing_table->size);
printk(BIOS_INFO, "done.\n");
if (IS_ENABLED(CONFIG_DEBUG_PIRQ))
if (CONFIG(DEBUG_PIRQ))
verify_copy_pirq_routing_table(addr, routing_table);
if (IS_ENABLED(CONFIG_PIRQ_ROUTE))
if (CONFIG(PIRQ_ROUTE))
pirq_route_irqs(addr);

return addr + routing_table->size;
Expand Down
3 changes: 3 additions & 0 deletions src/arch/x86/postcar.c
View file
Expand Up @@ -19,6 +19,7 @@
#include <cpu/x86/mtrr.h>
#include <main_decl.h>
#include <program_loading.h>
#include <timestamp.h>

/*
* Systems without a native coreboot cache-as-ram teardown may implement
Expand All @@ -35,6 +36,8 @@ void main(void)
/* Recover cbmem so infrastruture using it is functional. */
cbmem_initialize();

timestamp_add_now(TS_START_POSTCAR);

display_mtrrs();

/* Load and run ramstage. */
Expand Down
10 changes: 7 additions & 3 deletions src/arch/x86/postcar_loader.c
View file
Expand Up @@ -23,6 +23,7 @@
#include <rmodule.h>
#include <romstage_handoff.h>
#include <stage_cache.h>
#include <timestamp.h>

static inline void stack_push(struct postcar_frame *pcf, uint32_t val)
{
Expand Down Expand Up @@ -105,7 +106,7 @@ void postcar_frame_add_mtrr(struct postcar_frame *pcf,

void postcar_frame_add_romcache(struct postcar_frame *pcf, int type)
{
if (!IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED))
if (!CONFIG(BOOT_DEVICE_MEMORY_MAPPED))
return;
postcar_frame_add_mtrr(pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, type);
}
Expand Down Expand Up @@ -150,7 +151,7 @@ static void load_postcar_cbfs(struct prog *prog, struct postcar_frame *pcf)

finalize_load(rsl.params, pcf->stack);

if (!IS_ENABLED(CONFIG_NO_STAGE_CACHE))
if (!CONFIG(NO_STAGE_CACHE))
stage_cache_add(STAGE_POSTCAR, prog);
}

Expand All @@ -161,7 +162,7 @@ void run_postcar_phase(struct postcar_frame *pcf)

postcar_commit_mtrrs(pcf);

if (!IS_ENABLED(CONFIG_NO_STAGE_CACHE) &&
if (!CONFIG(NO_STAGE_CACHE) &&
romstage_handoff_is_resume()) {
stage_cache_load_stage(STAGE_POSTCAR, &prog);
/* This is here to allow platforms to pass different stack
Expand All @@ -171,5 +172,8 @@ void run_postcar_phase(struct postcar_frame *pcf)
} else
load_postcar_cbfs(&prog, pcf);

/* As postcar exist, it's end of romstage here */
timestamp_add_now(TS_END_ROMSTAGE);

prog_run(&prog);
}
90 changes: 61 additions & 29 deletions src/arch/x86/smbios.c
View file
Expand Up @@ -30,7 +30,7 @@
#include <memory_info.h>
#include <spd.h>
#include <cbmem.h>
#if IS_ENABLED(CONFIG_CHROMEOS)
#if CONFIG(CHROMEOS)
#include <vendorcode/google/chromeos/gnvs.h>
#endif

Expand Down Expand Up @@ -350,7 +350,7 @@ static int smbios_write_type0(unsigned long *current, int handle)
t->length = len - 2;

t->vendor = smbios_add_string(t->eos, "coreboot");
#if !IS_ENABLED(CONFIG_CHROMEOS)
#if !CONFIG(CHROMEOS)
t->bios_release_date = smbios_add_string(t->eos, coreboot_dmi_date);

t->bios_version = smbios_add_string(t->eos,
Expand All @@ -359,12 +359,12 @@ static int smbios_write_type0(unsigned long *current, int handle)
#define SPACES \
" "
t->bios_release_date = smbios_add_string(t->eos, coreboot_dmi_date);
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
#if CONFIG(HAVE_ACPI_TABLES)
u32 version_offset = (u32)smbios_string_table_len(t->eos);
#endif
t->bios_version = smbios_add_string(t->eos, SPACES);

#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
#if CONFIG(HAVE_ACPI_TABLES)
/* SMBIOS offsets start at 1 rather than 0 */
chromeos_get_chromeos_acpi()->vbt10 =
(u32)t->eos + (version_offset - 1);
Expand All @@ -390,10 +390,10 @@ static int smbios_write_type0(unsigned long *current, int handle)
BIOS_CHARACTERISTICS_SELECTABLE_BOOT |
BIOS_CHARACTERISTICS_UPGRADEABLE;

if (IS_ENABLED(CONFIG_CARDBUS_PLUGIN_SUPPORT))
if (CONFIG(CARDBUS_PLUGIN_SUPPORT))
t->bios_characteristics |= BIOS_CHARACTERISTICS_PC_CARD;

if (IS_ENABLED(CONFIG_HAVE_ACPI_TABLES))
if (CONFIG(HAVE_ACPI_TABLES))
t->bios_characteristics_ext1 = BIOS_EXT1_CHARACTERISTICS_ACPI;

t->bios_characteristics_ext2 = BIOS_EXT2_CHARACTERISTICS_TARGET;
Expand All @@ -402,8 +402,6 @@ static int smbios_write_type0(unsigned long *current, int handle)
return len;
}

#if !IS_ENABLED(CONFIG_SMBIOS_PROVIDED_BY_MOBO)

const char *__weak smbios_mainboard_serial_number(void)
{
return CONFIG_MAINBOARD_SERIAL_NUMBER;
Expand All @@ -424,12 +422,6 @@ const char *__weak smbios_mainboard_product_name(void)
return CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME;
}

void __weak smbios_mainboard_set_uuid(u8 *uuid)
{
/* leave all zero */
}
#endif

const char *__weak smbios_mainboard_asset_tag(void)
{
return "";
Expand All @@ -450,7 +442,32 @@ smbios_board_type __weak smbios_mainboard_board_type(void)
return SMBIOS_BOARD_TYPE_UNKNOWN;
}

const char *__weak smbios_mainboard_sku(void)
const char *__weak smbios_system_serial_number(void)
{
return smbios_mainboard_serial_number();
}

const char *__weak smbios_system_version(void)
{
return smbios_mainboard_version();
}

const char *__weak smbios_system_manufacturer(void)
{
return smbios_mainboard_manufacturer();
}

const char *__weak smbios_system_product_name(void)
{
return smbios_mainboard_product_name();
}

void __weak smbios_system_set_uuid(u8 *uuid)
{
/* leave all zero */
}

const char *__weak smbios_system_sku(void)
{
return "";
}
Expand All @@ -460,12 +477,27 @@ int __weak fill_mainboard_smbios_type16(unsigned long *current, int *handle)
return 0;
}

#ifdef CONFIG_MAINBOARD_FAMILY
const char *smbios_mainboard_family(void)
static int get_socket_type(void)
{
return CONFIG_MAINBOARD_FAMILY;
if (CONFIG(CPU_INTEL_SLOT_1))
return 0x08;
if (CONFIG(CPU_INTEL_SOCKET_MPGA604))
return 0x13;
if (CONFIG(CPU_INTEL_SOCKET_LGA775))
return 0x15;
if (CONFIG(CPU_AMD_SOCKET_AM2R2))
return 0x17;
if (CONFIG(CPU_AMD_SOCKET_F_1207))
return 0x18;
if (CONFIG(CPU_AMD_SOCKET_G34_NON_AGESA))
return 0x1a;
if (CONFIG(CPU_AMD_SOCKET_AM3))
return 0x1b;
if (CONFIG(CPU_AMD_SOCKET_C32_NON_AGESA))
return 0x1c;

return 0x02; /* Unknown */
}
#endif /* CONFIG_MAINBOARD_FAMILY */

static int smbios_write_type1(unsigned long *current, int handle)
{
Expand All @@ -477,17 +509,17 @@ static int smbios_write_type1(unsigned long *current, int handle)
t->handle = handle;
t->length = len - 2;
t->manufacturer = smbios_add_string(t->eos,
smbios_mainboard_manufacturer());
smbios_system_manufacturer());
t->product_name = smbios_add_string(t->eos,
smbios_mainboard_product_name());
smbios_system_product_name());
t->serial_number = smbios_add_string(t->eos,
smbios_mainboard_serial_number());
t->sku = smbios_add_string(t->eos, smbios_mainboard_sku());
t->version = smbios_add_string(t->eos, smbios_mainboard_version());
smbios_system_serial_number());
t->sku = smbios_add_string(t->eos, smbios_system_sku());
t->version = smbios_add_string(t->eos, smbios_system_version());
#ifdef CONFIG_MAINBOARD_FAMILY
t->family = smbios_add_string(t->eos, smbios_mainboard_family());
t->family = smbios_add_string(t->eos, CONFIG_MAINBOARD_FAMILY);
#endif
smbios_mainboard_set_uuid(t->uuid);
smbios_system_set_uuid(t->uuid);
len = t->length + smbios_string_table_len(t->eos);
*current += len;
return len;
Expand Down Expand Up @@ -531,7 +563,7 @@ static int smbios_write_type3(unsigned long *current, int handle)
t->handle = handle;
t->length = len - 2;
t->manufacturer = smbios_add_string(t->eos,
smbios_mainboard_manufacturer());
smbios_system_manufacturer());
t->bootup_state = SMBIOS_STATE_SAFE;
t->power_supply_state = SMBIOS_STATE_SAFE;
t->thermal_state = SMBIOS_STATE_SAFE;
Expand Down Expand Up @@ -569,7 +601,7 @@ static int smbios_write_type4(unsigned long *current, int handle)
t->l1_cache_handle = 0xffff;
t->l2_cache_handle = 0xffff;
t->l3_cache_handle = 0xffff;
t->processor_upgrade = 1;
t->processor_upgrade = get_socket_type();
len = t->length + smbios_string_table_len(t->eos);
*current += len;
return len;
Expand Down Expand Up @@ -768,7 +800,7 @@ unsigned long smbios_write_tables(unsigned long current)
handle++));
update_max(len, max_struct_size, smbios_write_type11(&current,
&handle));
if (IS_ENABLED(CONFIG_ELOG))
if (CONFIG(ELOG))
update_max(len, max_struct_size,
elog_smbios_write_type15(&current,handle++));
update_max(len, max_struct_size, smbios_write_type16(&current,
Expand Down
8 changes: 4 additions & 4 deletions src/arch/x86/tables.c
View file
Expand Up @@ -238,17 +238,17 @@ void arch_write_tables(uintptr_t coreboot_table)
unsigned long rom_table_end = 0xf0000;

/* This table must be between 0x0f0000 and 0x100000 */
if (IS_ENABLED(CONFIG_GENERATE_PIRQ_TABLE))
if (CONFIG(GENERATE_PIRQ_TABLE))
rom_table_end = write_pirq_table(rom_table_end);

/* The smp table must be in 0-1K, 639K-640K, or 960K-1M */
if (IS_ENABLED(CONFIG_GENERATE_MP_TABLE))
if (CONFIG(GENERATE_MP_TABLE))
rom_table_end = write_mptable(rom_table_end);

if (IS_ENABLED(CONFIG_HAVE_ACPI_TABLES))
if (CONFIG(HAVE_ACPI_TABLES))
rom_table_end = write_acpi_table(rom_table_end);

if (IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES))
if (CONFIG(GENERATE_SMBIOS_TABLES))
rom_table_end = write_smbios_table(rom_table_end);

sz = write_coreboot_forwarding_table(forwarding_table, coreboot_table);
Expand Down
2 changes: 1 addition & 1 deletion src/arch/x86/timestamp.c
View file
Expand Up @@ -24,7 +24,7 @@ uint64_t timestamp_get(void)
int timestamp_tick_freq_mhz(void)
{
/* Chipsets that have a constant TSC provide this value correctly. */
if (IS_ENABLED(CONFIG_TSC_CONSTANT_RATE))
if (CONFIG(TSC_CONSTANT_RATE))
return tsc_freq_mhz();

/* Filling tick_freq_mhz = 0 in timestamps-table will trigger
Expand Down
2 changes: 1 addition & 1 deletion src/commonlib/cbfs.c
View file
Expand Up @@ -27,7 +27,7 @@
#endif
#if defined(IS_ENABLED)

#if IS_ENABLED(CONFIG_DEBUG_CBFS)
#if CONFIG(DEBUG_CBFS)
#define DEBUG(x...) printk(BIOS_SPEW, "CBFS: " x)
#else
#define DEBUG(x...)
Expand Down
2 changes: 1 addition & 1 deletion src/commonlib/include/commonlib/cbmem_id.h
View file
Expand Up @@ -67,7 +67,7 @@
#define CBMEM_ID_TIMESTAMP 0x54494d45
#define CBMEM_ID_TPM2_TCG_LOG 0x54504d32
#define CBMEM_ID_VBOOT_HANDOFF 0x780074f0
#define CBMEM_ID_VBOOT_SEL_REG 0x780074f1
#define CBMEM_ID_VBOOT_SEL_REG 0x780074f1 /* deprecated */
#define CBMEM_ID_VBOOT_WORKBUF 0x78007343
#define CBMEM_ID_VPD 0x56504420
#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
Expand Down
1 change: 1 addition & 0 deletions src/commonlib/include/commonlib/coreboot_tables.h
View file
Expand Up @@ -292,6 +292,7 @@ struct lb_gpios {

#define LB_TAG_VBNV 0x0019
#define LB_TAB_VBOOT_HANDOFF 0x0020
#define LB_TAB_VBOOT_WORKBUF 0x0034
#define LB_TAB_DMA 0x0022
#define LB_TAG_RAM_OOPS 0x0023
#define LB_TAG_MTC 0x002b
Expand Down
2 changes: 1 addition & 1 deletion src/commonlib/include/commonlib/stdlib.h
View file
Expand Up @@ -35,7 +35,7 @@
#include <stdlib.h>
#include <string.h>

#if IS_ENABLED(CONFIG_COREBOOT_BUILD)
#if CONFIG(COREBOOT_BUILD)
#include <console/console.h>
#include <halt.h>
#define printf(...) printk(BIOS_ERR, __VA_ARGS__)
Expand Down
8 changes: 5 additions & 3 deletions src/commonlib/include/commonlib/tcpa_log_serialized.h
View file
Expand Up @@ -19,13 +19,15 @@
#include <stdint.h>

#define MAX_TCPA_LOG_ENTRIES 50
#define TCPA_LOG_STRING_LENGTH 512
#define TCPA_FORMAT_HASH_LENGTH 128
#define TCPA_DIGEST_MAX_LENGTH 64
#define TCPA_PCR_HASH_NAME 256
#define TCPA_PCR_HASH_NAME 50
#define TCPA_PCR_HASH_LEN 10
/* Assumption of 2K TCPA log size reserved for CAR/SRAM */
#define MAX_PRERAM_TCPA_LOG_ENTRIES 15

struct tcpa_entry {
uint32_t pcr;
char digest_type[TCPA_PCR_HASH_LEN];
uint8_t digest[TCPA_DIGEST_MAX_LENGTH];
uint32_t digest_length;
char name[TCPA_PCR_HASH_NAME];
Expand Down
4 changes: 4 additions & 0 deletions src/commonlib/include/commonlib/timestamp_serialized.h
View file
Expand Up @@ -63,6 +63,8 @@ enum timestamp_id {
TS_LOAD_PAYLOAD = 90,
TS_ACPI_WAKE_JUMP = 98,
TS_SELFBOOT_JUMP = 99,
TS_START_POSTCAR = 100,
TS_END_POSTCAR = 101,

/* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
TS_START_COPYVER = 501,
Expand Down Expand Up @@ -257,6 +259,8 @@ static const struct timestamp_id_to_name {
{ TS_FSP_BEFORE_END_OF_FIRMWARE, "calling FspNotify(EndOfFirmware)" },
{ TS_FSP_AFTER_END_OF_FIRMWARE,
"returning from FspNotify(EndOfFirmware)" },
{ TS_START_POSTCAR, "start of postcar" },
{ TS_END_POSTCAR, "end of postcar" },
};

#endif
4 changes: 4 additions & 0 deletions src/commonlib/sort.c
View file
Expand Up @@ -23,6 +23,10 @@ void bubblesort(int *v, size_t num_entries, sort_order_t order)
size_t i, j;
int swapped;

/* Make sure there are at least two entries to sort. */
if (num_entries < 2)
return;

for (j = 0; j < num_entries - 1; j++) {
swapped = 0;
for (i = 0; i < num_entries - j - 1; i++) {
Expand Down
1 change: 0 additions & 1 deletion src/commonlib/storage/bouncebuf.c
View file
Expand Up @@ -17,7 +17,6 @@

#include <arch/cache.h>
#include "bouncebuf.h"
#include <halt.h>
#include "storage.h"
#include <string.h>
#include <commonlib/stdlib.h>
Expand Down
2 changes: 1 addition & 1 deletion src/commonlib/storage/mmc.c
View file
Expand Up @@ -127,7 +127,7 @@ int mmc_send_ext_csd(struct sd_mmc_ctrlr *ctrlr, unsigned char *ext_csd)

rv = ctrlr->send_cmd(ctrlr, &cmd, &data);

if (!rv && IS_ENABLED(CONFIG_SD_MMC_TRACE)) {
if (!rv && CONFIG(SD_MMC_TRACE)) {
int i, size;

size = data.blocks * data.blocksize;
Expand Down
4 changes: 3 additions & 1 deletion src/commonlib/storage/pci_sdhci.c
View file
Expand Up @@ -22,8 +22,10 @@
#include <commonlib/sdhci.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include "sd_mmc.h"
#include <stdint.h>
#include <string.h>

#include "sd_mmc.h"
#include "storage.h"

/* Initialize an SDHCI port */
Expand Down
1 change: 0 additions & 1 deletion src/commonlib/storage/sd.c
View file
Expand Up @@ -26,7 +26,6 @@
#include <endian.h>
#include "sd_mmc.h"
#include "storage.h"
#include <string.h>
#include <timer.h>

int sd_send_if_cond(struct storage_media *media)
Expand Down
4 changes: 2 additions & 2 deletions src/commonlib/storage/sd_mmc.c
View file
Expand Up @@ -168,7 +168,7 @@ int sd_mmc_enter_standby(struct storage_media *media)

/* Test for SD version 2 */
err = CARD_TIMEOUT;
if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_SD)) {
if (CONFIG(COMMONLIB_STORAGE_SD)) {
err = sd_send_if_cond(media);

/* Get SD card operating condition */
Expand All @@ -177,7 +177,7 @@ int sd_mmc_enter_standby(struct storage_media *media)
}

/* If the command timed out, we check for an MMC card */
if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_MMC) && (err == CARD_TIMEOUT)) {
if (CONFIG(COMMONLIB_STORAGE_MMC) && (err == CARD_TIMEOUT)) {
/* Some cards seem to need this */
sd_mmc_go_idle(media);

Expand Down
8 changes: 4 additions & 4 deletions src/commonlib/storage/sd_mmc.h
View file
Expand Up @@ -75,25 +75,25 @@ int sd_set_partition(struct storage_media *media,
/* Controller debug functions */
#define sdhc_debug(format...) \
do { \
if (IS_ENABLED(CONFIG_SDHC_DEBUG)) \
if (CONFIG(SDHC_DEBUG)) \
printk(BIOS_DEBUG, format); \
} while (0)
#define sdhc_trace(format...) \
do { \
if (IS_ENABLED(CONFIG_SDHC_TRACE)) \
if (CONFIG(SDHC_TRACE)) \
printk(BIOS_DEBUG, format); \
} while (0)
#define sdhc_error(format...) printk(BIOS_ERR, "ERROR: " format)

/* Card/device debug functions */
#define sd_mmc_debug(format...) \
do { \
if (IS_ENABLED(CONFIG_SD_MMC_DEBUG)) \
if (CONFIG(SD_MMC_DEBUG)) \
printk(BIOS_DEBUG, format); \
} while (0)
#define sd_mmc_trace(format...) \
do { \
if (IS_ENABLED(CONFIG_SD_MMC_TRACE)) \
if (CONFIG(SD_MMC_TRACE)) \
printk(BIOS_DEBUG, format); \
} while (0)
#define sd_mmc_error(format...) printk(BIOS_ERR, "ERROR: " format)
Expand Down
14 changes: 6 additions & 8 deletions src/commonlib/storage/sdhci.c
View file
Expand Up @@ -24,17 +24,15 @@
#include <commonlib/storage.h>
#include <delay.h>
#include <endian.h>
#include <halt.h>
#include "sdhci.h"
#include "sd_mmc.h"
#include "storage.h"
#include <string.h>
#include <timer.h>
#include <commonlib/stdlib.h>

#define DMA_AVAILABLE ((CONFIG_SDHCI_ADMA_IN_BOOTBLOCK && ENV_BOOTBLOCK) \
|| (CONFIG_SDHCI_ADMA_IN_VERSTAGE && ENV_VERSTAGE) \
|| (CONFIG_SDHCI_ADMA_IN_ROMSTAGE && ENV_ROMSTAGE) \
#define DMA_AVAILABLE ((CONFIG(SDHCI_ADMA_IN_BOOTBLOCK) && ENV_BOOTBLOCK) \
|| (CONFIG(SDHCI_ADMA_IN_VERSTAGE) && ENV_VERSTAGE) \
|| (CONFIG(SDHCI_ADMA_IN_ROMSTAGE) && ENV_ROMSTAGE) \
|| ENV_POSTCAR || ENV_RAMSTAGE)

__weak void *dma_malloc(size_t length_in_bytes)
Expand Down Expand Up @@ -318,7 +316,7 @@ static int sdhci_send_command(struct sd_mmc_ctrlr *ctrlr,

sdhc_log_command(cmd);

if (IS_ENABLED(CONFIG_SDHCI_BOUNCE_BUFFER) && data) {
if (CONFIG(SDHCI_BOUNCE_BUFFER) && data) {
if (data->flags & DATA_FLAG_READ) {
buf = data->dest;
bbflags = GEN_BB_WRITE;
Expand Down Expand Up @@ -348,7 +346,7 @@ static int sdhci_send_command(struct sd_mmc_ctrlr *ctrlr,
sdhci_led_control(ctrlr, 0);
sdhc_log_ret(ret);

if (IS_ENABLED(CONFIG_SDHCI_BOUNCE_BUFFER) && bbstate)
if (CONFIG(SDHCI_BOUNCE_BUFFER) && bbstate)
bounce_buffer_stop(bbstate);

return ret;
Expand Down Expand Up @@ -594,7 +592,7 @@ static void sdhci_set_ios(struct sd_mmc_ctrlr *ctrlr)
}

/* Set the new bus width */
if (IS_ENABLED(CONFIG_SDHC_DEBUG)
if (CONFIG(SDHC_DEBUG)
&& ((ctrl ^ previous_ctrl) & (SDHCI_CTRL_4BITBUS
| ((version >= SDHCI_SPEC_300) ? SDHCI_CTRL_8BITBUS : 0))))
sdhc_debug("SDHCI bus width: %d bit%s\n", bus_width,
Expand Down
6 changes: 3 additions & 3 deletions src/commonlib/storage/sdhci_display.c
View file
Expand Up @@ -26,7 +26,7 @@

static void sdhci_display_bus_width(struct sdhci_ctrlr *sdhci_ctrlr)
{
if (IS_ENABLED(CONFIG_SDHC_DEBUG)) {
if (CONFIG(SDHC_DEBUG)) {
int bits;
uint8_t host_ctrl;
uint16_t host2;
Expand All @@ -53,7 +53,7 @@ static void sdhci_display_bus_width(struct sdhci_ctrlr *sdhci_ctrlr)

static void sdhci_display_clock(struct sdhci_ctrlr *sdhci_ctrlr)
{
if (IS_ENABLED(CONFIG_SDHC_DEBUG)) {
if (CONFIG(SDHC_DEBUG)) {
uint16_t clk_ctrl;
uint32_t clock;
uint32_t divisor;
Expand All @@ -79,7 +79,7 @@ static void sdhci_display_clock(struct sdhci_ctrlr *sdhci_ctrlr)

static void sdhci_display_voltage(struct sdhci_ctrlr *sdhci_ctrlr)
{
if (IS_ENABLED(CONFIG_SDHC_DEBUG)) {
if (CONFIG(SDHC_DEBUG)) {
u8 pwr_ctrl;
const char *voltage;
const char *voltage_table[8] = {
Expand Down
20 changes: 10 additions & 10 deletions src/commonlib/storage/storage.c
View file
Expand Up @@ -70,7 +70,7 @@ static void display_capacity(struct storage_media *media, int partition_number)
capacity = media->capacity[partition_number];
name = storage_partition_name(media, partition_number);
separator = "";
if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_MMC) && !IS_SD(media))
if (CONFIG(COMMONLIB_STORAGE_MMC) && !IS_SD(media))
separator = ": ";

/* Determine the decimal divisor for the capacity */
Expand Down Expand Up @@ -124,7 +124,7 @@ void storage_display_setup(struct storage_media *media)
* media->write_bl_len);

/* Display the partition capacities */
if (IS_ENABLED(CONFIG_SDHC_DEBUG)) {
if (CONFIG(SDHC_DEBUG)) {
for (partition_number = 0; partition_number
< ARRAY_SIZE(media->capacity); partition_number++) {
if (!media->capacity[partition_number])
Expand Down Expand Up @@ -175,9 +175,9 @@ int storage_startup(struct storage_media *media)
return err;

/* Increase the bus frequency */
if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_SD) && IS_SD(media))
if (CONFIG(COMMONLIB_STORAGE_SD) && IS_SD(media))
err = sd_change_freq(media);
else if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_MMC)) {
else if (CONFIG(COMMONLIB_STORAGE_MMC)) {
err = mmc_change_freq(media);
if (!err)
mmc_update_capacity(media);
Expand All @@ -189,9 +189,9 @@ int storage_startup(struct storage_media *media)
media->caps &= ctrlr->caps;

/* Increase the bus width if possible */
if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_SD) && IS_SD(media))
if (CONFIG(COMMONLIB_STORAGE_SD) && IS_SD(media))
err = sd_set_bus_width(media);
else if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_MMC))
else if (CONFIG(COMMONLIB_STORAGE_MMC))
err = mmc_set_bus_width(media);
if (err)
return err;
Expand Down Expand Up @@ -329,9 +329,9 @@ int storage_set_partition(struct storage_media *media,

/* Select the partition */
err = -1;
if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_SD) && IS_SD(media))
if (CONFIG(COMMONLIB_STORAGE_SD) && IS_SD(media))
err = sd_set_partition(media, partition_number);
else if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_MMC))
else if (CONFIG(COMMONLIB_STORAGE_MMC))
err = mmc_set_partition(media, partition_number);
if (err)
sd_mmc_error("Invalid partition number!\n");
Expand All @@ -345,9 +345,9 @@ const char *storage_partition_name(struct storage_media *media,

/* Get the partition name */
name = NULL;
if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_SD) && IS_SD(media))
if (CONFIG(COMMONLIB_STORAGE_SD) && IS_SD(media))
name = sd_partition_name(media, partition_number);
else if (IS_ENABLED(CONFIG_COMMONLIB_STORAGE_MMC))
else if (CONFIG(COMMONLIB_STORAGE_MMC))
name = mmc_partition_name(media, partition_number);
return name;
}
Expand Down
3 changes: 2 additions & 1 deletion src/commonlib/storage/storage_write.c
View file
Expand Up @@ -19,9 +19,10 @@
* GNU General Public License for more details.
*/

#include <stdlib.h>

#include "sd_mmc.h"
#include "storage.h"
#include <string.h>

static uint32_t storage_write(struct storage_media *media, uint32_t start,
uint64_t block_count, const void *src)
Expand Down
2 changes: 1 addition & 1 deletion src/console/console.c
View file
Expand Up @@ -79,7 +79,7 @@ void console_write_line(uint8_t *buffer, size_t number_of_bytes)
}


#if IS_ENABLED(CONFIG_GDB_STUB) && (ENV_ROMSTAGE || ENV_RAMSTAGE)
#if CONFIG(GDB_STUB) && (ENV_ROMSTAGE || ENV_RAMSTAGE)
void gdb_hw_init(void)
{
__gdb_hw_init();
Expand Down
6 changes: 3 additions & 3 deletions src/console/init.c
View file
Expand Up @@ -73,7 +73,7 @@ int console_log_level(int msg_level)
if (msg_level <= log_level)
return CONSOLE_LOG_ALL;

if (IS_ENABLED(CONFIG_CONSOLE_CBMEM) && (msg_level <= BIOS_DEBUG))
if (CONFIG(CONSOLE_CBMEM) && (msg_level <= BIOS_DEBUG))
return CONSOLE_LOG_FAST;

return 0;
Expand All @@ -83,10 +83,10 @@ asmlinkage void console_init(void)
{
init_log_level();

if (IS_ENABLED(CONFIG_DEBUG_CONSOLE_INIT))
if (CONFIG(DEBUG_CONSOLE_INIT))
car_set_var(console_inited, 1);

if (IS_ENABLED(CONFIG_EARLY_PCI_BRIDGE) && !ENV_SMM && !ENV_RAMSTAGE)
if (CONFIG(EARLY_PCI_BRIDGE) && !ENV_SMM && !ENV_RAMSTAGE)
pci_early_bridge_init();

console_hw_init();
Expand Down
24 changes: 12 additions & 12 deletions src/console/post.c
View file
Expand Up @@ -20,7 +20,7 @@
#include <device/device.h>
#include <pc80/mc146818rtc.h>
#include <smp/spinlock.h>
#if IS_ENABLED(CONFIG_POST_IO)
#if CONFIG(POST_IO)
#include <arch/io.h>
#endif

Expand All @@ -40,15 +40,15 @@ void __weak mainboard_post(uint8_t value)
#define mainboard_post(x)
#endif

#if IS_ENABLED(CONFIG_CMOS_POST)
#if CONFIG(CMOS_POST)

DECLARE_SPIN_LOCK(cmos_post_lock)

#if ENV_RAMSTAGE
void cmos_post_log(void)
{
u8 code = 0;
#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA)
#if CONFIG(CMOS_POST_EXTRA)
u32 extra = 0;
#endif

Expand All @@ -58,13 +58,13 @@ void cmos_post_log(void)
switch (cmos_read(CMOS_POST_BANK_OFFSET)) {
case CMOS_POST_BANK_0_MAGIC:
code = cmos_read(CMOS_POST_BANK_1_OFFSET);
#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA)
#if CONFIG(CMOS_POST_EXTRA)
extra = cmos_read32(CMOS_POST_BANK_1_EXTRA);
#endif
break;
case CMOS_POST_BANK_1_MAGIC:
code = cmos_read(CMOS_POST_BANK_0_OFFSET);
#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA)
#if CONFIG(CMOS_POST_EXTRA)
extra = cmos_read32(CMOS_POST_BANK_0_EXTRA);
#endif
break;
Expand All @@ -82,17 +82,17 @@ void cmos_post_log(void)
default:
printk(BIOS_WARNING, "POST: Unexpected post code "
"in previous boot: 0x%02x\n", code);
#if IS_ENABLED(CONFIG_ELOG)
#if CONFIG(ELOG)
elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code);
#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA)
#if CONFIG(CMOS_POST_EXTRA)
if (extra)
elog_add_event_dword(ELOG_TYPE_POST_EXTRA, extra);
#endif
#endif
}
}

#if IS_ENABLED(CONFIG_CMOS_POST_EXTRA)
#if CONFIG(CMOS_POST_EXTRA)
void post_log_extra(u32 value)
{
spin_lock(&cmos_post_lock);
Expand Down Expand Up @@ -146,14 +146,14 @@ static void cmos_post_code(u8 value)

void post_code(uint8_t value)
{
#if !IS_ENABLED(CONFIG_NO_POST)
#if IS_ENABLED(CONFIG_CONSOLE_POST)
#if !CONFIG(NO_POST)
#if CONFIG(CONSOLE_POST)
printk(BIOS_EMERG, "POST: 0x%02x\n", value);
#endif
#if IS_ENABLED(CONFIG_CMOS_POST)
#if CONFIG(CMOS_POST)
cmos_post_code(value);
#endif
#if IS_ENABLED(CONFIG_POST_IO)
#if CONFIG(POST_IO)
outb(value, CONFIG_POST_IO_PORT);
#endif
#endif
Expand Down
8 changes: 4 additions & 4 deletions src/console/printk.c
View file
Expand Up @@ -26,7 +26,7 @@
#include <stddef.h>
#include <trace.h>

#if (!defined(__PRE_RAM__) && IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK)) || !IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK)
#if (!defined(__PRE_RAM__) && CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK)) || !CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK)
DECLARE_SPIN_LOCK(console_lock)
#endif

Expand All @@ -49,7 +49,7 @@ int vprintk(int msg_level, const char *fmt, va_list args)
{
int i, log_this;

if (IS_ENABLED(CONFIG_SQUELCH_EARLY_SMP) && ENV_CACHE_AS_RAM &&
if (CONFIG(SQUELCH_EARLY_SMP) && ENV_CACHE_AS_RAM &&
!boot_cpu())
return 0;

Expand All @@ -59,7 +59,7 @@ int vprintk(int msg_level, const char *fmt, va_list args)

DISABLE_TRACE;
#ifdef __PRE_RAM__
#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK)
#if CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK)
spin_lock(romstage_console_lock());
#endif
#else
Expand All @@ -74,7 +74,7 @@ int vprintk(int msg_level, const char *fmt, va_list args)
}

#ifdef __PRE_RAM__
#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK)
#if CONFIG(HAVE_ROMSTAGE_CONSOLE_SPINLOCK)
spin_unlock(romstage_console_lock());
#endif
#else
Expand Down
2 changes: 1 addition & 1 deletion src/console/vtxprintf.c
View file
Expand Up @@ -20,7 +20,7 @@

#define call_tx(x) tx_byte(x, data)

#if !IS_ENABLED(CONFIG_ARCH_MIPS)
#if !CONFIG(ARCH_MIPS)
#define SUPPORT_64BIT_INTS
#endif

Expand Down
5 changes: 2 additions & 3 deletions src/cpu/amd/agesa/family12/model_12_init.c
View file
Expand Up @@ -19,7 +19,6 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
#include <device/device.h>
#include <string.h>
#include <cpu/x86/pae.h>
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
Expand All @@ -34,7 +33,7 @@ static void model_12_init(struct device *dev)
msr_t msr;
int num_banks;

#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
#if CONFIG(LOGICAL_CPUS)
u32 siblings;
#endif

Expand Down Expand Up @@ -65,7 +64,7 @@ static void model_12_init(struct device *dev)
/* Set the processor name string */
// init_processor_name();

#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
#if CONFIG(LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;

if (siblings > 0) {
Expand Down
5 changes: 2 additions & 3 deletions src/cpu/amd/agesa/family14/model_14_init.c
View file
Expand Up @@ -19,7 +19,6 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
#include <device/device.h>
#include <string.h>
#include <cpu/x86/pae.h>
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
Expand All @@ -33,7 +32,7 @@ static void model_14_init(struct device *dev)
msr_t msr;
int num_banks;
int msrno;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
#if CONFIG(LOGICAL_CPUS)
u32 siblings;
#endif
printk(BIOS_DEBUG, "Model 14 Init.\n");
Expand Down Expand Up @@ -83,7 +82,7 @@ static void model_14_init(struct device *dev)
/* Enable the local CPU APICs */
setup_lapic();

#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
#if CONFIG(LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;

if (siblings > 0) {
Expand Down
7 changes: 3 additions & 4 deletions src/cpu/amd/agesa/family15tn/model_15_init.c
View file
Expand Up @@ -20,7 +20,6 @@
#include <cpu/amd/mtrr.h>
#include <cpu/x86/smm.h>
#include <device/device.h>
#include <string.h>
#include <cpu/x86/pae.h>
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
Expand All @@ -37,7 +36,7 @@ static void model_15_init(struct device *dev)
int num_banks;
int msrno;
unsigned int cpu_idx;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
#if CONFIG(LOGICAL_CPUS)
u32 siblings;
#endif

Expand Down Expand Up @@ -82,7 +81,7 @@ static void model_15_init(struct device *dev)
/* Enable the local CPU APICs */
setup_lapic();

#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
#if CONFIG(LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;

if (siblings > 0) {
Expand All @@ -102,7 +101,7 @@ static void model_15_init(struct device *dev)
msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);

if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
if (CONFIG(HAVE_SMI_HANDLER)) {
cpu_idx = cpu_info()->index;
printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx);

Expand Down
5 changes: 2 additions & 3 deletions src/cpu/amd/agesa/family16kb/model_16_init.c
View file
Expand Up @@ -19,7 +19,6 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
#include <device/device.h>
#include <string.h>
#include <cpu/x86/pae.h>
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
Expand All @@ -35,7 +34,7 @@ static void model_16_init(struct device *dev)
msr_t msr;
int num_banks;
int msrno;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
#if CONFIG(LOGICAL_CPUS)
u32 siblings;
#endif

Expand Down Expand Up @@ -80,7 +79,7 @@ static void model_16_init(struct device *dev)
/* Enable the local CPU APICs */
setup_lapic();

#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
#if CONFIG(LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;

if (siblings > 0) {
Expand Down
4 changes: 2 additions & 2 deletions src/cpu/amd/car/cache_as_ram.inc
View file
Expand Up @@ -141,7 +141,7 @@ CAR_FAM10_out:

CAR_FAM10_errata_applied:

#if IS_ENABLED(CONFIG_MMCONF_SUPPORT)
#if CONFIG(MMCONF_SUPPORT)
#if (CONFIG_MMCONF_BASE_ADDRESS > 0xFFFFFFFF)
#error "MMCONF_BASE_ADDRESS too big"
#elif (CONFIG_MMCONF_BASE_ADDRESS & 0xFFFFF)
Expand Down Expand Up @@ -315,7 +315,7 @@ clear_fixed_var_mtrr_out:
*/
.endm

#if IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)
#if CONFIG(CPU_AMD_MODEL_10XXX)
#if CacheSize > 0x80000
#error Invalid CAR size, must be at most 128k (processor limit is 512k).
#endif
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/amd/car/disable_cache_as_ram.c
View file
Expand Up @@ -80,7 +80,7 @@ void disable_cache_as_ram_real(uint8_t skip_sharedc_config)

family = amd_fam1x_cpu_family();

#if IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)
#if CONFIG(CPU_AMD_MODEL_10XXX)
if (family >= 0x6f) {
/* Family 15h or later */

Expand Down
2 changes: 1 addition & 1 deletion src/cpu/amd/car/post_cache_as_ram.c
View file
Expand Up @@ -36,7 +36,7 @@
#error "You need to set CONFIG_RAMTOP greater than 1M"
#endif

#if IS_ENABLED(CONFIG_DEBUG_CAR)
#if CONFIG(DEBUG_CAR)
#define print_car_debug(format, arg...) printk(BIOS_DEBUG, "%s: " format, __func__, ##arg)
#else
#define print_car_debug(format, arg...)
Expand Down
20 changes: 10 additions & 10 deletions src/cpu/amd/family_10h-family_15h/fidvid.c
View file
Expand Up @@ -95,21 +95,21 @@ b.- prep_fid_change(...)

static inline void print_debug_fv(const char *str, u32 val)
{
#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG)
#if CONFIG(SET_FIDVID_DEBUG)
printk(BIOS_DEBUG, "%s%x\n", str, val);
#endif
}

static inline void print_debug_fv_8(const char *str, u8 val)
{
#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG)
#if CONFIG(SET_FIDVID_DEBUG)
printk(BIOS_DEBUG, "%s%02x\n", str, val);
#endif
}

static inline void print_debug_fv_64(const char *str, u32 val, u32 val2)
{
#if IS_ENABLED(CONFIG_SET_FIDVID_DEBUG)
#if CONFIG(SET_FIDVID_DEBUG)
printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
#endif
}
Expand Down Expand Up @@ -505,7 +505,7 @@ static void config_power_ctrl_misc_reg(pci_devfn_t dev, uint64_t cpuRev,
}

/* TODO: look into C1E state and F3xA0[IdleExitEn]*/
#if IS_ENABLED(CONFIG_SVI_HIGH_FREQ)
#if CONFIG(SVI_HIGH_FREQ)
if (cpuRev & AMD_FAM10_C3) {
dword |= SVI_HIGH_FREQ_ON;
}
Expand Down Expand Up @@ -585,7 +585,7 @@ static void config_acpi_pwr_state_ctrl_regs(pci_devfn_t dev, uint64_t cpuRev,
if (cpuRev & AMD_DR_Bx ) {
smaf001 = 0xA6;
} else {
#if IS_ENABLED(CONFIG_SVI_HIGH_FREQ)
#if CONFIG(SVI_HIGH_FREQ)
if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) {
smaf001 = 0xF6;
}
Expand Down Expand Up @@ -1036,7 +1036,7 @@ void init_fidvid_stage2(u32 apicid, u32 nodeid)
}


#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST)
#if CONFIG(SET_FIDVID_STORE_AP_APICID_AT_FIRST)
struct ap_apicid_st {
u32 num;
// it could use 256 bytes for 64 node quad core system
Expand All @@ -1055,7 +1055,7 @@ static void store_ap_apicid(unsigned ap_apicid, void *gp)

int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
{
#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST)
#if CONFIG(SET_FIDVID_STORE_AP_APICID_AT_FIRST)
struct ap_apicid_st ap_apicidx;
u32 i;
#endif
Expand All @@ -1070,8 +1070,8 @@ int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)

print_debug_fv("BSP fid = ", fv.common_fid);

#if IS_ENABLED(CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST) && \
!IS_ENABLED(CONFIG_SET_FIDVID_CORE0_ONLY)
#if CONFIG(SET_FIDVID_STORE_AP_APICID_AT_FIRST) && \
!CONFIG(SET_FIDVID_CORE0_ONLY)
/* For all APs (We know the APIC ID of all APs even when the APIC ID
is lifted) remote read from AP LAPIC_MSG_REG about max fid.
Then calculate the common max fid that can be used for all
Expand All @@ -1084,7 +1084,7 @@ int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv);
}
#else
for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, -1, init_fidvid_bsp_stage1, &fv);
for_each_ap(bsp_apicid, CONFIG(SET_FIDVID_CORE0_ONLY), -1, init_fidvid_bsp_stage1, &fv);
#endif

print_debug_fv("common_fid = ", fv.common_fid);
Expand Down
40 changes: 20 additions & 20 deletions src/cpu/amd/family_10h-family_15h/init_cpus.c
View file
Expand Up @@ -18,7 +18,7 @@
#include <device/pci_ops.h>
#include "init_cpus.h"

#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)
#if CONFIG(HAVE_OPTION_TABLE)
#include "option_table.h"
#endif
#include <pc80/mc146818rtc.h>
Expand All @@ -30,17 +30,17 @@

#include <southbridge/amd/common/reset.h>

#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700)
#if CONFIG(SOUTHBRIDGE_AMD_SB700)
#include <southbridge/amd/sb700/sb700.h>
#endif

#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB800)
#if CONFIG(SOUTHBRIDGE_AMD_SB800)
#include <southbridge/amd/sb800/sb800.h>
#endif

#include "cpu/amd/car/disable_cache_as_ram.c"

#if IS_ENABLED(CONFIG_PCI_IO_CFG_EXT)
#if CONFIG(PCI_IO_CFG_EXT)
static void set_EnableCf8ExtCfg(void)
{
// set the NB_CFG_MSR[46]=1;
Expand Down Expand Up @@ -156,7 +156,7 @@ static void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node,
/* get_nodes define in ht_wrapper.c */
nodes = get_nodes();

if (!IS_ENABLED(CONFIG_LOGICAL_CPUS) ||
if (!CONFIG(LOGICAL_CPUS) ||
read_option(multi_core, 0) != 0) { // 0 means multi core
disable_siblings = 1;
} else {
Expand Down Expand Up @@ -186,8 +186,8 @@ static void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node,
for (j = jstart; j <= jend; j++) {
ap_apicid = get_boot_apic_id(i, j);

#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)
#if !IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID)
#if CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)
#if !CONFIG(LIFT_BSP_APIC_ID)
if ((i != 0) || (j != 0)) /* except bsp */
#endif
ap_apicid += CONFIG_APIC_ID_OFFSET;
Expand Down Expand Up @@ -231,7 +231,7 @@ static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue)
return result;
}

#if IS_ENABLED(CONFIG_SET_FIDVID)
#if CONFIG(SET_FIDVID)
static void init_fidvid_ap(u32 apicid, u32 nodeid, u32 coreid);
#endif

Expand Down Expand Up @@ -402,17 +402,17 @@ u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
if (!is_fam15h())
set_apicid_cpuid_lo();
set_EnableCf8ExtCfg();
#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID)
#if CONFIG(ENABLE_APIC_EXT_ID)
enable_apic_ext_id(id.nodeid);
#endif
}

enable_lapic();

#if IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)
#if CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)
u32 initial_apicid = get_initial_apicid();

#if !IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID)
#if !CONFIG(LIFT_BSP_APIC_ID)
if (initial_apicid != 0) // other than bsp
#endif
{
Expand All @@ -424,7 +424,7 @@ u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)

lapic_write(LAPIC_ID, dword);
}
#if IS_ENABLED(CONFIG_LIFT_BSP_APIC_ID)
#if CONFIG(LIFT_BSP_APIC_ID)
bsp_apicid += CONFIG_APIC_ID_OFFSET;
#endif

Expand Down Expand Up @@ -477,8 +477,8 @@ u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
}
}

#if IS_ENABLED(CONFIG_SET_FIDVID)
#if IS_ENABLED(CONFIG_LOGICAL_CPUS) && IS_ENABLED(CONFIG_SET_FIDVID_CORE0_ONLY)
#if CONFIG(SET_FIDVID)
#if CONFIG(LOGICAL_CPUS) && CONFIG(SET_FIDVID_CORE0_ONLY)
// Run on all AP for proper FID/VID setup.
if (id.coreid == 0) // only need set fid for core0
#endif
Expand All @@ -501,7 +501,7 @@ u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
if (is_fam15h()) {
/* core 1 on node 0 is special; to avoid corrupting the
* BSP do not alter MTRRs on that core */
if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
fam15_bsp_core1_apicid = CONFIG_APIC_ID_OFFSET + 1;
else
fam15_bsp_core1_apicid = 1;
Expand Down Expand Up @@ -578,7 +578,7 @@ static void start_node(u8 node)
/* Enable routing table */
printk(BIOS_DEBUG, "Start node %02x", node);

#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10)
/* For FAM10 support, we need to set Dram base/limit for the new node */
pci_write_config32(NODE_MP(node), 0x44, 0);
pci_write_config32(NODE_MP(node), 0x40, 3);
Expand Down Expand Up @@ -1040,7 +1040,7 @@ void cpuSetAMDMSR(uint8_t node_id)
}
}

#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB800)
#if CONFIG(SOUTHBRIDGE_AMD_SB700) || CONFIG(SOUTHBRIDGE_AMD_SB800)
if (revision & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) {
/* Set up message triggered C1E */
msr = rdmsr(MSR_INTPEND);
Expand All @@ -1060,7 +1060,7 @@ void cpuSetAMDMSR(uint8_t node_id)

if (revision & (AMD_DR_Ex | AMD_FAM15_ALL)) {
enable_c_states = 0;
if (IS_ENABLED(CONFIG_HAVE_ACPI_TABLES))
if (CONFIG(HAVE_ACPI_TABLES))
if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS)
enable_c_states = !!nvram;

Expand Down Expand Up @@ -1869,7 +1869,7 @@ void finalize_node_setup(struct sys_info *sysinfo)
cpuSetAMDPCI(i);
}

#if IS_ENABLED(CONFIG_SET_FIDVID)
#if CONFIG(SET_FIDVID)
// Prep each node for FID/VID setup.
prep_fid_change();
#endif
Expand All @@ -1883,6 +1883,6 @@ void finalize_node_setup(struct sys_info *sysinfo)
#endif
}

#if IS_ENABLED(CONFIG_SET_FIDVID)
#if CONFIG(SET_FIDVID)
# include "fidvid.c"
#endif
1 change: 0 additions & 1 deletion src/cpu/amd/family_10h-family_15h/init_cpus.h
View file
Expand Up @@ -22,7 +22,6 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
#include <cpu/amd/multicore.h>
#include <reset.h>
#include <northbridge/amd/amdfam10/raminit.h>
#include "defaults.h"

Expand Down
7 changes: 3 additions & 4 deletions src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
View file
Expand Up @@ -22,7 +22,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <string.h>
#include <cpu/x86/smm.h>
#include <cpu/x86/pae.h>
#include <cpu/x86/lapic.h>
Expand Down Expand Up @@ -62,7 +61,7 @@ static void model_10xxx_init(struct device *dev)
msr_t msr;
int num_banks;
struct node_core_id id;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
#if CONFIG(LOGICAL_CPUS)
u32 siblings;
#endif
uint8_t delay_start;
Expand Down Expand Up @@ -123,7 +122,7 @@ static void model_10xxx_init(struct device *dev)
/* Set the processor name string */
init_processor_name();

#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
#if CONFIG(LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;

if (siblings > 0) {
Expand Down Expand Up @@ -204,7 +203,7 @@ static void model_10xxx_init(struct device *dev)
wrmsr(BU_CFG2_MSR, msr);
}

if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
if (CONFIG(HAVE_SMI_HANDLER)) {
printk(BIOS_DEBUG, "Initializing SMM ASeg memory\n");

/* Set SMM base address for this CPU */
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/amd/family_10h-family_15h/powernow_acpi.c
View file
Expand Up @@ -187,7 +187,7 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
uint8_t enable_c_states;

enable_c_states = 0;
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
#if CONFIG(HAVE_ACPI_TABLES)
if (get_option(&nvram, "cpu_c_states") == CB_SUCCESS)
enable_c_states = !!nvram;
#endif
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/amd/family_10h-family_15h/ram_calc.c
View file
Expand Up @@ -44,7 +44,7 @@ static inline uint8_t is_fam15h(void)
uint64_t get_uma_memory_size(uint64_t topmem)
{
uint64_t uma_size = 0;
if (IS_ENABLED(CONFIG_GFXUMA)) {
if (CONFIG(GFXUMA)) {
/* refer to UMA Size Consideration in 780 BDG. */
if (topmem >= 0x40000000) /* 1GB and above system memory */
uma_size = 0x10000000; /* 256M recommended UMA */
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/amd/microcode/Makefile.inc
View file
@@ -1,2 +1,2 @@
romstage-y += microcode.c
ramstage-y += microcode.c
romstage-y += microcode.c
6 changes: 3 additions & 3 deletions src/cpu/amd/microcode/microcode.c
View file
Expand Up @@ -200,7 +200,7 @@ void amd_update_microcode_from_cbfs(uint32_t equivalent_processor_rev_id)
}

#ifdef __PRE_RAM__
#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
spin_lock(romstage_microcode_cbfs_lock());
#endif
#endif
Expand All @@ -210,7 +210,7 @@ void amd_update_microcode_from_cbfs(uint32_t equivalent_processor_rev_id)
if (!ucode) {
UCODE_DEBUG("microcode file not found. Skipping updates.\n");
#ifdef __PRE_RAM__
#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
spin_unlock(romstage_microcode_cbfs_lock());
#endif
#endif
Expand All @@ -220,7 +220,7 @@ void amd_update_microcode_from_cbfs(uint32_t equivalent_processor_rev_id)
amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id);

#ifdef __PRE_RAM__
#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
spin_unlock(romstage_microcode_cbfs_lock());
#endif
#endif
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/amd/pi/00630F01/fixme.c
View file
Expand Up @@ -88,7 +88,7 @@ void amd_initmmio(void)
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);

if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){
if (CONFIG(UDELAY_LAPIC)){
LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
MsrReg |= 1 << 11;
LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);
Expand Down
7 changes: 3 additions & 4 deletions src/cpu/amd/pi/00630F01/model_15_init.c
View file
Expand Up @@ -21,7 +21,6 @@
#include <cpu/x86/smm.h>
#include <device/device.h>
#include <device/pci.h>
#include <string.h>
#include <cpu/x86/pae.h>
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
Expand All @@ -36,7 +35,7 @@ static void model_15_init(struct device *dev)
int num_banks;
int msrno;
unsigned int cpu_idx;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
#if CONFIG(LOGICAL_CPUS)
u32 siblings;
#endif

Expand Down Expand Up @@ -78,7 +77,7 @@ static void model_15_init(struct device *dev)
/* Enable the local CPU APICs */
setup_lapic();

#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
#if CONFIG(LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;

if (siblings > 0) {
Expand All @@ -98,7 +97,7 @@ static void model_15_init(struct device *dev)
msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);

if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
if (CONFIG(HAVE_SMI_HANDLER)) {
cpu_idx = cpu_info()->index;
printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx);

Expand Down
2 changes: 1 addition & 1 deletion src/cpu/amd/pi/00660F01/fixme.c
View file
Expand Up @@ -94,7 +94,7 @@ void amd_initmmio(void)
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);

if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) {
if (CONFIG(UDELAY_LAPIC)) {
LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
MsrReg |= 1 << 11;
LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);
Expand Down
5 changes: 2 additions & 3 deletions src/cpu/amd/pi/00660F01/model_15_init.c
View file
Expand Up @@ -20,7 +20,6 @@
#include <cpu/amd/mtrr.h>
#include <device/device.h>
#include <device/pci.h>
#include <string.h>
#include <cpu/x86/pae.h>
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
Expand Down Expand Up @@ -51,7 +50,7 @@ static void model_15_init(struct device *dev)
msr_t msr;
int num_banks;
int msrno;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
#if CONFIG(LOGICAL_CPUS)
u32 siblings;
#endif

Expand Down Expand Up @@ -90,7 +89,7 @@ static void model_15_init(struct device *dev)
/* Enable the local CPU APICs */
setup_lapic();

#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
#if CONFIG(LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;

if (siblings > 0) {
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/amd/pi/00730F01/fixme.c
View file
Expand Up @@ -99,7 +99,7 @@ void amd_initmmio(void)
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);

if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) {
if (CONFIG(UDELAY_LAPIC)) {
LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
MsrReg |= 1 << 11;
LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);
Expand Down
5 changes: 2 additions & 3 deletions src/cpu/amd/pi/00730F01/model_16_init.c
View file
Expand Up @@ -20,7 +20,6 @@
#include <cpu/amd/mtrr.h>
#include <device/device.h>
#include <device/pci.h>
#include <string.h>
#include <cpu/x86/pae.h>
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
Expand All @@ -34,7 +33,7 @@ static void model_16_init(struct device *dev)
msr_t msr;
int num_banks;
int msrno;
#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
#if CONFIG(LOGICAL_CPUS)
u32 siblings;
#endif

Expand Down Expand Up @@ -75,7 +74,7 @@ static void model_16_init(struct device *dev)
/* Enable the local CPU APICs */
setup_lapic();

#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
#if CONFIG(LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;

if (siblings > 0) {
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/amd/quadcore/amd_sibling.c
View file
Expand Up @@ -74,7 +74,7 @@ u32 get_apicid_base(u32 ioapic_num)
u32 siblings;
u32 nb_cfg_54;

u32 disable_siblings = !CONFIG_LOGICAL_CPUS;
u32 disable_siblings = !CONFIG(LOGICAL_CPUS);

get_option(&disable_siblings, "multi_core");

Expand Down
4 changes: 2 additions & 2 deletions src/cpu/amd/quadcore/quadcore.c
View file
Expand Up @@ -19,7 +19,7 @@
#include <console/console.h>
#include <device/pci_ops.h>
#include <pc80/mc146818rtc.h>
#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)
#if CONFIG(HAVE_OPTION_TABLE)
#include "option_table.h"
#endif

Expand Down Expand Up @@ -124,7 +124,7 @@ void real_start_other_core(uint32_t nodeid, uint32_t cores)
}
}

#if (!IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX))
#if (!CONFIG(CPU_AMD_MODEL_10XXX))
//it is running on core0 of node0
static void start_other_cores(void)
{
Expand Down
4 changes: 2 additions & 2 deletions src/cpu/intel/car/non-evict/cache_as_ram.S
View file
Expand Up @@ -134,7 +134,7 @@ addrsize_set_high:
orl $MTRR_DEF_TYPE_EN, %eax
wrmsr

#if IS_ENABLED(CONFIG_CPU_HAS_L2_ENABLE_MSR)
#if CONFIG(CPU_HAS_L2_ENABLE_MSR)
/*
* Enable the L2 cache. Currently this assumes that this
* only affect socketed CPU's for which this is always valid,
Expand All @@ -152,7 +152,7 @@ addrsize_set_high:
invd
movl %eax, %cr0

#if IS_ENABLED(CONFIG_MICROCODE_UPDATE_PRE_RAM)
#if CONFIG(MICROCODE_UPDATE_PRE_RAM)
update_microcode:
/* put the return address in %esp */
movl $end_microcode_update, %esp
Expand Down
4 changes: 2 additions & 2 deletions src/cpu/intel/car/p4-netburst/cache_as_ram.S
View file
Expand Up @@ -23,7 +23,7 @@

/* Macro to access Local APIC registers at default base. */
#define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK)
/* Fixed location, ASSERTED in failover.ld if it changes. */
.set ap_sipi_vector_in_rom, 0xff
#endif
Expand Down Expand Up @@ -318,7 +318,7 @@ no_msr_11e:
invd
movl %eax, %cr0

#if IS_ENABLED(CONFIG_MICROCODE_UPDATE_PRE_RAM)
#if CONFIG(MICROCODE_UPDATE_PRE_RAM)
update_microcode:
/* put the return address in %esp */
movl $end_microcode_update, %esp
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/intel/car/romstage.c
View file
Expand Up @@ -54,7 +54,7 @@ static void romstage_main(unsigned long bist)
platform_enter_postcar();
}

#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK)
/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
* keeping changes in cache_as_ram.S easy to manage.
*/
Expand Down
4 changes: 2 additions & 2 deletions src/cpu/intel/common/common_init.c
View file
Expand Up @@ -31,7 +31,7 @@ void set_feature_ctrl_vmx(void)
{
msr_t msr;
uint32_t feature_flag;
int enable = IS_ENABLED(CONFIG_ENABLE_VMX);
int enable = CONFIG(ENABLE_VMX);

feature_flag = cpu_get_feature_flags_ecx();
/* Check that the VMX is supported before reading or writing the MSR. */
Expand Down Expand Up @@ -71,7 +71,7 @@ void set_feature_ctrl_vmx(void)
void set_feature_ctrl_lock(void)
{
msr_t msr;
int lock = IS_ENABLED(CONFIG_SET_IA32_FC_LOCK_BIT);
int lock = CONFIG(SET_IA32_FC_LOCK_BIT);
uint32_t feature_flag = cpu_get_feature_flags_ecx();

/* Check if VMX is supported before reading or writing the MSR */
Expand Down
1 change: 0 additions & 1 deletion src/cpu/intel/fsp_model_406dx/bootblock.c
View file
Expand Up @@ -21,7 +21,6 @@
#include <cpu/x86/mtrr.h>
#include <arch/io.h>
#include <device/pci_ops.h>
#include <reset.h>
#include <southbridge/intel/fsp_rangeley/soc.h>

#include "model_406dx.h"
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/intel/fsp_model_406dx/model_406dx_init.c
View file
Expand Up @@ -132,7 +132,7 @@ static void model_406dx_init(struct device *cpu)
x86_enable_cache();

/* Load microcode */
if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS))
if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS))
intel_update_microcode_from_cbfs();

/* Clear out pending MCEs */
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/intel/haswell/bootblock.c
View file
Expand Up @@ -23,7 +23,7 @@
#include <cpu/intel/microcode/microcode.c>
#include "haswell.h"

#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT)
#if CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT)
/* Needed for RCBA access to set Soft Reset Data register */
#include <southbridge/intel/lynxpoint/pch.h>
#else
Expand Down
1 change: 0 additions & 1 deletion src/cpu/intel/haswell/haswell_init.c
View file
Expand Up @@ -17,7 +17,6 @@

#include <console/console.h>
#include <device/device.h>
#include <string.h>
#include <arch/acpi.h>
#include <cpu/cpu.h>
#include <cpu/x86/mtrr.h>
Expand Down
12 changes: 3 additions & 9 deletions src/cpu/intel/haswell/romstage.c
View file
Expand Up @@ -14,23 +14,20 @@
*/

#include <stdint.h>
#include <string.h>
#include <console/console.h>
#include <arch/cpu.h>
#include <cf9_reset.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <halt.h>
#include <lib.h>
#include <timestamp.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <cbmem.h>
#include <program_loading.h>
#include <romstage_handoff.h>
#include <vendorcode/google/chromeos/chromeos.h>
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
#if CONFIG(EC_GOOGLE_CHROMEEC)
#include <ec/google/chromeec/ec.h>
#endif
#include <northbridge/intel/haswell/haswell.h>
Expand Down Expand Up @@ -89,7 +86,7 @@ void romstage_common(const struct romstage_params *params)
printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n");

if (wake_from_s3) {
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
#if CONFIG(HAVE_ACPI_RESUME)
printk(BIOS_DEBUG, "Resume from S3 detected.\n");
#else
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
Expand Down Expand Up @@ -123,15 +120,12 @@ void romstage_common(const struct romstage_params *params)

intel_early_me_status();

quick_ram_check();
post_code(0x3e);

if (!wake_from_s3) {
cbmem_initialize_empty();
/* Save data returned from MRC on non-S3 resumes. */
save_mrc_data(params->pei_data);
} else if (cbmem_initialize()) {
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
#if CONFIG(HAVE_ACPI_RESUME)
/* Failed S3 resume, reset to come up cleanly */
system_reset();
#endif
Expand Down
4 changes: 2 additions & 2 deletions src/cpu/intel/hyperthreading/intel_sibling.c
View file
Expand Up @@ -19,12 +19,12 @@
#include <smp/spinlock.h>
#include <assert.h>

#if IS_ENABLED(CONFIG_PARALLEL_CPU_INIT)
#if CONFIG(PARALLEL_CPU_INIT)
#error Intel hyper-threading requires serialized CPU init
#endif

static int first_time = 1;
static int disable_siblings = !CONFIG_LOGICAL_CPUS;
static int disable_siblings = !CONFIG(LOGICAL_CPUS);

/* Return true if running thread does not have the smallest lapic ID
* within a CPU core.
Expand Down
1 change: 0 additions & 1 deletion src/cpu/intel/model_1067x/model_1067x_init.c
View file
Expand Up @@ -17,7 +17,6 @@

#include <console/console.h>
#include <device/device.h>
#include <string.h>
#include <cpu/cpu.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mp.h>
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/intel/model_1067x/mp_init.c
View file
Expand Up @@ -75,7 +75,7 @@ static void per_cpu_smm_trigger(void)
printk(BIOS_DEBUG, "SMRR status: %senabled\n",
ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
} else {
if (!IS_ENABLED(CONFIG_SET_IA32_FC_LOCK_BIT))
if (!CONFIG(SET_IA32_FC_LOCK_BIT))
printk(BIOS_INFO,
"Overriding CONFIG_SET_IA32_FC_LOCK_BIT to enable SMRR\n");
ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
Expand Down
1 change: 0 additions & 1 deletion src/cpu/intel/model_106cx/model_106cx_init.c
View file
Expand Up @@ -15,7 +15,6 @@

#include <console/console.h>
#include <device/device.h>
#include <string.h>
#include <cpu/cpu.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/intel/model_2065x/bootblock.c
View file
Expand Up @@ -23,7 +23,7 @@

#include <cpu/intel/microcode/microcode.c>

#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK)
#if CONFIG(SOUTHBRIDGE_INTEL_IBEXPEAK)
#include <southbridge/intel/ibexpeak/pch.h>
#include "model_2065x.h"
#else
Expand Down
1 change: 0 additions & 1 deletion src/cpu/intel/model_2065x/model_2065x_init.c
View file
Expand Up @@ -17,7 +17,6 @@

#include <console/console.h>
#include <device/device.h>
#include <string.h>
#include <arch/acpi.h>
#include <cpu/cpu.h>
#include <cpu/x86/mtrr.h>
Expand Down
4 changes: 2 additions & 2 deletions src/cpu/intel/model_206ax/bootblock.c
View file
Expand Up @@ -24,8 +24,8 @@
#include <cpu/intel/microcode/microcode.c>
#include "model_206ax.h"

#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) || \
IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_C216)
#if CONFIG(SOUTHBRIDGE_INTEL_BD82X6X) || \
CONFIG(SOUTHBRIDGE_INTEL_C216)
/* Needed for RCBA access to set Soft Reset Data register */
#include <southbridge/intel/bd82x6x/pch.h>
#else
Expand Down
1 change: 0 additions & 1 deletion src/cpu/intel/model_206ax/model_206ax_init.c
View file
Expand Up @@ -18,7 +18,6 @@
#include <assert.h>
#include <console/console.h>
#include <device/device.h>
#include <string.h>
#include <arch/acpi.h>
#include <arch/cpu.h>
#include <cpu/cpu.h>
Expand Down
1 change: 0 additions & 1 deletion src/cpu/intel/model_6ex/model_6ex_init.c
View file
Expand Up @@ -16,7 +16,6 @@

#include <console/console.h>
#include <device/device.h>
#include <string.h>
#include <cpu/cpu.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
Expand Down
1 change: 0 additions & 1 deletion src/cpu/intel/model_6fx/model_6fx_init.c
View file
Expand Up @@ -16,7 +16,6 @@

#include <console/console.h>
#include <device/device.h>
#include <string.h>
#include <cpu/cpu.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
Expand Down
4 changes: 2 additions & 2 deletions src/cpu/intel/model_f3x/model_f3x_init.c
View file
Expand Up @@ -24,7 +24,7 @@ static void model_f3x_init(struct device *cpu)
/* Turn on caching if we haven't already */
x86_enable_cache();

if (!IS_ENABLED(CONFIG_PARALLEL_MP) && !intel_ht_sibling()) {
if (!CONFIG(PARALLEL_MP) && !intel_ht_sibling()) {
/* MTRRs are shared between threads */
x86_setup_mtrrs();
x86_mtrr_check();
Expand All @@ -37,7 +37,7 @@ static void model_f3x_init(struct device *cpu)
setup_lapic();

/* Start up my CPU siblings */
if (!IS_ENABLED(CONFIG_PARALLEL_MP))
if (!CONFIG(PARALLEL_MP))
intel_sibling_init(cpu);
};

Expand Down
2 changes: 1 addition & 1 deletion src/cpu/intel/smm/gen1/smmrelocate.c
View file
Expand Up @@ -175,7 +175,7 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
}

/* Adjust available SMM handler memory size. */
if (IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)) {
if (CONFIG(CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)) {
ASSERT(params->smram_size > CONFIG_SMM_RESERVED_SIZE);
params->smram_size -= CONFIG_SMM_RESERVED_SIZE;
}
Expand Down
1 change: 0 additions & 1 deletion src/cpu/intel/speedstep/acpi.c
View file
Expand Up @@ -23,7 +23,6 @@
#include <cpu/x86/msr.h>
#include <cpu/intel/speedstep.h>
#include <device/device.h>
#include <string.h>

static int determine_total_number_of_cores(void)
{
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/intel/turbo/turbo.c
View file
Expand Up @@ -19,7 +19,7 @@
#include <cpu/x86/msr.h>
#include <arch/cpu.h>

#if IS_ENABLED(CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED)
#if CONFIG(CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED)
static inline int get_global_turbo_state(void)
{
return TURBO_UNKNOWN;
Expand Down
13 changes: 7 additions & 6 deletions src/cpu/ti/am335x/gpio.c
View file
Expand Up @@ -18,9 +18,10 @@
#include <stdint.h>
#include <stdlib.h>

static struct am335x_gpio_regs *gpio_regs_and_bit(unsigned gpio, uint32_t *bit)
static struct am335x_gpio_regs *gpio_regs_and_bit(unsigned int gpio,
uint32_t *bit)
{
unsigned bank = gpio / AM335X_GPIO_BITS_PER_BANK;
unsigned int bank = gpio / AM335X_GPIO_BITS_PER_BANK;

if (bank >= ARRAY_SIZE(am335x_gpio_banks)) {
printk(BIOS_ERR, "Bad gpio index %d.\n", gpio);
Expand All @@ -38,7 +39,7 @@ void am335x_disable_gpio_irqs(void)
write32(&am335x_gpio_banks[i]->irqstatus_clr_0, 0xffffffff);
}

int gpio_direction_input(unsigned gpio)
int gpio_direction_input(unsigned int gpio)
{
uint32_t bit;
struct am335x_gpio_regs *regs = gpio_regs_and_bit(gpio, &bit);
Expand All @@ -49,7 +50,7 @@ int gpio_direction_input(unsigned gpio)
return 0;
}

int gpio_direction_output(unsigned gpio, int value)
int gpio_direction_output(unsigned int gpio, int value)
{
uint32_t bit;
struct am335x_gpio_regs *regs = gpio_regs_and_bit(gpio, &bit);
Expand All @@ -64,7 +65,7 @@ int gpio_direction_output(unsigned gpio, int value)
return 0;
}

int gpio_get_value(unsigned gpio)
int gpio_get_value(unsigned int gpio)
{
uint32_t bit;
struct am335x_gpio_regs *regs = gpio_regs_and_bit(gpio, &bit);
Expand All @@ -74,7 +75,7 @@ int gpio_get_value(unsigned gpio)
return (read32(&regs->datain) & bit) ? 1 : 0;
}

int gpio_set_value(unsigned gpio, int value)
int gpio_set_value(unsigned int gpio, int value)
{
uint32_t bit;
struct am335x_gpio_regs *regs = gpio_regs_and_bit(gpio, &bit);
Expand Down
8 changes: 4 additions & 4 deletions src/cpu/ti/am335x/gpio.h
View file
Expand Up @@ -62,9 +62,9 @@ static struct am335x_gpio_regs * const am335x_gpio_banks[] = {

void am335x_disable_gpio_irqs(void);

int gpio_direction_input(unsigned gpio);
int gpio_direction_output(unsigned gpio, int value);
int gpio_get_value(unsigned gpio);
int gpio_set_value(unsigned gpio, int value);
int gpio_direction_input(unsigned int gpio);
int gpio_direction_output(unsigned int gpio, int value);
int gpio_get_value(unsigned int gpio);
int gpio_set_value(unsigned int gpio, int value);

#endif /* __CPU_TI_AM335X_CLOCK_H__ */
6 changes: 3 additions & 3 deletions src/cpu/x86/16bit/entry16.inc
View file
Expand Up @@ -29,8 +29,8 @@

#include <arch/rom_segs.h>

#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) || \
IS_ENABLED(CONFIG_SIPI_VECTOR_IN_ROM)
#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) || \
CONFIG(SIPI_VECTOR_IN_ROM)
/* Symbol _start16bit must be aligned to 4kB to start AP CPUs with
* Startup IPI message without RAM.
*/
Expand All @@ -44,7 +44,7 @@ _start16bit:
cli
/* Save the BIST result */
movl %eax, %ebp
#if !IS_ENABLED(CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES)
#if !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES)
post_code(POST_RESET_VECTOR_CORRECT)
#endif

Expand Down
2 changes: 1 addition & 1 deletion src/cpu/x86/32bit/entry32.inc
View file
Expand Up @@ -47,7 +47,7 @@ __protected_start:
/* Save the BIST value */
movl %eax, %ebp

#if !IS_ENABLED(CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES)
#if !CONFIG(NO_EARLY_BOOTBLOCK_POSTCODES)
post_code(POST_ENTER_PROTECTED_MODE)
#endif

Expand Down
2 changes: 1 addition & 1 deletion src/cpu/x86/backup_default_smm.c
View file
Expand Up @@ -25,7 +25,7 @@ void *backup_default_smm_area(void)
void *save_area;
const void *default_smm = (void *)SMM_DEFAULT_BASE;

if (!IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
if (!CONFIG(HAVE_ACPI_RESUME))
return NULL;

/*
Expand Down
8 changes: 4 additions & 4 deletions src/cpu/x86/car.c
View file
Expand Up @@ -20,7 +20,7 @@
#include <arch/early_variables.h>
#include <symbols.h>

#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0)
#if CONFIG(PLATFORM_USES_FSP1_0)
#include <drivers/intel/fsp1_0/fsp_util.h>
#endif
typedef void (* const car_migration_func_t)(void);
Expand Down Expand Up @@ -61,7 +61,7 @@ void *car_get_var_ptr(void *var)
return var;
}

#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0)
#if CONFIG(PLATFORM_USES_FSP1_0)
migrated_base = (char *)find_saved_temp_mem(
*(void **)CBMEM_FSP_HOB_PTR);
/* FSP 1.0 migrates the entire DCACHE RAM */
Expand Down Expand Up @@ -96,7 +96,7 @@ void *car_sync_var_ptr(void *var)
* keep console buffer in CAR until cbmemc_reinit() moves it.
*/
if (*mig_var == _preram_cbmem_console) {
if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0))
if (CONFIG(PLATFORM_USES_FSP1_0))
*mig_var += (char *)mig_var - (char *)var;
return mig_var;
}
Expand Down Expand Up @@ -142,7 +142,7 @@ static void do_car_migrate_variables(void)

static void car_migrate_variables(int is_recovery)
{
if (!IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_0))
if (!CONFIG(PLATFORM_USES_FSP1_0))
do_car_migrate_variables();
}
ROMSTAGE_CBMEM_INIT_HOOK(car_migrate_variables)
2 changes: 1 addition & 1 deletion src/cpu/x86/lapic/apic_timer.c
View file
Expand Up @@ -98,7 +98,7 @@ void udelay(u32 usecs)
} while ((start - value) < ticks);
}

#if IS_ENABLED(CONFIG_LAPIC_MONOTONIC_TIMER)
#if CONFIG(LAPIC_MONOTONIC_TIMER)
#include <timer.h>

static struct monotonic_counter {
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/x86/lapic/boot_cpu.c
View file
Expand Up @@ -15,7 +15,7 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic_def.h>

#if IS_ENABLED(CONFIG_SMP)
#if CONFIG(SMP)
int boot_cpu(void)
{
int bsp;
Expand Down
26 changes: 13 additions & 13 deletions src/cpu/x86/lapic/lapic_cpu_init.c
View file
Expand Up @@ -147,9 +147,9 @@ static int lapic_start_cpu(unsigned long apicid)
}
return 0;
}
#if !IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX) \
&& !IS_ENABLED(CONFIG_CPU_INTEL_MODEL_206AX) \
&& !IS_ENABLED(CONFIG_CPU_INTEL_MODEL_2065X)
#if !CONFIG(CPU_AMD_MODEL_10XXX) \
&& !CONFIG(CPU_INTEL_MODEL_206AX) \
&& !CONFIG(CPU_INTEL_MODEL_2065X)
mdelay(10);
#endif

Expand Down Expand Up @@ -320,7 +320,7 @@ int start_cpu(struct device *cpu)
return result;
}

#if IS_ENABLED(CONFIG_AP_IN_SIPI_WAIT)
#if CONFIG(AP_IN_SIPI_WAIT)

/**
* Sending INIT IPI to self is equivalent of asserting #INIT with a bit of
Expand Down Expand Up @@ -408,7 +408,7 @@ asmlinkage void secondary_cpu_init(unsigned int index)
{
atomic_inc(&active_cpus);

if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
if (!CONFIG(PARALLEL_CPU_INIT))
spin_lock(&start_cpu_lock);

#ifdef __SSE3__
Expand All @@ -423,7 +423,7 @@ asmlinkage void secondary_cpu_init(unsigned int index)
#endif
cpu_initialize(index);

if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
if (!CONFIG(PARALLEL_CPU_INIT))
spin_unlock(&start_cpu_lock);

atomic_dec(&active_cpus);
Expand All @@ -440,7 +440,7 @@ static void start_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu)
if (cpu->path.type != DEVICE_PATH_APIC)
continue;

if (IS_ENABLED(CONFIG_PARALLEL_CPU_INIT) && (cpu == bsp_cpu))
if (CONFIG(PARALLEL_CPU_INIT) && (cpu == bsp_cpu))
continue;

if (!cpu->enabled)
Expand All @@ -454,7 +454,7 @@ static void start_other_cpus(struct bus *cpu_bus, struct device *bsp_cpu)
printk(BIOS_ERR, "CPU 0x%02x would not start!\n",
cpu->path.apic.apic_id);

if (!IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
if (!CONFIG(PARALLEL_CPU_INIT))
udelay(10);
}

Expand Down Expand Up @@ -554,24 +554,24 @@ void initialize_cpus(struct bus *cpu_bus)
if (is_smp_boot())
copy_secondary_start_to_lowest_1M();

if (!IS_ENABLED(CONFIG_SERIALIZED_SMM_INITIALIZATION))
if (!CONFIG(SERIALIZED_SMM_INITIALIZATION))
smm_init();

/* start all aps at first, so we can init ECC all together */
if (is_smp_boot() && IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
if (is_smp_boot() && CONFIG(PARALLEL_CPU_INIT))
start_other_cpus(cpu_bus, info->cpu);

/* Initialize the bootstrap processor */
cpu_initialize(0);

if (is_smp_boot() && !IS_ENABLED(CONFIG_PARALLEL_CPU_INIT))
if (is_smp_boot() && !CONFIG(PARALLEL_CPU_INIT))
start_other_cpus(cpu_bus, info->cpu);

/* Now wait the rest of the cpus stop*/
if (is_smp_boot())
wait_other_cpus_stop(cpu_bus);

if (IS_ENABLED(CONFIG_SERIALIZED_SMM_INITIALIZATION)) {
if (CONFIG(SERIALIZED_SMM_INITIALIZATION)) {
/* At this point, all APs are sleeping:
* smm_init() will queue a pending SMI on all cpus
* and smm_other_cpus() will start them one by one */
Expand All @@ -589,7 +589,7 @@ void initialize_cpus(struct bus *cpu_bus)
recover_lowest_1M();
}

#if !IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
#if !CONFIG(HAVE_SMI_HANDLER)
/* Empty stubs for platforms without SMI handlers. */
void smm_init(void)
{
Expand Down
11 changes: 6 additions & 5 deletions src/cpu/x86/mp_init.c
View file
Expand Up @@ -16,6 +16,7 @@

#include <console/console.h>
#include <stdint.h>
#include <string.h>
#include <rmodule.h>
#include <arch/cpu.h>
#include <commonlib/helpers.h>
Expand Down Expand Up @@ -714,7 +715,7 @@ struct mp_state {

static int is_smm_enabled(void)
{
return IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && mp_state.do_smm;
return CONFIG(HAVE_SMI_HANDLER) && mp_state.do_smm;
}

static void smm_disable(void)
Expand All @@ -724,7 +725,7 @@ static void smm_disable(void)

static void smm_enable(void)
{
if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER))
if (CONFIG(HAVE_SMI_HANDLER))
mp_state.do_smm = 1;
}

Expand Down Expand Up @@ -891,7 +892,7 @@ static int run_ap_work(struct mp_callback *val, long expire_us)
struct stopwatch sw;
int cur_cpu = cpu_index();

if (!IS_ENABLED(CONFIG_PARALLEL_MP_AP_WORK)) {
if (!CONFIG(PARALLEL_MP_AP_WORK)) {
printk(BIOS_ERR, "APs already parked. PARALLEL_MP_AP_WORK not selected.\n");
return -1;
}
Expand Down Expand Up @@ -933,7 +934,7 @@ static void ap_wait_for_instruction(void)
struct mp_callback **per_cpu_slot;
int cur_cpu;

if (!IS_ENABLED(CONFIG_PARALLEL_MP_AP_WORK))
if (!CONFIG(PARALLEL_MP_AP_WORK))
return;

cur_cpu = cpu_index();
Expand Down Expand Up @@ -1028,7 +1029,7 @@ static void fill_mp_state(struct mp_state *state, const struct mp_ops *ops)
* Default to smm_initiate_relocation() if trigger callback isn't
* provided.
*/
if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) &&
if (CONFIG(HAVE_SMI_HANDLER) &&
ops->per_cpu_smm_trigger == NULL)
mp_state.ops.per_cpu_smm_trigger = smm_initiate_relocation;
}
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/x86/mtrr/debug.c
View file
Expand Up @@ -197,6 +197,6 @@ static void _display_mtrrs(void)

asmlinkage void display_mtrrs(void)
{
if (IS_ENABLED(CONFIG_DISPLAY_MTRRS))
if (CONFIG(DISPLAY_MTRRS))
_display_mtrrs();
}
6 changes: 3 additions & 3 deletions src/cpu/x86/mtrr/mtrr.c
View file
Expand Up @@ -36,7 +36,7 @@
#include <memrange.h>
#include <cpu/amd/mtrr.h>
#include <assert.h>
#if IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS)
#if CONFIG(X86_AMD_FIXED_MTRRS)
#define MTRR_FIXED_WRBACK_BITS (MTRR_READ_MEM | MTRR_WRITE_MEM)
#else
#define MTRR_FIXED_WRBACK_BITS 0
Expand Down Expand Up @@ -86,7 +86,7 @@ void fixed_mtrrs_expose_amd_rwdram(void)
{
msr_t syscfg;

if (!IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS))
if (!CONFIG(X86_AMD_FIXED_MTRRS))
return;

syscfg = rdmsr(SYSCFG_MSR);
Expand All @@ -98,7 +98,7 @@ void fixed_mtrrs_hide_amd_rwdram(void)
{
msr_t syscfg;

if (!IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS))
if (!CONFIG(X86_AMD_FIXED_MTRRS))
return;

syscfg = rdmsr(SYSCFG_MSR);
Expand Down
6 changes: 3 additions & 3 deletions src/cpu/x86/sipi_vector.S
View file
Expand Up @@ -172,7 +172,7 @@ microcode_done:
test %ebx, %ebx
jz 1f

#if IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS)
#if CONFIG(X86_AMD_FIXED_MTRRS)
/* Allow modification of RdDram and WrDram bits */
mov $SYSCFG_MSR, %ecx
rdmsr
Expand All @@ -189,7 +189,7 @@ load_msr:
dec %ebx
jnz load_msr

#if IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS)
#if CONFIG(X86_AMD_FIXED_MTRRS)
mov $SYSCFG_MSR, %ecx
rdmsr
and $~SYSCFG_MSR_MtrrFixDramModEn, %eax
Expand All @@ -202,7 +202,7 @@ load_msr:
and $~(CR0_CLEAR_FLAGS_CACHE_ENABLE), %eax
mov %eax, %cr0

#if IS_ENABLED(CONFIG_SSE)
#if CONFIG(SSE)
/* Enable sse instructions. */
mov %cr4, %eax
orl $(CR4_OSFXSR | CR4_OSXMMEXCPT), %eax
Expand Down
4 changes: 2 additions & 2 deletions src/cpu/x86/smm/smihandler.c
View file
Expand Up @@ -19,7 +19,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>

#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
#if CONFIG(SPI_FLASH_SMM)
#include <spi-generic.h>
#endif

Expand Down Expand Up @@ -186,7 +186,7 @@ void smi_handler(u32 smm_revision)

/* Allow drivers to initialize variables in SMM context. */
if (do_driver_init) {
#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
#if CONFIG(SPI_FLASH_SMM)
spi_init();
#endif
do_driver_init = 0;
Expand Down
6 changes: 3 additions & 3 deletions src/cpu/x86/smm/smm_module_handler.c
View file
Expand Up @@ -18,7 +18,7 @@
#include <cpu/x86/smm.h>
#include <rmodule.h>

#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
#if CONFIG(SPI_FLASH_SMM)
#include <spi-generic.h>
#endif

Expand Down Expand Up @@ -161,7 +161,7 @@ asmlinkage void smm_handler_start(void *arg)

/* Allow drivers to initialize variables in SMM context. */
if (do_driver_init) {
#if IS_ENABLED(CONFIG_SPI_FLASH_SMM)
#if CONFIG(SPI_FLASH_SMM)
spi_init();
#endif
do_driver_init = 0;
Expand All @@ -180,7 +180,7 @@ asmlinkage void smm_handler_start(void *arg)
expected_canary);

// Don't die if we can't indicate an error.
if (IS_ENABLED(CONFIG_DEBUG_SMI))
if (CONFIG(DEBUG_SMI))
die("SMM Handler caused a stack overflow\n");
}

Expand Down
4 changes: 2 additions & 2 deletions src/cpu/x86/smm/smm_module_loader.c
View file
Expand Up @@ -346,7 +346,7 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params)
return -1;

/* Clear SMM region */
if (IS_ENABLED(CONFIG_DEBUG_SMI))
if (CONFIG(DEBUG_SMI))
memset(smram, 0xcd, size);

total_stack_size = params->per_cpu_stack_size *
Expand All @@ -370,7 +370,7 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params)
base += alignment_size;
}

if (IS_ENABLED(CONFIG_SSE)) {
if (CONFIG(SSE)) {
fxsave_size = FXSAVE_SIZE * params->num_concurrent_stacks;
/* FXSAVE area below all the stacks stack. */
fxsave_area = params->stack_top;
Expand Down
4 changes: 2 additions & 2 deletions src/cpu/x86/smm/smmhandler.S
View file
Expand Up @@ -77,7 +77,7 @@
#endif
.global smm_handler_start
smm_handler_start:
#if IS_ENABLED(CONFIG_SMM_LAPIC_REMAP_MITIGATION)
#if CONFIG(SMM_LAPIC_REMAP_MITIGATION)
/* Check if the LAPIC register block overlaps with SMM.
* This block needs to work without data accesses because they
* may be routed into the LAPIC register block.
Expand Down Expand Up @@ -139,7 +139,7 @@ untampered_lapic:
/* This is an ugly hack, and we should find a way to read the CPU index
* without relying on the LAPIC ID.
*/
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN)
#if CONFIG(CPU_AMD_AGESA_FAMILY15_TN)
/* LAPIC IDs start from 0x10; map that to the proper core index */
subl $0x10, %ecx
#endif
Expand Down
8 changes: 4 additions & 4 deletions src/cpu/x86/smm/smmrelocate.S
View file
Expand Up @@ -21,9 +21,9 @@
// can it be cleaned up so this include is not required?
// It's needed right now because we get our DEFAULT_PMBASE from
// here.
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801DX)
#if CONFIG(SOUTHBRIDGE_INTEL_I82801DX)
#include <southbridge/intel/i82801dx/i82801dx.h>
#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801IX)
#elif CONFIG(SOUTHBRIDGE_INTEL_I82801IX)
#include <southbridge/intel/i82801ix/i82801ix.h>
#else
#error "Southbridge needs SMM handler support."
Expand All @@ -32,7 +32,7 @@
// ADDR32() macro
#include <arch/registers.h>

#if IS_ENABLED(CONFIG_SMM_TSEG)
#if CONFIG(SMM_TSEG)
#error "Don't use this file with TSEG."

#endif /* CONFIG_SMM_TSEG */
Expand Down Expand Up @@ -154,7 +154,7 @@ smm_relocate:

/* End of southbridge specific section. */

#if IS_ENABLED(CONFIG_DEBUG_SMM_RELOCATION)
#if CONFIG(DEBUG_SMM_RELOCATION)
/* print [SMM-x] so we can determine if CPUx went to SMM */
movw $CONFIG_TTYS0_BASE, %dx
mov $'[', %al
Expand Down
4 changes: 2 additions & 2 deletions src/cpu/x86/tsc/delay_tsc.c
View file
Expand Up @@ -98,7 +98,7 @@ static unsigned long calibrate_tsc_with_pit(void)

static unsigned long calibrate_tsc(void)
{
if (IS_ENABLED(CONFIG_TSC_CONSTANT_RATE))
if (CONFIG(TSC_CONSTANT_RATE))
return tsc_freq_mhz();
else
return calibrate_tsc_with_pit();
Expand Down Expand Up @@ -135,7 +135,7 @@ void udelay(unsigned int us)
}
}

#if IS_ENABLED(CONFIG_TSC_MONOTONIC_TIMER)
#if CONFIG(TSC_MONOTONIC_TIMER)
#include <timer.h>

static struct monotonic_counter {
Expand Down
36 changes: 35 additions & 1 deletion src/device/Kconfig
View file
Expand Up @@ -76,7 +76,6 @@ config MAINBOARD_USE_LIBGFXINIT
depends on MAINBOARD_HAS_LIBGFXINIT
select HAVE_VGA_TEXT_FRAMEBUFFER
select HAVE_LINEAR_FRAMEBUFFER
select RAMSTAGE_LIBHWBASE
select VGA if VGA_TEXT_FRAMEBUFFER
help
Use the SPARK library `libgfxinit` for the native graphics
Expand Down Expand Up @@ -613,6 +612,41 @@ config VGA_BIOS_ID

Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.

config VGA_BIOS_DGPU
bool "Add a discrete VGA BIOS image"
depends on VGA_BIOS
help
Select this option if you have a VGA BIOS image for discrete GPU
that you would like to add to your ROM.

You will be able to specify the location and file name of the
image later.

config VGA_BIOS_DGPU_FILE
string "Discrete VGA BIOS path and filename"
depends on VGA_BIOS_DGPU
default "vgabios_dgpu.bin"
help
The path and filename of the file to use as VGA BIOS for discrete GPU.

config VGA_BIOS_DGPU_ID
string "Discrete VGA device PCI IDs"
depends on VGA_BIOS_DGPU
default "1002,6663"
help
The comma-separated PCI vendor and device ID that would associate
your VGA BIOS to your discrete video card.

Examples:
1002,6663 for HD 8570M
1002,6665 for R5 M230

In the above examples 1002 is the PCI vendor ID (in hex, but without
the "0x" prefix) and 6663 / 6665 specifies the PCI device ID of the
discrete video card (also in hex, without "0x" prefix).

Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.

config INTEL_GMA_HAVE_VBT
bool
help
Expand Down
1 change: 0 additions & 1 deletion src/device/Makefile.inc
View file
Expand Up @@ -33,7 +33,6 @@ ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c
ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c
ramstage-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c
ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c
ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c
endif

subdirs-y += oprom dram
Expand Down
16 changes: 8 additions & 8 deletions src/device/device.c
View file
Expand Up @@ -45,7 +45,7 @@
#include <stdlib.h>
#include <string.h>
#include <smp/spinlock.h>
#if IS_ENABLED(CONFIG_ARCH_X86)
#if CONFIG(ARCH_X86)
#include <arch/ebda.h>
#endif
#include <timer.h>
Expand Down Expand Up @@ -99,7 +99,7 @@ void dev_finalize_chips(void)

DECLARE_SPIN_LOCK(dev_lock)

#if IS_ENABLED(CONFIG_GFXUMA)
#if CONFIG(GFXUMA)
/* IGD UMA memory */
uint64_t uma_memory_base = 0;
uint64_t uma_memory_size = 0;
Expand Down Expand Up @@ -790,12 +790,12 @@ static void set_vga_bridge_bits(void)
if (!vga)
vga = vga_onboard;

if (CONFIG_ONBOARD_VGA_IS_PRIMARY && vga_onboard)
if (CONFIG(ONBOARD_VGA_IS_PRIMARY) && vga_onboard)
vga = vga_onboard;

/* If we prefer plugin VGA over chipset VGA, the chipset might
want to know. */
if (!CONFIG_ONBOARD_VGA_IS_PRIMARY && (vga != vga_onboard) &&
if (!CONFIG(ONBOARD_VGA_IS_PRIMARY) && (vga != vga_onboard) &&
vga_onboard && vga_onboard->ops && vga_onboard->ops->disable) {
printk(BIOS_DEBUG, "Use plugin graphics over integrated.\n");
vga_onboard->ops->disable(vga_onboard);
Expand Down Expand Up @@ -1129,7 +1129,7 @@ static void init_dev(struct device *dev)
return;

if (!dev->initialized && dev->ops && dev->ops->init) {
#if IS_ENABLED(CONFIG_HAVE_MONOTONIC_TIMER)
#if CONFIG(HAVE_MONOTONIC_TIMER)
struct stopwatch sw;
stopwatch_init(&sw);
#endif
Expand All @@ -1141,7 +1141,7 @@ static void init_dev(struct device *dev)
printk(BIOS_DEBUG, "%s init ...\n", dev_path(dev));
dev->initialized = 1;
dev->ops->init(dev);
#if IS_ENABLED(CONFIG_HAVE_MONOTONIC_TIMER)
#if CONFIG(HAVE_MONOTONIC_TIMER)
printk(BIOS_DEBUG, "%s init finished in %ld usecs\n", dev_path(dev),
stopwatch_duration_usecs(&sw));
#endif
Expand Down Expand Up @@ -1177,12 +1177,12 @@ void dev_initialize(void)

printk(BIOS_INFO, "Initializing devices...\n");

#if IS_ENABLED(CONFIG_ARCH_X86)
#if CONFIG(ARCH_X86)
/*
* Initialize EBDA area in ramstage if early
* initialization is not done.
*/
if (!IS_ENABLED(CONFIG_EARLY_EBDA_INIT))
if (!CONFIG(EARLY_EBDA_INIT))
/* Ensure EBDA is prepared before Option ROMs. */
setup_default_ebda();
#endif
Expand Down
2 changes: 1 addition & 1 deletion src/device/device_const.c
View file
Expand Up @@ -191,7 +191,7 @@ DEVTREE_CONST struct device *pcidev_path_on_root(pci_devfn_t devfn)
* due tue complicated devicetree with topology
* being manipulated on-the-fly.
*/
if (IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10))
if (CONFIG(NORTHBRIDGE_AMD_AMDFAM10))
return dev_find_slot(0, devfn);

pci_domain = dev_find_path(NULL, DEVICE_PATH_DOMAIN);
Expand Down
14 changes: 14 additions & 0 deletions src/device/device_util.c
View file
Expand Up @@ -801,6 +801,20 @@ void fixed_mem_resource(struct device *dev, unsigned long index,
resource->flags |= type;
}

void fixed_io_resource(struct device *dev, unsigned long index,
unsigned long base, unsigned long size)
{
struct resource *resource;

resource = new_resource(dev, index);
resource->base = (resource_t)base;
resource->size = (resource_t)size;
resource->limit = resource->base + resource->size - 1;
resource->flags = IORESOURCE_IO | IORESOURCE_FIXED |
IORESOURCE_STORED | IORESOURCE_ASSIGNED |
IORESOURCE_RESERVE;
}

void mmconf_resource_init(struct resource *resource, resource_t base,
int buses)
{
Expand Down
2 changes: 1 addition & 1 deletion src/device/oprom/include/io.h
View file
Expand Up @@ -14,7 +14,7 @@
#ifndef __OPROM_IO_H__
#define __OPROM_IO_H__

#if IS_ENABLED(CONFIG_ARCH_X86)
#if CONFIG(ARCH_X86)
#include <arch/io.h>
#else
void outb(u8 val, u16 port);
Expand Down
2 changes: 1 addition & 1 deletion src/device/oprom/include/x86emu/fpu_regs.h
View file
Expand Up @@ -102,7 +102,7 @@ struct x86_fpu_registers {

#endif /* X86_FPU_SUPPORT */

#if IS_ENABLED(CONFIG_X86EMU_DEBUG)
#if CONFIG(X86EMU_DEBUG)
# define DECODE_PRINTINSTR32(t,mod,rh,rl) \
DECODE_PRINTF(t[(mod<<3)+(rh)]);
# define DECODE_PRINTINSTR256(t,mod,rh,rl) \
Expand Down
2 changes: 1 addition & 1 deletion src/device/oprom/include/x86emu/regs.h
View file
Expand Up @@ -278,7 +278,7 @@ typedef struct {
u32 mode;
volatile int intr; /* mask of pending interrupts */
volatile int debug;
#if IS_ENABLED(CONFIG_X86EMU_DEBUG)
#if CONFIG(X86EMU_DEBUG)
int check;
u16 saved_ip;
u16 saved_cs;
Expand Down
4 changes: 2 additions & 2 deletions src/device/oprom/include/x86emu/x86emu.h
View file
Expand Up @@ -43,7 +43,7 @@

#include <stddef.h>
#include <console/console.h>
#if IS_ENABLED(CONFIG_X86EMU_DEBUG)
#if CONFIG(X86EMU_DEBUG)
#define DEBUG
#endif

Expand Down Expand Up @@ -153,7 +153,7 @@ void X86EMU_setMemBase(void *base, size_t size);
void X86EMU_exec(void);
void X86EMU_halt_sys(void);

#if IS_ENABLED(CONFIG_X86EMU_DEBUG)
#if CONFIG(X86EMU_DEBUG)
#define HALT_SYS() \
printf("halt_sys: in %s\n", __func__); \
X86EMU_halt_sys();
Expand Down
8 changes: 4 additions & 4 deletions src/device/oprom/realmode/x86.c
View file
Expand Up @@ -212,7 +212,7 @@ static void setup_realmode_idt(void)
write_idt_stub((void *)0xffe6e, 0x1a);
}

#if IS_ENABLED(CONFIG_FRAMEBUFFER_SET_VESA_MODE)
#if CONFIG(FRAMEBUFFER_SET_VESA_MODE)
vbe_mode_info_t mode_info;
static int mode_info_valid;

Expand Down Expand Up @@ -268,7 +268,7 @@ void vbe_set_graphics(void)
}

vbe_set_mode(&mode_info);
#if IS_ENABLED(CONFIG_BOOTSPLASH)
#if CONFIG(BOOTSPLASH)
struct jpeg_decdata *decdata;
unsigned char *jpeg = cbfs_boot_map_with_leak("bootsplash.jpg",
CBFS_TYPE_BOOTSPLASH,
Expand Down Expand Up @@ -349,7 +349,7 @@ void run_bios(struct device *dev, unsigned long addr)
realmode_call(addr + 0x0003, num_dev, 0xffff, 0x0000, 0xffff, 0x0, 0x0);
printk(BIOS_DEBUG, "... Option ROM returned.\n");

#if IS_ENABLED(CONFIG_FRAMEBUFFER_SET_VESA_MODE)
#if CONFIG(FRAMEBUFFER_SET_VESA_MODE)
if ((dev->class >> 8)== PCI_CLASS_DISPLAY_VGA)
vbe_set_graphics();
#endif
Expand Down Expand Up @@ -383,7 +383,7 @@ int asmlinkage interrupt_handler(u32 intnumber,
cs = cs_ip >> 16;
flags = stackflags;

#if IS_ENABLED(CONFIG_REALMODE_DEBUG)
#if CONFIG(REALMODE_DEBUG)
printk(BIOS_DEBUG, "oprom: INT# 0x%x\n", intnumber);
printk(BIOS_DEBUG, "oprom: eax: %08x ebx: %08x ecx: %08x edx: %08x\n",
eax, ebx, ecx, edx);
Expand Down
2 changes: 1 addition & 1 deletion src/device/oprom/realmode/x86_interrupts.c
View file
Expand Up @@ -210,7 +210,7 @@ int int1a_handler(void)
break;
}

#if IS_ENABLED(CONFIG_REALMODE_DEBUG)
#if CONFIG(REALMODE_DEBUG)
printk(BIOS_DEBUG, "0x%x: bus %d devfn 0x%x reg 0x%x val 0x%x\n",
func, bus, devfn, reg, X86_ECX);
#endif
Expand Down
30 changes: 15 additions & 15 deletions src/device/oprom/yabel/biosemu.c
View file
Expand Up @@ -52,7 +52,7 @@
#include <device/device.h>
#include "compat/rtas.h"

#if IS_ENABLED(CONFIG_X86EMU_DEBUG_TIMINGS)
#if CONFIG(X86EMU_DEBUG_TIMINGS)
struct mono_time zero;
#endif

Expand Down Expand Up @@ -87,44 +87,44 @@ biosemu(u8 *biosmem, u32 biosmem_size, struct device * dev, unsigned long rom_ad
{
u8 *rom_image;
int i = 0;
#if IS_ENABLED(CONFIG_X86EMU_DEBUG)
#if CONFIG(X86EMU_DEBUG)
debug_flags = 0;
#if IS_ENABLED(CONFIG_X86EMU_DEBUG_JMP)
#if CONFIG(X86EMU_DEBUG_JMP)
debug_flags |= DEBUG_JMP;
#endif
#if IS_ENABLED(CONFIG_X86EMU_DEBUG_TRACE)
#if CONFIG(X86EMU_DEBUG_TRACE)
debug_flags |= DEBUG_TRACE_X86EMU;
#endif
#if IS_ENABLED(CONFIG_X86EMU_DEBUG_PNP)
#if CONFIG(X86EMU_DEBUG_PNP)
debug_flags |= DEBUG_PNP;
#endif
#if IS_ENABLED(CONFIG_X86EMU_DEBUG_DISK)
#if CONFIG(X86EMU_DEBUG_DISK)
debug_flags |= DEBUG_DISK;
#endif
#if IS_ENABLED(CONFIG_X86EMU_DEBUG_PMM)
#if CONFIG(X86EMU_DEBUG_PMM)
debug_flags |= DEBUG_PMM;
#endif
#if IS_ENABLED(CONFIG_X86EMU_DEBUG_VBE)
#if CONFIG(X86EMU_DEBUG_VBE)
debug_flags |= DEBUG_VBE;
#endif
#if IS_ENABLED(CONFIG_X86EMU_DEBUG_INT10)
#if CONFIG(X86EMU_DEBUG_INT10)
debug_flags |= DEBUG_PRINT_INT10;
#endif
#if IS_ENABLED(CONFIG_X86EMU_DEBUG_INTERRUPTS)
#if CONFIG(X86EMU_DEBUG_INTERRUPTS)
debug_flags |= DEBUG_INTR;
#endif
#if IS_ENABLED(CONFIG_X86EMU_DEBUG_CHECK_VMEM_ACCESS)
#if CONFIG(X86EMU_DEBUG_CHECK_VMEM_ACCESS)
debug_flags |= DEBUG_CHECK_VMEM_ACCESS;
#endif
#if IS_ENABLED(CONFIG_X86EMU_DEBUG_MEM)
#if CONFIG(X86EMU_DEBUG_MEM)
debug_flags |= DEBUG_MEM;
#endif
#if IS_ENABLED(CONFIG_X86EMU_DEBUG_IO)
#if CONFIG(X86EMU_DEBUG_IO)
debug_flags |= DEBUG_IO;
#endif

#endif
#if IS_ENABLED(CONFIG_X86EMU_DEBUG_TIMINGS)
#if CONFIG(X86EMU_DEBUG_TIMINGS)
/* required for i915tool compatible output */
zero.microseconds = 0;
#endif
Expand Down Expand Up @@ -345,7 +345,7 @@ biosemu(u8 *biosmem, u32 biosmem_size, struct device * dev, unsigned long rom_ad
* some boot device status in AX (see PNP BIOS Spec Section 3.3
*/
DEBUG_PRINTF_CS_IP("Option ROM Exit Status: %04x\n", M.x86.R_AX);
#if IS_ENABLED(CONFIG_X86EMU_DEBUG)
#if CONFIG(X86EMU_DEBUG)
DEBUG_PRINTF("Exit Status Decode:\n");
if (M.x86.R_AX & 0x100) { // bit 8
DEBUG_PRINTF
Expand Down
6 changes: 3 additions & 3 deletions src/device/oprom/yabel/compat/functions.c
View file
Expand Up @@ -45,7 +45,7 @@

#define VMEM_SIZE (1024 * 1024) /* 1 MB */

#if !IS_ENABLED(CONFIG_YABEL_DIRECTHW)
#if !CONFIG(YABEL_DIRECTHW)
#if CONFIG_YABEL_VIRTMEM_LOCATION
u8* vmem = (u8 *) CONFIG_YABEL_VIRTMEM_LOCATION;
#else
Expand All @@ -63,7 +63,7 @@ void run_bios(struct device * dev, unsigned long addr)

biosemu(vmem, VMEM_SIZE, dev, addr);

#if IS_ENABLED(CONFIG_FRAMEBUFFER_SET_VESA_MODE)
#if CONFIG(FRAMEBUFFER_SET_VESA_MODE)
vbe_set_graphics();
#endif
}
Expand All @@ -73,7 +73,7 @@ unsigned long tb_freq = 0;
u64 get_time(void)
{
u64 act = 0;
#if IS_ENABLED(CONFIG_ARCH_X86)
#if CONFIG(ARCH_X86)
u32 eax, edx;

__asm__ __volatile__(
Expand Down
6 changes: 3 additions & 3 deletions src/device/oprom/yabel/debug.h
View file
Expand Up @@ -37,7 +37,7 @@
#include <timer.h>
#include <types.h>

#if IS_ENABLED(CONFIG_X86EMU_DEBUG_TIMINGS)
#if CONFIG(X86EMU_DEBUG_TIMINGS)
extern struct mono_time zero;
#endif
extern u32 debug_flags;
Expand Down Expand Up @@ -91,15 +91,15 @@ static inline void set_ci(void) {};
// set to enable tracing of JMPs in x86emu
#define DEBUG_JMP 0x2000

#if IS_ENABLED(CONFIG_X86EMU_DEBUG)
#if CONFIG(X86EMU_DEBUG)

#define CHECK_DBG(_flag) if (debug_flags & _flag)

#define DEBUG_PRINTF(_x...) printf(_x);
// prints the CS:IP before the printout, NOTE: actually its CS:IP of the _next_ instruction
// to be executed, since the x86emu advances CS:IP _before_ actually executing an instruction

#if IS_ENABLED(CONFIG_X86EMU_DEBUG_TIMINGS)
#if CONFIG(X86EMU_DEBUG_TIMINGS)
#define DEBUG_PRINTF_CS_IP(_x...) DEBUG_PRINTF("[%08lx]%x:%x ", (current_time_from(&zero)).microseconds, M.x86.R_CS, M.x86.R_IP); DEBUG_PRINTF(_x);
#else
#define DEBUG_PRINTF_CS_IP(_x...) DEBUG_PRINTF("%x:%x ", M.x86.R_CS, M.x86.R_IP); DEBUG_PRINTF(_x);
Expand Down
18 changes: 9 additions & 9 deletions src/device/oprom/yabel/device.c
View file
Expand Up @@ -58,7 +58,7 @@ typedef struct {
u64 size;
} __packed assigned_address_t;

#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL)
#if CONFIG(PCI_OPTION_ROM_RUN_YABEL)
/* coreboot version */

static void
Expand Down Expand Up @@ -131,7 +131,7 @@ biosemu_dev_get_addr_info(void)
}
// store last entry index of translate_address_array
taa_last_entry = taa_index - 1;
#if IS_ENABLED(CONFIG_X86EMU_DEBUG)
#if CONFIG(X86EMU_DEBUG)
//dump translate_address_array
printf("translate_address_array:\n");
translate_address_t ta;
Expand Down Expand Up @@ -215,7 +215,7 @@ biosemu_dev_get_addr_info(void)
}
// store last entry index of translate_address_array
taa_last_entry = taa_index - 1;
#if IS_ENABLED(CONFIG_X86EMU_DEBUG)
#if CONFIG(X86EMU_DEBUG)
//dump translate_address_array
printf("translate_address_array:\n");
translate_address_t ta;
Expand Down Expand Up @@ -247,7 +247,7 @@ biosemu_add_special_memory(u32 start, u32 size)
translate_address_array[taa_index].address_offset = 0;
}

#if !IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL)
#if !CONFIG(PCI_OPTION_ROM_RUN_YABEL)
// to simulate accesses to legacy VGA Memory (0xA0000-0xBFFFF)
// we look for the first prefetchable memory BAR, if no prefetchable BAR found,
// we use the first memory BAR
Expand Down Expand Up @@ -309,7 +309,7 @@ biosemu_dev_get_device_vendor_id(void)
{

u32 pci_config_0;
#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL)
#if CONFIG(PCI_OPTION_ROM_RUN_YABEL)
pci_config_0 = pci_read_config32(bios_device.dev, 0x0);
#else
pci_config_0 =
Expand Down Expand Up @@ -371,7 +371,7 @@ biosemu_dev_check_exprom(unsigned long rom_base_addr)
memcpy(&pci_ds, (void *) (rom_base_addr + pci_ds_offset),
sizeof(pci_ds));
clr_ci();
#if IS_ENABLED(CONFIG_X86EMU_DEBUG)
#if CONFIG(X86EMU_DEBUG)
DEBUG_PRINTF("PCI Data Structure @%lx:\n",
rom_base_addr + pci_ds_offset);
dump((void *) &pci_ds, sizeof(pci_ds));
Expand Down Expand Up @@ -435,7 +435,7 @@ biosemu_dev_init(struct device * device)
DEBUG_PRINTF("%s\n", __func__);
memset(&bios_device, 0, sizeof(bios_device));

#if !IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL)
#if !CONFIG(PCI_OPTION_ROM_RUN_YABEL)
bios_device.ihandle = of_open(device_name);
if (bios_device.ihandle == 0) {
DEBUG_PRINTF("%s is no valid device!\n", device_name);
Expand All @@ -446,7 +446,7 @@ biosemu_dev_init(struct device * device)
bios_device.dev = device;
#endif
biosemu_dev_get_addr_info();
#if !IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL)
#if !CONFIG(PCI_OPTION_ROM_RUN_YABEL)
biosemu_dev_find_vmem_addr();
biosemu_dev_get_puid();
#endif
Expand All @@ -463,7 +463,7 @@ biosemu_dev_translate_address(int type, unsigned long * addr)
{
int i = 0;
translate_address_t ta;
#if !IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL)
#if !CONFIG(PCI_OPTION_ROM_RUN_YABEL)
/* we don't need this hack for coreboot... we can access legacy areas */
//check if it is an access to legacy VGA Mem... if it is, map the address
//to the vmem BAR and then translate it...
Expand Down