42 changes: 5 additions & 37 deletions src/Kconfig
View file
Expand Up @@ -234,7 +234,6 @@ config NO_RELOCATABLE_RAMSTAGE

config RELOCATABLE_RAMSTAGE
bool
depends on EARLY_CBMEM_INIT
default !NO_RELOCATABLE_RAMSTAGE
select RELOCATABLE_MODULES
help
Expand Down Expand Up @@ -451,12 +450,10 @@ config RESUME_PATH_SAME_AS_BOOT

config HAVE_ROMSTAGE_CONSOLE_SPINLOCK
bool
depends on EARLY_CBMEM_INIT
default n

config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK
bool
depends on EARLY_CBMEM_INIT
default n
help
This should be enabled on certain plaforms, such as the AMD
Expand All @@ -465,7 +462,6 @@ config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK

config HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK
bool
depends on EARLY_CBMEM_INIT
default n

config HAVE_MONOTONIC_TIMER
Expand Down Expand Up @@ -670,6 +666,11 @@ source "payloads/Kconfig"

menu "Debugging"

comment "CPU Debug Settings"
source "src/cpu/*/Kconfig.debug"

comment "General Debug Settings"

# TODO: Better help text and detailed instructions.
config GDB_STUB
bool "GDB debugging support"
Expand Down Expand Up @@ -722,24 +723,6 @@ config DEBUG_RAM_SETUP

If unsure, say N.

config HAVE_DEBUG_CAR
def_bool n

config DEBUG_CAR
def_bool n
depends on HAVE_DEBUG_CAR

if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
# printk(BIOS_DEBUG, ...) calls.
config DEBUG_CAR
bool "Output verbose Cache-as-RAM debug messages"
default n
depends on HAVE_DEBUG_CAR
help
This option enables additional CAR related debug messages.
endif

config DEBUG_PIRQ
bool "Check PIRQ table consistency"
default n
Expand Down Expand Up @@ -773,18 +756,6 @@ config DEBUG_SMI

If unsure, say N.

config DEBUG_SMM_RELOCATION
bool "Debug SMM relocation code"
default n
depends on HAVE_SMI_HANDLER
help
This option enables additional SMM handler relocation related
debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
# printk(BIOS_DEBUG, ...) calls.
config DEBUG_MALLOC
Expand Down Expand Up @@ -1158,9 +1129,6 @@ config NO_XIP_EARLY_STAGES
help
Identify if early stages are eXecute-In-Place(XIP).

config EARLY_CBMEM_INIT
def_bool !LATE_CBMEM_INIT

config EARLY_CBMEM_LIST
bool
default n
Expand Down
6 changes: 3 additions & 3 deletions src/arch/arm/armv7/mmu.c
View file
Expand Up @@ -236,7 +236,7 @@ void mmu_disable_range_kb(u32 start_kb, u32 size_kb)
printk(BIOS_DEBUG, "Setting address range [%#.8x:%#.8x) as unmapped\n",
start_kb * KiB, (start_kb + size_kb) * KiB);
mmu_fill_table(table, (start_kb & mask) / (PAGE_SIZE/KiB),
div_round_up((start_kb + size_kb) & mask, PAGE_SIZE/KiB),
DIV_ROUND_UP((start_kb + size_kb) & mask, PAGE_SIZE/KiB),
(start_kb & ~mask) * KiB, PAGE_SHIFT, 0);
}

Expand All @@ -246,7 +246,7 @@ void mmu_disable_range(u32 start_mb, u32 size_mb)
start_mb * MiB, (start_mb + size_mb) * MiB);
assert(start_mb + size_mb <= 4 * (GiB/MiB));
mmu_fill_table(ttb_buff, start_mb / (BLOCK_SIZE/MiB),
div_round_up(start_mb + size_mb, BLOCK_SIZE/MiB),
DIV_ROUND_UP(start_mb + size_mb, BLOCK_SIZE/MiB),
0, BLOCK_SHIFT, 0);
}

Expand All @@ -256,7 +256,7 @@ void mmu_config_range(u32 start_mb, u32 size_mb, enum dcache_policy policy)
start_mb * MiB, (start_mb + size_mb) * MiB, attrs[policy].name);
assert(start_mb + size_mb <= 4 * (GiB/MiB));
mmu_fill_table(ttb_buff, start_mb / (BLOCK_SIZE/MiB),
div_round_up(start_mb + size_mb, BLOCK_SIZE/MiB),
DIV_ROUND_UP(start_mb + size_mb, BLOCK_SIZE/MiB),
0, BLOCK_SHIFT, ATTR_BLOCK | attrs[policy].value);
}

Expand Down
6 changes: 1 addition & 5 deletions src/arch/arm/include/arch/pci_ops.h
View file
Expand Up @@ -17,13 +17,9 @@
#define ARCH_ARM_PCI_OPS_H

#include <stdint.h>

typedef u32 pci_devfn_t;
#include <device/pci_type.h>

#ifdef __SIMPLE_DEVICE__
// FIXME: Use of device_t is deprecated
typedef pci_devfn_t device_t;

u8 pci_read_config8(pci_devfn_t dev, unsigned int where);
u16 pci_read_config16(pci_devfn_t dev, unsigned int where);
u32 pci_read_config32(pci_devfn_t dev, unsigned int where);
Expand Down
42 changes: 21 additions & 21 deletions src/arch/arm/memmove.S
View file
Expand Up @@ -149,26 +149,26 @@ ENTRY(memmove)
PLD( pld [r1, #-96] )

12: PLD( pld [r1, #-128] )
13: ldmdb r1!, {r7, r8, r9, ip}
mov lr, r3, push #\push
subs r2, r2, #32
ldmdb r1!, {r3, r4, r5, r6}
orr lr, lr, ip, pull #\pull
mov ip, ip, push #\push
orr ip, ip, r9, pull #\pull
mov r9, r9, push #\push
orr r9, r9, r8, pull #\pull
mov r8, r8, push #\push
orr r8, r8, r7, pull #\pull
mov r7, r7, push #\push
orr r7, r7, r6, pull #\pull
mov r6, r6, push #\push
orr r6, r6, r5, pull #\pull
mov r5, r5, push #\push
orr r5, r5, r4, pull #\pull
mov r4, r4, push #\push
orr r4, r4, r3, pull #\pull
stmdb r0!, {r4 - r9, ip, lr}
13: ldmdb r1!, {r7, r8, r9, ip}
mov lr, r3, push #\push
subs r2, r2, #32
ldmdb r1!, {r3, r4, r5, r6}
orr lr, lr, ip, pull #\pull
mov ip, ip, push #\push
orr ip, ip, r9, pull #\pull
mov r9, r9, push #\push
orr r9, r9, r8, pull #\pull
mov r8, r8, push #\push
orr r8, r8, r7, pull #\pull
mov r7, r7, push #\push
orr r7, r7, r6, pull #\pull
mov r6, r6, push #\push
orr r6, r6, r5, pull #\pull
mov r5, r5, push #\push
orr r5, r5, r4, pull #\pull
mov r4, r4, push #\push
orr r4, r4, r3, pull #\pull
stmdb r0!, {r4 - r9, ip, lr}
bge 12b
PLD( cmn r2, #96 )
PLD( bge 13b )
Expand All @@ -178,7 +178,7 @@ ENTRY(memmove)
14: ands ip, r2, #28
beq 16f

15: mov lr, r3, push #\push
15: mov lr, r3, push #\push
ldr r3, [r1, #-4]!
subs ip, ip, #4
orr lr, lr, r3, pull #\pull
Expand Down
6 changes: 1 addition & 5 deletions src/arch/arm64/include/arch/pci_ops.h
View file
Expand Up @@ -17,13 +17,9 @@
#define ARCH_ARM64_PCI_OPS_H

#include <stdint.h>

typedef u32 pci_devfn_t;
#include <device/pci_type.h>

#ifdef __SIMPLE_DEVICE__
// FIXME: Use of device_t is deprecated
typedef pci_devfn_t device_t;

u8 pci_read_config8(pci_devfn_t dev, unsigned int where);
u16 pci_read_config16(pci_devfn_t dev, unsigned int where);
u32 pci_read_config32(pci_devfn_t dev, unsigned int where);
Expand Down
6 changes: 1 addition & 5 deletions src/arch/mips/include/arch/pci_ops.h
View file
Expand Up @@ -17,13 +17,9 @@
#define ARCH_MIPS_PCI_OPS_H

#include <stdint.h>

typedef u32 pci_devfn_t;
#include <device/pci_type.h>

#ifdef __SIMPLE_DEVICE__
// FIXME: Use of device_t is deprecated
typedef pci_devfn_t device_t;

u8 pci_read_config8(pci_devfn_t dev, unsigned int where);
u16 pci_read_config16(pci_devfn_t dev, unsigned int where);
u32 pci_read_config32(pci_devfn_t dev, unsigned int where);
Expand Down
25 changes: 0 additions & 25 deletions src/arch/power8/Kconfig
View file

This file was deleted.

25 changes: 25 additions & 0 deletions src/arch/ppc64/Kconfig
View file
@@ -0,0 +1,25 @@
config ARCH_PPC64
bool
default n

config ARCH_BOOTBLOCK_PPC64
bool
default n
select ARCH_PPC64
select BOOTBLOCK_CUSTOM
select C_ENVIRONMENT_BOOTBLOCK
select ARCH_VERSTAGE_PPC64
select ARCH_ROMSTAGE_PPC64
select ARCH_RAMSTAGE_PPC64

config ARCH_VERSTAGE_PPC64
bool
default n

config ARCH_ROMSTAGE_PPC64
bool
default n

config ARCH_RAMSTAGE_PPC64
bool
default n
20 changes: 10 additions & 10 deletions src/arch/power8/Makefile.inc → src/arch/ppc64/Makefile.inc
View file
Expand Up @@ -16,14 +16,14 @@
##
################################################################################

power8_flags = -I$(src)/arch/power8/ -mbig-endian -mcpu=power8 -mtune=power8
ppc64_flags = -I$(src)/arch/ppc64/ -mbig-endian -mcpu=power8 -mtune=power8

power8_asm_flags =
ppc64_asm_flags =

################################################################################
## bootblock
################################################################################
ifeq ($(CONFIG_ARCH_BOOTBLOCK_POWER8),y)
ifeq ($(CONFIG_ARCH_BOOTBLOCK_PPC64),y)

bootblock-y = bootblock.S stages.c
bootblock-y += boot.c
Expand All @@ -35,7 +35,7 @@ bootblock-y += \
$(top)/src/lib/memmove.c \
$(top)/src/lib/memset.c

bootblock-generic-ccopts += $(power8_flags)
bootblock-generic-ccopts += $(ppc64_flags)

$(objcbfs)/bootblock.debug: $$(bootblock-objs)
@printf " LINK $(subst $(obj)/,,$(@))\n"
Expand All @@ -48,7 +48,7 @@ endif
################################################################################
## romstage
################################################################################
ifeq ($(CONFIG_ARCH_ROMSTAGE_POWER8),y)
ifeq ($(CONFIG_ARCH_ROMSTAGE_PPC64),y)

romstage-y += boot.c
romstage-y += stages.c
Expand All @@ -68,15 +68,15 @@ $(objcbfs)/romstage.debug: $$(romstage-objs)
@printf " LINK $(subst $(obj)/,,$(@))\n"
$(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(call src-to-obj,romstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage)

romstage-c-ccopts += $(power8_flags)
romstage-S-ccopts += $(power8_asm_flags)
romstage-c-ccopts += $(ppc64_flags)
romstage-S-ccopts += $(ppc64_asm_flags)

endif

################################################################################
## ramstage
################################################################################
ifeq ($(CONFIG_ARCH_RAMSTAGE_POWER8),y)
ifeq ($(CONFIG_ARCH_RAMSTAGE_PPC64),y)

ramstage-y += rom_media.c
ramstage-y += stages.c
Expand All @@ -102,7 +102,7 @@ $(objcbfs)/ramstage.debug: $$(ramstage-objs)
@printf " CC $(subst $(obj)/,,$(@))\n"
$(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(call src-to-obj,ramstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage)

ramstage-c-ccopts += $(power8_flags)
ramstage-S-ccopts += $(power8_asm_flags)
ramstage-c-ccopts += $(ppc64_flags)
ramstage-S-ccopts += $(ppc64_asm_flags)

endif
0 src/arch/power8/boot.c → src/arch/ppc64/boot.c
View file
File renamed without changes.
0 src/arch/power8/bootblock.S → src/arch/ppc64/bootblock.S
View file
File renamed without changes.
0 src/arch/power8/id.ld → src/arch/ppc64/id.ld
View file
File renamed without changes.
0 src/arch/power8/include/arch/byteorder.h → src/arch/ppc64/include/arch/byteorder.h
View file
File renamed without changes.
0 src/arch/power8/include/arch/cache.h → src/arch/ppc64/include/arch/cache.h
View file
File renamed without changes.
0 src/arch/power8/include/arch/cbconfig.h → src/arch/ppc64/include/arch/cbconfig.h
View file
File renamed without changes.
8 changes: 4 additions & 4 deletions src/arch/power8/include/arch/cpu.h → src/arch/ppc64/include/arch/cpu.h
View file
Expand Up @@ -36,10 +36,10 @@ struct cpu_info {
#endif
};

struct cpuinfo_power8 {
uint8_t power8; /* CPU family */
uint8_t power8_vendor; /* CPU vendor */
uint8_t power8_model;
struct cpuinfo_ppc64 {
uint8_t ppc64; /* CPU family */
uint8_t ppc64_vendor; /* CPU vendor */
uint8_t ppc64_model;
};

#endif
Expand Down
0 ...rch/power8/include/arch/early_variables.h → ...arch/ppc64/include/arch/early_variables.h
View file
File renamed without changes.
0 src/arch/power8/include/arch/exception.h → src/arch/ppc64/include/arch/exception.h
View file
File renamed without changes.
0 src/arch/power8/include/arch/header.ld → src/arch/ppc64/include/arch/header.ld
View file
File renamed without changes.
0 src/arch/power8/include/arch/hlt.h → src/arch/ppc64/include/arch/hlt.h
View file
File renamed without changes.
0 src/arch/power8/include/arch/io.h → src/arch/ppc64/include/arch/io.h
View file
File renamed without changes.
0 src/arch/power8/include/arch/memlayout.h → src/arch/ppc64/include/arch/memlayout.h
View file
File renamed without changes.
0 src/arch/power8/include/arch/stages.h → src/arch/ppc64/include/arch/stages.h
View file
File renamed without changes.
6 changes: 3 additions & 3 deletions src/arch/power8/include/stdint.h → src/arch/ppc64/include/stdint.h
View file
Expand Up @@ -11,8 +11,8 @@
* GNU General Public License for more details.
*/

#ifndef POWER8_STDINT_H
#define POWER8_STDINT_H
#ifndef PPC64_STDINT_H
#define PPC64_STDINT_H

/* Exact integral types */
typedef unsigned char uint8_t;
Expand Down Expand Up @@ -73,4 +73,4 @@ typedef uint8_t bool;
typedef s64 intptr_t;
typedef u64 uintptr_t;

#endif /* POWER8_STDINT_H */
#endif /* PPC64_STDINT_H */
0 src/arch/power8/misc.c → src/arch/ppc64/misc.c
View file
File renamed without changes.
0 src/arch/power8/prologue.inc → src/arch/ppc64/prologue.inc
View file
File renamed without changes.
0 src/arch/power8/rom_media.c → src/arch/ppc64/rom_media.c
View file
File renamed without changes.
0 src/arch/power8/stages.c → src/arch/ppc64/stages.c
View file
File renamed without changes.
0 src/arch/power8/tables.c → src/arch/ppc64/tables.c
View file
File renamed without changes.
3 changes: 0 additions & 3 deletions src/arch/riscv/Kconfig
View file
Expand Up @@ -33,8 +33,5 @@ config RISCV_USE_ARCH_TIMER
bool
default n

config RISCV_HART_NUM
int

config RISCV_WORKING_HARTID
int
2 changes: 2 additions & 0 deletions src/arch/riscv/include/sbi.h
View file
Expand Up @@ -26,6 +26,8 @@
#define SBI_REMOTE_SFENCE_VMA_ASID 7
#define SBI_SHUTDOWN 8

#define SBI_ENOSYS 38

#define IPI_SOFT 1
#define IPI_FENCE_I 2
#define IPI_SFENCE_VMA 4
Expand Down
2 changes: 1 addition & 1 deletion src/arch/riscv/sbi.c
View file
Expand Up @@ -113,7 +113,7 @@ void handle_sbi(trapframe *tf)
ret = send_ipi((uintptr_t *)arg0, IPI_SHUTDOWN);
break;
default:
ret = -38;
ret = -SBI_ENOSYS;
break;
}
tf->gpr[10] = ret;
Expand Down
9 changes: 6 additions & 3 deletions src/arch/riscv/smp.c
View file
Expand Up @@ -55,7 +55,7 @@ void smp_pause(int working_hartid)
/* waiting for other Hart to enter the halt */
do {
barrier();
} while (SYNCB + 1 < CONFIG_RISCV_HART_NUM);
} while (SYNCB + 1 < CONFIG_MAX_CPUS);

/* initialize for the next call */
SYNCA = 0;
Expand All @@ -72,14 +72,17 @@ void smp_resume(void (*fn)(void *), void *arg)
if (fn == NULL)
die("must pass a non-null function pointer\n");

for (int i = 0; i < CONFIG_RISCV_HART_NUM; i++) {
for (int i = 0; i < CONFIG_MAX_CPUS; i++) {
OTHER_HLS(i)->entry.fn = fn;
OTHER_HLS(i)->entry.arg = arg;
}

for (int i = 0; i < CONFIG_RISCV_HART_NUM; i++)
for (int i = 0; i < CONFIG_MAX_CPUS; i++)
if (i != hartid)
set_msip(i, 1);

if (HLS()->entry.fn == NULL)
die("entry fn not set\n");

HLS()->entry.fn(HLS()->entry.arg);
}
14 changes: 2 additions & 12 deletions src/arch/riscv/virtual_memory.c
View file
Expand Up @@ -40,11 +40,6 @@ static int delegate = 0

void mstatus_init(void)
{
uintptr_t ms = 0;

ms = INSERT_FIELD(ms, MSTATUS_FS, 3);
write_csr(mstatus, ms);

// clear any pending timer interrupts.
clear_csr(mip, MIP_STIP | MIP_SSIP);

Expand All @@ -59,11 +54,6 @@ void mstatus_init(void)
set_csr(medeleg, delegate);
}

// Enable all user/supervisor-mode counters using
// v1.10 register addresses.
// They moved from the earlier spec.
// Until we trust our toolchain use the hardcoded constants.
// These were in flux and people who get the older toolchain
// will have difficult-to-debug failures.
write_csr(/*mcounteren*/0x306, 7);
// Enable all user/supervisor-mode counters
write_csr(mcounteren, 7);
}
14 changes: 1 addition & 13 deletions src/arch/x86/Kconfig
View file
Expand Up @@ -129,18 +129,6 @@ config CBMEM_TOP_BACKUP
Platform implements non-volatile storage to cache cbmem_top()
over stage transitions and optionally also over S3 suspend.

config LATE_CBMEM_INIT
def_bool n
select CBMEM_TOP_BACKUP
help
Enable this in chipset's Kconfig if northbridge does not implement
early cbmem_top() call for romstage. CBMEM tables will be allocated
late in ramstage, after PCI devices resources are known.

WARNING: Late CBMEM initialization is deprecated. Platforms that
don't support early CBMEM initialization will be removed after
the release of coreboot 4.7.

config PRERAM_CBMEM_CONSOLE_SIZE
hex
default 0xc00
Expand Down Expand Up @@ -275,7 +263,7 @@ config SKIP_MAX_REBOOT_CNT_CLEAR
Do not clear the reboot count immediately after successful boot.
Set to allow the payload to control normal/fallback image recovery.
Note that it is the responsibility of the payload to reset the
normal boot bit to 1 after each successsful boot.
normal boot bit to 1 after each successful boot.

config ACPI_CPU_STRING
string
Expand Down
10 changes: 5 additions & 5 deletions src/arch/x86/Makefile.inc
View file
Expand Up @@ -122,6 +122,8 @@ else
$(eval $(call early_x86_stage,bootblock,elf64-x86-64))
endif

bootblock-y += walkcbfs.S

else # !C_ENVIRONMENT_BOOTBLOCK

# x86-specific linker flags
Expand All @@ -143,7 +145,7 @@ $(call src-to-obj,bootblock,$(dir)/bootblock.ld): $(objgenerated)/bootblock.ld

bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
ifeq ($(CONFIG_SSE),y)
bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
bootblock_romccflags := -mcpu=k7 -mno-mmx -msse -O2 -D__PRE_RAM__ -D__BOOTBLOCK__
endif

# This is a hack in case there are no per chipset linker files.
Expand Down Expand Up @@ -233,6 +235,7 @@ romstage-y += memset.c
romstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
romstage-y += postcar_loader.c
romstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c
romstage-y += walkcbfs.S

romstage-srcs += $(wildcard $(src)/mainboard/$(MAINBOARDDIR)/romstage.c)
romstage-libs ?=
Expand Down Expand Up @@ -378,9 +381,6 @@ ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/smihandler.c),)
smm-srcs += src/mainboard/$(MAINBOARDDIR)/smihandler.c
endif
endif
ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/get_bus_conf.c),)
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/get_bus_conf.c
endif

ramstage-libs ?=

Expand All @@ -398,7 +398,7 @@ $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(call src-to-obj,ramstage

$(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs)
@printf " CC $(subst $(obj)/,,$(@))\n"
ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
$(LD_ramstage) -m elf_i386 -r -o $@ $(COMPILER_RT_FLAGS_ramstage) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) $(ramstage-libs) --no-whole-archive $(COMPILER_RT_ramstage) --end-group
else
$(LD_ramstage) -m elf_x86_64 -r -o $@ $(COMPILER_RT_FLAGS_ramstage) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) $(ramstage-libs) --no-whole-archive $(COMPILER_RT_ramstage) --end-group
Expand Down
39 changes: 39 additions & 0 deletions src/arch/x86/acpi.c
View file
Expand Up @@ -308,12 +308,47 @@ static void acpi_create_tcpa(acpi_tcpa_t *tcpa)
header->checksum = acpi_checksum((void *)tcpa, header->length);
}

static void *get_tpm2_log(u32 *size)
{
const struct cbmem_entry *ce;
const u32 tpm2_default_log_len = 0x10000;
void *lasa;
ce = cbmem_entry_find(CBMEM_ID_TPM2_TCG_LOG);
if (ce) {
lasa = cbmem_entry_start(ce);
*size = cbmem_entry_size(ce);
printk(BIOS_DEBUG, "TPM2 log found at %p\n", lasa);
return lasa;
}
lasa = cbmem_add(CBMEM_ID_TPM2_TCG_LOG, tpm2_default_log_len);
if (!lasa) {
printk(BIOS_ERR, "TPM2 log creation failed\n");
return NULL;
}

printk(BIOS_DEBUG, "TPM2 log created at %p\n", lasa);
memset(lasa, 0, tpm2_default_log_len);

*size = tpm2_default_log_len;
return lasa;
}

static void acpi_create_tpm2(acpi_tpm2_t *tpm2)
{
acpi_header_t *header = &(tpm2->header);
u32 tpm2_log_len;
void *lasa;

memset((void *)tpm2, 0, sizeof(acpi_tpm2_t));

/*
* Some payloads like SeaBIOS depend on log area to use TPM2.
* Get the memory size and address of TPM2 log area or initialize it.
*/
lasa = get_tpm2_log(&tpm2_log_len);
if (!lasa)
tpm2_log_len = 0;

/* Fill out header fields. */
memcpy(header->signature, "TPM2", 4);
memcpy(header->oem_id, OEM_ID, 6);
Expand All @@ -331,6 +366,10 @@ static void acpi_create_tpm2(acpi_tpm2_t *tpm2)
tpm2->start_method = 6;
memset(tpm2->msp, 0, sizeof(tpm2->msp));

/* Fill the log area size and start address fields. */
tpm2->laml = tpm2_log_len;
tpm2->lasa = (uintptr_t) lasa;

/* Calculate checksum. */
header->checksum = acpi_checksum((void *)tpm2, header->length);
}
Expand Down
5 changes: 3 additions & 2 deletions src/arch/x86/acpi/debug.asl
View file
Expand Up @@ -14,12 +14,13 @@
*/

/*
#include <arch/acpi.h>
DefinitionBlock (
"DSDT.AML",
"DSDT",
0x01,
"XXXXXX",
"XXXXXXXX",
OEM_ID,
ACPI_TABLE_CREATOR,
0x00010001
)
{
Expand Down
17 changes: 10 additions & 7 deletions src/arch/x86/acpi_pld.c
View file
Expand Up @@ -18,7 +18,8 @@
#include <arch/acpi.h>
#include <arch/acpi_pld.h>

int acpi_pld_fill_usb(struct acpi_pld *pld, enum acpi_upc_type type)
int acpi_pld_fill_usb(struct acpi_pld *pld, enum acpi_upc_type type,
struct acpi_pld_group *group)
{
if (!pld)
return -1;
Expand All @@ -32,6 +33,8 @@ int acpi_pld_fill_usb(struct acpi_pld *pld, enum acpi_upc_type type)
pld->horizontal_position = PLD_HORIZONTAL_POSITION_CENTER;
pld->rotation = PLD_ROTATE_0;
pld->visible = 1;
pld->group.token = group->token;
pld->group.position = group->position;

/* Set the shape based on port type */
switch (type) {
Expand Down Expand Up @@ -114,16 +117,16 @@ int acpi_pld_to_buffer(const struct acpi_pld *pld, uint8_t *buf, int buf_len)
/* [77:74] Shape */
buf[9] |= (pld->shape & 0xf) << 2;

/* [78] Group Orientation */
buf[9] |= (pld->group_orientation & 0x1) << 6;
/* [78] Orientation */
buf[9] |= (pld->orientation & 0x1) << 6;

/* [86:79] Group Token (incorrectly defined as 1 bit in ACPI 6.2A) */
buf[9] |= (pld->group_token & 0x1) << 7;
buf[10] |= (pld->group_token >> 0x1) & 0x7f;
buf[9] |= (pld->group.token & 0x1) << 7;
buf[10] |= (pld->group.token >> 0x1) & 0x7f;

/* [94:87] Group Position */
buf[10] |= (pld->group_position & 0x1) << 7;
buf[11] |= (pld->group_position >> 0x1) & 0x7f;
buf[10] |= (pld->group.position & 0x1) << 7;
buf[11] |= (pld->group.position >> 0x1) & 0x7f;

/* [95] Bay */
buf[11] |= (pld->bay & 0x1) << 7;
Expand Down
17 changes: 17 additions & 0 deletions src/arch/x86/acpigen.c
View file
Expand Up @@ -369,6 +369,23 @@ void acpigen_write_processor_package(const char *const name,
acpigen_pop_len();
}

/* Method to notify all CPU cores */
void acpigen_write_processor_cnot(const unsigned int number_of_cores)
{
int core_id;

acpigen_write_method("\\_PR.CNOT", 1);
for (core_id = 0; core_id < number_of_cores; core_id++) {
char buffer[DEVICE_PATH_MAX];
snprintf(buffer, sizeof(buffer), CONFIG_ACPI_CPU_STRING,
core_id);
acpigen_emit_byte(NOTIFY_OP);
acpigen_emit_namestring(buffer);
acpigen_emit_byte(ARG0_OP);
}
acpigen_pop_len();
}

/*
* Generate ACPI AML code for OperationRegion
* Arg0: Pointer to struct opregion opreg = OPREGION(rname, space, offset, len)
Expand Down
1 change: 0 additions & 1 deletion src/arch/x86/boot.c
View file
Expand Up @@ -13,7 +13,6 @@

#include <commonlib/helpers.h>
#include <console/console.h>
#include <arch/stages.h>
#include <program_loading.h>
#include <ip_checksum.h>
#include <string.h>
Expand Down
15 changes: 3 additions & 12 deletions src/arch/x86/bootblock_crt0.S
View file
Expand Up @@ -44,23 +44,14 @@ debug_spinloop:

bootblock_protected_mode_entry:

#if !IS_ENABLED(CONFIG_USE_MARCH_586)
/* MMX registers required here */

/* BIST result in eax */
movl %eax, %ebx

/* Get an early timestamp */
rdtsc

#if IS_ENABLED(CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP)
lea 1f, %ebp

/* eax: Low 32-bits of timestamp
* ebx: BIST result
* ebp: return address
* edx: High 32-bits of timestamp
*/
jmp bootblock_save_bist_and_timestamp
1:
#else
movd %ebx, %mm0
movd %eax, %mm1
movd %edx, %mm2
Expand Down
6 changes: 2 additions & 4 deletions src/arch/x86/bootblock_romcc.S
View file
Expand Up @@ -19,7 +19,7 @@
* - reset16.inc: the reset vector
* - entry16.inc: protected mode setup
* - entry32.inc: segment descriptor setup
* - CONFIG_CHIPSET_BOOTBLOCK_INCLUDE: chipset-specific initialization
* - timestamp.inc: store TSC in MMX registers
* - generated/bootblock.inc: ROMCC part of the bootblock
*
* This is used on platforms which do not select C_ENVIRONMENT_BOOTBLOCK, and it
Expand All @@ -35,9 +35,7 @@
#include <cpu/x86/16bit/reset16.inc>
#include <cpu/x86/32bit/entry32.inc>

#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
#endif
#include <arch/x86/timestamp.inc>

#if IS_ENABLED(CONFIG_SSE)
#include <cpu/x86/sse_enable.inc>
Expand Down
12 changes: 6 additions & 6 deletions src/arch/x86/c_start.S
View file
Expand Up @@ -49,8 +49,8 @@ _start:
movl %eax, %fs
movl %eax, %gs
#ifdef __x86_64__
mov $0x48, %ecx
call SetCodeSelector
mov $0x48, %ecx
call SetCodeSelector
#endif

post_code(POST_ENTRY_C_START) /* post 13 */
Expand Down Expand Up @@ -177,12 +177,12 @@ gdt:
/* The next two entries are used for executing VGA option ROMs */

/* selgdt 0x28 16 bit 64k code at 0x00000000 */
.word 0xffff, 0x0000
.byte 0, 0x9a, 0, 0
.word 0xffff, 0x0000
.byte 0, 0x9a, 0, 0

/* selgdt 0x30 16 bit 64k data at 0x00000000 */
.word 0xffff, 0x0000
.byte 0, 0x92, 0, 0
.word 0xffff, 0x0000
.byte 0, 0x92, 0, 0

/* The next two entries are used for ACPI S3 RESUME */

Expand Down
15 changes: 11 additions & 4 deletions src/arch/x86/car.ld
View file
Expand Up @@ -40,10 +40,10 @@
_car_stack_end = .;
#endif
/* The pre-ram cbmem console as well as the timestamp region are fixed
* in size. Therefore place them at the beginning .car.data section
* so that multiple stages (romstage and verstage) have a consistent
* link address of these shared objects. */
PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : CONFIG_PRERAM_CBMEM_CONSOLE_SIZE))
* in size. Therefore place them above the car global section so that
* multiple stages (romstage and verstage) have a consistent
* link address of these shared objects. */
PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE)
#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM)
. = ALIGN(32);
/* Page directory pointer table resides here. There are 4 8-byte entries
Expand All @@ -66,6 +66,9 @@
. += 256;
_car_drivers_storage_end = .;
#endif
_car_ehci_dbg_info_start = .;
. += 64;
_car_ehci_dbg_info_end = .;
/* _car_global_start and _car_global_end provide symbols to per-stage
* variables that are not shared like the timestamp and the pre-ram
* cbmem console. This is useful for clearing this area on a per-stage
Expand All @@ -86,6 +89,10 @@
_car_global_end = .;
_car_relocatable_data_end = .;

#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
_car_stack_start = .;
_car_stack_end = _car_region_end;
#endif
_car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start);
}

Expand Down
44 changes: 6 additions & 38 deletions src/arch/x86/cbmem.c
View file
Expand Up @@ -15,55 +15,23 @@
#include <cbmem.h>
#include <arch/acpi.h>

#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)

void __weak backup_top_of_low_cacheable(uintptr_t ramtop)
{
/* Do nothing. Chipset may have implementation to save ramtop in NVRAM.
*/
}

uintptr_t __weak restore_top_of_low_cacheable(void)
{
return 0;
}

#endif /* LATE_CBMEM_INIT */

#if IS_ENABLED(CONFIG_CBMEM_TOP_BACKUP)

static void *cbmem_top_backup;

void set_late_cbmem_top(uintptr_t ramtop)
{
backup_top_of_low_cacheable(ramtop);
if (ENV_RAMSTAGE)
cbmem_top_backup = (void *)ramtop;
}

/* Top of CBMEM is at highest usable DRAM address below 4GiB. */
uintptr_t __weak restore_cbmem_top(void)
{
if (IS_ENABLED(CONFIG_LATE_CBMEM_INIT) && ENV_ROMSTAGE)
if (!acpi_is_wakeup_s3())
return 0;

return restore_top_of_low_cacheable();
}

void *cbmem_top(void)
{
uintptr_t top_backup;
static void *cbmem_top_backup;
void *top_backup;

if (ENV_RAMSTAGE && cbmem_top_backup != NULL)
return cbmem_top_backup;

top_backup = restore_cbmem_top();
/* Top of CBMEM is at highest usable DRAM address below 4GiB. */
top_backup = (void *)restore_top_of_low_cacheable();

if (ENV_RAMSTAGE)
cbmem_top_backup = (void *)top_backup;
cbmem_top_backup = top_backup;

return (void *)top_backup;
return top_backup;
}

#endif /* CBMEM_TOP_BACKUP */
Expand Down
2 changes: 1 addition & 1 deletion src/arch/x86/cpu.c
View file
Expand Up @@ -183,7 +183,7 @@ static void identify_cpu(struct device *cpu)

/* Intel-defined flags: level 0x00000001 */
if (cpuid_level >= 0x00000001)
cpu->device = cpuid_eax(0x00000001);
cpu->device = cpu_get_cpuid();
else
/* Have CPUID level 0 only unheard of */
cpu->device = 0x00000400;
Expand Down
27 changes: 27 additions & 0 deletions src/arch/x86/cpu_common.c
View file
Expand Up @@ -66,3 +66,30 @@ int cpu_phys_address_size(void)
return 36;
return 32;
}

/*
* Get processor id using cpuid eax=1
* return value in EAX register
*/
uint32_t cpu_get_cpuid(void)
{
return cpuid_eax(1);
}

/*
* Get processor feature flag using cpuid eax=1
* return value in ECX register
*/
uint32_t cpu_get_feature_flags_ecx(void)
{
return cpuid_ecx(1);
}

/*
* Get processor feature flag using cpuid eax=1
* return value in EDX register
*/
uint32_t cpu_get_feature_flags_edx(void)
{
return cpuid_edx(1);
}
60 changes: 42 additions & 18 deletions src/arch/x86/include/arch/acpi.h
View file
Expand Up @@ -52,6 +52,9 @@
#define SLP_TYP_S5 5
#endif

#define ACPI_TABLE_CREATOR "COREBOOT" /* Must be exactly 8 bytes long! */
#define OEM_ID "COREv4" /* Must be exactly 6 bytes long! */

#if !defined(__ASSEMBLER__) && !defined(__ACPI__) && !defined(__ROMCC__)
#include <stdint.h>
#include <rules.h>
Expand All @@ -61,8 +64,6 @@
#include <cper.h>

#define RSDP_SIG "RSD PTR " /* RSDT pointer signature */
#define ACPI_TABLE_CREATOR "COREBOOT" /* Must be exactly 8 bytes long! */
#define OEM_ID "CORE " /* Must be exactly 6 bytes long! */
#define ASLC "CORE" /* Must be exactly 4 bytes long! */

/*
Expand Down Expand Up @@ -94,7 +95,7 @@ typedef struct acpi_rsdp {
char signature[8]; /* RSDP signature */
u8 checksum; /* Checksum of the first 20 bytes */
char oem_id[6]; /* OEM ID */
u8 revision; /* 0 for ACPI 1.0, 2 for ACPI 2.0/3.0/4.0 */
u8 revision; /* 0 for ACPI 1.0, 2 for ACPI 2.0/3.0/4.0/6.2a */
u32 rsdt_address; /* Physical address of RSDT (32 bits) */
u32 length; /* Total RSDP length (incl. extended part) */
u64 xsdt_address; /* Physical address of XSDT (64 bits) */
Expand All @@ -110,7 +111,8 @@ typedef struct acpi_gen_regaddr {
u8 bit_offset; /* Register bit offset */
union {
u8 resv; /* Reserved in ACPI 2.0 - 2.0b */
u8 access_size; /* Access size in ACPI 2.0c/3.0/4.0/5.0
u8 access_size; /* Access size in
* ACPI 2.0c/3.0/4.0/5.0/6.2a
*/
};
u32 addrl; /* Register address, low 32 bits */
Expand Down Expand Up @@ -198,6 +200,8 @@ typedef struct acpi_tpm2 {
u64 control_area;
u32 start_method;
u8 msp[12];
u32 laml;
u64 lasa;
} __packed acpi_tpm2_t;

typedef struct acpi_mcfg_mmconfig {
Expand Down Expand Up @@ -226,7 +230,7 @@ typedef struct acpi_srat_lapic {
u32 flags; /* Enable bit 0 = 1, other bits reserved to 0 */
u8 local_sapic_eid; /* Local SAPIC EID */
u8 proximity_domain_31_8[3]; /* Proximity domain bits[31:8] */
u32 resv; /* TODO: Clock domain in ACPI 4.0. */
u32 clock_domain; /* _CDM Clock Domain */
} __packed acpi_srat_lapic_t;

/* SRAT: Memory Affinity Structure */
Expand Down Expand Up @@ -313,7 +317,8 @@ enum dev_scope_type {
SCOPE_PCI_ENDPOINT = 1,
SCOPE_PCI_SUB = 2,
SCOPE_IOAPIC = 3,
SCOPE_MSI_HPET = 4
SCOPE_MSI_HPET = 4,
SCOPE_ACPI_NAMESPACE_DEVICE = 5
};

typedef struct dev_scope {
Expand All @@ -332,16 +337,18 @@ enum dmar_type {
DMAR_DRHD = 0,
DMAR_RMRR = 1,
DMAR_ATSR = 2,
DMAR_RHSA = 3
DMAR_RHSA = 3,
DMAR_ANDD = 4
};

enum {
DRHD_INCLUDE_PCI_ALL = 1
};

enum dmar_flags {
DMAR_INTR_REMAP = 1,
DMAR_X2APIC_OPT_OUT = 2,
DMAR_INTR_REMAP = 1,
DMAR_X2APIC_OPT_OUT = 2,
DMA_CTRL_PLATFORM_OPT_IN_FLAG = 3,
};

typedef struct dmar_entry {
Expand Down Expand Up @@ -393,7 +400,12 @@ enum acpi_apic_types {
PlatformIRQSources = 8, /* Platform interrupt sources */
Localx2Apic = 9, /* Processor local x2APIC */
Localx2ApicNMI = 10, /* Local x2APIC NMI */
/* 0x0b-0x7f: Reserved */
GICC = 11, /* GIC CPU Interface */
GICD = 12, /* GIC Distributor */
GIC_MSI_FRAME = 13, /* GIC MSI Frame */
GICR = 14, /* GIC Redistributor */
GIC_ITS = 15, /* Interrupt Translation Service */
/* 0x10-0x7f: Reserved */
/* 0x80-0xff: Reserved for OEM use */
};

Expand Down Expand Up @@ -477,7 +489,11 @@ typedef struct acpi_fadt {
struct acpi_table_header header;
u32 firmware_ctrl;
u32 dsdt;
u8 model;
u8 model; /* Eliminated in ACPI 2.0. Platforms should set
* this field to zero but field values of one
* are also allowed to maintain compatibility
* with ACPI 1.0.
*/
u8 preferred_pm_profile;
u16 sci_int;
u32 smi_cmd;
Expand Down Expand Up @@ -515,9 +531,8 @@ typedef struct acpi_fadt {
u32 flags;
struct acpi_gen_regaddr reset_reg;
u8 reset_value;
u8 res3;
u8 res4;
u8 res5;
u16 ARM_boot_arch;
u8 FADT_MinorVersion;
u32 x_firmware_ctl_l;
u32 x_firmware_ctl_h;
u32 x_dsdt_l;
Expand All @@ -538,6 +553,7 @@ typedef struct acpi_fadt {
#define ACPI_FADT_REV_ACPI_3_0 4
#define ACPI_FADT_REV_ACPI_4_0 4
#define ACPI_FADT_REV_ACPI_5_0 5
#define ACPI_FADT_REV_ACPI_6_0 6

/* Flags for p_lvl2_lat and p_lvl3_lat */
#define ACPI_FADT_C2_NOT_SUPPORTED 101
Expand Down Expand Up @@ -567,16 +583,22 @@ typedef struct acpi_fadt {
/* Bits 20-31: reserved ACPI 3.0 & 4.0 */
#define ACPI_FADT_HW_REDUCED_ACPI (1 << 20)
#define ACPI_FADT_LOW_PWR_IDLE_S0 (1 << 21)
/* bits 22-31: reserved ACPI 5.0 */
/* bits 22-31: reserved ACPI 5.0/6.2a */

/* FADT Boot Architecture Flags */
#define ACPI_FADT_LEGACY_DEVICES (1 << 0)
#define ACPI_FADT_8042 (1 << 1)
#define ACPI_FADT_VGA_NOT_PRESENT (1 << 2)
#define ACPI_FADT_MSI_NOT_SUPPORTED (1 << 3)
#define ACPI_FADT_NO_PCIE_ASPM_CONTROL (1 << 4)
#define ACPI_FADT_NO_CMOS_RTC (1 << 5)
#define ACPI_FADT_LEGACY_FREE 0x00 /* No legacy devices (including 8042) */

/* FADT ARM Boot Architecture Flags */
#define ACPI_FADT_ARM_PSCI_COMPLIANT (1 << 0)
#define ACPI_FADT_ARM_PSCI_USE_HVC (1 << 1)
/* bits 2-16: reserved ACPI 6.2a */

/* FADT Preferred Power Management Profile */
enum acpi_preferred_pm_profiles {
PM_UNSPECIFIED = 0,
Expand All @@ -587,7 +609,7 @@ enum acpi_preferred_pm_profiles {
PM_SOHO_SERVER = 5,
PM_APPLIANCE_PC = 6,
PM_PERFORMANCE_SERVER = 7,
PM_TABLET = 8, /* ACPI 5.0 */
PM_TABLET = 8, /* ACPI 5.0/6.2a */
};

/* FACS (Firmware ACPI Control Structure) */
Expand All @@ -600,8 +622,10 @@ typedef struct acpi_facs {
u32 flags; /* FACS flags */
u32 x_firmware_waking_vector_l; /* X FW waking vector, low */
u32 x_firmware_waking_vector_h; /* X FW waking vector, high */
u8 version; /* ACPI 4.0: 2 */
u8 resv[31]; /* FIXME: 4.0: ospm_flags */
u8 version; /* ACPI 6.2-A: 2 */
u8 resv1[3]; /* ACPI 6.2-A: 0 */
u32 ospm_flags; /* 64BIT_WAKE_F */
u8 resv2[24]; /* ACPI 6.2-A: 0 */
} __packed acpi_facs_t;

/* FACS flags */
Expand Down
19 changes: 15 additions & 4 deletions src/arch/x86/include/arch/acpi_pld.h
View file
Expand Up @@ -75,6 +75,17 @@ enum acpi_pld_rotate {
PLD_ROTATE_315
};

#define ACPI_PLD_GROUP(__token, __position) \
{ \
.token = __token, \
.position = __position, \
}

struct acpi_pld_group {
uint8_t token;
uint8_t position;
};

struct acpi_pld {
/* Color field can be explicitly ignored */
bool ignore_color;
Expand All @@ -100,9 +111,8 @@ struct acpi_pld {
enum acpi_pld_rotate rotation;

/* Port grouping */
enum acpi_pld_orientation group_orientation;
uint8_t group_token;
uint8_t group_position;
enum acpi_pld_orientation orientation;
struct acpi_pld_group group;
uint8_t draw_order;
uint8_t cabinet_number;
uint8_t card_cage_number;
Expand All @@ -112,7 +122,8 @@ struct acpi_pld {
};

/* Fill out PLD structure with defaults based on USB port type */
int acpi_pld_fill_usb(struct acpi_pld *pld, enum acpi_upc_type type);
int acpi_pld_fill_usb(struct acpi_pld *pld, enum acpi_upc_type type,
struct acpi_pld_group *group);

/* Turn PLD structure into a 20 byte ACPI buffer */
int acpi_pld_to_buffer(const struct acpi_pld *pld, uint8_t *buf, int buf_len);
Expand Down
1 change: 1 addition & 0 deletions src/arch/x86/include/arch/acpigen.h
View file
Expand Up @@ -277,6 +277,7 @@ void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len);
void acpigen_write_processor_package(const char *name,
unsigned int first_core,
unsigned int core_count);
void acpigen_write_processor_cnot(const unsigned int number_of_cores);
void acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list);
void acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype);
void acpigen_write_mem32fixed(int readwrite, u32 base, u32 size);
Expand Down
23 changes: 18 additions & 5 deletions src/arch/x86/include/arch/cpu.h
View file
Expand Up @@ -270,11 +270,6 @@ struct postcar_frame {
*/
int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size);

/*
* Initialize postcar_frame object with a fixed stacktop in low memory.
*/
void postcar_frame_init_lowmem(struct postcar_frame *pcf);

/*
* Add variable MTRR covering the provided range with MTRR type.
*/
Expand Down Expand Up @@ -311,4 +306,22 @@ void late_car_teardown(void);

#endif

/*
* Get processor id using cpuid eax=1
* return value in EAX register
*/
uint32_t cpu_get_cpuid(void);

/*
* Get processor feature flag using cpuid eax=1
* return value in ECX register
*/
uint32_t cpu_get_feature_flags_ecx(void);

/*
* Get processor feature flag using cpuid eax=1
* return value in EDX register
*/
uint32_t cpu_get_feature_flags_edx(void);

#endif /* ARCH_CPU_H */
10 changes: 1 addition & 9 deletions src/arch/x86/include/arch/io.h
View file
Expand Up @@ -17,11 +17,7 @@
#include <endian.h>
#include <stdint.h>
#include <rules.h>

/* FIXME: Sources for romstage still use device_t. */
/* Use pci_devfn_t or pnp_devfn_t instead */
typedef u32 pci_devfn_t;
typedef u32 pnp_devfn_t;
#include <device/pci_type.h>

/*
* This file contains the definitions for the x86 IO instructions
Expand Down Expand Up @@ -256,10 +252,6 @@ static inline int __ffs(u32 value)

#define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC))

/* FIXME: Sources for romstage still use device_t. */
/* Use pci_devfn_t or pnp_devfn_t instead */
typedef u32 device_t;

/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write
* memory above 4G, We don't need to set %fs, and %gs anymore
* Before that We need to use %gs, and leave %fs to other RAM access
Expand Down
2 changes: 2 additions & 0 deletions src/arch/x86/include/arch/symbols.h
View file
Expand Up @@ -34,6 +34,8 @@ extern char _car_stack_start[];
extern char _car_stack_end[];
#define _car_stack_size (_car_stack_end - _car_stack_start)

extern char _car_ehci_dbg_info_start[];

/*
* The _car_relocatable_data_[start|end] symbols cover CAR data which is
* relocatable once memory comes online. Variables with CAR_GLOBAL decoration
Expand Down
12 changes: 0 additions & 12 deletions src/arch/x86/include/stdint.h
View file
Expand Up @@ -99,23 +99,11 @@ typedef uint8_t bool;
# define UINT64_MAX (18446744073709551615ULL)
#endif

#ifdef __x86_64__

#ifndef UINT64_C
#define UINT64_C(c) c ## UL
#endif
#ifndef PRIu64
#define PRIu64 "lu"
#endif

#else

#ifndef UINT64_C
#define UINT64_C(c) c ## ULL
#endif
#ifndef PRIu64
#define PRIu64 "llu"
#endif

#endif

Expand Down
41 changes: 0 additions & 41 deletions src/arch/x86/mmap_boot.c
View file
Expand Up @@ -28,44 +28,3 @@ const struct region_device *boot_device_ro(void)
{
return &boot_dev.rdev;
}

static int cbfs_master_header_props(struct cbfs_props *props)
{
struct cbfs_header header;
int32_t offset;
const struct region_device *bdev;

bdev = boot_device_ro();

rdev_readat(bdev, &offset, CONFIG_ROM_SIZE - sizeof(offset),
sizeof(offset));

/* The offset is relative to the end of the media. */
offset += CONFIG_ROM_SIZE;

rdev_readat(bdev, &header, offset, sizeof(header));

header.magic = ntohl(header.magic);
header.romsize = ntohl(header.romsize);
header.bootblocksize = ntohl(header.bootblocksize);
header.offset = ntohl(header.offset);

if (header.magic != CBFS_HEADER_MAGIC)
return -1;

props->offset = header.offset;
if (header.romsize != CONFIG_ROM_SIZE)
props->size = CONFIG_ROM_SIZE;
else
props->size = header.romsize;
props->size -= props->offset;
props->size -= header.bootblocksize;
props->size = ALIGN_DOWN(props->size, 64);

return 0;
}

const struct cbfs_locator cbfs_master_header_locator = {
.name = "Master Header Locator",
.locate = cbfs_master_header_props,
};
6 changes: 2 additions & 4 deletions src/arch/x86/mpspec.c
View file
Expand Up @@ -161,14 +161,12 @@ void smp_write_processors(struct mp_config_table *mc)
unsigned int apic_version;
unsigned int cpu_features;
unsigned int cpu_feature_flags;
struct cpuid_result result;
struct device *cpu;

boot_apic_id = lapicid();
apic_version = lapic_read(LAPIC_LVR) & 0xff;
result = cpuid(1);
cpu_features = result.eax;
cpu_feature_flags = result.edx;
cpu_features = cpu_get_cpuid();
cpu_feature_flags = cpu_get_feature_flags_edx();
/* order the output of the cpus to fix a bug in kernel 2.6.11 */
for (order_id = 0; order_id < 256; order_id++) {
for (cpu = all_devices; cpu; cpu = cpu->next) {
Expand Down
6 changes: 2 additions & 4 deletions src/arch/x86/postcar.c
View file
Expand Up @@ -16,9 +16,9 @@
#include <arch/cpu.h>
#include <cbmem.h>
#include <console/console.h>
#include <cpu/x86/mtrr.h>
#include <main_decl.h>
#include <program_loading.h>
#include <soc/intel/common/util.h>

/*
* Systems without a native coreboot cache-as-ram teardown may implement
Expand All @@ -35,9 +35,7 @@ void main(void)
/* Recover cbmem so infrastruture using it is functional. */
cbmem_initialize();

/* Display the MTRRs */
if (IS_ENABLED(CONFIG_DISPLAY_MTRRS))
soc_display_mtrrs();
display_mtrrs();

/* Load and run ramstage. */
run_ramstage();
Expand Down
10 changes: 0 additions & 10 deletions src/arch/x86/postcar_loader.c
View file
Expand Up @@ -60,16 +60,6 @@ int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size)
return 0;
}

/*
* For use with LATE_CBMEM_INIT boards only, with a fixed stacktop in
* low memory.
*/
void postcar_frame_init_lowmem(struct postcar_frame *pcf)
{
postcar_frame_prepare(pcf);
pcf->stack = CONFIG_RAMTOP;
}

void postcar_frame_add_mtrr(struct postcar_frame *pcf,
uintptr_t addr, size_t size, int type)
{
Expand Down
13 changes: 7 additions & 6 deletions ...oc/intel/baytrail/bootblock/timestamp.inc → src/arch/x86/timestamp.inc
View file
Expand Up @@ -13,21 +13,22 @@

/*
* Store the initial timestamp for booting in mmx registers. This works
* because the bootblock isn't being compiled with MMX support so mm0 and
* mm1 will be preserved into romstage.
* because the bootblock isn't being compiled with MMX support so mm1 and
* mm2 will be preserved into romstage.
*/
.code32

.global stash_timestamp
stash_timestamp:

/* Save the BIST value */
movl %eax, %ebp
movl %eax, %ebx

finit
rdtsc
movd %eax, %mm0
movd %edx, %mm1
movd %ebx, %mm0
movd %eax, %mm1
movd %edx, %mm2

/* Restore the BIST value to %eax */
movl %ebp, %eax
movl %ebx, %eax
28 changes: 14 additions & 14 deletions src/arch/x86/wakeup.S
View file
Expand Up @@ -29,29 +29,29 @@
.globl __wakeup
__wakeup:
#ifdef __x86_64__
xor %rax,%rax
mov %ss, %ax
push %rax
mov %rsp, %rax
add $8, %rax
push %rax
xor %rax,%rax
mov %ss, %ax
push %rax
mov %rsp, %rax
add $8, %rax
push %rax
pushfq
push $0x10
lea 3(%rip), %rax
push %rax
push $0x10
lea 3(%rip), %rax
push %rax
iretq

.code32

/* disable paging */
mov %cr0, %eax
btc $31, %eax
mov %eax, %cr0
mov %cr0, %eax
btc $31, %eax
mov %eax, %cr0

/* disable long mode */
mov $0xC0000080, %ecx
mov $0xC0000080, %ecx
rdmsr
btc $8, %eax
btc $8, %eax
wrmsr
#endif
/* First prepare the jmp to the resume vector */
Expand Down
2 changes: 1 addition & 1 deletion src/commonlib/fsp_relocate.c
View file
Expand Up @@ -19,7 +19,7 @@
/*
* Intel's code does not have a handle on changing global packing state.
* Therefore, one needs to protect against packing policies that are set
* globally for a compliation unit just by including a header file.
* globally for a compilation unit just by including a header file.
*/
#pragma pack(push)

Expand Down
2 changes: 2 additions & 0 deletions src/commonlib/include/commonlib/cbmem_id.h
View file
Expand Up @@ -65,6 +65,7 @@
#define CBMEM_ID_TCPA_LOG 0x54435041
#define CBMEM_ID_TCPA_TCG_LOG 0x54445041
#define CBMEM_ID_TIMESTAMP 0x54494d45
#define CBMEM_ID_TPM2_TCG_LOG 0x54504d32
#define CBMEM_ID_VBOOT_HANDOFF 0x780074f0
#define CBMEM_ID_VBOOT_SEL_REG 0x780074f1
#define CBMEM_ID_VBOOT_WORKBUF 0x78007343
Expand Down Expand Up @@ -121,6 +122,7 @@
{ CBMEM_ID_TCPA_LOG, "TCPA LOG " }, \
{ CBMEM_ID_TCPA_TCG_LOG, "TCPA TCGLOG" }, \
{ CBMEM_ID_TIMESTAMP, "TIME STAMP " }, \
{ CBMEM_ID_TPM2_TCG_LOG, "TPM2 TCGLOG" }, \
{ CBMEM_ID_VBOOT_HANDOFF, "VBOOT " }, \
{ CBMEM_ID_VBOOT_SEL_REG, "VBOOT SEL " }, \
{ CBMEM_ID_VBOOT_WORKBUF, "VBOOT WORK " }, \
Expand Down
1 change: 0 additions & 1 deletion src/commonlib/include/commonlib/helpers.h
View file
Expand Up @@ -36,7 +36,6 @@
#define MAX(a, b) ((a) > (b) ? (a) : (b))
#endif
#define ABS(a) (((a) < 0) ? (-(a)) : (a))
#define CEIL_DIV(a, b) (((a) + (b) - 1) / (b))
#define IS_POWER_OF_2(x) (((x) & ((x) - 1)) == 0)
#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y))
/*
Expand Down
11 changes: 5 additions & 6 deletions src/console/init.c
View file
Expand Up @@ -35,8 +35,7 @@ static int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;

static inline int get_log_level(void)
{
if (!IS_ENABLED(CONFIG_LATE_CBMEM_INIT) &&
car_get_var(console_inited) == 0)
if (car_get_var(console_inited) == 0)
return -1;
if (CONSOLE_LEVEL_CONST)
return get_console_loglevel();
Expand Down Expand Up @@ -73,14 +72,14 @@ asmlinkage void console_init(void)
{
init_log_level();

#if IS_ENABLED(CONFIG_EARLY_PCI_BRIDGE) && !defined(__SMM__)
pci_early_bridge_init();
#if IS_ENABLED(CONFIG_EARLY_PCI_BRIDGE)
if (!ENV_SMM && !ENV_RAMSTAGE)
pci_early_bridge_init();
#endif

console_hw_init();

if (!IS_ENABLED(CONFIG_LATE_CBMEM_INIT))
car_set_var(console_inited, 1);
car_set_var(console_inited, 1);

printk(BIOS_NOTICE, "\n\ncoreboot-%s%s %s " ENV_STRING " starting...\n",
coreboot_version, coreboot_extra_version, coreboot_build);
Expand Down
6 changes: 3 additions & 3 deletions src/cpu/allwinner/a10/clock.c
View file
Expand Up @@ -247,9 +247,9 @@ void a1x_set_cpu_clock(u16 cpu_clk_mhz)
* will always be in spec, as long as AHB is in spec, although the max
* AHB0 clock we can get is 125 MHz
*/
axi = CEIL_DIV(actual_mhz, 450); /* Max 450 MHz */
ahb = CEIL_DIV(actual_mhz/axi, 250); /* Max 250 MHz */
apb0 = 2; /* Max 150 MHz */
axi = DIV_ROUND_UP(actual_mhz, 450); /* Max 450 MHz */
ahb = DIV_ROUND_UP(actual_mhz/axi, 250); /* Max 250 MHz */
apb0 = 2; /* Max 150 MHz */

ahb_exp = log2_ceil(ahb);
ahb = 1 << ahb_exp;
Expand Down
1 change: 0 additions & 1 deletion src/cpu/amd/Kconfig
View file
Expand Up @@ -7,7 +7,6 @@ source src/cpu/amd/socket_ASB2/Kconfig
source src/cpu/amd/socket_F_1207/Kconfig

source src/cpu/amd/family_10h-family_15h/Kconfig
source src/cpu/amd/geode_lx/Kconfig

source src/cpu/amd/agesa/Kconfig
source src/cpu/amd/pi/Kconfig
1 change: 0 additions & 1 deletion src/cpu/amd/Makefile.inc
View file
Expand Up @@ -5,7 +5,6 @@ subdirs-$(CONFIG_CPU_AMD_SOCKET_ASB2) += socket_ASB2
subdirs-$(CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA) += socket_C32
subdirs-$(CONFIG_CPU_AMD_SOCKET_FM2_NON_AGESA) += socket_FM2
subdirs-$(CONFIG_CPU_AMD_SOCKET_G34_NON_AGESA) += socket_G34
subdirs-$(CONFIG_CPU_AMD_GEODE_LX) += geode_lx

subdirs-$(CONFIG_CPU_AMD_AGESA) += agesa
subdirs-$(CONFIG_CPU_AMD_PI) += pi
1 change: 0 additions & 1 deletion src/cpu/amd/agesa/family12/model_12_init.c
View file
Expand Up @@ -21,7 +21,6 @@
#include <device/device.h>
#include <string.h>
#include <cpu/x86/pae.h>
#include <pc80/mc146818rtc.h>
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
Expand Down
1 change: 0 additions & 1 deletion src/cpu/amd/agesa/family14/model_14_init.c
View file
Expand Up @@ -21,7 +21,6 @@
#include <device/device.h>
#include <string.h>
#include <cpu/x86/pae.h>
#include <pc80/mc146818rtc.h>
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
Expand Down
1 change: 0 additions & 1 deletion src/cpu/amd/agesa/family15tn/model_15_init.c
View file
Expand Up @@ -22,7 +22,6 @@
#include <device/device.h>
#include <string.h>
#include <cpu/x86/pae.h>
#include <pc80/mc146818rtc.h>
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
Expand Down
1 change: 0 additions & 1 deletion src/cpu/amd/agesa/family16kb/model_16_init.c
View file
Expand Up @@ -21,7 +21,6 @@
#include <device/device.h>
#include <string.h>
#include <cpu/x86/pae.h>
#include <pc80/mc146818rtc.h>
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
Expand Down
1 change: 0 additions & 1 deletion src/cpu/amd/family_10h-family_15h/Kconfig
View file
Expand Up @@ -4,7 +4,6 @@ config CPU_AMD_MODEL_10XXX
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select SSE
select SSE2
select TSC_SYNC_LFENCE
select UDELAY_LAPIC
Expand Down
22 changes: 16 additions & 6 deletions src/cpu/amd/family_10h-family_15h/init_cpus.c
View file
Expand Up @@ -147,6 +147,9 @@ static void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node,
// here assume the OS don't change our apicid
u32 ap_apicid;

u8 nvram;
bool multicore;

u32 nodes;
u32 disable_siblings;
u32 cores_found;
Expand All @@ -155,12 +158,13 @@ static void for_each_ap(uint32_t bsp_apicid, uint32_t core_range, int8_t node,
/* get_nodes define in ht_wrapper.c */
nodes = get_nodes();

if (!IS_ENABLED(CONFIG_LOGICAL_CPUS) ||
read_option(multi_core, 0) != 0) { // 0 means multi core
multicore = true;
if (get_option(&nvram, "multi_core") == CB_SUCCESS)
multicore = !!nvram;

disable_siblings = 0;
if (!IS_ENABLED(CONFIG_LOGICAL_CPUS) || !multicore)
disable_siblings = 1;
} else {
disable_siblings = 0;
}

for (i = 0; i < nodes; i++) {
if ((node >= 0) && (i != node))
Expand Down Expand Up @@ -635,11 +639,17 @@ static void setup_remote_node(u8 node)
//it is running on core0 of node0
void start_other_cores(uint32_t bsp_apicid)
{
u8 nvram;
u32 nodes;
u32 nodeid;
bool multicore;

// disable multi_core
if (read_option(multi_core, 0) != 0) {
multicore = true;
if (get_option(&nvram, "multi_core") == CB_SUCCESS)
multicore = !!nvram;

if (!multicore) {
printk(BIOS_DEBUG, "Skip additional core init\n");
return;
}
Expand Down
10 changes: 6 additions & 4 deletions src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
View file
Expand Up @@ -24,7 +24,6 @@
#include <string.h>
#include <cpu/x86/smm.h>
#include <cpu/x86/pae.h>
#include <pc80/mc146818rtc.h>
#include <cpu/x86/lapic.h>
#include <northbridge/amd/amdfam10/amdfam10.h>
#include <cpu/amd/model_10xxx_rev.h>
Expand Down Expand Up @@ -143,7 +142,8 @@ static void model_10xxx_init(struct device *dev)
uint32_t f5x80;
uint8_t enabled;
uint8_t compute_unit_count = 0;
f5x80 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 5)), 0x80);
f5x80 = pci_read_config32(pcidev_on_root(0x18 + id.nodeid, 5),
0x80);
enabled = f5x80 & 0xf;
if (enabled == 0x1)
compute_unit_count = 1;
Expand All @@ -162,11 +162,13 @@ static void model_10xxx_init(struct device *dev)
uint32_t f0x160;
uint8_t core_count = 0;
uint8_t node_count = 0;
f0x60 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 0)), 0x60);
f0x60 = pci_read_config32(pcidev_on_root(0x18 + id.nodeid, 0),
0x60);
core_count = (f0x60 >> 16) & 0x1f;
node_count = ((f0x60 >> 4) & 0x7) + 1;
if (is_gt_rev_d()) {
f0x160 = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18 + id.nodeid, 0)), 0x160);
f0x160 = pci_read_config32(
pcidev_on_root(0x18 + id.nodeid, 0), 0x160);
core_count |= ((f0x160 >> 16) & 0x7) << 5;
}
core_count++;
Expand Down
4 changes: 2 additions & 2 deletions src/cpu/amd/family_10h-family_15h/monotonic_timer.c
View file
Expand Up @@ -19,7 +19,6 @@
#include <cpu/amd/msr.h>
#include <timer.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <northbridge/amd/amdht/AsPsDefs.h>

static struct monotonic_counter {
Expand Down Expand Up @@ -52,7 +51,8 @@ static void init_timer(void)

/* Get boost capability */
if ((model == 0x8) || (model == 0x9)) { /* revision D */
boost_capable = (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 4)), 0x15c) & 0x4) >> 2;
boost_capable = (pci_read_config32(pcidev_on_root(0x18, 4),
0x15c) & 0x4) >> 2;
}

/* Set up TSC (BKDG v3.62 section 2.9.4)*/
Expand Down
18 changes: 9 additions & 9 deletions src/cpu/amd/family_10h-family_15h/powernow_acpi.c
View file
Expand Up @@ -23,7 +23,6 @@
#include <arch/acpigen.h>
#include <cpu/amd/powernow.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/amd/mtrr.h>
#include <cpu/amd/amdfam10_sysconf.h>
#include <arch/cpu.h>
Expand Down Expand Up @@ -234,16 +233,17 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
fam15h = !!(mctGetLogicalCPUID(0) & AMD_FAM15_ALL);
/* Get number of cores */
if (fam15h) {
cmp_cap = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 5)), 0x84) & 0xff;
cmp_cap = pci_read_config32(pcidev_on_root(0x18, 5), 0x84) &
0xff;
} else {
dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xe8);
dtemp = pci_read_config32(pcidev_on_root(0x18, 3), 0xe8);
cmp_cap = (dtemp & 0x3000) >> 12;
if (mctGetLogicalCPUID(0) & (AMD_FAM10_REV_D | AMD_FAM15_ALL)) /* revision D or higher */
cmp_cap |= (dtemp & 0x8000) >> 13;
}

/* Get number of nodes */
dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 0)), 0x60);
dtemp = pci_read_config32(pcidev_on_root(0x18, 0), 0x60);
node_count = ((dtemp & 0x70) >> 4) + 1;
cores_per_node = cmp_cap + 1;

Expand All @@ -252,7 +252,7 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)

/* Get number of boost states */
uint8_t boost_count = 0;
dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 4)), 0x15c);
dtemp = pci_read_config32(pcidev_on_root(0x18, 4), 0x15c);
if (fam10h_rev_e)
boost_count = (dtemp >> 2) & 0x1;
else if (mctGetLogicalCPUID(0) & AMD_FAM15_ALL)
Expand Down Expand Up @@ -290,7 +290,7 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
uint8_t single_link;

/* Determine if this is a PVI or SVI system */
dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xA0);
dtemp = pci_read_config32(pcidev_on_root(0x18, 3), 0xA0);

if (dtemp & PVI_MODE)
pviModeFlag = 1;
Expand Down Expand Up @@ -362,10 +362,10 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
core_power = (core_voltage * cpuidd) / (expanded_cpuidv * 10);

/* Calculate transition latency */
dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xD4);
dtemp = pci_read_config32(pcidev_on_root(0x18, 3), 0xD4);
power_step_up = (dtemp & 0xf000000) >> 24;
power_step_down = (dtemp & 0xf00000) >> 20;
dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xA0);
dtemp = pci_read_config32(pcidev_on_root(0x18, 3), 0xA0);
pll_lock_time = (dtemp & 0x3800) >> 11;
if (all_enabled_cores_have_same_cpufid)
core_latency = ((12 * power_step_down) + power_step_up) / 1000;
Expand Down Expand Up @@ -397,7 +397,7 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
for (index = 0; index < total_core_count; index++) {
/* Determine if this is a single-link processor */
node_index = 0x18 + (index / cores_per_node);
dtemp = pci_read_config32(dev_find_slot(0, PCI_DEVFN(node_index, 0)), 0x80);
dtemp = pci_read_config32(pcidev_on_root(node_index, 0), 0x80);
single_link = !!(((dtemp & 0xff00) >> 8) == 0);

/* Enter processor core scope */
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/amd/family_10h-family_15h/processor_name.c
View file
Expand Up @@ -235,7 +235,7 @@ int init_processor_name(void)
if (fam15h) {
/* Family 15h or later */
uint32_t dword;
struct device *cpu_fn5_dev = dev_find_slot(0, PCI_DEVFN(0x18, 5));
struct device *cpu_fn5_dev = pcidev_on_root(0x18, 5);
pci_write_config32(cpu_fn5_dev, 0x194, 0);
dword = pci_read_config32(cpu_fn5_dev, 0x198);
if (dword == 0) {
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/amd/family_10h-family_15h/ram_calc.c
View file
Expand Up @@ -72,7 +72,7 @@ uint64_t get_cc6_memory_size()
if (pci_read_config32(PCI_DEV(0, 0x18, 2), 0x118) & (0x1 << 18))
enable_cc6 = 1;
#else
struct device *dct_dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
struct device *dct_dev = pcidev_on_root(0x18, 2);
if (pci_read_config32(dct_dev, 0x118) & (0x1 << 18))
enable_cc6 = 1;
#endif
Expand Down
56 changes: 0 additions & 56 deletions src/cpu/amd/geode_lx/Kconfig
View file

This file was deleted.

18 changes: 0 additions & 18 deletions src/cpu/amd/geode_lx/Makefile.inc
View file

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225 changes: 0 additions & 225 deletions src/cpu/amd/geode_lx/cache_as_ram.inc
View file

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84 changes: 0 additions & 84 deletions src/cpu/amd/geode_lx/cpubug.c
View file

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256 changes: 0 additions & 256 deletions src/cpu/amd/geode_lx/cpureginit.c
View file

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69 changes: 0 additions & 69 deletions src/cpu/amd/geode_lx/geode_lx_init.c
View file

This file was deleted.

60 changes: 0 additions & 60 deletions src/cpu/amd/geode_lx/msrinit.c
View file

This file was deleted.

39 changes: 0 additions & 39 deletions src/cpu/amd/geode_lx/syspreinit.c
View file

This file was deleted.

1 change: 0 additions & 1 deletion src/cpu/amd/pi/00630F01/model_15_init.c
View file
Expand Up @@ -23,7 +23,6 @@
#include <device/pci.h>
#include <string.h>
#include <cpu/x86/pae.h>
#include <pc80/mc146818rtc.h>
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
Expand Down
1 change: 0 additions & 1 deletion src/cpu/amd/pi/00660F01/model_15_init.c
View file
Expand Up @@ -22,7 +22,6 @@
#include <device/pci.h>
#include <string.h>
#include <cpu/x86/pae.h>
#include <pc80/mc146818rtc.h>
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
Expand Down
1 change: 0 additions & 1 deletion src/cpu/amd/pi/00730F01/model_16_init.c
View file
Expand Up @@ -22,7 +22,6 @@
#include <device/pci.h>
#include <string.h>
#include <cpu/x86/pae.h>
#include <pc80/mc146818rtc.h>
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
Expand Down
42 changes: 42 additions & 0 deletions src/cpu/intel/car/bootblock.c
View file
@@ -0,0 +1,42 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include <bootblock_common.h>
#include <cpu/intel/car/bootblock.h>
#include <cpu/x86/bist.h>

static uint32_t saved_bist;

asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
{
saved_bist = bist;
/* Call lib/bootblock.c main */
bootblock_main_with_timestamp(base_timestamp, NULL, 0);
}

void __weak bootblock_early_northbridge_init(void) { }
void __weak bootblock_early_southbridge_init(void) { }
void __weak bootblock_early_cpu_init(void) { }

void bootblock_soc_early_init(void)
{
bootblock_early_northbridge_init();
bootblock_early_southbridge_init();
bootblock_early_cpu_init();
}

void bootblock_soc_init(void)
{
/* Halt if there was a built in self test failure */
report_bist_failure(saved_bist);
}
12 changes: 6 additions & 6 deletions src/soc/broadcom/cygnus/include/soc/i2c.h → src/cpu/intel/car/bootblock.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2015 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand All @@ -13,9 +11,11 @@
* GNU General Public License for more details.
*/

#ifndef __SOC_BROADCOM_CYGNUS_I2C_H__
#define __SOC_BROADCOM_CYGNUS_I2C_H__
#ifndef _CPU_INTEL_CAR_BOOTBLOCK_H
#define _CPU_INTEL_CAR_BOOTBLOCK_H

void i2c_init(unsigned int bus, unsigned int hz);
void bootblock_early_cpu_init(void);
void bootblock_early_northbridge_init(void);
void bootblock_early_southbridge_init(void);

#endif /* __SOC_BROADCOM_CYGNUS_I2C_H__ */
#endif
31 changes: 17 additions & 14 deletions src/cpu/intel/car/core2/cache_as_ram.S
View file
Expand Up @@ -22,11 +22,12 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE

.global bootblock_pre_c_entry

.code32
_cache_as_ram_setup:

/* Save the BIST result. */
movl %eax, %ebp
bootblock_pre_c_entry:

cache_as_ram:
post_code(0x20)
Expand Down Expand Up @@ -167,22 +168,24 @@ addrsize_set_high:
movl %eax, %cr0

/* Setup the stack. */
movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
movl %eax, %esp
/* Align the stack 16 bytes */
mov $_car_stack_end, %esp

/* Need to align stack to 16 bytes at call instruction. Account for
the pushes below. */
andl $0xfffffff0, %esp
/* Account for pushing the BIST result */
subl $12, %esp
subl $4, %esp

/* Restore the BIST result. */
movl %ebp, %eax
movl %esp, %ebp
pushl %eax
/* push TSC and BIST to stack */
movd %mm0, %eax
pushl %eax /* BIST */
movd %mm2, %eax
pushl %eax /* tsc[63:32] */
movd %mm1, %eax
pushl %eax /* tsc[31:0] */

before_romstage:
before_c_entry:
post_code(0x29)
/* Call romstage.c main function. */
call romstage_main
call bootblock_c_entry_bist

/* Should never see this postcode */
post_code(POST_DEAD_CODE)
Expand Down
40 changes: 21 additions & 19 deletions src/cpu/intel/car/non-evict/cache_as_ram.S
View file
Expand Up @@ -25,11 +25,12 @@

#define NoEvictMod_MSR 0x2e0

.global bootblock_pre_c_entry

.code32
_cache_as_ram_setup:

/* Save the BIST result. */
movl %eax, %ebp
bootblock_pre_c_entry:

cache_as_ram:
post_code(0x20)
Expand Down Expand Up @@ -128,10 +129,10 @@ addrsize_set_high:
movl %eax, %cr0

/* enable the 'no eviction' mode */
movl $NoEvictMod_MSR, %ecx
movl $NoEvictMod_MSR, %ecx
rdmsr
orl $1, %eax
andl $~2, %eax
orl $1, %eax
andl $~2, %eax
wrmsr

/* Clear the cache memory region. This will also fill up the cache. */
Expand All @@ -142,9 +143,9 @@ addrsize_set_high:
rep stosl

/* enable the 'no eviction run' state */
movl $NoEvictMod_MSR, %ecx
movl $NoEvictMod_MSR, %ecx
rdmsr
orl $3, %eax
orl $3, %eax
wrmsr

post_code(0x26)
Expand All @@ -171,23 +172,24 @@ addrsize_set_high:
movl %eax, %cr0

/* Setup the stack. */
movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
movl %eax, %esp
mov $_car_stack_end, %esp

/* Align the stack 16 bytes */
/* Need to align stack to 16 bytes at call instruction. Account for
the pushes below. */
andl $0xfffffff0, %esp
/* Account for pushing the BIST result */
subl $12, %esp
subl $4, %esp

/* Restore the BIST result. */
movl %ebp, %eax
movl %esp, %ebp
pushl %eax
/* push TSC and BIST to stack */
movd %mm0, %eax
pushl %eax /* BIST */
movd %mm2, %eax
pushl %eax /* tsc[63:32] */
movd %mm1, %eax
pushl %eax /* tsc[31:0] */

before_romstage:
before_c_entry:
post_code(0x29)
/* Call romstage.c main function. */
call romstage_main
call bootblock_c_entry_bist

/* Should never see this postcode */
post_code(POST_DEAD_CODE)
Expand Down
6 changes: 3 additions & 3 deletions src/cpu/intel/car/non-evict/exit_car.S
View file
Expand Up @@ -42,11 +42,11 @@ chipset_teardown_car:
wrmsr

/* Disable the no eviction run state */
movl $NoEvictMod_MSR, %ecx
movl $NoEvictMod_MSR, %ecx
rdmsr
andl $~2, %eax
andl $~2, %eax
wrmsr
andl $~1, %eax
andl $~1, %eax
wrmsr

post_code(0x32)
Expand Down
35 changes: 21 additions & 14 deletions src/cpu/intel/car/p3/cache_as_ram.S
View file
Expand Up @@ -23,11 +23,12 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE

.global bootblock_pre_c_entry

.code32
_cache_as_ram_setup:

/* Save the BIST result. */
movl %eax, %ebp
bootblock_pre_c_entry:

cache_as_ram:
post_code(0x20)
Expand Down Expand Up @@ -156,18 +157,24 @@ addrsize_set_high:
movl %eax, %cr0

/* Setup the stack. */
movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
movl %eax, %esp

/* Restore the BIST result. */
movl %ebp, %eax
movl %esp, %ebp
pushl %eax

before_romstage:
post_code(0x2f)
/* Call romstage.c main function. */
call romstage_main
mov $_car_stack_end, %esp

/* Need to align stack to 16 bytes at call instruction. Account for
the pushes below. */
andl $0xfffffff0, %esp
subl $4, %esp

/* push TSC and BIST to stack */
movd %mm0, %eax
pushl %eax /* BIST */
movd %mm2, %eax
pushl %eax /* tsc[63:32] */
movd %mm1, %eax
pushl %eax /* tsc[31:0] */

before_c_entry:
post_code(0x29)
call bootblock_c_entry_bist

/* Should never see this postcode */
post_code(POST_DEAD_CODE)
Expand Down
31 changes: 17 additions & 14 deletions src/cpu/intel/car/p4-netburst/cache_as_ram.S
View file
Expand Up @@ -28,11 +28,12 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE

.global bootblock_pre_c_entry

.code32
_cache_as_ram_setup:

/* Save the BIST result. */
movl %eax, %ebp
bootblock_pre_c_entry:

cache_as_ram:
post_code(0x20)
Expand Down Expand Up @@ -353,22 +354,24 @@ skip_cache_rom:
movl %eax, %cr0

/* Setup the stack. */
movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax
movl %eax, %esp
/* Align the stack 16 bytes */
mov $_car_stack_end, %esp

/* Need to align stack to 16 bytes at call instruction. Account for
the pushes below. */
andl $0xfffffff0, %esp
/* Account for pushing the BIST result */
subl $12, %esp
subl $4, %esp

/* Restore the BIST result. */
movl %ebp, %eax
movl %esp, %ebp
pushl %eax
/* push TSC and BIST to stack */
movd %mm0, %eax
pushl %eax /* BIST */
movd %mm2, %eax
pushl %eax /* tsc[63:32] */
movd %mm1, %eax
pushl %eax /* tsc[31:0] */

before_romstage:
before_c_entry:
post_code(0x2f)
/* Call romstage.c main function. */
call romstage_main
call bootblock_c_entry_bist

/* Should never see this postcode */
post_code(POST_DEAD_CODE)
Expand Down
39 changes: 27 additions & 12 deletions src/cpu/intel/car/romstage.c
View file
Expand Up @@ -11,15 +11,17 @@
* GNU General Public License for more details.
*/

#include <bootblock_common.h>
#include <console/console.h>
#include <cpu/intel/romstage.h>
#include <cpu/x86/mtrr.h>
#include <arch/symbols.h>
#include <program_loading.h>
#include <timestamp.h>

#define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000

asmlinkage void *romstage_main(unsigned long bist)
static void romstage_main(unsigned long bist)
{
int i;
const int num_guards = 4;
Expand All @@ -28,15 +30,14 @@ asmlinkage void *romstage_main(unsigned long bist)
u32 size;

/* Size of unallocated CAR. */
size = _car_region_end - _car_relocatable_data_end;
size = ALIGN_DOWN(size, 16);
size = ALIGN_DOWN(_car_stack_size, 16);

size = MIN(size, DCACHE_RAM_ROMSTAGE_STACK_SIZE);
if (size < DCACHE_RAM_ROMSTAGE_STACK_SIZE)
printk(BIOS_DEBUG, "Romstage stack size limited to 0x%x!\n",
size);

stack_base = (u32 *) (_car_region_end - size);
stack_base = (u32 *) (_car_stack_end - size);

for (i = 0; i < num_guards; i++)
stack_base[i] = stack_guard;
Expand All @@ -50,17 +51,31 @@ asmlinkage void *romstage_main(unsigned long bist)
printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n");
}

if (!IS_ENABLED(CONFIG_POSTCAR_STAGE))
return setup_stack_and_mtrrs();

platform_enter_postcar();
}

/* We do not return. */
return NULL;
#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
* keeping changes in cache_as_ram.S easy to manage.
*/
asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
{
timestamp_init(base_timestamp);
timestamp_add_now(TS_START_ROMSTAGE);
romstage_main(bist);
}
#endif

asmlinkage void romstage_after_car(void)

/* We don't carry BIST from bootblock in a good location to read from.
* Any error should have been reported in bootblock already.
*/
#define NO_BIST 0

asmlinkage void car_stage_entry(void)
{
/* Load the ramstage. */
run_ramstage();
/* Assumes the hardware was set up during the bootblock */
console_init();

romstage_main(NO_BIST);
}
5 changes: 2 additions & 3 deletions src/cpu/intel/common/Kconfig
View file
Expand Up @@ -7,9 +7,8 @@ config ENABLE_VMX
bool "Enable VMX for virtualization"
default y

config SET_VMX_LOCK_BIT
bool "Set lock bit after configuring VMX"
depends on ENABLE_VMX
config SET_IA32_FC_LOCK_BIT
bool "Set IA32_FEATURE_CONTROL lock bit"
default y
help
Although the Intel manual says you must set the lock bit in addition
Expand Down
31 changes: 18 additions & 13 deletions ...hbridge/intel/i82801jx/acpi/pcie_port.asl → src/cpu/intel/common/acpi/cpu.asl
View file
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved.
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
Expand All @@ -14,18 +14,23 @@
* GNU General Public License for more details.
*/

/* Included in each PCIe Root Port device */
/* These come from the dynamically created CPU SSDT */
External (\_PR.CNOT, MethodObj)

OperationRegion (RPCS, PCI_Config, 0x00, 0xFF)
Field (RPCS, AnyAcc, NoLock, Preserve)
/* Notify OS to re-read CPU tables */
Method (PNOT)
{
Offset (0x4c), // Link Capabilities
, 24,
RPPN, 8, // Root Port Number
Offset (0x5A),
, 3,
PDC, 1,
Offset (0xDF),
, 6,
HPCS, 1,
\_PR.CNOT (0x81)
}

/* Notify OS to re-read CPU _PPC limit */
Method (PPCN)
{
\_PR.CNOT (0x80)
}

/* Notify OS to re-read Throttle Limit tables */
Method (TNOT)
{
\_PR.CNOT (0x82)
}