diff --git a/src/arch/x86/ioapic.c b/src/arch/x86/ioapic.c
@@ -27,18 +27,44 @@ static void write_vector(void *ioapic_base, u8 vector, u32 high, u32 low)
 	       vector, high, low);
 }
 
-static int ioapic_interrupt_count(void *ioapic_base)
+/* Bits 23-16 of register 0x01 specify the maximum redirection entry, which
+ * is the number of interrupts minus 1. */
+unsigned int ioapic_get_max_vectors(void *ioapic_base)
 {
-	/* Read the available number of interrupts. */
-	int ioapic_interrupts = (io_apic_read(ioapic_base, 0x01) >> 16) & 0xff;
-	if (!ioapic_interrupts || ioapic_interrupts == 0xff)
-		ioapic_interrupts = 23;
-	ioapic_interrupts += 1; /* Bits 23-16 specify the maximum redirection
-				   entry, which is the number of interrupts
-				   minus 1. */
-	printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts);
-
-	return ioapic_interrupts;
+	u32 reg;
+	u8 count;
+
+	reg = io_apic_read(ioapic_base, 0x01);
+	count = (reg >> 16) & 0xff;
+
+	if (count == 0xff)
+		count = 23;
+	count++;
+
+	printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", count);
+	return count;
+}
+
+/* Set maximum number of redirection entries (MRE). It is write-once register
+ * for some chipsets, and a negative mre_count will lock it to the number
+ * of vectors read from the register. */
+void ioapic_set_max_vectors(void *ioapic_base, int mre_count)
+{
+	u32 reg;
+	u8 count;
+
+	reg = io_apic_read(ioapic_base, 0x01);
+	count = (reg >> 16) & 0xff;
+	if (mre_count > 0)
+		count = mre_count - 1;
+	reg &= ~(0xff << 16);
+	reg |= count << 16;
+	io_apic_write(ioapic_base, 0x01, reg);
+}
+
+void ioapic_lock_max_vectors(void *ioapic_base)
+{
+	ioapic_set_max_vectors(ioapic_base, -1);
 }
 
 static void clear_vectors(void *ioapic_base, u8 first, u8 last)
@@ -60,11 +86,6 @@ static void clear_vectors(void *ioapic_base, u8 first, u8 last)
 	}
 }
 
-void clear_ioapic(void *ioapic_base)
-{
-	clear_vectors(ioapic_base, 0, ioapic_interrupt_count(ioapic_base) - 1);
-}
-
 static void route_i8259_irq0(void *ioapic_base)
 {
 	u32 bsp_lapicid = lapicid();
@@ -136,17 +157,9 @@ void ioapic_set_boot_config(void *ioapic_base, bool irq_on_fsb)
 	}
 }
 
-void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool enable_virtual_wire)
-{
-	set_ioapic_id(ioapic_base, ioapic_id);
-	clear_ioapic(ioapic_base);
-
-	if (enable_virtual_wire)
-		route_i8259_irq0(ioapic_base);
-}
-
-
 void setup_ioapic(void *ioapic_base, u8 ioapic_id)
 {
-	setup_ioapic_helper(ioapic_base, ioapic_id, true);
+	set_ioapic_id(ioapic_base, ioapic_id);
+	clear_vectors(ioapic_base, 0, ioapic_get_max_vectors(ioapic_base) - 1);
+	route_i8259_irq0(ioapic_base);
 }
diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
@@ -224,6 +224,9 @@ static int create_smbios_type17_for_dimm(struct dimm_info *dimm,
 					 unsigned long *current, int *handle,
 					 int type16_handle)
 {
+	struct spd_info info;
+	get_spd_info(dimm->ddr_type, dimm->mod_type, &info);
+
 	struct smbios_type17 *t = smbios_carve_table(*current, SMBIOS_MEMORY_DEVICE,
 						     sizeof(*t), *handle);
 
@@ -244,24 +247,7 @@ static int create_smbios_type17_for_dimm(struct dimm_info *dimm,
 	}
 	t->data_width = 8 * (1 << (dimm->bus_width & 0x7));
 	t->total_width = t->data_width + 8 * ((dimm->bus_width & 0x18) >> 3);
-
-	switch (dimm->mod_type) {
-	case SPD_RDIMM:
-	case SPD_MINI_RDIMM:
-		t->form_factor = MEMORY_FORMFACTOR_RIMM;
-		break;
-	case SPD_UDIMM:
-	case SPD_MICRO_DIMM:
-	case SPD_MINI_UDIMM:
-		t->form_factor = MEMORY_FORMFACTOR_DIMM;
-		break;
-	case SPD_SODIMM:
-		t->form_factor = MEMORY_FORMFACTOR_SODIMM;
-		break;
-	default:
-		t->form_factor = MEMORY_FORMFACTOR_UNKNOWN;
-		break;
-	}
+	t->form_factor = info.form_factor;
 
 	smbios_fill_dimm_manufacturer_from_id(dimm->mod_id, t);
 	smbios_fill_dimm_serial_number(dimm, t);
@@ -278,19 +264,8 @@ static int create_smbios_type17_for_dimm(struct dimm_info *dimm,
 	t->maximum_voltage = dimm->vdd_voltage;
 
 	/* Fill in type detail */
-	switch (dimm->mod_type) {
-	case SPD_RDIMM:
-	case SPD_MINI_RDIMM:
-		t->type_detail = MEMORY_TYPE_DETAIL_REGISTERED;
-		break;
-	case SPD_UDIMM:
-	case SPD_MINI_UDIMM:
-		t->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED;
-		break;
-	default:
-		t->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
-		break;
-	}
+	t->type_detail = info.type_detail;
+
 	/* Synchronous = 1 */
 	t->type_detail |= MEMORY_TYPE_DETAIL_SYNCHRONOUS;
 	/* no handle for error information */
@@ -489,6 +464,7 @@ static int smbios_write_type1(unsigned long *current, int handle)
 	t->manufacturer = smbios_add_string(t->eos, smbios_system_manufacturer());
 	t->product_name = smbios_add_string(t->eos, smbios_system_product_name());
 	t->serial_number = smbios_add_string(t->eos, smbios_system_serial_number());
+	t->wakeup_type = smbios_system_wakeup_type();
 	t->sku = smbios_add_string(t->eos, smbios_system_sku());
 	t->version = smbios_add_string(t->eos, smbios_system_version());
 #ifdef CONFIG_MAINBOARD_FAMILY
@@ -1031,6 +1007,50 @@ static int smbios_write_type19(unsigned long *current, int *handle, int type16)
 	return len;
 }
 
+static int smbios_write_type20_table(unsigned long *current, int *handle, u32 addr_start,
+		u32 addr_end, int type17_handle, int type19_handle)
+{
+	struct smbios_type20 *t = smbios_carve_table(*current, SMBIOS_MEMORY_DEVICE_MAPPED_ADDRESS,
+						     sizeof(*t), *handle);
+
+	t->memory_device_handle = type17_handle;
+	t->memory_array_mapped_address_handle = type19_handle;
+	t->addr_start = addr_start;
+	t->addr_end = addr_end;
+	t->partition_row_pos = 0xff;
+	t->interleave_pos = 0xff;
+	t->interleave_depth = 0xff;
+
+	const int len = smbios_full_table_len(&t->header, t->eos);
+	*current += len;
+	*handle += 1;
+	return len;
+}
+
+static int smbios_write_type20(unsigned long *current, int *handle,
+		int type17_handle, int type19_handle)
+{
+	u32 start_addr = 0;
+	int totallen = 0;
+	int i;
+
+	struct memory_info *meminfo;
+	meminfo = cbmem_find(CBMEM_ID_MEMINFO);
+	if (meminfo == NULL)
+		return 0;	/* can't find mem info in cbmem */
+
+	printk(BIOS_INFO, "Create SMBIOS type 20\n");
+	for (i = 0; i < meminfo->dimm_cnt && i < ARRAY_SIZE(meminfo->dimm); i++) {
+		struct dimm_info *dimm;
+		dimm = &meminfo->dimm[i];
+		u32 end_addr = start_addr + (dimm->dimm_size << 10) - 1;
+		totallen += smbios_write_type20_table(current, handle, start_addr, end_addr,
+				type17_handle, type19_handle);
+		start_addr = end_addr + 1;
+	}
+	return totallen;
+}
+
 static int smbios_write_type32(unsigned long *current, int handle)
 {
 	struct smbios_type32 *t = smbios_carve_table(*current, SMBIOS_SYSTEM_BOOT_INFORMATION,
@@ -1132,30 +1152,55 @@ static u8 smbios_get_device_type_from_dev(struct device *dev)
 	}
 }
 
-static int smbios_generate_type41_from_devtree(struct device *dev, int *handle,
-					       unsigned long *current)
+static bool smbios_get_type41_instance_id(struct device *dev, u8 device_type, u8 *instance_id)
 {
+#if CONFIG(SMBIOS_TYPE41_PROVIDED_BY_DEVTREE)
+	*instance_id = dev->smbios_instance_id;
+	return dev->smbios_instance_id_valid;
+#else
 	static u8 type41_inst_cnt[SMBIOS_DEVICE_TYPE_COUNT + 1] = {};
 
+	if (device_type == SMBIOS_DEVICE_TYPE_OTHER ||
+	    device_type == SMBIOS_DEVICE_TYPE_UNKNOWN)
+		return false;
+
+	if (device_type > SMBIOS_DEVICE_TYPE_COUNT)
+		return false;
+
+	*instance_id = type41_inst_cnt[device_type]++;
+	return true;
+#endif
+}
+
+static const char *smbios_get_type41_refdes(struct device *dev)
+{
+#if CONFIG(SMBIOS_TYPE41_PROVIDED_BY_DEVTREE)
+	if (dev->smbios_refdes)
+		return dev->smbios_refdes;
+#endif
+	return get_pci_subclass_name(dev);
+}
+
+static int smbios_generate_type41_from_devtree(struct device *dev, int *handle,
+					       unsigned long *current)
+{
 	if (dev->path.type != DEVICE_PATH_PCI)
 		return 0;
 	if (!dev->on_mainboard)
 		return 0;
 
-	u8 device_type = smbios_get_device_type_from_dev(dev);
+	const u8 device_type = smbios_get_device_type_from_dev(dev);
 
-	if (device_type == SMBIOS_DEVICE_TYPE_OTHER ||
-	    device_type == SMBIOS_DEVICE_TYPE_UNKNOWN)
-		return 0;
+	u8 instance_id;
 
-	if (device_type > SMBIOS_DEVICE_TYPE_COUNT)
+	if (!smbios_get_type41_instance_id(dev, device_type, &instance_id))
 		return 0;
 
-	const char *name = get_pci_subclass_name(dev);
+	const char *name = smbios_get_type41_refdes(dev);
 
 	return smbios_write_type41(current, handle,
 					name, // name
-					type41_inst_cnt[device_type]++, // inst
+					instance_id, // inst
 					0, // segment
 					dev->bus->secondary, //bus
 					PCI_SLOT(dev->path.pci.devfn), // device
@@ -1281,8 +1326,12 @@ unsigned long smbios_write_tables(unsigned long current)
 
 	const int type16 = handle;
 	update_max(len, max_struct_size, smbios_write_type16(&current, &handle));
+	const int type17 = handle;
 	update_max(len, max_struct_size, smbios_write_type17(&current, &handle, type16));
+	const int type19 = handle;
 	update_max(len, max_struct_size, smbios_write_type19(&current, &handle, type16));
+	update_max(len, max_struct_size,
+			smbios_write_type20(&current, &handle, type17, type19));
 	update_max(len, max_struct_size, smbios_write_type32(&current, handle++));
 
 	update_max(len, max_struct_size, smbios_walk_device_tree(all_devices,

diff --git a/src/arch/x86/smbios_defaults.c b/src/arch/x86/smbios_defaults.c
@@ -27,6 +27,11 @@ __weak void smbios_fill_dimm_asset_tag(const struct dimm_info *dimm, struct smbi
 	t->asset_tag = smbios_add_string(t->eos, buf);
 }
 
+__weak smbios_wakeup_type smbios_system_wakeup_type(void)
+{
+	return SMBIOS_WAKEUP_TYPE_RESERVED;
+}
+
 __weak const char *smbios_mainboard_bios_version(void)
 {
 	return NULL;

diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c
@@ -143,7 +143,7 @@ static unsigned long write_smbios_table(unsigned long rom_table_end)
 {
 	unsigned long high_table_pointer;
 
-#define MAX_SMBIOS_SIZE 2048
+#define MAX_SMBIOS_SIZE (4 * KiB)
 
 	high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_SMBIOS,
 		MAX_SMBIOS_SIZE);

diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc
@@ -22,6 +22,9 @@ smm-y += region.c
 postcar-y += region.c
 
 ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp_relocate.c
+ifeq ($(CONFIG_FSP_M_XIP),)
+romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c
+endif
 ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c
 
 bootblock-y += cbfs.c

diff --git a/src/commonlib/bsd/include/commonlib/bsd/compiler.h b/src/commonlib/bsd/include/commonlib/bsd/compiler.h
@@ -36,7 +36,7 @@
 #endif
 
 /* This evaluates to the type of the first expression, unless that is constant
-   in which case it evalutates to the type of the second. This is useful when
+   in which case it evaluates to the type of the second. This is useful when
    assigning macro parameters to temporary variables, because that would
    normally circumvent the special loosened type promotion rules for integer
    literals. By using this macro, the promotion can happen at the time the

diff --git a/src/commonlib/include/commonlib/iobuf.h b/src/commonlib/include/commonlib/iobuf.h
@@ -81,7 +81,7 @@ int ibuf_split(const struct ibuf *src, struct ibuf *a, struct ibuf *b,
 /* Out-of-band drain of ibuf by returning pointer to data of specified size. */
 const void *ibuf_oob_drain(struct ibuf *ib, size_t sz);
 
-/* Read arbitray data from input buffer. */
+/* Read arbitrary data from input buffer. */
 int ibuf_read(struct ibuf *ib, void *data, size_t sz);
 
 /* Read big endian fixed size values. */
@@ -125,7 +125,7 @@ int obuf_split(const struct obuf *src, struct obuf *a, struct obuf *b,
 /* Fill the buffer out-of-band. The size is accounted for. */
 void *obuf_oob_fill(struct obuf *ob, size_t sz);
 
-/* Write arbitray data to output buffer. */
+/* Write arbitrary data to output buffer. */
 int obuf_write(struct obuf *ob, const void *data, size_t sz);
 
 /* Write big endian fixed size values. */

diff --git a/src/commonlib/include/commonlib/mem_pool.h b/src/commonlib/include/commonlib/mem_pool.h
@@ -3,6 +3,7 @@
 #ifndef _MEM_POOL_H_
 #define _MEM_POOL_H_
 
+#include <assert.h>
 #include <stddef.h>
 #include <stdint.h>
 
@@ -16,23 +17,23 @@
  * were chosen to optimize for the CBFS cache case which may need two buffers
  * to map a single compressed file, and will free them in reverse order.)
  *
- * The memory returned by allocations are at least 8 byte aligned. Note
- * that this requires the backing buffer to start on at least an 8 byte
- * alignment.
+ * You must ensure the backing buffer is 'alignment' aligned.
  */
 
 struct mem_pool {
 	uint8_t *buf;
 	size_t size;
+	size_t alignment;
 	uint8_t *last_alloc;
 	uint8_t *second_to_last_alloc;
 	size_t free_offset;
 };
 
-#define MEM_POOL_INIT(buf_, size_)		\
+#define MEM_POOL_INIT(buf_, size_, alignment_)	\
 	{					\
 		.buf = (buf_),			\
 		.size = (size_),		\
+		.alignment = (alignment_),	\
 		.last_alloc = NULL,		\
 		.second_to_last_alloc = NULL,	\
 		.free_offset = 0,		\
@@ -46,10 +47,15 @@ static inline void mem_pool_reset(struct mem_pool *mp)
 }
 
 /* Initialize a memory pool. */
-static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
+static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz,
+					 size_t alignment)
 {
+	assert(alignment);
+	assert((uintptr_t)buf % alignment == 0);
+
 	mp->buf = buf;
 	mp->size = sz;
+	mp->alignment = alignment;
 	mem_pool_reset(mp);
 }
 

diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h
@@ -157,6 +157,17 @@ static inline int rdev_chain_full(struct region_device *child,
 	return rdev_chain(child, parent, 0, region_device_sz(parent));
 }
 
+/*
+ * Returns < 0 on error otherwise returns size of data read at provided
+ * offset filling in the buffer passed.
+ *
+ * You must ensure the buffer is large enough to hold the full region_device.
+ */
+static inline ssize_t rdev_readat_full(const struct region_device *rd, void *b)
+{
+	return rdev_readat(rd, b, 0, region_device_sz(rd));
+}
+
 /*
  * Compute relative offset of the child (c) w.r.t. the parent (p). Returns < 0
  * when child is not within the parent's region.

diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h
@@ -56,6 +56,8 @@ enum timestamp_id {
 	TS_DELAY_END = 111,
 	TS_READ_UCODE_START = 112,
 	TS_READ_UCODE_END = 113,
+	TS_ELOG_INIT_START = 114,
+	TS_ELOG_INIT_END = 115,
 
 	/* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
 	TS_START_COPYVER = 501,
@@ -113,6 +115,11 @@ enum timestamp_id {
 	TS_ME_INFORM_DRAM_DONE = 941,
 	TS_ME_BEFORE_END_OF_POST = 942,
 	TS_ME_AFTER_END_OF_POST = 943,
+	TS_ME_BOOT_STALL_DONE = 944,
+	TS_ME_ICC_CONFIG_START = 945,
+	TS_ME_HOST_BOOT_PREP_DONE = 946,
+	TS_ME_RECEIVED_CRDA_FROM_PMC = 947,
+	TS_FIT_UCODE_LOADED = 948,
 
 	/* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
 	TS_FSP_MEMORY_INIT_START = 950,
@@ -195,6 +202,8 @@ static const struct timestamp_id_to_name {
 	{ TS_DELAY_END,		"Forced delay end" },
 	{ TS_READ_UCODE_START,	"started reading uCode" },
 	{ TS_READ_UCODE_END,	"finished reading uCode" },
+	{ TS_ELOG_INIT_START,	"started elog init" },
+	{ TS_ELOG_INIT_END,	"finished elog init" },
 
 	{ TS_START_COPYVER,	"starting to load verstage" },
 	{ TS_END_COPYVER,	"finished loading verstage" },
@@ -267,6 +276,11 @@ static const struct timestamp_id_to_name {
 	{ TS_ME_INFORM_DRAM_DONE,	"finished waiting for ME response"},
 	{ TS_ME_BEFORE_END_OF_POST,	"before sending EOP to ME"},
 	{ TS_ME_AFTER_END_OF_POST,	"after sending EOP to ME"},
+	{ TS_ME_BOOT_STALL_DONE,	"CSE sent 'Boot Stall Done' to PMC"},
+	{ TS_ME_ICC_CONFIG_START,	"CSE started to handle ICC configuration"},
+	{ TS_ME_HOST_BOOT_PREP_DONE,	"CSE sent 'Host BIOS Prep Done' to PMC"},
+	{ TS_ME_RECEIVED_CRDA_FROM_PMC,	"CSE received 'CPU Reset Done Ack sent' from PMC"},
+	{ TS_FIT_UCODE_LOADED,		"CPU has loaded UCODE/PCODE from FIT"},
 
 	/* FSP related timestamps */
 	{ TS_FSP_MEMORY_INIT_START, "calling FspMemoryInit" },

diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c
@@ -7,8 +7,11 @@ void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
 {
 	void *p;
 
-	/* Make all allocations be at least 8 byte aligned. */
-	sz = ALIGN_UP(sz, 8);
+	if (mp->alignment == 0)
+		return NULL;
+
+	/* We assume that mp->buf started mp->alignment aligned */
+	sz = ALIGN_UP(sz, mp->alignment);
 
 	/* Determine if any space available. */
 	if ((mp->size - mp->free_offset) < sz)

diff --git a/src/console/Kconfig b/src/console/Kconfig
@@ -193,7 +193,7 @@ config CONSOLE_NE2K
 	help
 	  Send coreboot debug output to a Ethernet console, it works
 	  same way as Linux netconsole, packets are received to UDP
-	  port 6666 on IP/MAC specified with options bellow.
+	  port 6666 on IP/MAC specified with options below.
 	  Use following netcat command: nc -u -l -p 6666
 
 config CONSOLE_NE2K_DST_MAC

diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig
@@ -3,11 +3,3 @@
 config CPU_AMD_AGESA_FAMILY14
 	bool
 	select X86_AMD_FIXED_MTRRS
-
-if CPU_AMD_AGESA_FAMILY14
-
-config CPU_ADDR_BITS
-	int
-	default 36
-
-endif
diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc
@@ -7,7 +7,3 @@ ramstage-y += chip_name.c
 ramstage-y += model_14_init.c
 
 subdirs-y += ../../mtrr
-subdirs-y += ../../../x86/lapic
-subdirs-y += ../../../x86/cache
-subdirs-y += ../../../x86/mtrr
-subdirs-y += ../../../x86/pae
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -25,9 +25,7 @@ static void model_14_init(struct device *dev)
 	disable_cache();
 	/*
 	 * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set
-	 * by coreboot. The amd_setup_mtrrs should work, but needs debug on fam14.
-	 * TODO:
-	 * amd_setup_mtrrs();
+	 * by coreboot.
 	 */
 
 	/* Enable access to AMD RdDram and WrDram extension bits */
@@ -54,7 +52,7 @@ static void model_14_init(struct device *dev)
 		restore_mtrr();
 
 	x86_mtrr_check();
-	x86_enable_cache();
+	enable_cache();
 
 	/* zero the machine check error status registers */
 	mca_clear_status();

diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig
@@ -4,11 +4,3 @@ config CPU_AMD_AGESA_FAMILY15_TN
 	bool
 	select IDS_OPTIONS_HOOKED_UP
 	select X86_AMD_FIXED_MTRRS
-
-if CPU_AMD_AGESA_FAMILY15_TN
-
-config CPU_ADDR_BITS
-	int
-	default 48
-
-endif
diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc
@@ -10,7 +10,3 @@ smm-y += udelay.c
 
 subdirs-y += ../../mtrr
 subdirs-y += ../../smm
-subdirs-y += ../../../x86/lapic
-subdirs-y += ../../../x86/cache
-subdirs-y += ../../../x86/mtrr
-subdirs-y += ../../../x86/pae
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -25,9 +25,10 @@ static void model_15_init(struct device *dev)
 	u32 siblings;
 #endif
 
-	//x86_enable_cache();
-	//amd_setup_mtrrs();
-	//x86_mtrr_check();
+	/*
+	 * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set
+	 * by coreboot.
+	 */
 	disable_cache();
 	/* Enable access to AMD RdDram and WrDram extension bits */
 	msr = rdmsr(SYSCFG_MSR);
@@ -53,7 +54,7 @@ static void model_15_init(struct device *dev)
 		restore_mtrr();
 
 	x86_mtrr_check();
-	x86_enable_cache();
+	enable_cache();
 
 	/* zero the machine check error status registers */
 	mca_clear_status();

diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig
@@ -6,10 +6,6 @@ config CPU_AMD_AGESA_FAMILY16_KB
 
 if CPU_AMD_AGESA_FAMILY16_KB
 
-config CPU_ADDR_BITS
-	int
-	default 40
-
 config FORCE_AM1_SOCKET_SUPPORT
 	bool
 	default n

diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc
@@ -7,7 +7,3 @@ ramstage-y += chip_name.c
 ramstage-y += model_16_init.c
 
 subdirs-y += ../../mtrr
-subdirs-y += ../../../x86/lapic
-subdirs-y += ../../../x86/cache
-subdirs-y += ../../../x86/mtrr
-subdirs-y += ../../../x86/pae
diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c
@@ -23,9 +23,10 @@ static void model_16_init(struct device *dev)
 	u32 siblings;
 #endif
 
-	//x86_enable_cache();
-	//amd_setup_mtrrs();
-	//x86_mtrr_check();
+	/*
+	 * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set
+	 * by coreboot.
+	 */
 	disable_cache();
 	/* Enable access to AMD RdDram and WrDram extension bits */
 	msr = rdmsr(SYSCFG_MSR);
@@ -51,7 +52,7 @@ static void model_16_init(struct device *dev)
 		restore_mtrr();
 
 	x86_mtrr_check();
-	x86_enable_cache();
+	enable_cache();
 
 	/* zero the machine check error status registers */
 	mca_clear_status();

diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -3,72 +3,11 @@
 #include <amdblocks/biosram.h>
 #include <console/console.h>
 #include <device/device.h>
-#include <arch/cpu.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
-#include <cpu/x86/cache.h>
-
-/* These will likely move to some device node or cbmem. */
-static uint64_t amd_topmem = 0;
-static uint64_t amd_topmem2 = 0;
-
-uint64_t bsp_topmem(void)
-{
-	return amd_topmem;
-}
-
-uint64_t bsp_topmem2(void)
-{
-	return amd_topmem2;
-}
-
-/* Take a copy of BSP CPUs TOP_MEM and TOP_MEM2 registers,
- * so they can be distributed to AP CPUs. Not strictly MTRRs,
- * but this is not that bad a place to have this code.
- */
-void setup_bsp_ramtop(void)
-{
-	msr_t msr, msr2;
-
-	/* TOP_MEM: the top of DRAM below 4G */
-	msr = rdmsr(TOP_MEM);
-	printk(BIOS_INFO,
-	    "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
-	     __func__, msr.lo, msr.hi);
-
-	/* TOP_MEM2: the top of DRAM above 4G */
-	msr2 = rdmsr(TOP_MEM2);
-	printk(BIOS_INFO,
-	    "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
-	     __func__, msr2.lo, msr2.hi);
-
-	amd_topmem = (uint64_t) msr.hi << 32 | msr.lo;
-	amd_topmem2 = (uint64_t) msr2.hi << 32 | msr2.lo;
-}
-
-static void setup_ap_ramtop(void)
-{
-	msr_t msr;
-	uint64_t v;
-
-	v = bsp_topmem();
-	if (!v)
-		return;
-
-	msr.hi = v >> 32;
-	msr.lo = (uint32_t) v;
-	wrmsr(TOP_MEM, msr);
-
-	v = bsp_topmem2();
-	msr.hi = v >> 32;
-	msr.lo = (uint32_t) v;
-	wrmsr(TOP_MEM2, msr);
-}
 
 void add_uma_resource_below_tolm(struct device *nb, int idx)
 {
-	uint32_t topmem = bsp_topmem();
+	uint32_t topmem = amd_topmem();
 	uint32_t top_of_cacheable = restore_top_of_low_cacheable();
 
 	if (top_of_cacheable == topmem)
@@ -82,79 +21,3 @@ void add_uma_resource_below_tolm(struct device *nb, int idx)
 
 	uma_resource(nb, idx, uma_base / KiB, uma_size / KiB);
 }
-
-void amd_setup_mtrrs(void)
-{
-	unsigned long address_bits;
-	unsigned long i;
-	msr_t msr, sys_cfg;
-	// Test if this CPU is a Fam 0Fh rev. F or later
-	const int cpu_id = cpuid_eax(0x80000001);
-	printk(BIOS_SPEW, "CPU ID 0x80000001: %x\n", cpu_id);
-	const int has_tom2wb =
-		// ExtendedFamily > 0
-		 (((cpu_id>>20)&0xf) > 0) ||
-		// Family == 0F
-		((((cpu_id>>8)&0xf) == 0xf) &&
-		// Rev>=F deduced from rev tables
-		 (((cpu_id>>16)&0xf) >= 0x4));
-	if (has_tom2wb)
-		printk(BIOS_DEBUG, "CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB\n");
-
-	/* Enable the access to AMD RdDram and WrDram extension bits */
-	disable_cache();
-	sys_cfg = rdmsr(SYSCFG_MSR);
-	sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramModEn;
-	wrmsr(SYSCFG_MSR, sys_cfg);
-	enable_cache();
-
-	/* Setup fixed MTRRs, but do not enable them just yet. */
-	x86_setup_fixed_mtrrs_no_enable();
-
-	disable_cache();
-
-	setup_ap_ramtop();
-
-	/* if DRAM above 4GB: set SYSCFG_MSR_TOM2En and SYSCFG_MSR_TOM2WB */
-	sys_cfg.lo &= ~(SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB);
-	if (bsp_topmem2() > (uint64_t)1 << 32) {
-		sys_cfg.lo |= SYSCFG_MSR_TOM2En;
-		if (has_tom2wb)
-			sys_cfg.lo |= SYSCFG_MSR_TOM2WB;
-	}
-
-	/* zero the IORR's before we enable to prevent
-	 * undefined side effects.
-	 */
-	msr.lo = msr.hi = 0;
-	for (i = MTRR_IORR0_BASE; i <= MTRR_IORR1_MASK; i++)
-		wrmsr(i, msr);
-
-	/* Enable Variable Mtrrs
-	 * Enable the RdMem and WrMem bits in the fixed mtrrs.
-	 * Disable access to the RdMem and WrMem in the fixed mtrr.
-	 */
-	sys_cfg.lo |= SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn;
-	sys_cfg.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
-	wrmsr(SYSCFG_MSR, sys_cfg);
-
-	enable_fixed_mtrr();
-
-	enable_cache();
-
-	//K8 could be 40, and GH could be 48
-	address_bits = CONFIG_CPU_ADDR_BITS;
-
-	/* AMD specific cpuid function to query number of address bits */
-	if (cpuid_eax(0x80000000) >= 0x80000008)
-		address_bits = cpuid_eax(0x80000008) & 0xff;
-
-	/* Now that I have mapped what is memory and what is not
-	 * Set up the mtrrs so we can cache the memory.
-	 */
-
-	// Rev. F K8 supports has SYSCFG_MSR_TOM2WB and doesn't need
-	// variable MTRR to span memory above 4GB
-	// Lower revisions K8 need variable MTRR over 4GB
-	x86_setup_var_mtrrs(address_bits, has_tom2wb ? 0 : 1);
-}
diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig
@@ -5,11 +5,3 @@ config CPU_AMD_PI_00730F01
 	select X86_AMD_FIXED_MTRRS
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select MICROCODE_BLOB_UNDISCLOSED
-
-if CPU_AMD_PI_00730F01
-
-config CPU_ADDR_BITS
-	int
-	default 40
-
-endif
diff --git a/src/cpu/amd/pi/00730F01/Makefile.inc b/src/cpu/amd/pi/00730F01/Makefile.inc
@@ -8,7 +8,3 @@ ramstage-y += model_16_init.c
 ramstage-y += update_microcode.c
 
 subdirs-y += ../../mtrr
-subdirs-y += ../../../x86/lapic
-subdirs-y += ../../../x86/cache
-subdirs-y += ../../../x86/mtrr
-subdirs-y += ../../../x86/pae
diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h
@@ -4,6 +4,7 @@
 #define _CPU_INTEL_COMMON_H
 
 #include <types.h>
+#include <acpi/acpigen.h>
 
 void set_vmx_and_lock(void);
 void set_feature_ctrl_vmx(void);

diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c
@@ -103,184 +103,37 @@ void set_feature_ctrl_lock(void)
  */
 void cpu_init_cppc_config(struct cppc_config *config, u32 version)
 {
-	acpi_addr_t msr = {
-		.space_id   = ACPI_ADDRESS_SPACE_FIXED,
-		.bit_width  = 8,
-		.bit_offset = 0,
-		.access_size = ACPI_ACCESS_SIZE_QWORD_ACCESS,
-		.addrl      = 0,
-		.addrh      = 0,
-	};
-	static const acpi_addr_t unsupported = {
-		.space_id   = ACPI_ADDRESS_SPACE_MEMORY,
-		.bit_width  = 0,
-		.bit_offset = 0,
-		.access_size = ACPI_ACCESS_SIZE_UNDEFINED,
-		.addrl      = 0,
-		.addrh      = 0,
-	};
-
 	config->version = version;
 
-	msr.addrl = IA32_HWP_CAPABILITIES;
-
-	/*
-	 * Highest Performance:
-	 * ResourceTemplate(){Register(FFixedHW, 0x08, 0x00, 0x771, 0x04,)},
-	 */
-	config->regs[CPPC_HIGHEST_PERF] = msr;
-
-	/*
-	 * Lowest Nonlinear Performance -> Most Efficient Performance:
-	 * ResourceTemplate(){Register(FFixedHW, 0x08, 0x10, 0x771, 0x04,)},
-	 */
-	msr.bit_offset = 16;
-	config->regs[CPPC_LOWEST_NONL_PERF] = msr;
-
-	/*
-	 * Lowest Performance:
-	 * ResourceTemplate(){Register(FFixedHW, 0x08, 0x18, 0x771, 0x04,)},
-	 */
-	msr.bit_offset = 24;
-	config->regs[CPPC_LOWEST_PERF] = msr;
-
-	/*
-	 * Guaranteed Performance Register:
-	 * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0x771, 0x04,)},
-	 */
-	msr.bit_offset = 8;
-	config->regs[CPPC_GUARANTEED_PERF] = msr;
-
-	msr.addrl = MSR_PLATFORM_INFO;
-
-	/*
-	 * Nominal Performance -> Maximum Non-Turbo Ratio:
-	 * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0xce, 0x04,)},
-	 */
-	msr.bit_offset = 8;
-	config->regs[CPPC_NOMINAL_PERF] = msr;
-
-	msr.addrl = IA32_HWP_REQUEST;
-
-	/*
-	 * Desired Performance Register:
-	 * ResourceTemplate(){Register(FFixedHW, 0x08, 0x10, 0x774, 0x04,)},
-	 */
-	msr.bit_offset = 16;
-	config->regs[CPPC_DESIRED_PERF] = msr;
-
-	/*
-	 * Minimum Performance Register:
-	 * ResourceTemplate(){Register(FFixedHW, 0x08, 0x00, 0x774, 0x04,)},
-	 */
-	msr.bit_offset = 0;
-	config->regs[CPPC_MIN_PERF] = msr;
-
-	/*
-	 * Maximum Performance Register:
-	 * ResourceTemplate(){Register(FFixedHW, 0x08, 0x08, 0x774, 0x04,)},
-	 */
-	msr.bit_offset = 8;
-	config->regs[CPPC_MAX_PERF] = msr;
-
-	/*
-	 * Performance Reduction Tolerance Register:
-	 * ResourceTemplate(){Register(SystemMemory, 0x00, 0x00, 0x0,,)},
-	 */
-	config->regs[CPPC_PERF_REDUCE_TOLERANCE] = unsupported;
-
-	/*
-	 * Time Window Register:
-	 * ResourceTemplate(){Register(SystemMemory, 0x00, 0x00, 0x0,,)},
-	 */
-	config->regs[CPPC_TIME_WINDOW] = unsupported;
-
-	/*
-	 * Counter Wraparound Time:
-	 * ResourceTemplate(){Register(SystemMemory, 0x00, 0x00, 0x0,,)},
-	 */
-	config->regs[CPPC_COUNTER_WRAP] = unsupported;
-
-	msr.addrl = IA32_MPERF;
-
-	/*
-	 * Reference Performance Counter Register:
-	 * ResourceTemplate(){Register(FFixedHW, 0x40, 0x00, 0x0E7, 0x04,)},
-	 */
-	msr.bit_width = 64;
-	msr.bit_offset = 0;
-	config->regs[CPPC_REF_PERF_COUNTER] = msr;
-
-	msr.addrl = IA32_APERF;
-
-	/*
-	 * Delivered Performance Counter Register:
-	 * ResourceTemplate(){Register(FFixedHW, 0x40, 0x00, 0x0E8, 0x04,)},
-	 */
-	config->regs[CPPC_DELIVERED_PERF_COUNTER] = msr;
-
-	msr.addrl = IA32_HWP_STATUS;
-
-	/*
-	 * Performance Limited Register:
-	 * ResourceTemplate(){Register(FFixedHW, 0x01, 0x02, 0x777, 0x04,)},
-	 */
-	msr.bit_width = 1;
-	msr.bit_offset = 2;
-	config->regs[CPPC_PERF_LIMITED] = msr;
-
-	msr.addrl = IA32_PM_ENABLE;
-
-	/*
-	 * CPPC Enable Register:
-	 * ResourceTemplate(){Register(FFixedHW, 0x01, 0x00, 0x770, 0x04,)},
-	 */
-	msr.bit_offset = 0;
-	config->regs[CPPC_ENABLE] = msr;
-
-	if (version >= 2) {
-		/* Autonomous Selection Enable is populated below */
-
-		msr.addrl = IA32_HWP_REQUEST;
+	config->entries[CPPC_HIGHEST_PERF]		= CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 0, 8);
+	config->entries[CPPC_NOMINAL_PERF]		= CPPC_REG_MSR(MSR_PLATFORM_INFO, 8, 8);
+	config->entries[CPPC_LOWEST_NONL_PERF]		= CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 16, 8);
+	config->entries[CPPC_LOWEST_PERF]		= CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 24, 8);
+	config->entries[CPPC_GUARANTEED_PERF]		= CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 8, 8);
+	config->entries[CPPC_DESIRED_PERF]		= CPPC_REG_MSR(IA32_HWP_REQUEST, 16, 8);
+	config->entries[CPPC_MIN_PERF]			= CPPC_REG_MSR(IA32_HWP_REQUEST, 0, 8);
+	config->entries[CPPC_MAX_PERF]			= CPPC_REG_MSR(IA32_HWP_REQUEST, 8, 8);
+	config->entries[CPPC_PERF_REDUCE_TOLERANCE]	= CPPC_UNSUPPORTED;
+	config->entries[CPPC_TIME_WINDOW]		= CPPC_UNSUPPORTED;
+	config->entries[CPPC_COUNTER_WRAP]		= CPPC_UNSUPPORTED;
+	config->entries[CPPC_REF_PERF_COUNTER]		= CPPC_REG_MSR(IA32_MPERF, 0, 64);
+	config->entries[CPPC_DELIVERED_PERF_COUNTER]	= CPPC_REG_MSR(IA32_APERF, 0, 64);
+	config->entries[CPPC_PERF_LIMITED]		= CPPC_REG_MSR(IA32_HWP_STATUS, 2, 1);
+	config->entries[CPPC_ENABLE]			= CPPC_REG_MSR(IA32_PM_ENABLE, 0, 1);
+
+	if (version < 2)
+		return;
 
-		/*
-		 * Autonomous Activity Window Register
-		 * ResourceTemplate(){Register(FFixedHW, 0x0a, 0x20, 0x774, 0x04,)},
-		 */
-		msr.bit_width = 10;
-		msr.bit_offset = 32;
-		config->regs[CPPC_AUTO_ACTIVITY_WINDOW] = msr;
+	config->entries[CPPC_AUTO_SELECT]		= CPPC_DWORD(1);
+	config->entries[CPPC_AUTO_ACTIVITY_WINDOW]	= CPPC_REG_MSR(IA32_HWP_REQUEST, 32, 10);
+	config->entries[CPPC_PERF_PREF]			= CPPC_REG_MSR(IA32_HWP_REQUEST, 24, 8);
+	config->entries[CPPC_REF_PERF]			= CPPC_UNSUPPORTED;
 
-		/*
-		 * Autonomous Energy Performance Preference Register
-		 * ResourceTemplate(){Register(FFixedHW, 0x08, 0x18, 0x774, 0x04,)},
-		 */
-		msr.bit_width = 8;
-		msr.bit_offset = 24;
-		config->regs[CPPC_PERF_PREF] = msr;
-
-		/* Reference Performance */
-		config->regs[CPPC_REF_PERF] = unsupported;
-
-		if (version >= 3) {
-			/* Lowest Frequency */
-			config->regs[CPPC_LOWEST_FREQ] = unsupported;
-			/* Nominal Frequency */
-			config->regs[CPPC_NOMINAL_FREQ] = unsupported;
-		}
+	if (version < 3)
+		return;
 
-		/*
-		 * Autonomous Selection Enable = 1
-		 * This field is actually the first addition in version 2 but
-		 * it's so unlike the others I'm populating it last.
-		 */
-		msr.space_id    = ACPI_ADDRESS_SPACE_MEMORY;
-		msr.bit_width   = 32;
-		msr.bit_offset  = 0;
-		msr.access_size = ACPI_ACCESS_SIZE_UNDEFINED;
-		msr.addrl       = 1;
-		config->regs[CPPC_AUTO_SELECT] = msr;
-	}
+	config->entries[CPPC_LOWEST_FREQ]		= CPPC_UNSUPPORTED;
+	config->entries[CPPC_NOMINAL_FREQ]		= CPPC_UNSUPPORTED;
 }
 
 void set_aesni_lock(void)

diff --git a/src/cpu/intel/common/hyperthreading.c b/src/cpu/intel/common/hyperthreading.c
@@ -1,6 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <cpu/x86/lapic.h>
 #include <cpu/intel/common/common.h>
 #include <arch/cpu.h>
 #include <types.h>
@@ -18,31 +17,36 @@ bool intel_ht_supported(void)
 bool intel_ht_sibling(void)
 {
 	struct cpuid_result result;
-	unsigned int core_ids, apic_ids, threads;
+	unsigned int core_ids, apic_ids;
+	unsigned int max_leaf;
+	uint32_t initial_lapicid, threads;
 
 	if (!intel_ht_supported())
 		return false;
 
-	if (is_x2apic_mode()) {
-		if (cpuid_eax(0) >= 0xb) {
-			result = cpuid_ext(0xb, 0);
-			const uint32_t div = 1 << (result.eax & 0x1f);
-			return result.edx % div > 0;
-		}
+	max_leaf = cpuid_get_max_func();
+
+	/* Detect from 32-bit X2APIC ID. */
+	if (max_leaf >= 0xb) {
+		result = cpuid_ext(0xb, 0);
+		threads = 1 << (result.eax & 0x1f);
+		initial_lapicid = result.edx;
+		return initial_lapicid % threads > 0;
 	}
 
-	apic_ids = 1;
-	if (cpuid_eax(0) >= 1)
-		apic_ids = (cpuid_ebx(1) >> 16) & 0xff;
+	/* Detect from 8-bit XAPIC ID. */
+	result = cpuid_ext(0x1, 0);
+	initial_lapicid = result.ebx >> 24;
+	apic_ids = (result.ebx >> 16) & 0xff;
 	if (apic_ids == 0)
 		apic_ids = 1;
 
 	core_ids = 1;
-	if (cpuid_eax(0) >= 4) {
+	if (max_leaf >= 4) {
 		result = cpuid_ext(4, 0);
 		core_ids += (result.eax >> 26) & 0x3f;
 	}
 
 	threads = (apic_ids / core_ids);
-	return !!(lapicid() & (threads - 1));
+	return initial_lapicid % threads > 0;
 }
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig
@@ -19,7 +19,6 @@ config CPU_SPECIFIC_OPTIONS
 	select CPU_INTEL_COMMON
 	select CPU_INTEL_COMMON_TIMEBASE
 	select HAVE_ASAN_IN_ROMSTAGE
-	select HAVE_DISPLAY_MTRRS
 	select CPU_INTEL_COMMON_VOLTAGE
 
 config SMM_TSEG_SIZE

diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc
@@ -15,9 +15,6 @@ bootblock-y += bootblock.c
 
 postcar-y += ../car/non-evict/exit_car.S
 
-subdirs-y += ../../x86/mtrr
-subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
 subdirs-y += ../microcode
 subdirs-y += ../turbo
 

diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
@@ -17,6 +17,7 @@
 #include <northbridge/intel/haswell/haswell.h>
 #include <southbridge/intel/lynxpoint/pch.h>
 #include <cpu/intel/common/common.h>
+#include <types.h>
 #include "haswell.h"
 #include "chip.h"
 
@@ -395,6 +396,7 @@ static void configure_c_states(void)
 	msr.lo |= (1 << 27);	// C3 Auto Undemotion Enable
 	msr.lo |= (1 << 26);	// C1 Auto Demotion Enable
 	msr.lo |= (1 << 25);	// C3 Auto Demotion Enable
+	msr.lo |= (1 << 15);	// Lock bits 15:0
 	msr.lo &= ~(1 << 10);	// Disable IO MWAIT redirection
 
 	if (timed_mwait_capable)
@@ -586,8 +588,8 @@ static void pre_mp_init(void)
 static int get_cpu_count(void)
 {
 	msr_t msr;
-	int num_threads;
-	int num_cores;
+	unsigned int num_threads;
+	unsigned int num_cores;
 
 	msr = rdmsr(MSR_CORE_THREAD_COUNT);
 	num_threads = (msr.lo >> 0) & 0xffff;
@@ -640,8 +642,8 @@ static const struct mp_ops mp_ops = {
 
 void mp_init_cpus(struct bus *cpu_bus)
 {
-	if (mp_init_with_smm(cpu_bus, &mp_ops))
-		printk(BIOS_ERR, "MP initialization failure.\n");
+	/* TODO: Handle mp_init_with_smm failure? */
+	mp_init_with_smm(cpu_bus, &mp_ops);
 }
 
 static struct device_operations cpu_dev_ops = {

diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
@@ -7,6 +7,7 @@
 #include <cpu/intel/smm_reloc.h>
 #include <cpu/intel/common/common.h>
 #include <device/device.h>
+#include <types.h>
 
 /* Parallel MP initialization support. */
 static void pre_mp_init(void)
@@ -22,7 +23,7 @@ static void pre_mp_init(void)
 static int get_cpu_count(void)
 {
 	const struct cpuid_result cpuid1 = cpuid(1);
-	const char cores = (cpuid1.ebx >> 16) & 0xf;
+	const unsigned int cores = (cpuid1.ebx >> 16) & 0xf;
 
 	printk(BIOS_DEBUG, "CPU has %u cores.\n", cores);
 
@@ -97,6 +98,6 @@ static const struct mp_ops mp_ops = {
 
 void mp_init_cpus(struct bus *cpu_bus)
 {
-	if (mp_init_with_smm(cpu_bus, &mp_ops))
-		printk(BIOS_ERR, "MP initialization failure.\n");
+	/* TODO: Handle mp_init_with_smm failure? */
+	mp_init_with_smm(cpu_bus, &mp_ops);
 }
diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig
@@ -11,11 +11,3 @@ config CPU_INTEL_MODEL_106CX
 	select SERIALIZED_SMM_INITIALIZATION
 	select CPU_INTEL_COMMON
 	select CPU_INTEL_COMMON_TIMEBASE
-
-if CPU_INTEL_MODEL_106CX
-
-config CPU_ADDR_BITS
-	int
-	default 32
-
-endif
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc
@@ -1,8 +1,5 @@
 ramstage-y += model_2065x_init.c
 subdirs-y += ../../x86/name
-subdirs-y += ../../x86/cache
-subdirs-y += ../../x86/mtrr
-subdirs-y += ../../x86/lapic
 subdirs-y += ../../intel/turbo
 subdirs-y += ../../intel/microcode
 subdirs-y += ../smm/gen1

diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c
@@ -19,6 +19,7 @@
 #include <cpu/intel/smm_reloc.h>
 #include <cpu/intel/common/common.h>
 #include <smp/node.h>
+#include <types.h>
 
 static void configure_thermal_target(void)
 {
@@ -123,8 +124,8 @@ static void pre_mp_init(void)
 static int get_cpu_count(void)
 {
 	msr_t msr;
-	int num_threads;
-	int num_cores;
+	unsigned int num_threads;
+	unsigned int num_cores;
 
 	msr = rdmsr(MSR_CORE_THREAD_COUNT);
 	num_threads = (msr.lo >> 0) & 0xffff;
@@ -174,8 +175,8 @@ static const struct mp_ops mp_ops = {
 
 void mp_init_cpus(struct bus *cpu_bus)
 {
-	if (mp_init_with_smm(cpu_bus, &mp_ops))
-		printk(BIOS_ERR, "MP initialization failure.\n");
+	/* TODO: Handle mp_init_with_smm failure? */
+	mp_init_with_smm(cpu_bus, &mp_ops);
 }
 
 static struct device_operations cpu_dev_ops = {

diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
@@ -2,9 +2,6 @@ ramstage-y += model_206ax_init.c
 subdirs-y += ../../x86/name
 subdirs-y += ../smm/gen1
 
-subdirs-y += ../../x86/mtrr
-subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
 subdirs-y += ../microcode
 subdirs-y += ../turbo
 

diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -19,6 +19,7 @@
 #include <cpu/intel/smm_reloc.h>
 #include <cpu/intel/common/common.h>
 #include <smbios.h>
+#include <types.h>
 
 /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
 static const u8 power_limit_time_sec_to_msr[] = {
@@ -379,8 +380,8 @@ static void pre_mp_init(void)
 static int get_cpu_count(void)
 {
 	msr_t msr;
-	int num_threads;
-	int num_cores;
+	unsigned int num_threads;
+	unsigned int num_cores;
 
 	msr = rdmsr(MSR_CORE_THREAD_COUNT);
 	num_threads = (msr.lo >> 0) & 0xffff;
@@ -430,8 +431,8 @@ static const struct mp_ops mp_ops = {
 
 void mp_init_cpus(struct bus *cpu_bus)
 {
-	if (mp_init_with_smm(cpu_bus, &mp_ops))
-		printk(BIOS_ERR, "MP initialization failure.\n");
+	/* TODO: Handle mp_init_with_smm failure? */
+	mp_init_with_smm(cpu_bus, &mp_ops);
 }
 
 static struct device_operations cpu_dev_ops = {

diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c
@@ -16,7 +16,7 @@ static void model_65x_init(struct device *dev)
 	p6_configure_l2_cache();
 
 	/* Turn on caching if we haven't already */
-	x86_enable_cache();
+	enable_cache();
 	x86_setup_mtrrs();
 	x86_mtrr_check();
 

diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c
@@ -17,7 +17,7 @@ static void model_67x_init(struct device *cpu)
 	p6_configure_l2_cache();
 
 	/* Turn on caching if we haven't already */
-	x86_enable_cache();
+	enable_cache();
 
 	/* Setup MTRRs */
 	x86_setup_mtrrs();

diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c
@@ -14,7 +14,7 @@ static void model_68x_init(struct device *cpu)
 	char processor_name[49];
 
 	/* Turn on caching if we haven't already */
-	x86_enable_cache();
+	enable_cache();
 
 	/* Update the microcode */
 	intel_update_microcode_from_cbfs();

diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c
@@ -14,7 +14,7 @@ static void model_6bx_init(struct device *cpu)
 	char processor_name[49];
 
 	/* Turn on caching if we haven't already */
-	x86_enable_cache();
+	enable_cache();
 
 	/* Update the microcode */
 	intel_update_microcode_from_cbfs();

diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -97,7 +97,7 @@ static void model_6ex_init(struct device *cpu)
 	char processor_name[49];
 
 	/* Turn on caching if we haven't already */
-	x86_enable_cache();
+	enable_cache();
 
 	/* Print processor name */
 	fill_processor_name(processor_name);

diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -111,7 +111,7 @@ static void model_6fx_init(struct device *cpu)
 	char processor_name[49];
 
 	/* Turn on caching if we haven't already */
-	x86_enable_cache();
+	enable_cache();
 
 	/* Print processor name */
 	fill_processor_name(processor_name);

diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c
@@ -10,7 +10,7 @@
 static void model_6xx_init(struct device *dev)
 {
 	/* Turn on caching if we haven't already */
-	x86_enable_cache();
+	enable_cache();
 	x86_setup_mtrrs();
 	x86_mtrr_check();
 

diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c
@@ -12,7 +12,7 @@
 static void model_f2x_init(struct device *cpu)
 {
 	/* Turn on caching if we haven't already */
-	x86_enable_cache();
+	enable_cache();
 
 	if (!intel_ht_sibling()) {
 		/* MTRRs are shared between threads */

diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c
@@ -12,7 +12,7 @@
 static void model_f3x_init(struct device *cpu)
 {
 	/* Turn on caching if we haven't already */
-	x86_enable_cache();
+	enable_cache();
 
 	if (!CONFIG(PARALLEL_MP) && !intel_ht_sibling()) {
 		/* MTRRs are shared between threads */

diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c
@@ -8,7 +8,7 @@
 static void model_f4x_init(struct device *cpu)
 {
 	/* Turn on caching if we haven't already */
-	x86_enable_cache();
+	enable_cache();
 
 	/* Enable the local CPU APICs */
 	setup_lapic();

diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc
@@ -7,9 +7,6 @@ subdirs-y += ../model_65x
 subdirs-y += ../model_67x
 subdirs-y += ../model_68x
 subdirs-y += ../model_6bx
-subdirs-y += ../../x86/mtrr
-subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
 subdirs-y += ../microcode
 
 bootblock-y += ../car/p3/cache_as_ram.S

diff --git a/src/cpu/intel/socket_441/Makefile.inc b/src/cpu/intel/socket_441/Makefile.inc
@@ -1,7 +1,4 @@
 subdirs-y += ../model_106cx
-subdirs-y += ../../x86/mtrr
-subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
 subdirs-y += ../microcode
 subdirs-y += ../speedstep
 

diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc
@@ -1,7 +1,4 @@
 subdirs-y += ../model_1067x
-subdirs-y += ../../x86/mtrr
-subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
 subdirs-y += ../microcode
 subdirs-y += ../speedstep
 

diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc
@@ -1,7 +1,4 @@
 subdirs-y += ../model_106cx
-subdirs-y += ../../x86/mtrr
-subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
 subdirs-y += ../microcode
 subdirs-y += ../speedstep
 

diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig
@@ -8,8 +8,6 @@ config SOCKET_SPECIFIC_OPTIONS
 	select CPU_INTEL_MODEL_6FX
 	select CPU_INTEL_MODEL_F3X
 	select CPU_INTEL_MODEL_F4X
-#	select CPU_INTEL_MODEL_F6X
-#	select CPU_INTEL_MODEL_1066X
 	select CPU_INTEL_MODEL_1067X
 	select MMX
 	select SSE

diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc
@@ -1,12 +1,7 @@
 subdirs-y += ../model_6fx
 subdirs-y += ../model_f3x
 subdirs-y += ../model_f4x
-#subdirs-y += ../model_f6x
-#subdirs-y += ../model_1066x
 subdirs-y += ../model_1067x
-subdirs-y += ../../x86/mtrr
-subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
 subdirs-y += ../microcode
 subdirs-y += ../speedstep
 

diff --git a/src/cpu/intel/socket_m/Makefile.inc b/src/cpu/intel/socket_m/Makefile.inc
@@ -1,8 +1,6 @@
 subdirs-y += ../model_6ex
 subdirs-y += ../model_6fx
-subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
 subdirs-y += ../microcode
 subdirs-y += ../speedstep
 

diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc
@@ -1,7 +1,5 @@
 subdirs-y += ../model_f2x
-subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
 subdirs-y += ../microcode
 
 bootblock-y += ../car/p4-netburst/cache_as_ram.S

diff --git a/src/cpu/intel/socket_p/Makefile.inc b/src/cpu/intel/socket_p/Makefile.inc
@@ -1,8 +1,6 @@
 subdirs-y += ../model_6fx
 subdirs-y += ../model_1067x
-subdirs-y += ../../x86/mtrr
 subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
 subdirs-y += ../microcode
 subdirs-y += ../speedstep
 

diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
@@ -88,7 +88,7 @@ void generate_cpu_entries(const struct device *device)
 						       CPUs share the same
 						       layout. */
 	int num_cstates;
-	acpi_cstate_t *cstates;
+	const acpi_cstate_t *cstates;
 	sst_table_t pstates;
 	uint8_t coordination;
 

diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc
@@ -6,6 +6,3 @@ bootblock-y += bootblock.c
 romstage-y += ../intel/car/romstage.c
 
 ramstage-y += qemu.c
-
-subdirs-y += ../x86/mtrr
-subdirs-y += ../x86/lapic
diff --git a/src/cpu/x86/64bit/exit32.inc b/src/cpu/x86/64bit/exit32.inc
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 /*
- * For droping from long mode to protected mode.
+ * For dropping from long mode to protected mode.
  *
  * For reference see "AMD64 ArchitectureProgrammer's Manual Volume 2",
  * Document 24593-Rev. 3.31-July 2019 Chapter 5.3
@@ -47,7 +47,7 @@ SetCodeSelector32:
 
 	# use iret to jump to a 32-bit offset in a new code segment
 	# iret will pop cs:rip, flags, then ss:rsp
-	mov	%ss, %ax	# need to push ss, but push ss instuction
+	mov	%ss, %ax	# need to push ss, but push ss instruction
 	push	%rax		# not valid in x64 mode, so use ax
 	push	%rdx		# the rsp to load
 	pushfq			# push rflags

diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
@@ -2,6 +2,7 @@ config PARALLEL_MP
 	def_bool y
 	depends on !LEGACY_SMP_INIT
 	depends on SMP
+	select CPU_INFO_V2
 	help
 	 This option uses common MP infrastructure for bringing up APs
 	 in parallel. It additionally provides a more flexible mechanism
@@ -89,10 +90,6 @@ config SETUP_XIP_CACHE
 	  non-eviction mode and therefore need to be careful to avoid
 	  eviction.
 
-config CPU_ADDR_BITS
-	int
-	default 36
-
 config LOGICAL_CPUS
 	bool
 	default y
@@ -193,3 +190,11 @@ config RESERVE_MTRRS_FOR_OS
 	  the system BIOS and the last 2 are to be reserved for OS usage.
 	  However, modern OSes use PAT to control cacheability instead of
 	  using MTRRs.
+
+config CPU_INFO_V2
+	bool
+	depends on PARALLEL_MP
+	help
+	  Enables the new method of locating struct cpu_info. This new method
+	  uses the %gs segment to locate the cpu_info pointer. The old method
+	  relied on the stack being CONFIG_STACK_SIZE aligned.
diff --git a/src/cpu/x86/Kconfig.debug_cpu b/src/cpu/x86/Kconfig.debug_cpu
@@ -5,12 +5,8 @@ config DEBUG_CAR
 	bool "Output verbose Cache-as-RAM debug messages"
 	depends on HAVE_DEBUG_CAR
 
-config HAVE_DISPLAY_MTRRS
-	bool
-
 config DISPLAY_MTRRS
 	bool "Display intermediate MTRR settings"
-	depends on HAVE_DISPLAY_MTRRS
 
 config DEBUG_SMM_RELOCATION
 	bool "Debug SMM relocation code"

diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc
@@ -1,3 +1,5 @@
+subdirs-y += lapic
+subdirs-y += mtrr
 subdirs-y += pae
 subdirs-$(CONFIG_HAVE_SMI_HANDLER) += smm
 subdirs-$(CONFIG_UDELAY_TSC) += tsc

diff --git a/src/cpu/x86/cache/Makefile.inc b/src/cpu/x86/cache/Makefile.inc
diff --git a/src/cpu/x86/cache/cache.c b/src/cpu/x86/cache/cache.c
diff --git a/src/cpu/x86/cpu_info.S.inc b/src/cpu/x86/cpu_info.S.inc
@@ -1,10 +1,72 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+/*
+ * Pushes a 32-bit register onto the stack.
+ *
+ * There are two possible code sections where this code can be included:
+ *   .code32 and .code64
+ *
+ * Doing a `push %eax` while in a .code64 section will result in a compiler
+ * error. This macro manually pushes the 32-bit register onto the stack so we
+ * can share the code between 32 and 64 bit builds.
+ */
+.macro pushr reg:req
+#if ENV_X86_64
+	movl	$0, -4(%esp)
+	movl	\reg, -8(%esp)
+	sub	$8, %esp
+#else
+	push	\reg
+#endif
+.endm
+
 /* Push struct cpu_info */
 .macro push_cpu_info index=$0
-#if CONFIG(COOP_MULTITASKING)
-	push	$0	/* *thread */
-#endif
-	push	\index	/* index */
-	push	$0	/* *cpu */
+	pushr	\index	/* index (size_t) */
+	pushr	$0	/* *cpu */
+.endm
+
+/* Push struct per_cpu_segment_data */
+.macro push_per_cpu_segment_data cpu_info_pointer=%esp
+	pushr	\cpu_info_pointer	/* *cpu_info */
+.endm
+
+/*
+ * Sets the base address in the segment descriptor array.
+ *
+ * A segment descriptor has the following structure:
+ *     struct {
+ *         uint16_t segment_limit_0_15;
+ *         uint16_t base_address_0_15;
+ *         uint8_t base_address_16_23;
+ *         uint8_t attrs[2];
+ *         uint8_t base_address_24_31;
+ *     };
+ *
+ * @desc_array: Address of the descriptor table
+ * @base: Address to set in the descriptor
+ * @desc_index: Index of the descriptor in the table. Defaults to 0. Must be a
+ *              register if specified.
+ *
+ * Clobbers %eax, %ebx.
+ */
+.macro set_segment_descriptor_base desc_array:req, base:req, desc_index
+	mov	\base, %eax
+
+	mov	\desc_array, %ebx
+
+.ifb \desc_index
+	movw	%ax, 2(%ebx)
+	shr	$16, %eax
+	movb	%al, 4(%ebx)
+	shr	$8, %eax
+	movb	%al, 7(%ebx)
+.else
+	movw	%ax, 2(%ebx, \desc_index, 8)
+	shr	$16, %eax
+	movb	%al, 4(%ebx, \desc_index, 8)
+	shr	$8, %eax
+	movb	%al, 7(%ebx, \desc_index, 8)
+.endif
+
 .endm
diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c
@@ -5,17 +5,21 @@
 #include <cpu/x86/lapic_def.h>
 #include <cpu/x86/msr.h>
 #include <console/console.h>
+#include <smp/node.h>
 #include <stdint.h>
 
 void enable_lapic(void)
 {
 	msr_t msr;
+
 	msr = rdmsr(LAPIC_BASE_MSR);
 	msr.hi &= 0xffffff00;
 	msr.lo &= ~LAPIC_BASE_MSR_ADDR_MASK;
 	msr.lo |= LAPIC_DEFAULT_BASE;
 	msr.lo |= LAPIC_BASE_MSR_ENABLE;
 	wrmsr(LAPIC_BASE_MSR, msr);
+
+	printk(BIOS_INFO, "Setting up local APIC 0x%x\n", lapicid());
 }
 
 void disable_lapic(void)
@@ -39,45 +43,38 @@ static int need_lapic_init(void)
 
 static void lapic_virtual_wire_mode_init(void)
 {
-	/* this is so interrupts work. This is very limited scope --
-	 * linux will do better later, we hope ...
-	 */
-	/* this is the first way we learned to do it. It fails on real SMP
-	 * stuff. So we have to do things differently ...
-	 * see the Intel mp1.4 spec, page A-3
-	 */
-
-	printk(BIOS_INFO, "Setting up local APIC...\n");
-
-	/* Enable the local APIC */
-	enable_lapic();
-
 	/*
 	 * Set Task Priority to 'accept all'.
 	 */
 	lapic_update32(LAPIC_TASKPRI, ~LAPIC_TPRI_MASK, 0);
 
-	/* Put the local APIC in virtual wire mode */
+	/* Set spurious interrupt vector to 0 and keep LAPIC enabled to
+	   be able to clear LVT register mask bits. */
 	lapic_update32(LAPIC_SPIV, ~LAPIC_VECTOR_MASK, LAPIC_SPIV_ENABLE);
 
-	uint32_t mask = LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER | LAPIC_LVT_REMOTE_IRR |
-			LAPIC_INPUT_POLARITY | LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
+	/* Put the local APIC in virtual wire mode */
+	uint32_t mask = LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER | LAPIC_INPUT_POLARITY |
 			LAPIC_DELIVERY_MODE_MASK;
 
-	lapic_update32(LAPIC_LVT0, ~mask, LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
-					  LAPIC_DELIVERY_MODE_EXTINT);
-
-	lapic_update32(LAPIC_LVT1, ~mask, LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
-					  LAPIC_DELIVERY_MODE_NMI);
+	if (boot_cpu())
+		lapic_update32(LAPIC_LVT0, ~mask, LAPIC_DELIVERY_MODE_EXTINT);
+	else
+		lapic_update32(LAPIC_LVT0, ~mask, LAPIC_LVT_MASKED |
+						  LAPIC_DELIVERY_MODE_EXTINT);
 
-	printk(BIOS_DEBUG, " apic_id: 0x%x ", lapicid());
-	printk(BIOS_INFO, "done.\n");
+	lapic_update32(LAPIC_LVT1, ~mask, LAPIC_DELIVERY_MODE_NMI);
 }
 
 void setup_lapic(void)
 {
+	/* Enable the local APIC */
 	if (need_lapic_init())
-		lapic_virtual_wire_mode_init();
-	else
+		enable_lapic();
+	else if (!CONFIG(UDELAY_LAPIC))
 		disable_lapic();
+
+	/* This programming is for PIC mode i8259 interrupts to be delivered to CPU
+	   while LAPIC is enabled. */
+	if (need_lapic_init())
+		lapic_virtual_wire_mode_init();
 }
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -128,7 +128,7 @@ static int lapic_start_cpu(unsigned long apicid)
 		printk(BIOS_ERR, "ESR is 0x%x\n", lapic_read(LAPIC_ESR));
 		if (lapic_read(LAPIC_ESR)) {
 			printk(BIOS_ERR, "Try to reset ESR\n");
-			xapic_write_atomic(LAPIC_ESR, 0);
+			lapic_write(LAPIC_ESR, 0);
 			printk(BIOS_ERR, "ESR is 0x%x\n",
 				lapic_read(LAPIC_ESR));
 		}
@@ -253,7 +253,6 @@ static int start_cpu(struct device *cpu)
 	info->index = index;
 	info->cpu   = cpu;
 	cpu_add_map_entry(info->index);
-	thread_init_cpu_info_non_bsp(info);
 
 	/* Advertise the new stack and index to start_cpu */
 	secondary_stack = stack_top;

diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c
diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c
@@ -104,7 +104,7 @@ void paging_disable_pae(void)
  * Use PAE to map a page and then memset it with the pattern specified.
  * In order to use PAE pagetables for virtual addressing are set up and reloaded
  * on a 2MiB boundary. After the function is done, virtual addressing mode is
- * disabled again. The PAT are set to all cachable, but MTRRs still apply.
+ * disabled again. The PAT are set to all cacheable, but MTRRs still apply.
  *
  * Requires a scratch memory for pagetables and a virtual address for
  * non identity mapped memory.
@@ -124,7 +124,7 @@ void paging_disable_pae(void)
  *                  Content at physical address isn't preserved.
  * @param length    The length of the memory segment to memset
  * @param dest      Physical memory address to memset
- * @param pat       The pattern to write to the pyhsical memory
+ * @param pat       The pattern to write to the physical memory
  * @return 0 on success, 1 on error
  */
 int memset_pae(uint64_t dest, unsigned char pat, uint64_t length, void *pgtbl,

diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <cpu/x86/cpu_info.S.inc>
 #include <cpu/x86/cr.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/x86/msr.h>
@@ -19,6 +20,10 @@ gdtaddr:
 .word 0 /* unused */
 idt_ptr:
 .long 0
+per_cpu_segment_descriptors:
+.long 0
+per_cpu_segment_selector:
+.long 0
 stack_top:
 .long 0
 stack_size:
@@ -57,7 +62,7 @@ _start:
 	movw	%cs, %ax
 	movw	%ax, %ds
 
-	/* The gdtaddr needs to be releative to the data segment in order
+	/* The gdtaddr needs to be relative to the data segment in order
 	 * to properly dereference it. The .text section comes first in an
 	 * rmodule so _start can be used as a proxy for the load address. */
 	movl	$(gdtaddr), %ebx
@@ -98,10 +103,20 @@ _start:
 	movl	stack_top, %edx
 	subl	%eax, %edx
 	mov	%edx, %esp
-	andl	$0xfffffff0, %esp /* ensure stack alignment */
 
-	/* Save CPU number. */
-	mov	%ecx, %esi
+	push_cpu_info index=%ecx
+	push_per_cpu_segment_data
+
+	/*
+	 * Update the AP's per_cpu_segment_descriptor to point to the
+	 * per_cpu_segment_data that was allocated on the stack.
+	 */
+	set_segment_descriptor_base per_cpu_segment_descriptors, %esp, %ecx
+
+	mov	%ecx, %eax
+	shl	$3, %eax /* The index is << 3 in the segment selector */
+	add	per_cpu_segment_selector, %eax
+	mov	%eax, %gs
 
 	/*
 	 * The following code only needs to run on Intel platforms and thus the caller
@@ -215,19 +230,15 @@ load_msr:
 	mov	%eax, %cr4
 #endif
 
+	andl	$0xfffffff0, %esp /* ensure stack alignment */
+
 #if ENV_X86_64
 	/* entry64.inc preserves ebx. */
 #include <cpu/x86/64bit/entry64.inc>
 
-	mov	%rsi, %rdi	/* cpu_num */
-
 	movabs	c_handler, %eax
 	call	*%rax
 #else
-	/* c_handler(cpu_num), preserve proper stack alignment */
-	sub	$12, %esp
-	push	%esi	/* cpu_num */
-
 	mov	c_handler, %eax
 	call	*%eax
 #endif

diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S
@@ -95,7 +95,7 @@ smm_trampoline32:
 	movw	%ax, %ss
 	xor	%ax, %ax /* zero out the gs and fs segment index */
 	movw	%ax, %fs
-	movw	%ax, %gs /* Will be used for cpu_info */
+	movw	%ax, %gs /* Used by cpu_info in ramstage */
 
 	/* The CPU number is calculated by reading the initial APIC id. Since
 	 * the OS can manipulate the APIC id use the non-changing cpuid result

diff --git a/src/device/Kconfig b/src/device/Kconfig
@@ -166,7 +166,7 @@ config ALWAYS_RUN_OPROM
 	def_bool n
 	depends on VGA_ROM_RUN && ALWAYS_LOAD_OPROM
 	help
-	  Always uncondtionally run the option regardless of other
+	  Always unconditionally run the option regardless of other
 	  policies.
 
 config ON_DEVICE_ROM_LOAD
@@ -499,13 +499,21 @@ config PCI
 
 if PCI
 
-config NO_MMCONF_SUPPORT
+config NO_ECAM_MMCONF_SUPPORT
 	bool
 	default n
+	help
+	  Disable the use of the Enhanced Configuration
+	  Access mechanism (ECAM) method for accessing PCI config
+	  address space.
 
-config MMCONF_SUPPORT
+config ECAM_MMCONF_SUPPORT
 	bool
-	default !NO_MMCONF_SUPPORT
+	default !NO_ECAM_MMCONF_SUPPORT
+	help
+	  Enable the use of the Enhanced Configuration
+	  Access mechanism (ECAM) method for accessing PCI config
+	  address space.
 
 config PCIX_PLUGIN_SUPPORT
 	bool
@@ -540,20 +548,20 @@ config PCIEXP_PLUGIN_SUPPORT
 	bool
 	default y
 
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
 	hex
-	depends on MMCONF_SUPPORT
+	depends on ECAM_MMCONF_SUPPORT
 
-config MMCONF_BUS_NUMBER
+config ECAM_MMCONF_BUS_NUMBER
 	int
-	depends on MMCONF_SUPPORT
+	depends on ECAM_MMCONF_SUPPORT
 
-config MMCONF_LENGTH
+config ECAM_MMCONF_LENGTH
 	hex
-	depends on MMCONF_SUPPORT
-	default 0x04000000 if MMCONF_BUS_NUMBER = 64
-	default 0x08000000 if MMCONF_BUS_NUMBER = 128
-	default 0x10000000 if MMCONF_BUS_NUMBER = 256
+	depends on ECAM_MMCONF_SUPPORT
+	default 0x04000000 if ECAM_MMCONF_BUS_NUMBER = 64
+	default 0x08000000 if ECAM_MMCONF_BUS_NUMBER = 128
+	default 0x10000000 if ECAM_MMCONF_BUS_NUMBER = 256
 	default 0x0
 
 config PCI_ALLOW_BUS_MASTER
@@ -619,7 +627,7 @@ config PCIEXP_CLK_PM
 config PCIEXP_L1_SUB_STATE
 	prompt "Enable PCIe ASPM L1 SubState"
 	bool
-	depends on (MMCONF_SUPPORT || PCI_IO_CFG_EXT)
+	depends on (ECAM_MMCONF_SUPPORT || PCI_IO_CFG_EXT)
 	default n
 	help
 	  Detect and enable ASPM on PCIe links.
@@ -635,8 +643,8 @@ if PCIEXP_HOTPLUG
 
 config PCIEXP_HOTPLUG_BUSES
 	int "PCI Express Hotplug Buses"
-	default  8 if MMCONF_SUPPORT && MMCONF_BUS_NUMBER <=  64
-	default 16 if MMCONF_SUPPORT && MMCONF_BUS_NUMBER <= 128
+	default  8 if ECAM_MMCONF_SUPPORT && ECAM_MMCONF_BUS_NUMBER <=  64
+	default 16 if ECAM_MMCONF_SUPPORT && ECAM_MMCONF_BUS_NUMBER <= 128
 	default 32
 	help
 	  This is the number of buses allocated for hotplug PCI express

diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c
@@ -227,7 +227,7 @@ __weak void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid)
 {
 }
 
-static void codec_init(struct device *dev, u8 *base, int addr)
+void azalia_codec_init(u8 *base, int addr, const u32 *verb_table, u32 verb_table_bytes)
 {
 	u32 reg32;
 	const u32 *verb;
@@ -252,7 +252,7 @@ static void codec_init(struct device *dev, u8 *base, int addr)
 	/* 2 */
 	reg32 = read32(base + HDA_IR_REG);
 	printk(BIOS_DEBUG, "azalia_audio: codec viddid: %08x\n", reg32);
-	verb_size = azalia_find_verb(cim_verb_data, cim_verb_data_size, reg32, &verb);
+	verb_size = azalia_find_verb(verb_table, verb_table_bytes, reg32, &verb);
 
 	if (!verb_size) {
 		printk(BIOS_DEBUG, "azalia_audio: No verb!\n");
@@ -261,19 +261,22 @@ static void codec_init(struct device *dev, u8 *base, int addr)
 	printk(BIOS_DEBUG, "azalia_audio: verb_size: %u\n", verb_size);
 
 	/* 3 */
-	azalia_program_verb_table(base, verb, verb_size);
-	printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n");
+	const int rc = azalia_program_verb_table(base, verb, verb_size);
+	if (rc < 0)
+		printk(BIOS_DEBUG, "azalia_audio: verb not loaded.\n");
+	else
+		printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n");
 
 	mainboard_azalia_program_runtime_verbs(base, reg32);
 }
 
-static void codecs_init(struct device *dev, u8 *base, u16 codec_mask)
+void azalia_codecs_init(u8 *base, u16 codec_mask)
 {
 	int i;
 
 	for (i = CONFIG_AZALIA_MAX_CODECS - 1; i >= 0; i--) {
 		if (codec_mask & (1 << i))
-			codec_init(dev, base, i);
+			azalia_codec_init(base, i, cim_verb_data, cim_verb_data_size);
 	}
 
 	azalia_program_verb_table(base, pc_beep_verbs, pc_beep_verbs_size);
@@ -285,19 +288,19 @@ void azalia_audio_init(struct device *dev)
 	struct resource *res;
 	u16 codec_mask;
 
-	res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	res = probe_resource(dev, PCI_BASE_ADDRESS_0);
 	if (!res)
 		return;
 
-	// NOTE this will break as soon as the azalia_audio get's a bar above 4G.
+	// NOTE this will break as soon as the azalia_audio gets a bar above 4G.
 	// Is there anything we can do about it?
 	base = res2mmio(res, 0, 0);
 	printk(BIOS_DEBUG, "azalia_audio: base = %p\n", base);
 	codec_mask = codec_detect(base);
 
 	if (codec_mask) {
 		printk(BIOS_DEBUG, "azalia_audio: codec_mask = %02x\n", codec_mask);
-		codecs_init(dev, base, codec_mask);
+		azalia_codecs_init(base, codec_mask);
 	}
 }
 

diff --git a/src/device/device_util.c b/src/device/device_util.c
@@ -857,8 +857,8 @@ void fixed_io_resource(struct device *dev, unsigned long index,
 void mmconf_resource(struct device *dev, unsigned long index)
 {
 	struct resource *resource = new_resource(dev, index);
-	resource->base = CONFIG_MMCONF_BASE_ADDRESS;
-	resource->size = CONFIG_MMCONF_LENGTH;
+	resource->base = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
+	resource->size = CONFIG_ECAM_MMCONF_LENGTH;
 	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
 		IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 

diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c
@@ -545,19 +545,19 @@ enum cb_err spd_add_smbios17(const u8 channel, const u8 slot,
 
 		switch (info->dimm_type) {
 		case SPD_DDR3_DIMM_TYPE_SO_DIMM:
-			dimm->mod_type = SPD_SODIMM;
+			dimm->mod_type = DDR3_SPD_SODIMM;
 			break;
 		case SPD_DDR3_DIMM_TYPE_72B_SO_CDIMM:
-			dimm->mod_type = SPD_72B_SO_CDIMM;
+			dimm->mod_type = DDR3_SPD_72B_SO_CDIMM;
 			break;
 		case SPD_DDR3_DIMM_TYPE_72B_SO_RDIMM:
-			dimm->mod_type = SPD_72B_SO_RDIMM;
+			dimm->mod_type = DDR3_SPD_72B_SO_RDIMM;
 			break;
 		case SPD_DDR3_DIMM_TYPE_UDIMM:
-			dimm->mod_type = SPD_UDIMM;
+			dimm->mod_type = DDR3_SPD_UDIMM;
 			break;
 		case SPD_DDR3_DIMM_TYPE_RDIMM:
-			dimm->mod_type = SPD_RDIMM;
+			dimm->mod_type = DDR3_SPD_RDIMM;
 			break;
 		case SPD_DDR3_DIMM_TYPE_UNDEFINED:
 		default:

diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c
@@ -205,7 +205,7 @@ int spd_decode_ddr4(struct dimm_attr_ddr4_st *dimm, spd_raw_data spd)
 
 	/* Verify CRC of blocks that have them, do not step over 'used' length */
 	for (int i = 0; i < ARRAY_SIZE(spd_blocks); i++) {
-		/* this block is not checksumed */
+		/* this block is not checksummed */
 		if (spd_blocks[i].crc_start == 0)
 			continue;
 		/* we shouldn't have this block */
@@ -299,16 +299,16 @@ enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot, const u16 sel
 
 		switch (info->dimm_type) {
 		case SPD_DDR4_DIMM_TYPE_SO_DIMM:
-			dimm->mod_type = SPD_SODIMM;
+			dimm->mod_type = DDR4_SPD_SODIMM;
 			break;
 		case SPD_DDR4_DIMM_TYPE_72B_SO_RDIMM:
-			dimm->mod_type = SPD_72B_SO_RDIMM;
+			dimm->mod_type = DDR4_SPD_72B_SO_RDIMM;
 			break;
 		case SPD_DDR4_DIMM_TYPE_UDIMM:
-			dimm->mod_type = SPD_UDIMM;
+			dimm->mod_type = DDR4_SPD_UDIMM;
 			break;
 		case SPD_DDR4_DIMM_TYPE_RDIMM:
-			dimm->mod_type = SPD_RDIMM;
+			dimm->mod_type = DDR4_SPD_RDIMM;
 			break;
 		default:
 			dimm->mod_type = SPD_UNDEFINED;

diff --git a/src/device/dram/spd.c b/src/device/dram/spd.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <device/dram/spd.h>
+#include <spd.h>
 
 const char *spd_manufacturer_name(const uint16_t mod_id)
 {
@@ -38,3 +39,219 @@ const char *spd_manufacturer_name(const uint16_t mod_id)
 		return NULL;
 	}
 }
+
+static void convert_default_module_type_to_spd_info(struct spd_info *info)
+{
+	info->form_factor = MEMORY_FORMFACTOR_UNKNOWN;
+	info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
+}
+
+static void convert_ddr2_module_type_to_spd_info(enum ddr2_module_type module_type,
+		struct spd_info *info)
+{
+	switch (module_type) {
+	case DDR2_SPD_RDIMM:
+	case DDR2_SPD_MINI_RDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_RIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED;
+		break;
+	case DDR2_SPD_UDIMM:
+	case DDR2_SPD_MINI_UDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_DIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED;
+		break;
+	case DDR2_SPD_MICRO_DIMM:
+		info->form_factor = MEMORY_FORMFACTOR_DIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
+		break;
+	case DDR2_SPD_SODIMM:
+		info->form_factor = MEMORY_FORMFACTOR_SODIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
+		break;
+	default:
+		convert_default_module_type_to_spd_info(info);
+		break;
+	}
+}
+
+static void convert_ddr3_module_type_to_spd_info(enum ddr3_module_type module_type,
+		struct spd_info *info)
+{
+	switch (module_type) {
+	case DDR3_SPD_RDIMM:
+	case DDR3_SPD_MINI_RDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_RIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED;
+		break;
+	case DDR3_SPD_UDIMM:
+	case DDR3_SPD_MINI_UDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_DIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED;
+		break;
+	case DDR3_SPD_MICRO_DIMM:
+		info->form_factor = MEMORY_FORMFACTOR_DIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
+		break;
+	case DDR3_SPD_SODIMM:
+	case DDR3_SPD_72B_SO_UDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_SODIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
+		break;
+	default:
+		convert_default_module_type_to_spd_info(info);
+		break;
+	}
+}
+
+static void convert_ddr4_module_type_to_spd_info(enum ddr4_module_type module_type,
+		struct spd_info *info)
+{
+	switch (module_type) {
+	case DDR4_SPD_RDIMM:
+	case DDR4_SPD_MINI_RDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_RIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED;
+		break;
+	case DDR4_SPD_UDIMM:
+	case DDR4_SPD_MINI_UDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_DIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED;
+		break;
+	case DDR4_SPD_SODIMM:
+	case DDR4_SPD_72B_SO_UDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_SODIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
+		break;
+	default:
+		convert_default_module_type_to_spd_info(info);
+		break;
+	}
+}
+
+static void convert_ddr5_module_type_to_spd_info(enum ddr5_module_type module_type,
+		struct spd_info *info)
+{
+	switch (module_type) {
+	case DDR5_SPD_RDIMM:
+	case DDR5_SPD_MINI_RDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_RIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED;
+		break;
+	case DDR5_SPD_UDIMM:
+	case DDR5_SPD_MINI_UDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_DIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED;
+		break;
+	case DDR5_SPD_SODIMM:
+	case DDR5_SPD_72B_SO_UDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_SODIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
+		break;
+	case DDR5_SPD_2DPC:
+		info->form_factor = MEMORY_FORMFACTOR_PROPRIETARY_CARD;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
+		break;
+	default:
+		convert_default_module_type_to_spd_info(info);
+		break;
+	}
+}
+
+static void convert_lpx_module_type_to_spd_info(enum lpx_module_type module_type,
+		struct spd_info *info)
+{
+	switch (module_type) {
+	case LPX_SPD_NONDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_ROC;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
+		break;
+	default:
+		convert_default_module_type_to_spd_info(info);
+		break;
+	}
+}
+
+void get_spd_info(smbios_memory_type memory_type, uint8_t module_type, struct spd_info *info)
+{
+	switch (memory_type) {
+	case MEMORY_TYPE_DDR2:
+		convert_ddr2_module_type_to_spd_info(module_type, info);
+		break;
+	case MEMORY_TYPE_DDR3:
+		convert_ddr3_module_type_to_spd_info(module_type, info);
+		break;
+	case MEMORY_TYPE_DDR4:
+		convert_ddr4_module_type_to_spd_info(module_type, info);
+		break;
+	case MEMORY_TYPE_DDR5:
+		convert_ddr5_module_type_to_spd_info(module_type, info);
+		break;
+	case MEMORY_TYPE_LPDDR3:
+	case MEMORY_TYPE_LPDDR4:
+	case MEMORY_TYPE_LPDDR5:
+		convert_lpx_module_type_to_spd_info(module_type, info);
+		break;
+	default:
+		convert_default_module_type_to_spd_info(info);
+		break;
+	}
+}
+
+static uint8_t convert_default_form_factor_to_module_type(void)
+{
+	return SPD_UNDEFINED;
+}
+
+static uint8_t convert_ddrx_form_factor_to_module_type(smbios_memory_type memory_type,
+		smbios_memory_form_factor form_factor)
+{
+	uint8_t module_type;
+
+	switch (form_factor) {
+	case MEMORY_FORMFACTOR_DIMM:
+		return DDR2_SPD_UDIMM;
+	case MEMORY_FORMFACTOR_RIMM:
+		return DDR2_SPD_RDIMM;
+	case MEMORY_FORMFACTOR_SODIMM:
+		module_type = (memory_type == MEMORY_TYPE_DDR2) ? DDR2_SPD_SODIMM
+				: DDR3_SPD_SODIMM;
+		return module_type;
+	default:
+		return convert_default_form_factor_to_module_type();
+	}
+}
+
+static uint8_t convert_lpx_form_factor_to_module_type(smbios_memory_form_factor form_factor)
+{
+	switch (form_factor) {
+	case MEMORY_FORMFACTOR_ROC:
+		return LPX_SPD_NONDIMM;
+	default:
+		return convert_default_form_factor_to_module_type();
+	}
+}
+
+uint8_t convert_form_factor_to_module_type(smbios_memory_type memory_type,
+		smbios_memory_form_factor form_factor)
+{
+	uint8_t module_type;
+
+	switch (memory_type) {
+	case MEMORY_TYPE_DDR2:
+	case MEMORY_TYPE_DDR3:
+	case MEMORY_TYPE_DDR4:
+	case MEMORY_TYPE_DDR5:
+		module_type = convert_ddrx_form_factor_to_module_type(memory_type, form_factor);
+		break;
+	case MEMORY_TYPE_LPDDR3:
+	case MEMORY_TYPE_LPDDR4:
+	case MEMORY_TYPE_LPDDR5:
+		module_type = convert_lpx_form_factor_to_module_type(form_factor);
+		break;
+	default:
+		module_type = convert_default_form_factor_to_module_type();
+		break;
+	}
+
+	return module_type;
+}
diff --git a/src/device/oprom/include/x86emu/regs.h b/src/device/oprom/include/x86emu/regs.h
@@ -54,7 +54,7 @@
  * EAX & 0xff  === AL
  * EAX & 0xffff == AX
  *
- * etc.  The result is that alot of the calculations can then be
+ * etc.  The result is that a lot of the calculations can then be
  * done using the native instruction set fully.
  */
 

diff --git a/src/device/oprom/x86emu/LICENSE b/src/device/oprom/x86emu/LICENSE
@@ -1,7 +1,7 @@
                          License information
                          -------------------
 
-The x86emu library is under a BSD style license, comaptible
+The x86emu library is under a BSD style license, compatible
 with the XFree86 and X licenses used by XFree86. The
 original x86emu libraries were under the GNU General Public
 License. Due to license incompatibilities between the GPL

diff --git a/src/device/oprom/x86emu/prim_ops.c b/src/device/oprom/x86emu/prim_ops.c
@@ -2458,7 +2458,7 @@ void x86emu_cpuid(void)
     switch (feature) {
     case 0:
         /* Regardless if we have real data from the hardware, the emulator
-         * will only support upto feature 1, which we set in register EAX.
+         * will only support up to feature 1, which we set in register EAX.
          * Registers EBX:EDX:ECX contain a string identifying the CPU.
          */
         M.x86.R_EAX = 1;

diff --git a/src/device/pci_early.c b/src/device/pci_early.c
@@ -104,7 +104,7 @@ void pci_early_bridge_init(void)
 }
 
 /* FIXME: A lot of issues using the following, please avoid.
- * Assumes 256 PCI busses, scans them all even when PCI bridges are still
+ * Assumes 256 PCI buses, scans them all even when PCI bridges are still
  * disabled. Probes all functions even if 0 is not present.
  */
 pci_devfn_t pci_locate_device(unsigned int pci_id, pci_devfn_t dev)

diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c
@@ -7,7 +7,7 @@
 #include <device/pci_ops.h>
 #include <device/pci_type.h>
 
-u8 *const pci_mmconf = (void *)(uintptr_t)CONFIG_MMCONF_BASE_ADDRESS;
+u8 *const pci_mmconf = (void *)(uintptr_t)CONFIG_ECAM_MMCONF_BASE_ADDRESS;
 
 /**
  * Given a device, a capability type, and a last position, return the next

diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c
@@ -16,6 +16,21 @@
 void __weak map_oprom_vendev_rev(u32 *vendev, u8 *rev) { return; }
 u32 __weak map_oprom_vendev(u32 vendev) { return vendev; }
 
+void vga_oprom_preload(void)
+{
+/* The CONFIG_VGA_BIOS_ID symbol is only defined when VGA_BIOS is selected */
+#if CONFIG(VGA_BIOS)
+	const char name[] = "pci" CONFIG_VGA_BIOS_ID ".rom";
+
+	if (!CONFIG(CBFS_PRELOAD))
+		return;
+
+	printk(BIOS_DEBUG, "Preloading VGA ROM %s\n", name);
+
+	cbfs_preload(name);
+#endif
+}
+
 static void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device)
 {
 	char name[17] = "pciXXXX,XXXX.rom";

diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c
@@ -238,7 +238,7 @@ static void pnp_get_ioresource(struct device *dev, u8 index, u16 mask)
 	resource->limit = (1 << (bit + 1)) - 1;
 
 	/* The block of ones in the mask is expected to be continuous.
-	   If there is any zero inbetween the block of ones, it is ignored
+	   If there is any zero in between the block of ones, it is ignored
 	   in the calculation of the resource size and limit. */
 	if (mask != (resource->limit ^ (resource->size - 1)))
 		printk(BIOS_WARNING,

diff --git a/src/device/resource_allocator_v4.c b/src/device/resource_allocator_v4.c
@@ -637,7 +637,7 @@ static void allocate_domain_resources(const struct device *domain)
  * order to accomplish best fit for the resources, a list of ranges is maintained by each
  * resource type (i/o and mem). Domain does not differentiate between mem and prefmem. Since
  * they are allocated space from the same window, the resource allocator at the domain level
- * ensures that the biggest requirement is selected indepedent of the prefetch type. Once the
+ * ensures that the biggest requirement is selected independent of the prefetch type. Once the
  * resource allocation for all immediate downstream devices is complete at the domain level,
  * resource allocator walks down the subtree for each downstream bridge to continue the
  * allocation process at the bridge level. Since bridges have separate windows for i/o, mem and

diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S
@@ -5,7 +5,7 @@
  *
  * $Workfile:: cache_as_ram.S
  *
- * Description: cache_as_ram.S - AGESA Module Entry Point for GCC complier
+ * Description: cache_as_ram.S - AGESA Module Entry Point for GCC compiler
  *
  ******************************************************************************
  */

diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c
@@ -36,22 +36,18 @@ static void romstage_main(void)
 	struct postcar_frame pcf;
 	struct sysinfo romstage_state;
 	struct sysinfo *cb = &romstage_state;
-	unsigned int initial_apic_id = initial_lapicid();
 	int cbmem_initted = 0;
 
 	fill_sysinfo(cb);
 
-	if (initial_apic_id == 0) {
+	timestamp_add_now(TS_START_ROMSTAGE);
 
-		timestamp_add_now(TS_START_ROMSTAGE);
+	board_BeforeAgesa(cb);
 
-		board_BeforeAgesa(cb);
-
-		console_init();
-	}
+	console_init();
 
 	printk(BIOS_DEBUG, "APIC %02u: CPU Family_Model = %08x\n",
-		initial_apic_id, cpuid_eax(1));
+	       initial_lapicid(), cpuid_eax(1));
 
 	set_ap_entry_ptr(ap_romstage_main);
 

diff --git a/src/drivers/aspeed/common/ast_mode_corebootfb.c b/src/drivers/aspeed/common/ast_mode_corebootfb.c
@@ -22,7 +22,7 @@ int ast_crtc_do_set_base(struct drm_crtc *crtc)
 	struct drm_framebuffer *fb = crtc->primary->fb;
 
 	/* PCI BAR 0 */
-	struct resource *res = find_resource(crtc->dev->pdev, PCI_BASE_ADDRESS_0);
+	struct resource *res = probe_resource(crtc->dev->pdev, PCI_BASE_ADDRESS_0);
 	if (!res) {
 		printk(BIOS_ERR, "BAR0 resource not found.\n");
 		return -EIO;

diff --git a/src/drivers/crb/tpm.c b/src/drivers/crb/tpm.c
@@ -6,7 +6,7 @@
  *
  * TPM starts in IDLE Mode
  *
- *   IDLE  --> READY --> Command Receiption
+ *   IDLE  --> READY --> Command Reception
  *    ^	                        |
  *    |	                        v
       -- Cmd Complete <-- Command Execution

diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c
@@ -16,6 +16,7 @@
 #include <smbios.h>
 #include <stdint.h>
 #include <string.h>
+#include <timestamp.h>
 
 #define ELOG_MIN_AVAILABLE_ENTRIES	2  /* Shrink when this many can't fit */
 #define ELOG_SHRINK_PERCENTAGE		25 /* Percent of total area to remove */
@@ -749,6 +750,9 @@ int elog_init(void)
 	}
 	elog_state.elog_initialized = ELOG_BROKEN;
 
+	if (!ENV_SMM)
+		timestamp_add_now(TS_ELOG_INIT_START);
+
 	elog_debug("%s()\n", __func__);
 
 	/* Set up the backing store */
@@ -781,6 +785,10 @@ int elog_init(void)
 
 	if (ENV_PAYLOAD_LOADER)
 		elog_add_boot_count();
+
+	if (!ENV_SMM)
+		timestamp_add_now(TS_ELOG_INIT_END);
+
 	return 0;
 }
 

diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c
@@ -2,6 +2,7 @@
 
 #include <stdint.h>
 #include <arch/io.h>
+#include <arch/mmio.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>

diff --git a/src/drivers/generic/gpio_keys/chip.h b/src/drivers/generic/gpio_keys/chip.h
@@ -81,7 +81,7 @@ struct drivers_generic_gpio_keys_config {
 	struct acpi_gpio gpio;
 	/* Is this a polled GPIO button? - Optional */
 	bool is_polled;
-	/* Poll inverval - Mandatory only if GPIO is polled. */
+	/* Poll interval - Mandatory only if GPIO is polled. */
 	uint32_t poll_interval;
 	/* Details about the key - Mandatory */
 	struct key_info key;

diff --git a/src/drivers/generic/ioapic/chip.h b/src/drivers/generic/ioapic/chip.h
@@ -6,7 +6,6 @@
 typedef struct drivers_generic_ioapic_config {
 	u32 version;
 	u8 apicid;
-	u8 enable_virtual_wire;
 	u8 have_isa_interrupts;
 	void *base;
 } ioapic_config_t;

diff --git a/src/drivers/generic/ioapic/ioapic.c b/src/drivers/generic/ioapic/ioapic.c
@@ -13,7 +13,7 @@ static void ioapic_init(struct device *dev)
 	if (!dev->enabled || !config)
 		return;
 
-	setup_ioapic_helper(config->base, config->apicid, config->enable_virtual_wire);
+	setup_ioapic(config->base, config->apicid);
 }
 
 static void ioapic_read_resources(struct device *dev)

diff --git a/src/drivers/i2c/lm96000/chip.h b/src/drivers/i2c/lm96000/chip.h
@@ -90,7 +90,7 @@ struct lm96000_temp_zone {
 	enum {
 		/* turn fan off below `low_temp - hysteresis` */
 		LM96000_LOW_TEMP_OFF = 0,
-		/* keep PWM at mininum duty cycle */
+		/* keep PWM at minimum duty cycle */
 		LM96000_LOW_TEMP_MIN = 1,
 	} min_off;
 	u8 hysteresis;

diff --git a/src/drivers/i2c/nct7802y/chip.h b/src/drivers/i2c/nct7802y/chip.h
@@ -37,7 +37,7 @@ enum nct7802y_fan_mode {
 
 enum nct7802y_fan_smartmode {
 	SMART_FAN_DUTY = 0,	/* Target values given in duty cycle %. */
-	SMART_FAN_RPM,		/* Target valuse given in RPM. */
+	SMART_FAN_RPM,		/* Target values given in RPM. */
 };
 
 enum nct7802y_fan_speed {

diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c
@@ -3,7 +3,7 @@
 /* Based on Linux Kernel TPM driver */
 
 /*
- * cr50 is a TPM 2.0 capable device that requries special
+ * cr50 is a TPM 2.0 capable device that requires special
  * handling for the I2C interface.
  *
  * - Use an interrupt for transaction status instead of hardcoded delays

diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c
@@ -35,7 +35,7 @@
 
 /* max. number of iterations after I2C NAK for 'long' commands
  * we need this especially for sending TPM_READY, since the cleanup after the
- * transtion to the ready state may take some time, but it is unpredictable
+ * transition to the ready state may take some time, but it is unpredictable
  * how long it will take.
  */
 #define MAX_COUNT_LONG 50

diff --git a/src/drivers/i2c/ww_ring/ww_ring_programs.c b/src/drivers/i2c/ww_ring/ww_ring_programs.c
@@ -91,7 +91,7 @@ static const TiLp55231Program solid_000000_program = {
  *
  * When solid patterns are deployed with instanteneous color intensity
  * changes, all three LEDs can be controlled by one engine in sequential
- * accesses. But the controllers still neeed to be synchronized.
+ * accesses. But the controllers still need to be synchronized.
  *
  * The maximum timer duration of lp55231 is .48 seconds. To achieve longer
  * blinking intervals the loops delays are deployed. Only the first controller

diff --git a/src/drivers/i2c/ww_ring/ww_ring_programs.h b/src/drivers/i2c/ww_ring/ww_ring_programs.h
@@ -21,15 +21,15 @@
 #include <stdint.h>
 #include "drivers/i2c/ww_ring/ww_ring.h"
 
-/* There are threee independent engines/cores in the controller. */
+/* There are three independent engines/cores in the controller. */
 #define LP55231_NUM_OF_ENGINES 3
 
 /* Number of lp55321 controllers on the ring */
 #define WW_RING_NUM_LED_CONTROLLERS 1
 
 /*
  * Structure to describe an lp55231 program: pointer to the text of the
- * program, its size and load address (load addr + size sould not exceed
+ * program, its size and load address (load addr + size should not exceed
  * LP55231_MAX_PROG_SIZE), and start addresses for all of the three
  * engines.
  */

diff --git a/src/drivers/intel/dptf/dptf.c b/src/drivers/intel/dptf/dptf.c
@@ -5,16 +5,21 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <intelblocks/pmc_ipc.h>
+#include <soc/pci_devs.h>
 #include "chip.h"
 #include "dptf.h"
 
 /* Generic DPTF participants have a PTYP field to distinguish them */
 enum dptf_generic_participant_type {
 	DPTF_GENERIC_PARTICIPANT_TYPE_TSR	= 0x3,
+	DPTF_GENERIC_PARTICIPANT_TYPE_TPCH	= 0x5,
 	DPTF_GENERIC_PARTICIPANT_TYPE_CHARGER	= 0xB,
 };
 
 #define DEFAULT_CHARGER_STR		"Battery Charger"
+#define DEFAULT_TPCH_STR		"Intel PCH FIVR Participant"
+
+#define PMC_IPC_COMMAND_FIVR_SIZE	0x8
 
 /*
  * Helper method to determine if a device is "used" (called out anywhere as a source or a target
@@ -195,45 +200,170 @@ static void write_generic_devices(const struct drivers_intel_dptf_config *config
 	}
 }
 
-/* \_SB.DPTF.TPCH.RFC methods */
-static void write_tpch_rfc_methods(const char *tpch_rfc_method_name,
+static const char *get_pmc_ipcs_method(void)
+{
+	const char *method = acpi_device_path_join(
+				pcidev_path_on_root(PCH_DEVFN_PMC), "IPCS");
+	if (!method) {
+		printk(BIOS_ERR, "%s: Unable to find PMC device IPCS method\n", __func__);
+		return NULL;
+	}
+	return method;
+}
+
+static void write_tpch_write_method(const char *tpch_write_method_name,
 				unsigned int ipc_subcmd_ctrl_value)
 {
-	acpigen_write_method_serialized(tpch_rfc_method_name, 1);
-	acpigen_emit_namestring("IPCS");
+	/* Get IPCS method from the PMC device */
+	const char *ipcs = get_pmc_ipcs_method();
+	acpigen_write_method_serialized(tpch_write_method_name, 1);
+	acpigen_emit_namestring(ipcs);
 	acpigen_write_integer(PMC_IPC_CMD_COMMAND_FIVR);
 	acpigen_write_integer(PMC_IPC_CMD_CMD_ID_FIVR_WRITE);
-	acpigen_write_integer(0x8);
+	acpigen_write_integer(PMC_IPC_COMMAND_FIVR_SIZE);
 	acpigen_write_integer(ipc_subcmd_ctrl_value);
 	acpigen_emit_byte(ARG0_OP);
-	acpigen_write_dword(0);
-	acpigen_write_dword(0);
+	acpigen_write_zero();
+	acpigen_write_zero();
 	/* The reason for returning a value here is a W/A for the ESIF shell */
 	acpigen_emit_byte(RETURN_OP);
-	acpigen_write_package(0);
+	acpigen_write_package(1);
+	acpigen_write_zero();
 	acpigen_write_package_end();
 	acpigen_write_method_end();
 }
 
+static void write_ppkg_package(const uint8_t i)
+{
+	acpigen_write_store();
+	acpigen_emit_byte(DEREF_OP);
+	acpigen_emit_byte(INDEX_OP);
+	acpigen_emit_byte(ARG0_OP);
+	acpigen_write_integer(i);
+	acpigen_emit_byte(ZERO_OP);
+	acpigen_emit_byte(INDEX_OP);
+	acpigen_emit_namestring("PPKG");
+	acpigen_write_integer(i);
+	acpigen_emit_byte(ZERO_OP);
+}
+
+/*
+ * Truncate Package received from IPC
+ * Arguments:
+ *  Arg0: Package returned from the IPCS read call from the Pmc
+ * Return Value:
+ *  Return Package with just the Status and ReadBuf0
+ *  Status returns 0 for success and 2 for device error
+ */
+static void write_pkgc_method(void)
+{
+	acpigen_write_method_serialized("PKGC", 1);
+	acpigen_write_name("PPKG");
+	acpigen_write_package(2);
+	acpigen_write_zero();
+	acpigen_write_zero();
+	acpigen_write_package_end();
+
+	write_ppkg_package(0);
+	write_ppkg_package(1);
+
+	acpigen_write_return_namestr("PPKG");
+	acpigen_write_method_end();
+}
+
+static void write_tpch_read_method(const char *tpch_read_method_name,
+				unsigned int ipc_subcmd_ctrl_value)
+{
+	/* Get IPCS method from the PMC device */
+	const char *ipcs = get_pmc_ipcs_method();
+	acpigen_write_method_serialized(tpch_read_method_name, 0);
+	acpigen_write_store();
+	acpigen_emit_namestring(ipcs);
+	acpigen_write_integer(PMC_IPC_CMD_COMMAND_FIVR);
+	acpigen_write_integer(PMC_IPC_CMD_CMD_ID_FIVR_READ);
+	acpigen_write_integer(PMC_IPC_COMMAND_FIVR_SIZE);
+	acpigen_write_integer(ipc_subcmd_ctrl_value);
+	acpigen_write_zero();
+	acpigen_write_zero();
+	acpigen_write_zero();
+	acpigen_emit_byte(LOCAL0_OP);
+
+	acpigen_write_store();
+	acpigen_emit_namestring("PKGC");
+	acpigen_emit_byte(LOCAL0_OP);
+	acpigen_emit_byte(LOCAL1_OP);
+
+	acpigen_emit_byte(RETURN_OP);
+	acpigen_emit_byte(LOCAL1_OP);
+	acpigen_write_method_end();
+}
+
 static void write_create_tpch(const struct dptf_platform_info *platform_info)
 {
 	acpigen_write_device("TPCH");
 	acpigen_write_name("_HID");
 	dptf_write_hid(platform_info->use_eisa_hids, platform_info->tpch_device_hid);
-	acpigen_write_name_integer("_UID", 0);
+	acpigen_write_name_string("_STR", DEFAULT_TPCH_STR);
+	acpigen_write_name_integer("PTYP", DPTF_GENERIC_PARTICIPANT_TYPE_TPCH);
 	acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);
 }
 
 static void write_tpch_methods(const struct dptf_platform_info *platform_info)
 {
 	write_create_tpch(platform_info);
 
-	/* Create RFC0 method */
-	write_tpch_rfc_methods(platform_info->tpch_rfc0_method,
-			PMC_IPC_SUBCMD_RFI_CTRL0_LOGIC);
-	/* Create RFC1 method */
-	write_tpch_rfc_methods(platform_info->tpch_rfc1_method,
-			PMC_IPC_SUBCMD_RFI_CTRL4_LOGIC);
+	const struct {
+		enum { READ, WRITE } type;
+		const char *method_name;
+		unsigned int subcommand;
+	} tpch_methods[] = {
+		{	.type = WRITE,
+			.method_name =
+				platform_info->tpch_method_names.set_fivr_low_clock_method,
+			.subcommand = PMC_IPC_SUBCMD_RFI_CTRL0_LOGIC
+		},
+		{	.type = WRITE,
+			.method_name =
+				platform_info->tpch_method_names.set_fivr_high_clock_method,
+			.subcommand = PMC_IPC_SUBCMD_RFI_CTRL4_LOGIC
+		},
+		{	.type = READ,
+			.method_name =
+				platform_info->tpch_method_names.get_fivr_low_clock_method,
+			.subcommand = PMC_IPC_SUBCMD_RFI_CTRL0_LOGIC
+		},
+		{	.type = READ,
+			.method_name =
+				platform_info->tpch_method_names.get_fivr_high_clock_method,
+			.subcommand = PMC_IPC_SUBCMD_RFI_CTRL4_LOGIC
+		},
+		{	.type = READ,
+			.method_name =
+				platform_info->tpch_method_names.get_fivr_ssc_method,
+			.subcommand = PMC_IPC_SUBCMD_EMI_CTRL0_LOGIC
+		},
+		{	.type = READ,
+			.method_name =
+			platform_info->tpch_method_names.get_fivr_switching_fault_status,
+			.subcommand = PMC_IPC_SUBCMD_FFFC_FAULT_STATUS
+		},
+		{	.type = READ,
+			.method_name =
+				platform_info->tpch_method_names.get_fivr_switching_freq_mhz,
+			.subcommand = PMC_IPC_SUBCMD_FFFC_RFI_STATUS
+		},
+	};
+
+	write_pkgc_method();
+	for (size_t i = 0; i < ARRAY_SIZE(tpch_methods); i++) {
+		if (tpch_methods[i].type == READ) {
+			write_tpch_read_method(tpch_methods[i].method_name,
+						tpch_methods[i].subcommand);
+		} else if (tpch_methods[i].type == WRITE) {
+			write_tpch_write_method(tpch_methods[i].method_name,
+						tpch_methods[i].subcommand);
+		}
+	}
 
 	acpigen_write_device_end(); /* TPCH Device */
 }

diff --git a/src/drivers/intel/dptf/dptf.h b/src/drivers/intel/dptf/dptf.h
@@ -15,8 +15,15 @@ struct dptf_platform_info {
 	const char *generic_hid;
 	const char *fan_hid;
 	const char *tpch_device_hid;
-	const char *tpch_rfc0_method;
-	const char *tpch_rfc1_method;
+	struct {
+		const char *set_fivr_low_clock_method;
+		const char *set_fivr_high_clock_method;
+		const char *get_fivr_low_clock_method;
+		const char *get_fivr_high_clock_method;
+		const char *get_fivr_ssc_method;
+		const char *get_fivr_switching_fault_status;
+		const char *get_fivr_switching_freq_mhz;
+	} tpch_method_names;
 };
 
 const struct dptf_platform_info *get_dptf_platform_info(void);

diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S
@@ -181,7 +181,7 @@ CAR_init_done:
 	pushl	%eax	/* tsc[31:0] */
 
 before_romstage:
-	post_code(0x2A)
+	post_code(0x2a)
 
 	/* Call bootblock_c_entry(uint64_t base_timestamp) */
 	call	bootblock_c_entry

diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
@@ -18,7 +18,6 @@
 #include <stage_cache.h>
 #include <string.h>
 #include <timestamp.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 static void raminit_common(struct romstage_params *params)
 {
@@ -104,9 +103,9 @@ void cache_as_ram_stage_main(FSP_INFO_HEADER *fih)
 	timestamp_add_now(TS_START_ROMSTAGE);
 
 	/* Display parameters */
-	if (!CONFIG(NO_MMCONF_SUPPORT))
-		printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n",
-			CONFIG_MMCONF_BASE_ADDRESS);
+	if (!CONFIG(NO_ECAM_MMCONF_SUPPORT))
+		printk(BIOS_SPEW, "CONFIG_ECAM_MMCONF_BASE_ADDRESS: 0x%08x\n",
+			CONFIG_ECAM_MMCONF_BASE_ADDRESS);
 	printk(BIOS_INFO, "Using FSP 1.1\n");
 
 	/* Display FSP banner */

diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
@@ -218,6 +218,16 @@ config FSP_COMPRESS_FSP_M_LZ4
 	bool
 	depends on !FSP_M_XIP
 
+config FSP_ALIGNMENT_FSP_S
+	int
+	help
+	  Sets the CBFS alignment for FSP-S
+
+config FSP_ALIGNMENT_FSP_M
+	int
+	help
+	  Sets the CBFS alignment for FSP-M
+
 config FSP_M_ADDR
 	hex
 	help

diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc
@@ -65,6 +65,9 @@ endif
 ifeq ($(CONFIG_FSP_COMPRESS_FSP_M_LZ4),y)
 $(FSP_M_CBFS)-compression := LZ4
 endif
+ifneq ($(CONFIG_FSP_ALIGNMENT_FSP_M),)
+$(FSP_M_CBFS)-align := $(CONFIG_FSP_ALIGNMENT_FSP_M)
+endif
 
 cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(FSP_S_CBFS)
 $(FSP_S_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_S_FILE))
@@ -75,10 +78,13 @@ endif
 ifeq ($(CONFIG_FSP_COMPRESS_FSP_S_LZ4),y)
 $(FSP_S_CBFS)-compression := LZ4
 endif
+ifneq ($(CONFIG_FSP_ALIGNMENT_FSP_S),)
+$(FSP_S_CBFS)-align := $(CONFIG_FSP_ALIGNMENT_FSP_S)
+endif
 
 ifeq ($(CONFIG_FSP_FULL_FD),y)
 $(obj)/Fsp_M.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(DOTCONFIG)
-	python2 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)" -n "Fsp.fd"
+	python 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)" -n "Fsp.fd"
 
 $(obj)/Fsp_S.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(obj)/Fsp_M.fd
 	true

diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -32,7 +32,9 @@ enum fsp_notify_phase {
 };
 
 /* Main FSP stages */
+void preload_fspm(void);
 void fsp_memory_init(bool s3wake);
+void preload_fsps(void);
 void fsp_silicon_init(void);
 
 /*

diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
@@ -340,6 +340,15 @@ static void *fspm_allocator(void *arg, size_t size, const union cbfs_mdata *unus
 	return (void *)fspm_begin;
 }
 
+void preload_fspm(void)
+{
+	if (!CONFIG(CBFS_PRELOAD))
+		return;
+
+	printk(BIOS_DEBUG, "Preloading %s\n", CONFIG_FSP_M_CBFS);
+	cbfs_preload(CONFIG_FSP_M_CBFS);
+}
+
 void fsp_memory_init(bool s3wake)
 {
 	struct range_entry prog_ranges[2];

diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
@@ -9,6 +9,7 @@
 #include <fsp/ppi/mp_service_ppi.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/mp_init.h>
+#include <types.h>
 
 #define BSP_CPU_SLOT 0
 
@@ -72,7 +73,8 @@ efi_return_status_t mp_startup_all_aps(efi_ap_procedure procedure,
 	if (procedure == NULL)
 		return FSP_INVALID_PARAMETER;
 
-	if (mp_run_on_all_aps((void *)procedure, argument, timeout_usec, !run_serial)) {
+	if (mp_run_on_all_aps((void *)procedure, argument, timeout_usec, !run_serial) !=
+				CB_SUCCESS) {
 		printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__);
 		return FSP_NOT_STARTED;
 	}
@@ -92,9 +94,22 @@ efi_return_status_t mp_startup_all_cpus(efi_ap_procedure procedure,
 	/* Run on BSP */
 	procedure(argument);
 
-	/* Run on APs */
-	if (mp_run_on_aps((void *)procedure, argument,
-			MP_RUN_ON_ALL_CPUS, timeout_usec)) {
+	/*
+	 * Run on APs Serially
+	 *
+	 * FIXME: As per MP service specification, EDK2 is allowed to specify the mode
+	 * in which a 'func' routine should be executed on APs (i.e. execute serially
+	 * or concurrently).
+	 *
+	 * MP service API `StartupAllCPUs` doesn't specify such requirement.
+	 * Hence, running the `CpuCacheInfoCollectCoreAndCacheData`
+	 * (UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c#194)
+	 * simultaneously on APs results in a coherency issue (hang while executing `func`)
+	 * due to lack of acquiring a spin lock while accessing common data structure in
+	 * multiprocessor environment.
+	 */
+	if (mp_run_on_all_aps((void *)procedure, argument, timeout_usec, false) !=
+				CB_SUCCESS) {
 		printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__);
 		return FSP_NOT_STARTED;
 	}
@@ -118,7 +133,7 @@ efi_return_status_t mp_startup_this_ap(efi_ap_procedure procedure,
 		return FSP_INVALID_PARAMETER;
 
 	if (mp_run_on_aps((void *)procedure, argument,
-			processor_number, timeout_usec)) {
+			processor_number, timeout_usec) != CB_SUCCESS) {
 		printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__);
 		return FSP_NOT_STARTED;
 	}

diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -230,6 +230,15 @@ void fsps_load(void)
 	load_done = 1;
 }
 
+void preload_fsps(void)
+{
+	if (!CONFIG(CBFS_PRELOAD))
+		return;
+
+	printk(BIOS_DEBUG, "Preloading %s\n", CONFIG_FSP_S_CBFS);
+	cbfs_preload(CONFIG_FSP_S_CBFS);
+}
+
 void fsp_silicon_init(void)
 {
 	timestamp_add_now(TS_FSP_SILICON_INIT_LOAD);

diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c
@@ -163,8 +163,8 @@ enum cb_err fsp_load_component(struct fsp_load_descriptor *fspld, struct fsp_hea
 	if (!dest)
 		return CB_ERR;
 
-	/* Don't allow FSP-M relocation. */
-	if (!fspm_env() && fsp_component_relocate((uintptr_t)dest, dest, output_size) < 0) {
+	/* Don't allow FSP-M relocation when XIP. */
+	if (!fspm_xip() && fsp_component_relocate((uintptr_t)dest, dest, output_size) < 0) {
 		printk(BIOS_ERR, "Unable to relocate FSP component!\n");
 		return CB_ERR;
 	}

diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c
@@ -847,6 +847,9 @@ static void write_i2c_camera_device(const struct device *dev, const char *scope)
 	acpigen_write_name_integer("_UID", config->acpi_uid);
 	acpigen_write_name_string("_DDN", config->chip_name);
 	acpigen_write_STA(acpi_device_status(dev));
+	acpigen_write_method("_DSC", 0);
+	acpigen_write_return_integer(config->max_dstate_for_probe);
+	acpigen_pop_len(); /* Method _DSC */
 
 	/* Resources */
 	acpigen_write_name("_CRS");

diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h
@@ -257,6 +257,17 @@ struct drivers_intel_mipi_camera_config {
 	bool has_power_resource;
 	/* Perform low power probe */
 	bool low_power_probe;
+	/*
+	 * This will create a _DSC method in ACPI which returns an integer, to tell the kernel
+	 * the highest allowed D state for a device during probe
+	 * Number   State   Description
+	 * 0	    D0	    Device fully powered on
+	 * 1	    D1
+	 * 2	    D2
+	 * 3	    D3hot
+	 * 4	    D3cold  Off
+	 */
+	uint8_t max_dstate_for_probe;
 };
 
 #endif
diff --git a/src/drivers/ipmi/ipmi_fru.c b/src/drivers/ipmi/ipmi_fru.c
@@ -525,7 +525,7 @@ void print_fru_areas(struct fru_info_str *fru_info_str)
 	if (prod_info.product_name != NULL)
 		printk(BIOS_DEBUG, "product name: %s\n", prod_info.product_name);
 	if (prod_info.product_partnumber != NULL)
-		printk(BIOS_DEBUG, "product part numer: %s\n", prod_info.product_partnumber);
+		printk(BIOS_DEBUG, "product part number: %s\n", prod_info.product_partnumber);
 	if (prod_info.product_version != NULL)
 		printk(BIOS_DEBUG, "product version: %s\n", prod_info.product_version);
 	if (prod_info.serial_number != NULL)

diff --git a/src/drivers/ipmi/supermicro_oem.c b/src/drivers/ipmi/supermicro_oem.c
@@ -26,7 +26,7 @@ static void set_coreboot_ver(const uint16_t kcs_port)
 	int ret;
 	size_t i;
 
-	/* Only 8 charactars are visible in UI. Cut of on first dash */
+	/* Only 8 characters are visible in UI. Cut of on first dash */
 	for (i = 0; i < 15; i++) {
 		if (coreboot_ver[i] == '-')
 			break;

diff --git a/src/drivers/net/Kconfig b/src/drivers/net/Kconfig
@@ -33,11 +33,18 @@ config RT8168_SET_LED_MODE
 	select REALTEK_8168_RESET
 	help
 	  This is to set a customized LED mode to distinguish 10/100/1000
-	  link and speed status with limited LEDs avaiable on a board.
+	  link and speed status with limited LEDs available on a board.
 	  Please refer to RTL811x datasheet section 7.2 Customizable LED
 	  Configuration for details. With this flag enabled, the
 	  customized_leds variable will be read from devicetree setting.
 
+config RT8168_GEN_ACPI_POWER_RESOURCE
+	bool
+	default n
+	depends on REALTEK_8168_RESET
+	help
+	  Select this if an ACPI power resource needs to be generated.
+
 config ATHEROS_ATL1E_SETMAC
 	bool
 	help

diff --git a/src/drivers/net/atl1e.c b/src/drivers/net/atl1e.c
@@ -106,7 +106,7 @@ static int atl1e_eeprom_exist(u32 mem_base)
 static void atl1e_init(struct device *dev)
 {
 	/* Get the resource of the NIC mmio */
-	struct resource *nic_res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	struct resource *nic_res = probe_resource(dev, PCI_BASE_ADDRESS_0);
 
 	if (nic_res == NULL) {
 		printk(BIOS_ERR, "atl1e: resource not found\n");
@@ -127,7 +127,7 @@ static void atl1e_init(struct device *dev)
 
 	/* Check if the base is invalid */
 	if (!mem_base) {
-		printk(BIOS_ERR, "atl1e: Error cant find MEM resource\n");
+		printk(BIOS_ERR, "atl1e: Error can't find MEM resource\n");
 		return;
 	}
 	/* Enable but do not set bus master */

diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c
@@ -280,7 +280,7 @@ static void r8168_init(struct device *dev)
 
 	/* Check if the base is invalid */
 	if (!io_base) {
-		printk(BIOS_ERR, "r8168: Error cant find IO resource\n");
+		printk(BIOS_ERR, "r8168: Error can't find IO resource\n");
 		return;
 	}
 	/* Enable but do not set bus master */
@@ -317,7 +317,7 @@ static void r8168_net_fill_ssdt(const struct device *dev)
 		acpigen_write_name_string("_DDN", dev->chip_ops->name);
 
 	/* Power Resource */
-	if (config->has_power_resource) {
+	if (CONFIG(RT8168_GEN_ACPI_POWER_RESOURCE) && config->has_power_resource) {
 		const struct acpi_power_res_params power_res_params = {
 			.stop_gpio = &config->stop_gpio,
 			.stop_delay_ms = config->stop_delay_ms,