135 changes: 45 additions & 90 deletions src/cpu/amd/pi/00630F01/acpi/cpu.asl
View file
Expand Up @@ -11,94 +11,49 @@
* GNU General Public License for more details.
*/

/*
* Processor Object
*
*/
Scope (\_PR) { /* define processor scope */
Processor(
P000, /* name space name */
0, /* Unique core number for this processor within a socket */
0x810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
/*
* Processor Object
*
*/
Scope (\_PR) { /* define processor scope */

Device (P000) {
Name(_HID, "ACPI0007")
Name(_UID, 0)
}

Device (P001) {
Name(_HID, "ACPI0007")
Name(_UID, 1)
}

Device (P002) {
Name(_HID, "ACPI0007")
Name(_UID, 2)
}

Device (P003) {
Name(_HID, "ACPI0007")
Name(_UID, 3)
}

Device (P004) {
Name(_HID, "ACPI0007")
Name(_UID, 4)
}

Device (P005) {
Name(_HID, "ACPI0007")
Name(_UID, 5)
}

Device (P006) {
Name(_HID, "ACPI0007")
Name(_UID, 6)
}

Processor(
P001, /* name space name */
1, /* Unique core number for this processor within a socket */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P002, /* name space name */
2, /* Unique core number for this processor within a socket */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P003, /* name space name */
3, /* Unique core number for this processor within a socket */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P004, /* name space name */
4, /* Unique core number for this processor within a socket */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P005, /* name space name */
5, /* Unique core number for this processor within a socket */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P006, /* name space name */
6, /* Unique core number for this processor within a socket */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P007, /* name space name */
7, /* Unique core number for this processor within a socket */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P008, /* name space name */
8, /* Unique core number for this processor within a socket */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P009, /* name space name */
9, /* Unique core number for this processor within a socket */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P010, /* name space name */
10, /* Unique core number for this processor within a socket */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P011, /* name space name */
11, /* Unique core number for this processor within a socket */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
} /* End _PR scope */
Device (P007) {
Name(_HID, "ACPI0007")
Name(_UID, 7)
}
} /* End _PR scope */
4 changes: 0 additions & 4 deletions src/cpu/amd/pi/00660F01/Kconfig
View file
Expand Up @@ -21,8 +21,4 @@ config CPU_ADDR_BITS
int
default 48

config XIP_ROM_SIZE
hex
default 0x100000

endif
81 changes: 32 additions & 49 deletions src/cpu/amd/pi/00660F01/acpi/cpu.asl
View file
Expand Up @@ -15,62 +15,45 @@
* Processor Object
*
*/
Scope (\_PR) { /* define processor scope */
Processor(
P000, /* name space name */
0, /* Unique number for this processor */
0x810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
Scope (\_PR) { /* define processor scope */

Device (P000) {
Name(_HID, "ACPI0007")
Name(_UID, 0)
}

Processor(
P001, /* name space name */
1, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
Device (P001) {
Name(_HID, "ACPI0007")
Name(_UID, 1)
}
Processor(
P002, /* name space name */
2, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {

Device (P002) {
Name(_HID, "ACPI0007")
Name(_UID, 2)
}
Processor(
P003, /* name space name */
3, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {

Device (P003) {
Name(_HID, "ACPI0007")
Name(_UID, 3)
}
Processor(
P004, /* name space name */
4, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {

Device (P004) {
Name(_HID, "ACPI0007")
Name(_UID, 4)
}
Processor(
P005, /* name space name */
5, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {

Device (P005) {
Name(_HID, "ACPI0007")
Name(_UID, 5)
}
Processor(
P006, /* name space name */
6, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {

Device (P006) {
Name(_HID, "ACPI0007")
Name(_UID, 6)
}
Processor(
P007, /* name space name */
7, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {

Device (P007) {
Name(_HID, "ACPI0007")
Name(_UID, 7)
}
} /* End _PR scope */
4 changes: 0 additions & 4 deletions src/cpu/amd/pi/00730F01/Kconfig
View file
Expand Up @@ -23,8 +23,4 @@ config CPU_ADDR_BITS
int
default 40

config XIP_ROM_SIZE
hex
default 0x100000

endif
107 changes: 45 additions & 62 deletions src/cpu/amd/pi/00730F01/acpi/cpu.asl
View file
Expand Up @@ -11,66 +11,49 @@
* GNU General Public License for more details.
*/

/*
* Processor Object
*
*/
Scope (\_PR) { /* define processor scope */
Processor(
P000, /* name space name */
0, /* Unique number for this processor */
0x810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
/*
* Processor Object
*
*/
Scope (\_PR) { /* define processor scope */

Device (P000) {
Name(_HID, "ACPI0007")
Name(_UID, 0)
}

Device (P001) {
Name(_HID, "ACPI0007")
Name(_UID, 1)
}

Device (P002) {
Name(_HID, "ACPI0007")
Name(_UID, 2)
}

Device (P003) {
Name(_HID, "ACPI0007")
Name(_UID, 3)
}

Device (P004) {
Name(_HID, "ACPI0007")
Name(_UID, 4)
}

Device (P005) {
Name(_HID, "ACPI0007")
Name(_UID, 5)
}

Device (P006) {
Name(_HID, "ACPI0007")
Name(_UID, 6)
}

Processor(
P001, /* name space name */
1, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P002, /* name space name */
2, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P003, /* name space name */
3, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P004, /* name space name */
4, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P005, /* name space name */
5, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P006, /* name space name */
6, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
Processor(
P007, /* name space name */
7, /* Unique number for this processor */
0x0810, /* PBLK system I/O address !hardcoded! */
0x06 /* PBLKLEN for boot processor */
) {
}
} /* End _PR scope */
Device (P007) {
Name(_HID, "ACPI0007")
Name(_UID, 7)
}
} /* End _PR scope */
12 changes: 1 addition & 11 deletions src/cpu/amd/pi/Kconfig
View file
Expand Up @@ -28,23 +28,13 @@ config CPU_AMD_PI
select SPI_FLASH if HAVE_ACPI_RESUME
select CAR_GLOBAL_MIGRATION if BINARYPI_LEGACY_WRAPPER
select SMM_ASEG
select NO_FIXED_XIP_ROM_SIZE

if CPU_AMD_PI

config BINARYPI_LEGACY_WRAPPER
def_bool n

config XIP_ROM_SIZE
hex
default 0x100000
help
Overwride the default write through caching size as 1M Bytes.
On some AMD platforms, one socket supports 2 or more kinds of
processor family, compiling several CPU families agesa code
will increase the romstage size.
In order to execute romstage in place on the flash ROM,
more space is required to be set as write through caching.

config UDELAY_LAPIC_FIXED_FSB
int
default 200
Expand Down
13 changes: 11 additions & 2 deletions src/cpu/intel/car/core2/cache_as_ram.S
View file
Expand Up @@ -18,6 +18,15 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE

#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
#endif
#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
#else
#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE
#endif

.global bootblock_pre_c_entry

.code32
Expand Down Expand Up @@ -148,13 +157,13 @@ addrsize_set_high:
* https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html
*/
movl $_program, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
andl $(~(XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRPROT, %eax
wrmsr

movl $MTRR_PHYS_MASK(1), %ecx
rdmsr
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $(~(XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr

post_code(0x28)
Expand Down
13 changes: 11 additions & 2 deletions src/cpu/intel/car/p3/cache_as_ram.S
View file
Expand Up @@ -18,6 +18,15 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE

#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
#endif
#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
#else
#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE
#endif

.global bootblock_pre_c_entry

.code32
Expand Down Expand Up @@ -136,13 +145,13 @@ addrsize_set_high:
* https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html
*/
movl $_program, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
andl $(~(XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRPROT, %eax
wrmsr

movl $MTRR_PHYS_MASK(1), %ecx
rdmsr
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $(~(XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr

post_code(0x2e)
Expand Down
25 changes: 11 additions & 14 deletions src/cpu/intel/car/p4-netburst/cache_as_ram.S
View file
Expand Up @@ -26,6 +26,15 @@
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE

#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
#if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
#error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
#endif
#define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
#else
#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE
#endif

.global bootblock_pre_c_entry

.code32
Expand Down Expand Up @@ -168,12 +177,6 @@ cores_counted:

hyper_threading_cpu:

/* delay 10 ms */
movl $10000, %ecx
1: inb $0x80, %al
dec %ecx
jnz 1b

post_code(0x25)

/* Send Start IPI to all excluding ourself. */
Expand All @@ -189,12 +192,6 @@ hyper_threading_cpu:
andl $LAPIC_ICR_BUSY, %ecx
jnz 1b

/* delay 250 us */
movl $250, %ecx
1: inb $0x80, %al
dec %ecx
jnz 1b

post_code(0x26)

/* Wait for sibling CPU to start. */
Expand Down Expand Up @@ -354,13 +351,13 @@ cache_rom:
* https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html
*/
movl $_program, %eax
andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
andl $(~(XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRPROT, %eax
wrmsr

movl $MTRR_PHYS_MASK(1), %ecx
rdmsr
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $(~(XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr

fill_cache:
Expand Down
7 changes: 6 additions & 1 deletion src/cpu/intel/common/common_init.c
View file
Expand Up @@ -56,8 +56,13 @@ void set_feature_ctrl_vmx(void)

if (enable) {
msr.lo |= (1 << 2);
if (feature_flag & CPUID_SMX)
if (feature_flag & CPUID_SMX) {
msr.lo |= (1 << 1);
if (CONFIG(INTEL_TXT)) {
/* Enable GetSec and all GetSec leaves */
msr.lo |= (0xff << 8);
}
}
}

wrmsr(IA32_FEATURE_CONTROL, msr);
Expand Down
1 change: 0 additions & 1 deletion src/cpu/intel/common/fsb.c
View file
Expand Up @@ -12,7 +12,6 @@
*/

#include <arch/early_variables.h>
#include <cpu/cpu.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/tsc.h>
#include <cpu/intel/speedstep.h>
Expand Down
1 change: 0 additions & 1 deletion src/cpu/intel/fsp_model_406dx/Kconfig
View file
Expand Up @@ -32,7 +32,6 @@ config CPU_SPECIFIC_OPTIONS
select PARALLEL_CPU_INIT
select TSC_SYNC_MFENCE
select TSC_MONOTONIC_TIMER
select TSC_CONSTANT_RATE
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
select NO_SMM
Expand Down
1 change: 0 additions & 1 deletion src/cpu/intel/haswell/Kconfig
View file
Expand Up @@ -14,7 +14,6 @@ config CPU_SPECIFIC_OPTIONS
select MMX
select SSE2
select UDELAY_TSC
select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER
select SUPPORT_CPU_UCODE_IN_CBFS
#select AP_IN_SIPI_WAIT
Expand Down
19 changes: 0 additions & 19 deletions src/cpu/intel/haswell/finalize.c
View file
Expand Up @@ -22,25 +22,6 @@
* Document Number 504790
* Revision 1.6.0, June 2012 */

#if 0
static void msr_set_bit(unsigned int reg, unsigned int bit)
{
msr_t msr = rdmsr(reg);

if (bit < 32) {
if (msr.lo & (1 << bit))
return;
msr.lo |= 1 << bit;
} else {
if (msr.hi & (1 << (bit - 32)))
return;
msr.hi |= 1 << (bit - 32);
}

wrmsr(reg, msr);
}
#endif

void intel_cpu_haswell_finalize_smm(void)
{
#if 0
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/intel/model_1067x/Kconfig
View file
Expand Up @@ -7,9 +7,9 @@ config CPU_INTEL_MODEL_1067X
select SMP
select SSE2
select UDELAY_TSC
select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER
select TSC_SYNC_MFENCE
select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
select SETUP_XIP_CACHE if C_ENVIRONMENT_BOOTBLOCK
1 change: 0 additions & 1 deletion src/cpu/intel/model_106cx/Kconfig
View file
Expand Up @@ -7,7 +7,6 @@ config CPU_INTEL_MODEL_106CX
select SMP
select SSE2
select UDELAY_TSC
select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER
select SIPI_VECTOR_IN_ROM
select AP_IN_SIPI_WAIT
Expand Down
5 changes: 0 additions & 5 deletions src/cpu/intel/model_2065x/Kconfig
View file
Expand Up @@ -12,7 +12,6 @@ config CPU_SPECIFIC_OPTIONS
select SMP
select SSE2
select UDELAY_TSC
select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER
select SUPPORT_CPU_UCODE_IN_CBFS
select PARALLEL_CPU_INIT
Expand All @@ -23,10 +22,6 @@ config CPU_SPECIFIC_OPTIONS
select NO_FIXED_XIP_ROM_SIZE
select PARALLEL_MP

config BOOTBLOCK_CPU_INIT
string
default "cpu/intel/model_2065x/bootblock.c"

config SMM_TSEG_SIZE
hex
default 0x800000
Expand Down
5 changes: 4 additions & 1 deletion src/cpu/intel/model_2065x/Makefile.inc
View file
Expand Up @@ -15,7 +15,10 @@ smm-y += finalize.c

cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-25-*)

cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
bootblock-y += ../car/non-evict/cache_as_ram.S
bootblock-y += ../car/bootblock.c
bootblock-y += ../../x86/early_reset.S

postcar-y += ../car/non-evict/exit_car.S

romstage-y += ../car/romstage.c
64 changes: 0 additions & 64 deletions src/cpu/intel/model_2065x/bootblock.c
View file

This file was deleted.

17 changes: 0 additions & 17 deletions src/cpu/intel/model_2065x/finalize.c
View file
Expand Up @@ -23,23 +23,6 @@
* Document Number 504790
* Revision 1.6.0, June 2012 */

static void msr_set_bit(unsigned int reg, unsigned int bit)
{
msr_t msr = rdmsr(reg);

if (bit < 32) {
if (msr.lo & (1 << bit))
return;
msr.lo |= 1 << bit;
} else {
if (msr.hi & (1 << (bit - 32)))
return;
msr.hi |= 1 << (bit - 32);
}

wrmsr(reg, msr);
}

void intel_model_2065x_finalize_smm(void)
{
/* Lock C-State MSR */
Expand Down
1 change: 0 additions & 1 deletion src/cpu/intel/model_206ax/Kconfig
View file
Expand Up @@ -13,7 +13,6 @@ config CPU_SPECIFIC_OPTIONS
select MMX
select SSE2
select UDELAY_TSC
select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER
select SUPPORT_CPU_UCODE_IN_CBFS
#select AP_IN_SIPI_WAIT
Expand Down
17 changes: 0 additions & 17 deletions src/cpu/intel/model_206ax/finalize.c
View file
Expand Up @@ -23,23 +23,6 @@
* Document Number 504790
* Revision 1.6.0, June 2012 */

static void msr_set_bit(unsigned int reg, unsigned int bit)
{
msr_t msr = rdmsr(reg);

if (bit < 32) {
if (msr.lo & (1 << bit))
return;
msr.lo |= 1 << bit;
} else {
if (msr.hi & (1 << (bit - 32)))
return;
msr.hi |= 1 << (bit - 32);
}

wrmsr(reg, msr);
}

void intel_model_206ax_finalize_smm(void)
{
/* Lock C-State MSR */
Expand Down
1 change: 0 additions & 1 deletion src/cpu/intel/model_6ex/Kconfig
View file
Expand Up @@ -7,7 +7,6 @@ config CPU_INTEL_MODEL_6EX
select SMP
select SSE2
select UDELAY_TSC
select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER
select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/intel/model_6fx/Kconfig
View file
Expand Up @@ -7,10 +7,10 @@ config CPU_INTEL_MODEL_6FX
select SMP
select SSE2
select UDELAY_TSC
select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER
select AP_IN_SIPI_WAIT
select TSC_SYNC_MFENCE
select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
select SETUP_XIP_CACHE if C_ENVIRONMENT_BOOTBLOCK
4 changes: 3 additions & 1 deletion src/cpu/intel/slot_1/Kconfig
View file
Expand Up @@ -24,7 +24,9 @@ config SLOT_SPECIFIC_OPTIONS # dummy
select CPU_INTEL_MODEL_6BX
select CPU_INTEL_MODEL_6XX
select NO_SMM
select NO_MONOTONIC_TIMER
select UDELAY_TSC
select TSC_MONOTONIC_TIMER
select UNKNOWN_TSC_RATE

config DCACHE_RAM_BASE
hex
Expand Down
10 changes: 9 additions & 1 deletion src/cpu/intel/smm/gen1/smmrelocate.c
View file
Expand Up @@ -168,6 +168,9 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
if (smm_reloc_params.ied_size)
setup_ied_area(&smm_reloc_params);

/* This may not be be correct for older CPU's supported by this code,
but given that em64t101_smm_state_save_area_t is larger than the
save_state of these CPU's it works. */
*smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);
}

Expand All @@ -191,6 +194,8 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
{
msr_t mtrr_cap;
struct smm_relocation_params *relo_params = &smm_reloc_params;
/* The em64t101 save state is sufficiently compatible with older
save states with regards of smbase, smm_revision. */
em64t101_smm_state_save_area_t *save_state;
u32 smbase = staggered_smbase;
u32 iedbase = relo_params->ied_base;
Expand All @@ -208,7 +213,10 @@ void smm_relocation_handler(int cpu, uintptr_t curr_smbase,
save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE -
sizeof(*save_state));
save_state->smbase = smbase;
save_state->iedbase = iedbase;

printk(BIOS_SPEW, "SMM revision: 0x%08x\n", save_state->smm_revision);
if (save_state->smm_revision == 0x00030101)
save_state->iedbase = iedbase;

/* Write EMRR and SMRR MSRs based on indicated support. */
mtrr_cap = rdmsr(MTRR_CAP_MSR);
Expand Down
4 changes: 4 additions & 0 deletions src/cpu/intel/socket_BGA956/Kconfig
View file
Expand Up @@ -14,4 +14,8 @@ config DCACHE_RAM_SIZE
hex
default 0x8000

config DCACHE_BSP_STACK_SIZE
hex
default 0x2000

endif
3 changes: 2 additions & 1 deletion src/cpu/intel/socket_BGA956/Makefile.inc
View file
Expand Up @@ -8,7 +8,8 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep

cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S
bootblock-y += ../car/core2/cache_as_ram.S
bootblock-y += ../car/bootblock.c
postcar-y += ../car/p4-netburst/exit_car.S

romstage-y += ../car/romstage.c
1 change: 0 additions & 1 deletion src/cpu/intel/socket_mPGA604/Kconfig
View file
Expand Up @@ -9,7 +9,6 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
select MMX
select SSE
select UDELAY_TSC
select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER
select SIPI_VECTOR_IN_ROM
select C_ENVIRONMENT_BOOTBLOCK
Expand Down
4 changes: 4 additions & 0 deletions src/cpu/intel/socket_p/Kconfig
View file
Expand Up @@ -15,4 +15,8 @@ config DCACHE_RAM_SIZE
hex
default 0x8000

config DCACHE_BSP_STACK_SIZE
hex
default 0x2000

endif
3 changes: 2 additions & 1 deletion src/cpu/intel/socket_p/Makefile.inc
View file
Expand Up @@ -9,7 +9,8 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading
subdirs-y += ../speedstep

cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S
bootblock-y += ../car/core2/cache_as_ram.S
bootblock-y += ../car/bootblock.c
postcar-y += ../car/p4-netburst/exit_car.S

romstage-y += ../car/romstage.c
1 change: 1 addition & 0 deletions src/cpu/qemu-x86/Kconfig
View file
Expand Up @@ -20,5 +20,6 @@ config CPU_QEMU_X86
select SMP
select UDELAY_TSC
select TSC_MONOTONIC_TIMER
select UNKNOWN_TSC_RATE
select C_ENVIRONMENT_BOOTBLOCK
select SMM_ASEG
11 changes: 10 additions & 1 deletion src/cpu/qemu-x86/cache_as_ram_bootblock.S
View file
Expand Up @@ -38,16 +38,25 @@ cache_as_ram:

/* Align the stack and keep aligned for call to bootblock_c_entry() */
and $0xfffffff0, %esp
sub $4, %esp

/* Restore the BIST result and timestamps. */
#if defined(__x86_64__)
movd %mm1, %rdi
shld %rdi, 32
movd %mm1, %rsi
or %rsi, %rdi
movd %mm2, %rsi
#else
sub $4, %esp

movd %mm0, %ebx
movd %mm1, %eax
movd %mm2, %edx

pushl %ebx
pushl %edx
pushl %eax
#endif

before_c_entry:
post_code(0x29)
Expand Down
4 changes: 3 additions & 1 deletion src/cpu/ti/am335x/Makefile.inc
View file
Expand Up @@ -3,14 +3,16 @@ bootblock-y += bootblock_media.c
bootblock-y += dmtimer.c
bootblock-y += gpio.c
bootblock-y += pinmux.c
bootblock-y += monotonic_timer.c

romstage-y += nand.c
romstage-y += cbmem.c
romstage-y += dmtimer.c
romstage-y += monotonic_timer.c

ramstage-y += dmtimer.c
ramstage-y += monotonic_timer.c
ramstage-y += nand.c
ramstage-y += cbmem.c

bootblock-y += uart.c
romstage-y += uart.c
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/ti/am335x/cbmem.c
View file
Expand Up @@ -15,7 +15,7 @@
#include <cbmem.h>
#include <symbols.h>

void *cbmem_top(void)
void *cbmem_top_chipset(void)
{
return _dram + (CONFIG_DRAM_SIZE_MB << 20);
}
1 change: 1 addition & 0 deletions src/cpu/via/nano/Kconfig
View file
Expand Up @@ -25,6 +25,7 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_RAMSTAGE_X86_32
select UDELAY_TSC
select TSC_MONOTONIC_TIMER
select UNKNOWN_TSC_RATE
select MMX
select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/via/nano/microcode_blob.c
View file
@@ -1,4 +1,4 @@
unsigned array[3588] =
unsigned int array[3588] =
{
#include "../../../../3rdparty/blobs/cpu/via/nano/microcode.h"
};
2 changes: 1 addition & 1 deletion src/cpu/via/nano/update_ucode.h
View file
Expand Up @@ -14,7 +14,7 @@
#ifndef __UPDATE_UCODE_H
#define __UPDATE_UCODE_H

#include <cpu/cpu.h>
#include <stdint.h>

#define MSR_UCODE_UPDATE_STATUS 0x00001205

Expand Down
62 changes: 62 additions & 0 deletions src/cpu/x86/64bit/entry64.inc
View file
@@ -0,0 +1,62 @@
/*
* This file is part of the coreboot project.
*
* Copyright (c) 2019 Patrick Rudolph <siro@das-labor.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

/*
* For starting coreboot in long mode.
*
* For reference see "AMD64 ArchitectureProgrammer's Manual Volume 2",
* Document 24593-Rev. 3.31-July 2019 Chapter 5.3
*
* Clobbers: eax, ecx, edx
*/

#if defined(__x86_64__)
.code32
#if (CONFIG_ARCH_X86_64_PGTBL_LOC & 0xfff) > 0
#error pagetables must be 4KiB aligned!
#endif

#include <cpu/x86/msr.h>
#include <arch/rom_segs.h>

setup_longmode:
/* Get page table address */
movl $(CONFIG_ARCH_X86_64_PGTBL_LOC), %eax

/* load identity mapped page tables */
movl %eax, %cr3

/* enable PAE */
movl %cr4, %eax
btsl $5, %eax
movl %eax, %cr4

/* enable long mode */
movl $(IA32_EFER), %ecx
rdmsr
btsl $8, %eax
wrmsr

/* enable paging */
movl %cr0, %eax
btsl $31, %eax
movl %eax, %cr0

/* use long jump to switch to 64-bit code segment */
ljmp $ROM_CODE_SEG64, $__longmode_start
.code64
__longmode_start:

#endif
19 changes: 13 additions & 6 deletions src/cpu/x86/Kconfig
View file
Expand Up @@ -34,12 +34,9 @@ config UDELAY_TSC
bool
default n

config TSC_CONSTANT_RATE
def_bool n
depends on UDELAY_TSC
help
This option asserts that the TSC ticks at a known constant rate.
Therefore, no TSC calibration is required.
config UNKNOWN_TSC_RATE
bool
default y if LAPIC_MONOTONIC_TIMER

config TSC_MONOTONIC_TIMER
def_bool n
Expand Down Expand Up @@ -78,6 +75,16 @@ config XIP_ROM_SIZE
depends on !NO_FIXED_XIP_ROM_SIZE
default 0x10000

config SETUP_XIP_CACHE
bool
depends on C_ENVIRONMENT_BOOTBLOCK
depends on !NO_XIP_EARLY_STAGES
help
Select this option to set up an MTRR to cache XIP stages loaded
from the bootblock. This is useful on platforms lacking a
non-eviction mode and therefore need to be careful to avoid
eviction.

config CPU_ADDR_BITS
int
default 36
Expand Down
0 src/cpu/x86/Kconfig.debug → src/cpu/x86/Kconfig.debug_cpu
View file
File renamed without changes.
1 change: 1 addition & 0 deletions src/cpu/x86/lapic/lapic_cpu_init.c
View file
Expand Up @@ -28,6 +28,7 @@
#include <smp/spinlock.h>
#include <cpu/cpu.h>
#include <cpu/intel/speedstep.h>
#include <stdlib.h>
#include <thread.h>

/* This is a lot more paranoid now, since Linux can NOT handle
Expand Down
7 changes: 4 additions & 3 deletions src/cpu/x86/lapic/secondary.S
View file
Expand Up @@ -13,6 +13,7 @@

#include <cpu/x86/mtrr.h>
#include <cpu/x86/lapic_def.h>
#include <arch/ram_segs.h>

.text
.globl _secondary_start, _secondary_start_end, _secondary_gdt_addr
Expand All @@ -38,7 +39,7 @@ _secondary_start:
orl $0x60000001, %eax /* CD, NW, PE = 1 */
movl %eax, %cr0

ljmpl $0x10, $__ap_protected_start
ljmpl $RAM_CODE_SEG, $__ap_protected_start

/* This will get filled in by C code. */
_secondary_gdt_addr:
Expand All @@ -51,11 +52,11 @@ _secondary_start_end:
ap_protected_start:
.code32
lgdt gdtaddr
ljmpl $0x10, $__ap_protected_start
ljmpl $RAM_CODE_SEG, $__ap_protected_start

__ap_protected_start:

movw $0x18, %ax
movw $RAM_DATA_SEG, %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %ss
Expand Down
3 changes: 1 addition & 2 deletions src/cpu/x86/mirror_payload.c
View file
Expand Up @@ -11,13 +11,12 @@
* GNU General Public License for more details.
*/

#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <commonlib/helpers.h>
#include <console/console.h>
#include <bootmem.h>
#include <program_loading.h>
#include <types.h>

void mirror_payload(struct prog *payload)
{
Expand Down
4 changes: 4 additions & 0 deletions src/cpu/x86/mtrr/Makefile.inc
View file
Expand Up @@ -2,8 +2,12 @@ ramstage-y += mtrr.c

romstage-y += earlymtrr.c
bootblock-y += earlymtrr.c
verstage-y += earlymtrr.c

bootblock-y += debug.c
romstage-y += debug.c
postcar-y += debug.c
ramstage-y += debug.c

bootblock-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c
verstage-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c
109 changes: 109 additions & 0 deletions src/cpu/x86/mtrr/xip_cache.c
View file
@@ -0,0 +1,109 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include <arch/cpu.h>
#include <program_loading.h>
#include <commonlib/region.h>
#include <console/console.h>
#include <cpu/x86/mtrr.h>

/* For now this is a good lowest common denominator for the total CPU cache.
TODO: fetch the total amount of cache from CPUID leaf2. */
#define MAX_CPU_CACHE (256 * KiB)

/* This makes the 'worst' case assumption that all cachelines covered by
the MTRR, no matter the caching type, are filled and not overlapping. */
static uint32_t max_cache_used(void)
{
msr_t msr = rdmsr(MTRR_CAP_MSR);
int i, total_mtrrs = msr.lo & MTRR_CAP_VCNT;
uint32_t total_cache = 0;

for (i = 0; i < total_mtrrs; i++) {
msr_t mtrr = rdmsr(MTRR_PHYS_MASK(i));
if (!(mtrr.lo & MTRR_PHYS_MASK_VALID))
continue;
total_cache += ~(mtrr.lo & 0xfffff000) + 1;
}
return total_cache;
}

void platform_prog_run(struct prog *prog)
{
const uint32_t base = region_device_offset(&prog->rdev);
const uint32_t size = region_device_sz(&prog->rdev);
const uint32_t end = base + size;
const uint32_t cache_used = max_cache_used();
/* This will accumulate MTRR's as XIP stages are run.
For now this includes bootblock which sets ups its own
caching elsewhere, verstage and romstage */
int mtrr_num = get_free_var_mtrr();
uint32_t mtrr_base;
uint32_t mtrr_size = 4 * KiB;
struct cpuinfo_x86 cpu_info;

get_fms(&cpu_info, cpuid_eax(1));
/*
* An unidentified combination of speculative reads and branch
* predictions inside WRPROT-cacheable memory can cause invalidation
* of cachelines and loss of stack on models based on NetBurst
* microarchitecture. Therefore disable WRPROT region entirely for
* all family F models.
*/
if (cpu_info.x86 == 0xf) {
printk(BIOS_NOTICE,
"PROG_RUN: CPU does not support caching ROM\n"
"The next stage will run slowly!\n");
return;
}

if (mtrr_num == -1) {
printk(BIOS_NOTICE,
"PROG_RUN: No MTRR available to cache ROM!\n"
"The next stage will run slowly!\n");
return;
}

if (cache_used + mtrr_size > MAX_CPU_CACHE) {
printk(BIOS_NOTICE,
"PROG_RUN: No more cache available for the next stage\n"
"The next stage will run slowly!\n");
return;
}

while (1) {
if (ALIGN_DOWN(base, mtrr_size) + mtrr_size >= end)
break;
if (cache_used + mtrr_size * 2 > MAX_CPU_CACHE)
break;
mtrr_size *= 2;
}

mtrr_base = ALIGN_DOWN(base, mtrr_size);
if (mtrr_base + mtrr_size < end) {
printk(BIOS_NOTICE, "PROG_RUN: Limiting XIP cache to %uKiB!\n",
mtrr_size / KiB);
/* Check if we can cover a bigger range by aligning up. */
const uint32_t alt_base = ALIGN_UP(base, mtrr_size);
const uint32_t lower_coverage = mtrr_base + mtrr_size - base;
const uint32_t upper_coverage = MIN(alt_base + mtrr_size, end) - alt_base;
if (upper_coverage > lower_coverage)
mtrr_base = alt_base;
}

printk(BIOS_DEBUG,
"PROG_RUN: Setting MTRR to cache XIP stage. base: 0x%08x, size: 0x%08x\n",
mtrr_base, mtrr_size);

set_var_mtrr(mtrr_num, mtrr_base, mtrr_size, MTRR_TYPE_WRPROT);
}
9 changes: 3 additions & 6 deletions src/cpu/x86/sipi_vector.S
View file
Expand Up @@ -15,15 +15,12 @@
#include <cpu/x86/cr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/x86/msr.h>
#include <arch/ram_segs.h>

/* The SIPI vector is responsible for initializing the APs in the system. It
* loads microcode, sets up MSRs, and enables caching before calling into
* C code. */

/* These segment selectors need to match the gdt entries in c_start.S. */
#define CODE_SEG 0x10
#define DATA_SEG 0x18

.section ".module_parameters", "aw", @progbits
ap_start_params:
gdtaddr:
Expand Down Expand Up @@ -83,10 +80,10 @@ _start:
orl $CR0_SET_FLAGS, %eax
movl %eax, %cr0

ljmpl $CODE_SEG, $1f
ljmpl $RAM_CODE_SEG, $1f
1:
.code32
movw $DATA_SEG, %ax
movw $RAM_DATA_SEG, %ax
movw %ax, %ds
movw %ax, %es
movw %ax, %ss
Expand Down
8 changes: 4 additions & 4 deletions src/cpu/x86/tsc/Makefile.inc
View file
@@ -1,6 +1,6 @@
bootblock-$(CONFIG_UDELAY_TSC) += delay_tsc.c
ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c
romstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
verstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
postcar-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
smm-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
romstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c
verstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c
postcar-$(CONFIG_UDELAY_TSC) += delay_tsc.c
smm-$(CONFIG_UDELAY_TSC) += delay_tsc.c
101 changes: 4 additions & 97 deletions src/cpu/x86/tsc/delay_tsc.c
View file
Expand Up @@ -12,108 +12,15 @@
*/

#include <arch/early_variables.h>
#include <console/console.h>
#include <arch/io.h>
#include <cpu/x86/tsc.h>
#include <pc80/i8254.h>
#include <smp/spinlock.h>
#include <delay.h>
#include <thread.h>

static unsigned long clocks_per_usec CAR_GLOBAL;

#define CLOCK_TICK_RATE 1193180U /* Underlying HZ */

/* ------ Calibrate the TSC -------
* Too much 64-bit arithmetic here to do this cleanly in C, and for
* accuracy's sake we want to keep the overhead on the CTC speaker (channel 2)
* output busy loop as low as possible. We avoid reading the CTC registers
* directly because of the awkward 8-bit access mechanism of the 82C54
* device.
*/

#define CALIBRATE_INTERVAL ((2*CLOCK_TICK_RATE)/1000) /* 2ms */
#define CALIBRATE_DIVISOR (2*1000) /* 2ms / 2000 == 1usec */

static unsigned long calibrate_tsc_with_pit(void)
{
/* Set the Gate high, disable speaker */
outb((inb(0x61) & ~0x02) | 0x01, 0x61);

/*
* Now let's take care of CTC channel 2
*
* Set the Gate high, program CTC channel 2 for mode 0,
* (interrupt on terminal count mode), binary count,
* load 5 * LATCH count, (LSB and MSB) to begin countdown.
*/
outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */

outb(CALIBRATE_INTERVAL & 0xff, 0x42); /* LSB of count */
outb(CALIBRATE_INTERVAL >> 8, 0x42); /* MSB of count */

{
tsc_t start;
tsc_t end;
unsigned long count;

start = rdtsc();
count = 0;
do {
count++;
} while ((inb(0x61) & 0x20) == 0);
end = rdtsc();

/* Error: ECTCNEVERSET */
if (count <= 1)
goto bad_ctc;

/* 64-bit subtract - gcc just messes up with long longs */
__asm__("subl %2,%0\n\t"
"sbbl %3,%1"
: "=a" (end.lo), "=d" (end.hi)
: "g" (start.lo), "g" (start.hi),
"0" (end.lo), "1" (end.hi));

/* Error: ECPUTOOFAST */
if (end.hi)
goto bad_ctc;


/* Error: ECPUTOOSLOW */
if (end.lo <= CALIBRATE_DIVISOR)
goto bad_ctc;

return DIV_ROUND_UP(end.lo, CALIBRATE_DIVISOR);
}

/*
* The CTC wasn't reliable: we got a hit on the very first read,
* or the CPU was so fast/slow that the quotient wouldn't fit in
* 32 bits..
*/
bad_ctc:
printk(BIOS_ERR, "bad_ctc\n");
return 0;
}

static unsigned long calibrate_tsc(void)
{
if (CONFIG(TSC_CONSTANT_RATE))
return tsc_freq_mhz();
else
return calibrate_tsc_with_pit();
}

void init_timer(void)
{
if (!car_get_var(clocks_per_usec))
car_set_var(clocks_per_usec, calibrate_tsc());
}

static inline unsigned long get_clocks_per_usec(void)
{
init_timer();
return car_get_var(clocks_per_usec);
(void)tsc_freq_mhz();
}

void udelay(unsigned int us)
Expand All @@ -127,7 +34,7 @@ void udelay(unsigned int us)

start = rdtscll();
clocks = us;
clocks *= get_clocks_per_usec();
clocks *= tsc_freq_mhz();
current = rdtscll();
while ((current - start) < clocks) {
cpu_relax();
Expand Down Expand Up @@ -165,7 +72,7 @@ void timer_monotonic_get(struct mono_time *mt)

current_tick = rdtscll();
ticks_elapsed = current_tick - mono_counter->last_value;
ticks_per_usec = get_clocks_per_usec();
ticks_per_usec = tsc_freq_mhz();

/* Update current time and tick values only if a full tick occurred. */
if (ticks_elapsed >= ticks_per_usec) {
Expand Down
17 changes: 16 additions & 1 deletion src/device/Kconfig
View file
Expand Up @@ -36,6 +36,11 @@ config HAVE_FSP_GOP
Selected by drivers that support to run a blob that implements
the Graphics Output Protocol (GOP).

config MAINBOARD_NO_FSP_GOP
bool
help
Selected by mainboards that do not have any graphics ports connected to the SoC.

config MAINBOARD_HAS_NATIVE_VGA_INIT
def_bool n
help
Expand Down Expand Up @@ -94,7 +99,7 @@ config VGA_ROM_RUN

config RUN_FSP_GOP
bool "Run a GOP driver"
depends on HAVE_FSP_GOP
depends on HAVE_FSP_GOP && !MAINBOARD_NO_FSP_GOP
select HAVE_LINEAR_FRAMEBUFFER
help
Some platforms (e.g. Intel Braswell and Skylake/Kaby Lake) support
Expand All @@ -111,6 +116,16 @@ config NO_GFX_INIT

endchoice

config ONBOARD_VGA_IS_PRIMARY
bool "Use onboard VGA as primary video device"
default n
depends on PCI
help
This option lets you select which VGA device will be used
to decode legacy VGA cycles. Not all chipsets implement this
however. If not selected, the last adapter found will be used,
else the onboard adapter is used.

config S3_VGA_ROM_RUN
bool "Re-run VGA Option ROMs on S3 resume"
default y
Expand Down
1 change: 0 additions & 1 deletion src/device/cardbus_device.c
View file
Expand Up @@ -15,7 +15,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <device/cardbus.h>

/*
Expand Down
9 changes: 5 additions & 4 deletions src/device/device_util.c
View file
Expand Up @@ -16,6 +16,7 @@
#include <device/path.h>
#include <device/pci_def.h>
#include <device/resource.h>
#include <stdlib.h>
#include <string.h>

/**
Expand All @@ -24,7 +25,7 @@
* @param apic_id The Local APIC ID number.
* @return Pointer to the device structure (if found), 0 otherwise.
*/
struct device *dev_find_lapic(unsigned apic_id)
struct device *dev_find_lapic(unsigned int apic_id)
{
struct device *dev;
struct device *result = NULL;
Expand Down Expand Up @@ -324,7 +325,7 @@ void compact_resources(struct device *dev)
* @param index The index of the resource on the device.
* @return The resource, if it already exists.
*/
struct resource *probe_resource(const struct device *dev, unsigned index)
struct resource *probe_resource(const struct device *dev, unsigned int index)
{
struct resource *res;

Expand All @@ -347,7 +348,7 @@ struct resource *probe_resource(const struct device *dev, unsigned index)
* @param index The index of the resource on the device.
* @return TODO.
*/
struct resource *new_resource(struct device *dev, unsigned index)
struct resource *new_resource(struct device *dev, unsigned int index)
{
struct resource *resource, *tail;

Expand Down Expand Up @@ -394,7 +395,7 @@ struct resource *new_resource(struct device *dev, unsigned index)
* @param index The index of the resource on the device.
* return TODO.
*/
struct resource *find_resource(const struct device *dev, unsigned index)
struct resource *find_resource(const struct device *dev, unsigned int index)
{
struct resource *resource;

Expand Down
18 changes: 16 additions & 2 deletions src/device/dram/ddr4.c
View file
Expand Up @@ -111,17 +111,31 @@ int spd_decode_ddr4(dimm_attr *dimm, spd_raw_data spd)
return SPD_STATUS_INVALID;
}

spd_bytes_total = (spd[0] >> 4) & ((1 << 3) - 1);
spd_bytes_used = spd[0] & ((1 << 4) - 1);
spd_bytes_total = (spd[0] >> 4) & 0x7;
spd_bytes_used = spd[0] & 0xf;

if (!spd_bytes_total || !spd_bytes_used) {
printk(BIOS_ERR, "SPD failed basic sanity checks\n");
return SPD_STATUS_INVALID;
}

if (spd_bytes_total >= 3)
printk(BIOS_WARNING, "SPD Bytes Total value is reserved\n");

spd_bytes_total = 256 << (spd_bytes_total - 1);

if (spd_bytes_used > 4) {
printk(BIOS_ERR, "SPD Bytes Used value is reserved\n");
return SPD_STATUS_INVALID;
}

spd_bytes_used = spd_bytes_used_table[spd_bytes_used];

if (spd_bytes_used > spd_bytes_total) {
printk(BIOS_ERR, "SPD Bytes Used is greater than SPD Bytes Total\n");
return SPD_STATUS_INVALID;
}

/* Verify CRC of blocks that have them, do not step over 'used' length */
for (int i = 0; i < ARRAY_SIZE(spd_blocks); i++) {
/* this block is not checksumed */
Expand Down
1 change: 0 additions & 1 deletion src/device/dram/ddr_common.c
View file
Expand Up @@ -11,7 +11,6 @@
* GNU General Public License for more details.
*/

#include <console/console.h>
#include <device/dram/common.h>
#include <types.h>

Expand Down
20 changes: 10 additions & 10 deletions src/device/hypertransport.c
View file
Expand Up @@ -21,7 +21,7 @@

struct ht_link {
struct device *dev;
unsigned pos;
unsigned int pos;
unsigned char ctrl_off, config_off, freq_off, freq_cap_off;
};

Expand Down Expand Up @@ -64,7 +64,7 @@ static struct device *ht_scan_get_devs(struct device **old_devices)
return first;
}

static int ht_setup_link(struct ht_link *prev, struct device *dev, unsigned pos)
static int ht_setup_link(struct ht_link *prev, struct device *dev, unsigned int pos)
{
struct ht_link cur[1];
int linkb_to_host;
Expand Down Expand Up @@ -113,9 +113,9 @@ static int ht_setup_link(struct ht_link *prev, struct device *dev, unsigned pos)
return 0;
}

static unsigned ht_lookup_slave_capability(struct device *dev)
static unsigned int ht_lookup_slave_capability(struct device *dev)
{
unsigned pos;
unsigned int pos;

pos = 0;
do {
Expand All @@ -135,7 +135,7 @@ static unsigned ht_lookup_slave_capability(struct device *dev)
}

static void ht_collapse_early_enumeration(struct bus *bus,
unsigned offset_unitid)
unsigned int offset_unitid)
{
unsigned int devfn;
struct ht_link prev;
Expand Down Expand Up @@ -207,7 +207,7 @@ static void ht_collapse_early_enumeration(struct bus *bus,
for (devfn = PCI_DEVFN(1, 0); devfn <= 0xff; devfn += 8) {
struct device dummy;
u32 id;
unsigned pos, flags;
unsigned int pos, flags;

dummy.bus = bus;
dummy.path.type = DEVICE_PATH_PCI;
Expand Down Expand Up @@ -236,10 +236,10 @@ static void ht_collapse_early_enumeration(struct bus *bus,
}
}

static unsigned int do_hypertransport_scan_chain(struct bus *bus, unsigned min_devfn,
unsigned max_devfn,
unsigned *ht_unitid_base,
unsigned offset_unitid)
static unsigned int do_hypertransport_scan_chain(struct bus *bus, unsigned int min_devfn,
unsigned int max_devfn,
unsigned int *ht_unitid_base,
unsigned int offset_unitid)
{
/*
* Even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this
Expand Down
4 changes: 2 additions & 2 deletions src/device/i2c.c
View file
Expand Up @@ -14,7 +14,7 @@
#include <device/i2c_simple.h>
#include <stdint.h>

int i2c_read_field(unsigned bus, uint8_t chip, uint8_t reg, uint8_t *data,
int i2c_read_field(unsigned int bus, uint8_t chip, uint8_t reg, uint8_t *data,
uint8_t mask, uint8_t shift)
{
int ret;
Expand All @@ -28,7 +28,7 @@ int i2c_read_field(unsigned bus, uint8_t chip, uint8_t reg, uint8_t *data,
return ret;
}

int i2c_write_field(unsigned bus, uint8_t chip, uint8_t reg, uint8_t data,
int i2c_write_field(unsigned int bus, uint8_t chip, uint8_t reg, uint8_t data,
uint8_t mask, uint8_t shift)
{
int ret;
Expand Down
1 change: 1 addition & 0 deletions src/device/oprom/realmode/x86.c
View file
Expand Up @@ -21,6 +21,7 @@
#include <device/pci_ids.h>
#include <pc80/i8259.h>
#include <pc80/i8254.h>
#include <stdlib.h>
#include <string.h>
#include <vbe.h>

Expand Down
26 changes: 14 additions & 12 deletions src/device/oprom/realmode/x86_asm.S
View file
Expand Up @@ -14,6 +14,8 @@
#define REALMODE_BASE 0x600
#define RELOCATED(x) (x - __realmode_code + REALMODE_BASE)

#include <arch/ram_segs.h>

/* CR0 bits */
#define PE (1 << 0)

Expand Down Expand Up @@ -106,7 +108,7 @@ __realmode_call:
movl %eax, __registers + 20 /* edi */

/* Activate the right segment descriptor real mode. */
ljmp $0x28, $RELOCATED(1f)
ljmp $RAM_CODE16_SEG, $RELOCATED(1f)
1:
.code16
/* 16 bit code from here on... */
Expand All @@ -116,7 +118,7 @@ __realmode_call:
* configurations (limits, writability, etc.) once
* protected mode is turned off.
*/
mov $0x30, %ax
mov $RAM_DATA16_SEG, %ax
mov %ax, %ds
mov %ax, %es
mov %ax, %fs
Expand Down Expand Up @@ -186,10 +188,10 @@ __lcall_instr = RELOCATED(.)
/* Now that we are in protected mode
* jump to a 32 bit code segment.
*/
ljmpl $0x10, $RELOCATED(1f)
ljmpl $RAM_CODE_SEG, $RELOCATED(1f)
1:
.code32
mov $0x18, %ax
mov $RAM_DATA_SEG, %ax
mov %ax, %ds
mov %ax, %es
mov %ax, %fs
Expand Down Expand Up @@ -242,15 +244,15 @@ __realmode_interrupt:
movl %eax, __registers + 20 /* edi */

/* This configures CS properly for real mode. */
ljmp $0x28, $RELOCATED(1f)
ljmp $RAM_CODE16_SEG, $RELOCATED(1f)
1:
.code16 /* 16 bit code from here on... */

/* Load the segment registers w/ properly configured segment
* descriptors. They will retain these configurations (limits,
* writability, etc.) once protected mode is turned off.
*/
mov $0x30, %ax
mov $RAM_DATA16_SEG, %ax
mov %ax, %ds
mov %ax, %es
mov %ax, %fs
Expand Down Expand Up @@ -314,10 +316,10 @@ __intXX_instr = RELOCATED(.)
movl %eax, %cr0

/* Now that we are in protected mode jump to a 32-bit code segment. */
ljmpl $0x10, $RELOCATED(1f)
ljmpl $RAM_CODE_SEG, $RELOCATED(1f)
1:
.code32
mov $0x18, %ax
mov $RAM_DATA_SEG, %ax
mov %ax, %ds
mov %ax, %es
mov %ax, %fs
Expand Down Expand Up @@ -363,10 +365,10 @@ __interrupt_handler_16bit = RELOCATED(.)
movl %eax, %cr0

/* ... and jump to a 32 bit code segment. */
ljmpl $0x10, $RELOCATED(1f)
ljmpl $RAM_CODE_SEG, $RELOCATED(1f)
1:
.code32
mov $0x18, %ax
mov $RAM_DATA_SEG, %ax
mov %ax, %ds
mov %ax, %es
mov %ax, %fs
Expand All @@ -380,14 +382,14 @@ __interrupt_handler_16bit = RELOCATED(.)
call *%eax

/* Now return to real mode ... */
ljmp $0x28, $RELOCATED(1f)
ljmp $RAM_CODE16_SEG, $RELOCATED(1f)
1:
.code16
/* Load the segment registers with properly configured segment
* descriptors. They will retain these configurations (limits,
* writability, etc.) once protected mode is turned off.
*/
mov $0x30, %ax
mov $RAM_DATA16_SEG, %ax
mov %ax, %ds
mov %ax, %es
mov %ax, %fs
Expand Down
1 change: 0 additions & 1 deletion src/device/oprom/realmode/x86_interrupts.c
View file
Expand Up @@ -15,7 +15,6 @@
#include <console/console.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <string.h>

/* we use x86emu's register file representation */
#include <x86emu/regs.h>
Expand Down
14 changes: 7 additions & 7 deletions src/device/oprom/x86emu/decode.c
View file
Expand Up @@ -735,7 +735,7 @@ Value of scale * index
Decodes scale/index of SIB byte and returns relevant offset part of
effective address.
****************************************************************************/
static unsigned decode_sib_si(
static unsigned int decode_sib_si(
int scale,
int index)
{
Expand Down Expand Up @@ -785,7 +785,7 @@ Offset in memory for the address decoding
REMARKS:
Decodes SIB addressing byte and returns calculated effective address.
****************************************************************************/
static unsigned decode_sib_address(
static unsigned int decode_sib_address(
int mod)
{
int sib = fetch_byte_imm();
Expand Down Expand Up @@ -874,10 +874,10 @@ NOTE: The code which specifies the corresponding segment (ds vs ss)
if a SS access is needed, set this bit. Otherwise, DS access
occurs (unless any of the segment override bits are set).
****************************************************************************/
unsigned decode_rm00_address(
unsigned int decode_rm00_address(
int rm)
{
unsigned offset;
unsigned int offset;

if (M.x86.mode & SYSMODE_PREFIX_ADDR) {
/* 32-bit addressing */
Expand Down Expand Up @@ -954,7 +954,7 @@ Offset in memory for the address decoding
Return the offset given by mod=01 addressing. Also enables the
decoding of instructions.
****************************************************************************/
unsigned decode_rm01_address(
unsigned int decode_rm01_address(
int rm)
{
int displacement;
Expand Down Expand Up @@ -1043,7 +1043,7 @@ Offset in memory for the address decoding
Return the offset given by mod=10 addressing. Also enables the
decoding of instructions.
****************************************************************************/
unsigned decode_rm10_address(
unsigned int decode_rm10_address(
int rm)
{
if (M.x86.mode & SYSMODE_PREFIX_ADDR) {
Expand Down Expand Up @@ -1136,7 +1136,7 @@ the decode_rmXX_address functions
Return the offset given by "mod" addressing.
****************************************************************************/

unsigned decode_rmXX_address(int mod, int rm)
unsigned int decode_rmXX_address(int mod, int rm)
{
if (mod == 0)
return decode_rm00_address(rm);
Expand Down
8 changes: 4 additions & 4 deletions src/device/oprom/x86emu/decode.h
View file
Expand Up @@ -76,10 +76,10 @@ u8* decode_rm_byte_register(int reg);
u16* decode_rm_word_register(int reg);
u32* decode_rm_long_register(int reg);
u16* decode_rm_seg_register(int reg);
unsigned decode_rm00_address(int rm);
unsigned decode_rm01_address(int rm);
unsigned decode_rm10_address(int rm);
unsigned decode_rmXX_address(int mod, int rm);
unsigned int decode_rm00_address(int rm);
unsigned int decode_rm01_address(int rm);
unsigned int decode_rm10_address(int rm);
unsigned int decode_rmXX_address(int mod, int rm);

#ifdef __cplusplus
} /* End of "C" linkage for C++ */
Expand Down
1 change: 0 additions & 1 deletion src/device/oprom/x86emu/sys.c
View file
Expand Up @@ -50,7 +50,6 @@
#ifdef IN_MODULE
#include "xf86_ansic.h"
#else
#include <string.h>
#endif
/*------------------------- Global Variables ------------------------------*/

Expand Down
1 change: 0 additions & 1 deletion src/device/oprom/x86emu/x86emui.h
View file
Expand Up @@ -72,7 +72,6 @@
#ifdef IN_MODULE
#include <xf86_ansic.h>
#else
#include <string.h>
#endif
/*--------------------------- Inline Functions ----------------------------*/

Expand Down
1 change: 0 additions & 1 deletion src/device/oprom/yabel/compat/functions.c
View file
Expand Up @@ -36,7 +36,6 @@
*/

#include <types.h>
#include <string.h>
#include <device/device.h>
#include "../debug.h"
#include "../biosemu.h"
Expand Down
1 change: 1 addition & 0 deletions src/device/oprom/yabel/vbe.c
View file
Expand Up @@ -32,6 +32,7 @@
* IBM Corporation - initial implementation
*****************************************************************************/

#include <boot/coreboot_tables.h>
#include <string.h>
#include <types.h>

Expand Down
1 change: 0 additions & 1 deletion src/device/pci_class.c
View file
Expand Up @@ -14,7 +14,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <stdlib.h>

typedef struct {
Expand Down
10 changes: 5 additions & 5 deletions src/device/pci_device.c
View file
Expand Up @@ -345,7 +345,7 @@ static void pci_read_bases(struct device *dev, unsigned int howmany)
}

static void pci_record_bridge_resource(struct device *dev, resource_t moving,
unsigned index, unsigned long type)
unsigned int index, unsigned long type)
{
struct resource *resource;
unsigned long gran;
Expand Down Expand Up @@ -1162,8 +1162,8 @@ unsigned int pci_match_simple_dev(struct device *dev, pci_devfn_t sdev)
* @param min_devfn Minimum devfn to look at in the scan, usually 0x00.
* @param max_devfn Maximum devfn to look at in the scan, usually 0xff.
*/
void pci_scan_bus(struct bus *bus, unsigned min_devfn,
unsigned max_devfn)
void pci_scan_bus(struct bus *bus, unsigned int min_devfn,
unsigned int max_devfn)
{
unsigned int devfn;
struct device *dev, **prev;
Expand Down Expand Up @@ -1311,8 +1311,8 @@ static void pci_bridge_route(struct bus *link, scan_state state)
*/
void do_pci_scan_bridge(struct device *dev,
void (*do_scan_bus) (struct bus * bus,
unsigned min_devfn,
unsigned max_devfn))
unsigned int min_devfn,
unsigned int max_devfn))
{
struct bus *bus;

Expand Down
8 changes: 4 additions & 4 deletions src/device/pci_rom.c
View file
Expand Up @@ -197,10 +197,10 @@ static struct rom_header *check_initialized(struct device *dev)
}

static unsigned long
pci_rom_acpi_fill_vfct(struct device *device, struct acpi_vfct *vfct_struct,
pci_rom_acpi_fill_vfct(struct device *device, acpi_vfct_t *vfct_struct,
unsigned long current)
{
struct acpi_vfct_image_hdr *header = &vfct_struct->image_hdr;
acpi_vfct_image_hdr_t *header = &vfct_struct->image_hdr;
struct rom_header *rom;

rom = check_initialized(device);
Expand Down Expand Up @@ -245,10 +245,10 @@ pci_rom_write_acpi_tables(struct device *device, unsigned long current,

/* AMD/ATI uses VFCT */
if (device->vendor == PCI_VENDOR_ID_ATI) {
struct acpi_vfct *vfct;
acpi_vfct_t *vfct;

current = ALIGN_UP(current, 8);
vfct = (struct acpi_vfct *)current;
vfct = (acpi_vfct_t *)current;
acpi_create_vfct(device, vfct, pci_rom_acpi_fill_vfct);
if (vfct->header.length) {
printk(BIOS_DEBUG, "ACPI: * VFCT at %lx\n", current);
Expand Down
17 changes: 8 additions & 9 deletions src/device/pciexp_device.c
View file
Expand Up @@ -15,7 +15,6 @@
#include <delay.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <device/pciexp.h>

Expand Down Expand Up @@ -46,7 +45,7 @@ unsigned int pciexp_find_extended_cap(struct device *dev, unsigned int cap)
* Re-train a PCIe link
*/
#define PCIE_TRAIN_RETRY 10000
static int pciexp_retrain_link(struct device *dev, unsigned cap)
static int pciexp_retrain_link(struct device *dev, unsigned int cap)
{
unsigned int try;
u16 lnk;
Expand Down Expand Up @@ -91,8 +90,8 @@ static int pciexp_retrain_link(struct device *dev, unsigned cap)
* and enable Common Clock Configuration if possible. If CCC is
* enabled the link must be retrained.
*/
static void pciexp_enable_common_clock(struct device *root, unsigned root_cap,
struct device *endp, unsigned endp_cap)
static void pciexp_enable_common_clock(struct device *root, unsigned int root_cap,
struct device *endp, unsigned int endp_cap)
{
u16 root_scc, endp_scc, lnkctl;

Expand Down Expand Up @@ -123,7 +122,7 @@ static void pciexp_enable_common_clock(struct device *root, unsigned root_cap,
}
}

static void pciexp_enable_clock_power_pm(struct device *endp, unsigned endp_cap)
static void pciexp_enable_clock_power_pm(struct device *endp, unsigned int endp_cap)
{
/* check if per port clk req is supported in device */
u32 endp_ca;
Expand Down Expand Up @@ -329,8 +328,8 @@ static void pciexp_config_L1_sub_state(struct device *root, struct device *dev)
* by checking both root port and endpoint and returning
* the highest latency value.
*/
static int pciexp_aspm_latency(struct device *root, unsigned root_cap,
struct device *endp, unsigned endp_cap,
static int pciexp_aspm_latency(struct device *root, unsigned int root_cap,
struct device *endp, unsigned int endp_cap,
enum aspm_type type)
{
int root_lat = 0, endp_lat = 0;
Expand Down Expand Up @@ -365,8 +364,8 @@ static int pciexp_aspm_latency(struct device *root, unsigned root_cap,
/*
* Enable ASPM on PCIe root port and endpoint.
*/
static void pciexp_enable_aspm(struct device *root, unsigned root_cap,
struct device *endp, unsigned endp_cap)
static void pciexp_enable_aspm(struct device *root, unsigned int root_cap,
struct device *endp, unsigned int endp_cap)
{
const char *aspm_type_str[] = { "None", "L0s", "L1", "L0s and L1" };
enum aspm_type apmc = PCIE_ASPM_NONE;
Expand Down
2 changes: 1 addition & 1 deletion src/device/pnp_device.c
View file
Expand Up @@ -109,7 +109,7 @@ void pnp_read_resources(struct device *dev)
static void pnp_set_resource(struct device *dev, struct resource *resource)
{
if (!(resource->flags & IORESOURCE_ASSIGNED)) {
/* The PNP_MSC super IO registers have the IRQ flag set. If no
/* The PNP_MSC Super IO registers have the IRQ flag set. If no
value is assigned in the devicetree, the corresponding
PNP_MSC register doesn't get written, which should be printed
as warning and not as error. */
Expand Down
45 changes: 12 additions & 33 deletions src/device/root_device.c
View file
Expand Up @@ -19,7 +19,7 @@
const char mainboard_name[] = CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER;

/**
* Scan devices on static buses.
* Enable devices on static buses.
*
* The enumeration of certain buses is purely static. The existence of
* devices on those buses can be completely determined at compile time
Expand All @@ -36,7 +36,7 @@ const char mainboard_name[] = CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_
* @param bus Pointer to the device to which the static buses are attached to.
*/

void scan_static_bus(struct device *bus)
void enable_static_devices(struct device *bus)
{
struct device *child;
struct bus *link;
Expand All @@ -56,30 +56,6 @@ void scan_static_bus(struct device *bus)
}
}

void scan_lpc_bus(struct device *bus)
{
printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus));

scan_static_bus(bus);

printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus));
}

void scan_usb_bus(struct device *bus)
{
struct bus *link;

printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus));

scan_static_bus(bus);

/* Scan bridges in case this device is a hub */
for (link = bus->link_list; link; link = link->next)
scan_bridges(link);

printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus));
}

void scan_generic_bus(struct device *bus)
{
struct device *child;
Expand Down Expand Up @@ -116,20 +92,23 @@ void scan_smbus(struct device *bus)
scan_generic_bus(bus);
}

/**
* Scan root bus for generic systems.
/*
* Default scan_bus() implementation
*
* This function is the default scan_bus() method of the root device.
* This is the default implementation for buses that can't
* be probed at runtime. It simply walks through the topology
* given by the mainboard's `devicetree.cb`.
*
* @param root The root device structure.
* First, all direct descendants of the given device are
* enabled. Then, downstream buses are scanned.
*/
static void root_dev_scan_bus(struct device *bus)
void scan_static_bus(struct device *bus)
{
struct bus *link;

printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus));

scan_static_bus(bus);
enable_static_devices(bus);

for (link = bus->link_list; link; link = link->next)
scan_bridges(link);
Expand Down Expand Up @@ -162,7 +141,7 @@ struct device_operations default_dev_ops_root = {
.set_resources = DEVICE_NOOP,
.enable_resources = DEVICE_NOOP,
.init = DEVICE_NOOP,
.scan_bus = root_dev_scan_bus,
.scan_bus = scan_static_bus,
.reset_bus = root_dev_reset,
#if CONFIG(HAVE_ACPI_TABLES)
.acpi_name = root_dev_acpi_name,
Expand Down
28 changes: 14 additions & 14 deletions src/device/software_i2c.c
View file
Expand Up @@ -38,7 +38,7 @@ struct software_i2c_ops *software_i2c[SOFTWARE_I2C_MAX_BUS];
* Waits until either timeout_us have passed or (iff for_scl is set) until SCL
* goes high. Will report random line changes during the wait and return SCL.
*/
static int __wait(unsigned bus, int timeout_us, int for_scl)
static int __wait(unsigned int bus, int timeout_us, int for_scl)
{
int us;
int sda = software_i2c[bus]->get_sda(bus);
Expand All @@ -63,13 +63,13 @@ static int __wait(unsigned bus, int timeout_us, int for_scl)
}

/* Waits the default DELAY_US to allow line state to stabilize. */
static void wait(unsigned bus)
static void wait(unsigned int bus)
{
__wait(bus, DELAY_US, 0);
}

/* Waits until SCL goes high. Prints a contextual error message on timeout. */
static int wait_for_scl(unsigned bus, const char *error_context)
static int wait_for_scl(unsigned int bus, const char *error_context)
{
if (!__wait(bus, TIMEOUT_US, 1)) {
printk(BIOS_ERR, "software_i2c(%d): ERROR: Clock stretching "
Expand All @@ -80,7 +80,7 @@ static int wait_for_scl(unsigned bus, const char *error_context)
return 0;
}

static int start_cond(unsigned bus)
static int start_cond(unsigned int bus)
{
spew("software_i2c(%d): Sending start condition... ", bus);

Expand Down Expand Up @@ -112,7 +112,7 @@ static int start_cond(unsigned bus)
return 0;
}

static int stop_cond(unsigned bus)
static int stop_cond(unsigned int bus)
{
spew("software_i2c(%d): Sending stop condition... ", bus);

Expand Down Expand Up @@ -141,7 +141,7 @@ static int stop_cond(unsigned bus)
return 0;
}

static int out_bit(unsigned bus, int bit)
static int out_bit(unsigned int bus, int bit)
{
spew("software_i2c(%d): Sending a %d bit... ", bus, bit);

Expand Down Expand Up @@ -174,7 +174,7 @@ static int out_bit(unsigned bus, int bit)
return 0;
}

static int in_bit(unsigned bus)
static int in_bit(unsigned int bus)
{
int bit;

Expand Down Expand Up @@ -202,9 +202,9 @@ static int in_bit(unsigned bus)
}

/* Write a byte to I2C bus. Return 0 if ack by the slave. */
static int out_byte(unsigned bus, u8 byte)
static int out_byte(unsigned int bus, u8 byte)
{
unsigned bit;
unsigned int bit;
int nack, ret;

for (bit = 0; bit < 8; bit++)
Expand All @@ -220,7 +220,7 @@ static int out_byte(unsigned bus, u8 byte)
return nack > 0 ? ERR_NACK : nack;
}

static int in_byte(unsigned bus, int ack)
static int in_byte(unsigned int bus, int ack)
{
u8 byte = 0;
int i, ret;
Expand All @@ -241,7 +241,7 @@ static int in_byte(unsigned bus, int ack)
return byte;
}

int software_i2c_transfer(unsigned bus, struct i2c_msg *segments, int count)
int software_i2c_transfer(unsigned int bus, struct i2c_msg *segments, int count)
{
int i, ret;
struct i2c_msg *seg;
Expand Down Expand Up @@ -269,7 +269,7 @@ int software_i2c_transfer(unsigned bus, struct i2c_msg *segments, int count)
return 0;
}

void software_i2c_wedge_ack(unsigned bus, u8 chip)
void software_i2c_wedge_ack(unsigned int bus, u8 chip)
{
int i;

Expand All @@ -292,7 +292,7 @@ void software_i2c_wedge_ack(unsigned bus, u8 chip)
software_i2c[bus]->get_scl(bus));
}

void software_i2c_wedge_read(unsigned bus, u8 chip, u8 reg, int bits)
void software_i2c_wedge_read(unsigned int bus, u8 chip, u8 reg, int bits)
{
int i;

Expand Down Expand Up @@ -321,7 +321,7 @@ void software_i2c_wedge_read(unsigned bus, u8 chip, u8 reg, int bits)
software_i2c[bus]->get_scl(bus));
}

void software_i2c_wedge_write(unsigned bus, u8 chip, u8 reg, int bits)
void software_i2c_wedge_write(unsigned int bus, u8 chip, u8 reg, int bits)
{
int i;

Expand Down
3 changes: 0 additions & 3 deletions src/drivers/amd/agesa/acpi_tables.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011-2012 Advanced Micro Devices, Inc.
* Copyright (C) 2016 Kyösti Mälkki
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/amd/agesa/cache_as_ram.S
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
3 changes: 0 additions & 3 deletions src/drivers/amd/agesa/def_callouts.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
* Copyright (C) 2013 Sage Electronic Engineering, LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/amd/agesa/eventlog.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2016-2019 Kyösti Mälkki
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/amd/agesa/oem_s3.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/amd/agesa/romstage.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Kyösti Mälkki
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
4 changes: 1 addition & 3 deletions src/drivers/amd/agesa/s3_mtrr.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand All @@ -21,7 +19,7 @@
#include <string.h>
#include <northbridge/amd/agesa/agesa_helper.h>

static void write_mtrr(u8 **p_nvram_pos, unsigned idx)
static void write_mtrr(u8 **p_nvram_pos, unsigned int idx)
{
msr_t msr_data;
msr_data = rdmsr(idx);
Expand Down
3 changes: 0 additions & 3 deletions src/drivers/amd/agesa/state_machine.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011-2012 Advanced Micro Devices, Inc.
* Copyright (C) 2016 Kyösti Mälkki
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/ams/as3722rtc.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/asmedia/Makefile.inc
View file
@@ -1,8 +1,6 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2018 secunet Security Networks AG
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/asmedia/aspm_blacklist.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 secunet Security Networks AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/aspeed/ast2050/ast2050.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/aspeed/common/aspeed_coreboot.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
Expand Down
10 changes: 6 additions & 4 deletions src/drivers/aspeed/common/ast_dp501.c
View file
@@ -1,10 +1,6 @@
/*
* This file is part of the coreboot project.
*
* File taken from the Linux ast driver (v3.18.5)
* coreboot-specific includes added at top and/or contents modified
* as needed to function within the coreboot environment.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand All @@ -15,6 +11,12 @@
* GNU General Public License for more details.
*/

/*
* File taken from the Linux ast driver (v3.18.5)
* coreboot-specific includes added at top and/or contents modified
* as needed to function within the coreboot environment.
*/

#include <delay.h>

#include "ast_drv.h"
Expand Down
9 changes: 5 additions & 4 deletions src/drivers/aspeed/common/ast_dram_tables.h
View file
@@ -1,10 +1,6 @@
/*
* This file is part of the coreboot project.
*
* File taken from the Linux ast driver (v3.18.5)
* coreboot-specific includes added at top and/or contents modified
* as needed to function within the coreboot environment.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand All @@ -15,6 +11,11 @@
* GNU General Public License for more details.
*/

/*
* File taken from the Linux ast driver (v3.18.5)
* coreboot-specific includes added at top and/or contents modified
* as needed to function within the coreboot environment.
*/
#ifndef AST_DRAM_TABLES_H
#define AST_DRAM_TABLES_H

Expand Down
2 changes: 2 additions & 0 deletions src/drivers/aspeed/common/ast_drv.h
View file
@@ -1,4 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2012 Red Hat Inc.
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
*
Expand Down
2 changes: 2 additions & 0 deletions src/drivers/aspeed/common/ast_main.c
View file
@@ -1,4 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2012 Red Hat Inc.
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
*
Expand Down
5 changes: 2 additions & 3 deletions src/drivers/aspeed/common/ast_post.c
View file
@@ -1,4 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2012 Red Hat Inc.
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
*
Expand All @@ -23,9 +25,6 @@
* of the Software.
*
*/
/*
* Authors: Dave Airlie <airlied@redhat.com>
*/

#define COREBOOT_AST_FAILOVER_TIMEOUT 10000000

Expand Down
2 changes: 2 additions & 0 deletions src/drivers/aspeed/common/ast_tables.h
View file
@@ -1,4 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (c) 2005 ASPEED Technology Inc.
*
* Permission to use, copy, modify, distribute, and sell this software and its
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/crb/chip.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/dec/21143/21143.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/elog/Kconfig
View file
@@ -1,8 +1,6 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/elog/boot_count.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/elog/elog.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/elog/elog_internal.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/elog/gsmi.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/emulation/qemu/bochs.c
View file
Expand Up @@ -15,11 +15,9 @@
#include <edid.h>
#include <stdlib.h>
#include <arch/io.h>
#include <boot/coreboot_tables.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <pc80/vga.h>
#include <pc80/vga_io.h>
Expand Down
34 changes: 15 additions & 19 deletions src/drivers/emulation/qemu/cirrus.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
Expand All @@ -17,11 +15,9 @@
#include <stdint.h>
#include <edid.h>
#include <stdlib.h>
#include <boot/coreboot_tables.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <pc80/vga.h>
#include <pc80/vga_io.h>
Expand Down Expand Up @@ -201,23 +197,23 @@ write_hidden_dac (uint8_t data)
static void cirrus_init_linear_fb(struct device *dev)
{
uint8_t cr_ext, cr_overlay;
unsigned pitch = (width * 4) / VGA_CR_PITCH_DIVISOR;
unsigned int pitch = (width * 4) / VGA_CR_PITCH_DIVISOR;
uint8_t sr_ext = 0, hidden_dac = 0;
unsigned vdisplay_end = height - 2;
unsigned line_compare = 0x3ff;
unsigned int vdisplay_end = height - 2;
unsigned int line_compare = 0x3ff;
uint8_t overflow, cell_height_reg;
unsigned horizontal_end = width / VGA_CR_WIDTH_DIVISOR;
unsigned horizontal_total = horizontal_end + 40;
unsigned horizontal_blank_start = horizontal_end;
unsigned horizontal_sync_pulse_start = horizontal_end + 3;
unsigned horizontal_sync_pulse_end = 0;

unsigned horizontal_blank_end = 0;
unsigned vertical_blank_start = height + 1;
unsigned vertical_blank_end = 0;
unsigned vertical_sync_start = height + 3;
unsigned vertical_sync_end = 0;
unsigned vertical_total = height + 40;
unsigned int horizontal_end = width / VGA_CR_WIDTH_DIVISOR;
unsigned int horizontal_total = horizontal_end + 40;
unsigned int horizontal_blank_start = horizontal_end;
unsigned int horizontal_sync_pulse_start = horizontal_end + 3;
unsigned int horizontal_sync_pulse_end = 0;

unsigned int horizontal_blank_end = 0;
unsigned int vertical_blank_start = height + 1;
unsigned int vertical_blank_end = 0;
unsigned int vertical_sync_start = height + 3;
unsigned int vertical_sync_end = 0;
unsigned int vertical_total = height + 40;

/* find lfb pci bar */
addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
Expand Down
3 changes: 0 additions & 3 deletions src/drivers/emulation/qemu/qemu_debugcon.c
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Red Hat Inc.
* Written by Gerd Hoffmann <kraxel@redhat.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/generic/adau7002/adau7002.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2018 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/generic/adau7002/chip.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2018 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
6 changes: 2 additions & 4 deletions src/drivers/generic/bayhub/bh720.c
View file
@@ -1,10 +1,6 @@
/*
* Driver for BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge
*
* This file is part of the coreboot project.
*
* Copyright 2018 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand All @@ -15,6 +11,8 @@
* GNU General Public License for more details.
*/

/* Driver for BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge */

#include <console/console.h>
#include <device/device.h>
#include <device/path.h>
Expand Down
6 changes: 2 additions & 4 deletions src/drivers/generic/bayhub/bh720.h
View file
@@ -1,10 +1,6 @@
/*
* Driver for BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge
*
* This file is part of the coreboot project.
*
* Copyright 2018 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand All @@ -15,6 +11,8 @@
* GNU General Public License for more details.
*/

/* Driver for BayHub Technology BH720 PCI to eMMC 5.0 HS200 bridge */

#include <types.h>

enum {
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/generic/bayhub/chip.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2018 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/generic/generic/chip.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2018 Google LLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/generic/generic/generic.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2018 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/generic/gpio_keys/chip.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2018 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/generic/gpio_keys/gpio_keys.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2018 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/generic/gpio_regulator/Kconfig
View file
@@ -1,8 +1,6 @@
#
# This file is part of the coreboot project.
#
# Copyright 2016 Google Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/generic/gpio_regulator/Makefile.inc
View file
@@ -1,8 +1,6 @@
#
# This file is part of the coreboot project.
#
# Copyright 2016 Google Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/generic/gpio_regulator/chip.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/generic/gpio_regulator/gpio_regulator.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
3 changes: 0 additions & 3 deletions src/drivers/generic/ioapic/chip.h
View file
@@ -1,9 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
* Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
13 changes: 13 additions & 0 deletions src/drivers/generic/ioapic/ioapic.c
View file
@@ -1,3 +1,16 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include <console/console.h>
#include <device/device.h>
#include "chip.h"
Expand Down
19 changes: 16 additions & 3 deletions src/drivers/generic/max98357a/chip.h
View file
@@ -1,13 +1,26 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include <arch/acpi_device.h>

struct drivers_generic_max98357a_config {
/* SDMODE GPIO */
struct acpi_gpio sdmode_gpio;

/* SDMODE Delay */
unsigned sdmode_delay;
unsigned int sdmode_delay;

/* GPIO used to indicate if this device is present */
unsigned device_present_gpio;
unsigned device_present_gpio_invert;
unsigned int device_present_gpio;
unsigned int device_present_gpio_invert;
};
2 changes: 0 additions & 2 deletions src/drivers/generic/max98357a/max98357a.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/gic/gic.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/gic/gic.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down
13 changes: 13 additions & 0 deletions src/drivers/i2c/adm1026/adm1026.c
View file
@@ -1,3 +1,16 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include <console/console.h>
#include <device/device.h>
#include <device/smbus.h>
Expand Down
13 changes: 13 additions & 0 deletions src/drivers/i2c/adm1027/adm1027.c
View file
@@ -1,3 +1,16 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include <console/console.h>
#include <device/device.h>
#include <device/smbus.h>
Expand Down
4 changes: 0 additions & 4 deletions src/drivers/i2c/adt7463/adt7463.c
View file
@@ -1,10 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2005 Tyan
* (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
* Copyright (C) 2007 Ward Vandewege <ward@gnu.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
Expand Down
2 changes: 0 additions & 2 deletions src/drivers/i2c/at24rf08c/at24rf08c.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
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4 changes: 1 addition & 3 deletions src/drivers/i2c/at24rf08c/lenovo_serials.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down Expand Up @@ -118,7 +116,7 @@ const char *smbios_mainboard_product_name(void)
void smbios_system_set_uuid(u8 *uuid)
{
static char result[16];
unsigned i;
unsigned int i;
static int already_read;
struct device *dev;
const int remap[16] = {
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2 changes: 0 additions & 2 deletions src/drivers/i2c/ck505/chip.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
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2 changes: 0 additions & 2 deletions src/drivers/i2c/ck505/ck505.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
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41 changes: 27 additions & 14 deletions src/drivers/i2c/da7219/chip.h
View file
@@ -1,3 +1,16 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include <arch/acpi_device.h>

/*
Expand All @@ -12,13 +25,13 @@ struct drivers_i2c_da7219_config {
struct acpi_gpio irq_gpio;

/* I2C Bus Frequency in Hertz (default 400kHz) */
unsigned bus_speed;
unsigned int bus_speed;

/*
* micbias-lvl : Voltage (mV) for Mic Bias
* [<1600>, <1800>, <2000>, <2200>, <2400>, <2600>]
*/
unsigned micbias_lvl;
unsigned int micbias_lvl;

/*
* mic-amp-in-sel : Mic input source type
Expand All @@ -34,30 +47,30 @@ struct drivers_i2c_da7219_config {
* micbias-pulse-lvl : Mic bias higher voltage pulse level (mV)
* [<2800>, <2900>]
*/
unsigned micbias_pulse_lvl;
unsigned int micbias_pulse_lvl;

/*
* micbias-pulse-time : Mic bias higher voltage pulse duration (ms)
*/
unsigned micbias_pulse_time;
unsigned int micbias_pulse_time;

/*
* btn-cfg : Periodic button press measurements for 4-pole jack (ms)
* [<2>, <5>, <10>, <50>, <100>, <200>, <500>]
*/
unsigned btn_cfg;
unsigned int btn_cfg;

/*
* mic-det-thr : Impedance threshold for mic detection measurement (Ohms)
* [<200>, <500>, <750>, <1000>]
*/
unsigned mic_det_thr;
unsigned int mic_det_thr;

/*
* jack-ins-deb : Debounce time for jack insertion (ms)
* [<5>, <10>, <20>, <50>, <100>, <200>, <500>, <1000>]
*/
unsigned jack_ins_deb;
unsigned int jack_ins_deb;

/*
* jack-det-rate : Jack type detection latency (3/4 pole)
Expand All @@ -69,43 +82,43 @@ struct drivers_i2c_da7219_config {
* jack-rem-deb : Debounce time for jack removal (ms)
* [<1>, <5>, <10>, <20>]
*/
unsigned jack_rem_deb;
unsigned int jack_rem_deb;

/*
* a-d-btn-thr : Impedance threshold between buttons A and D
* [0x0 - 0xFF]
*/
unsigned a_d_btn_thr;
unsigned int a_d_btn_thr;

/*
* d-b-btn-thr : Impedance threshold between buttons D and B
* [0x0 - 0xFF]
*/
unsigned d_b_btn_thr;
unsigned int d_b_btn_thr;

/*
* b-c-btn-thr : Impedance threshold between buttons B and C
* [0x0 - 0xFF]
*/
unsigned b_c_btn_thr;
unsigned int b_c_btn_thr;

/*
* c-mic-btn-thr : Impedance threshold between button C and Mic
* [0x0 - 0xFF]
*/
unsigned c_mic_btn_thr;
unsigned int c_mic_btn_thr;

/*
* btn-avg : Number of 8-bit readings for averaged button measurement
* [<1>, <2>, <4>, <8>]
*/
unsigned btn_avg;
unsigned int btn_avg;

/*
* adc-1bit-rpt : Repeat count for 1-bit button measurement
* [<1>, <2>, <4>, <8>]
*/
unsigned adc_1bit_rpt;
unsigned int adc_1bit_rpt;

/*
* mclk-name : Pass the system clk to da7219
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2 changes: 0 additions & 2 deletions src/drivers/i2c/da7219/da7219.c
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
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4 changes: 0 additions & 4 deletions src/drivers/i2c/designware/dw_i2c.c
View file
@@ -1,10 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2009 Vipin Kumar, ST Microelectronics
* Copyright 2017 Google Inc.
* Copyright 2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
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2 changes: 0 additions & 2 deletions src/drivers/i2c/designware/dw_i2c.h
View file
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
Expand Down