48 changes: 47 additions & 1 deletion src/device/Kconfig
View file
Expand Up @@ -413,6 +413,8 @@ choice
prompt "Framebuffer mode"
default VBE_LINEAR_FRAMEBUFFER if HAVE_VBE_LINEAR_FRAMEBUFFER && CHROMEOS
default GENERIC_LINEAR_FRAMEBUFFER if HAVE_LINEAR_FRAMEBUFFER && CHROMEOS
default VBE_LINEAR_FRAMEBUFFER if HAVE_VBE_LINEAR_FRAMEBUFFER && PAYLOAD_TIANOCORE
default GENERIC_LINEAR_FRAMEBUFFER if HAVE_LINEAR_FRAMEBUFFER && PAYLOAD_TIANOCORE
default VGA_TEXT_FRAMEBUFFER

config VGA_TEXT_FRAMEBUFFER
Expand Down Expand Up @@ -555,6 +557,50 @@ config PCIEXP_L1_SUB_STATE
help
Detect and enable ASPM on PCIe links.

config PCIEXP_HOTPLUG
prompt "Enable PCIe Hotplug Support"
bool
default n
help
Allocate resources for PCIe hotplug bridges

if PCIEXP_HOTPLUG

config PCIEXP_HOTPLUG_BUSES
int "PCI Express Hotplug Buses"
default 32
help
This is the number of buses allocated for hotplug PCI express
bridges, for use by hotplugged child devices. The default is 32
buses.

config PCIEXP_HOTPLUG_MEM
hex "PCI Express Hotplug Memory"
default 0x800000
help
This is the amount of memory space, in bytes, to allocate to
hotplug PCI express bridges, for use by hotplugged child devices.
This size should be page-aligned. The default is 8 MiB.

config PCIEXP_HOTPLUG_PREFETCH_MEM
hex "PCI Express Hotplug Prefetch Memory"
default 0x10000000
help
This is the amount of pre-fetchable memory space, in bytes, to
allocate to hot-plug PCI express bridges, for use by hotplugged
child devices. This size should be page-aligned. The default is
256 MiB.

config PCIEXP_HOTPLUG_IO
hex "PCI Express Hotplug I/O Space"
default 0x2000
help
This is the amount of I/O space to allocate to hot-plug PCI
express bridges, for use by hotplugged child devices. The default
is 8 KiB.

endif # PCIEXP_HOTPLUG

endif # PCIEXP_PLUGIN_SUPPORT

config EARLY_PCI_BRIDGE
Expand Down Expand Up @@ -677,7 +723,7 @@ config INTEL_GMA_HAVE_VBT

config INTEL_GMA_ADD_VBT
depends on SOC_INTEL_COMMON || CPU_INTEL_COMMON
bool "Add a Video Bios Table (VBT) binary to CBFS"
bool "Add a Video BIOS Table (VBT) binary to CBFS"
default y if INTEL_GMA_HAVE_VBT
help
Add a VBT data file to CBFS. The VBT describes the integrated
Expand Down
2 changes: 1 addition & 1 deletion src/device/oprom/include/x86emu/x86emu.h
View file
Expand Up @@ -170,7 +170,7 @@ void X86EMU_halt_sys(void);
#define DEBUG_SVC_F 0x000020
#define DEBUG_FS_F 0x000080
#define DEBUG_PROC_F 0x000100
#define DEBUG_SYSINT_F 0x000200 /* bios system interrupts. */
#define DEBUG_SYSINT_F 0x000200 /* BIOS system interrupts. */
#define DEBUG_TRACECALL_F 0x000400
#define DEBUG_INSTRUMENT_F 0x000800
#define DEBUG_MEM_TRACE_F 0x001000
Expand Down
16 changes: 15 additions & 1 deletion src/device/pci_device.c
View file
Expand Up @@ -878,6 +878,14 @@ static struct device_operations *get_pci_bridge_ops(struct device *dev)
case PCI_EXP_TYPE_DOWNSTREAM:
printk(BIOS_DEBUG, "%s subordinate bus PCI Express\n",
dev_path(dev));
#if CONFIG(PCIEXP_HOTPLUG)
u16 sltcap;
sltcap = pci_read_config16(dev, pciexpos + PCI_EXP_SLTCAP);
if (sltcap & PCI_EXP_SLTCAP_HPC) {
printk(BIOS_DEBUG, "%s hot-plug capable\n", dev_path(dev));
return &default_pciexp_hotplug_ops_bus;
}
#endif /* CONFIG(PCIEXP_HOTPLUG) */
return &default_pciexp_ops_bus;
case PCI_EXP_TYPE_PCI_BRIDGE:
printk(BIOS_DEBUG, "%s subordinate PCI\n",
Expand Down Expand Up @@ -1187,6 +1195,12 @@ void pci_scan_bus(struct bus *bus, unsigned int min_devfn,
* non-existence and single function devices.
*/
for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
if (CONFIG(MINIMAL_PCI_SCANNING)) {
dev = pcidev_path_behind(bus, devfn);
if (!dev || !dev->mandatory)
continue;
}

/* First thing setup the device structure. */
dev = pci_scan_get_dev(bus, devfn);

Expand Down Expand Up @@ -1259,7 +1273,7 @@ static void pci_bridge_route(struct bus *link, scan_state state)

if (state == PCI_ROUTE_SCAN) {
link->secondary = parent->subordinate + 1;
link->subordinate = link->secondary;
link->subordinate = link->secondary + dev->hotplug_buses;
}

if (state == PCI_ROUTE_CLOSE) {
Expand Down
59 changes: 59 additions & 0 deletions src/device/pciexp_device.c
View file
Expand Up @@ -518,3 +518,62 @@ struct device_operations default_pciexp_ops_bus = {
.reset_bus = pci_bus_reset,
.ops_pci = &pciexp_bus_ops_pci,
};

#if CONFIG(PCIEXP_HOTPLUG)

static void pciexp_hotplug_dummy_read_resources(struct device *dev)
{
struct resource *resource;

// Add extra memory space
resource = new_resource(dev, 0x10);
resource->size = CONFIG_PCIEXP_HOTPLUG_MEM;
resource->align = 12;
resource->gran = 12;
resource->limit = 0xffffffff;
resource->flags |= IORESOURCE_MEM;

// Add extra prefetchable memory space
resource = new_resource(dev, 0x14);
resource->size = CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM;
resource->align = 12;
resource->gran = 12;
resource->limit = 0xffffffffffffffff;
resource->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;

// Add extra I/O space
resource = new_resource(dev, 0x18);
resource->size = CONFIG_PCIEXP_HOTPLUG_IO;
resource->align = 12;
resource->gran = 12;
resource->limit = 0xffff;
resource->flags |= IORESOURCE_IO;
}

static struct device_operations pciexp_hotplug_dummy_ops = {
.read_resources = pciexp_hotplug_dummy_read_resources,
};

void pciexp_hotplug_scan_bridge(struct device *dev)
{
dev->hotplug_buses = CONFIG_PCIEXP_HOTPLUG_BUSES;

/* Normal PCIe Scan */
pciexp_scan_bridge(dev);

/* Add dummy slot to preserve resources, must happen after bus scan */
struct device *dummy;
struct device_path dummy_path = { .type = DEVICE_PATH_NONE };
dummy = alloc_dev(dev->link_list, &dummy_path);
dummy->ops = &pciexp_hotplug_dummy_ops;
}

struct device_operations default_pciexp_hotplug_ops_bus = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources,
.scan_bus = pciexp_hotplug_scan_bridge,
.reset_bus = pci_bus_reset,
.ops_pci = &pciexp_bus_ops_pci,
};
#endif /* CONFIG(PCIEXP_HOTPLUG) */
4 changes: 2 additions & 2 deletions src/device/pnp_device.c
View file
Expand Up @@ -129,12 +129,12 @@ static void pnp_set_resource(struct device *dev, struct resource *resource)
(resource->index != PNP_IDX_IRQ0) &&
(resource->index != PNP_IDX_IRQ1))
printk(BIOS_WARNING, "WARNING: %s %02lx %s size: "
"0x%010llx not assigned\n", dev_path(dev),
"0x%010llx not assigned in devicetree\n", dev_path(dev),
resource->index, resource_type(resource),
resource->size);
else
printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx "
"not assigned\n", dev_path(dev), resource->index,
"not assigned in devicetree\n", dev_path(dev), resource->index,
resource_type(resource), resource->size);
return;
}
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/analogix/anx7625/anx7625.c
View file
Expand Up @@ -273,7 +273,7 @@ static int anx7625_calculate_m_n(u32 pixelclock,
return 1;
}

*m = (unsigned long long)pixelclock * 599 / 600;
*m = pixelclock;
*n = XTAL_FRQ / post_divider;
*pd = post_divider;

Expand Down
1 change: 0 additions & 1 deletion src/drivers/generic/gfx/Makefile.inc
View file

This file was deleted.

2 changes: 1 addition & 1 deletion src/drivers/generic/gfx/Kconfig → src/drivers/gfx/generic/Kconfig
View file
@@ -1,4 +1,4 @@
config DRIVERS_GENERIC_GFX
config DRIVERS_GFX_GENERIC
bool
default n
depends on HAVE_ACPI_TABLES
Expand Down
1 change: 1 addition & 0 deletions src/drivers/gfx/generic/Makefile.inc
View file
@@ -0,0 +1 @@
ramstage-$(CONFIG_DRIVERS_GFX_GENERIC) += generic.c
16 changes: 8 additions & 8 deletions src/drivers/generic/gfx/chip.h → src/drivers/gfx/generic/chip.h
View file
Expand Up @@ -13,11 +13,11 @@
* GNU General Public License for more details.
*/

#ifndef __DRIVERS_GENERIC_GFX_CHIP_H__
#define __DRIVERS_GENERIC_GFX_CHIP_H__
#ifndef __DRIVERS_GFX_GENERIC_CHIP_H__
#define __DRIVERS_GFX_GENERIC_CHIP_H__

/* Config for electronic privacy screen */
struct drivers_generic_gfx_privacy_screen_config {
struct drivers_gfx_generic_privacy_screen_config {
/* Is privacy screen available on this graphics device */
int enabled;
/* ACPI namespace path to privacy screen detection function */
Expand All @@ -31,17 +31,17 @@ struct drivers_generic_gfx_privacy_screen_config {
};

/* Config for an output device as defined in section A.5 of the ACPI spec */
struct drivers_generic_gfx_device_config {
struct drivers_gfx_generic_device_config {
/* ACPI device name of the output device */
const char *name;
/* The address of the output device. See section A.3.2 */
unsigned int addr;
/* Electronic privacy screen specific config */
struct drivers_generic_gfx_privacy_screen_config privacy;
struct drivers_gfx_generic_privacy_screen_config privacy;
};

/* Config for an ACPI video device defined in Appendix A of the ACPI spec */
struct drivers_generic_gfx_config {
struct drivers_gfx_generic_config {
/*
* ACPI device name of the graphics card, "GFX0" will be used if name is
* not set
Expand All @@ -50,7 +50,7 @@ struct drivers_generic_gfx_config {
/* The number of output devices defined */
int device_count;
/* Config for output devices */
struct drivers_generic_gfx_device_config device[5];
struct drivers_gfx_generic_device_config device[5];
};

#endif /* __DRIVERS_GENERIC_GFX_CHIP_H__ */
#endif /* __DRIVERS_GFX_GENERIC_CHIP_H__ */
21 changes: 12 additions & 9 deletions src/drivers/generic/gfx/gfx.c → src/drivers/gfx/generic/generic.c
View file
Expand Up @@ -26,7 +26,7 @@

static void privacy_screen_detect_cb(void *arg)
{
struct drivers_generic_gfx_privacy_screen_config *config = arg;
struct drivers_gfx_generic_privacy_screen_config *config = arg;

acpigen_write_store();
acpigen_emit_namestring(config->detect_function);
Expand All @@ -37,20 +37,20 @@ static void privacy_screen_detect_cb(void *arg)
}
static void privacy_screen_get_status_cb(void *arg)
{
struct drivers_generic_gfx_privacy_screen_config *config = arg;
struct drivers_gfx_generic_privacy_screen_config *config = arg;

acpigen_emit_byte(RETURN_OP);
acpigen_emit_namestring(config->status_function);
}
static void privacy_screen_enable_cb(void *arg)
{
struct drivers_generic_gfx_privacy_screen_config *config = arg;
struct drivers_gfx_generic_privacy_screen_config *config = arg;

acpigen_emit_namestring(config->enable_function);
}
static void privacy_screen_disable_cb(void *arg)
{
struct drivers_generic_gfx_privacy_screen_config *config = arg;
struct drivers_gfx_generic_privacy_screen_config *config = arg;

acpigen_emit_namestring(config->disable_function);
}
Expand All @@ -65,10 +65,13 @@ static void (*privacy_screen_callbacks[])(void *) = {
static void gfx_fill_ssdt_generator(struct device *dev)
{
size_t i;
struct drivers_generic_gfx_config *config = dev->chip_info;
struct drivers_gfx_generic_config *config = dev->chip_info;

const char *scope = acpi_device_scope(dev);

if (!scope)
return;

acpigen_write_scope(scope);

/* Method (_DOD, 0) */
Expand Down Expand Up @@ -100,7 +103,7 @@ static void gfx_fill_ssdt_generator(struct device *dev)

static const char *gfx_acpi_name(const struct device *dev)
{
struct drivers_generic_gfx_config *config = dev->chip_info;
struct drivers_gfx_generic_config *config = dev->chip_info;

return config->name ? : "GFX0";
}
Expand All @@ -112,15 +115,15 @@ static struct device_operations gfx_ops = {

static void gfx_enable(struct device *dev)
{
struct drivers_generic_gfx_config *config = dev->chip_info;
struct drivers_gfx_generic_config *config = dev->chip_info;

if (!config)
return;

dev->ops = &gfx_ops;
}

struct chip_operations drivers_generic_gfx_ops = {
CHIP_NAME("Graphics Device")
struct chip_operations drivers_gfx_generic_ops = {
CHIP_NAME("Generic Graphics Device")
.enable_dev = gfx_enable
};
2 changes: 1 addition & 1 deletion src/drivers/intel/fsp1_1/exit_car.S
View file
Expand Up @@ -17,7 +17,7 @@
chipset_teardown_car:

pop %ebx
/* Move the stack pointer to real ram */
/* Move the stack pointer to real RAM */
movl post_car_stack_top, %esp
/* Align the stack 16 bytes */
andl $0xfffffff0, %esp
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/intel/fsp2_0/Kconfig
View file
Expand Up @@ -61,7 +61,7 @@ config FSP_USE_REPO
and FSP_FD_PATH correctly so FSP splitting works.

config FSP_T_FILE
string "Intel FSP-T (temp ram init) binary path and filename"
string "Intel FSP-T (temp RAM init) binary path and filename"
depends on FSP_CAR
default "$(obj)/Fsp_T.fd" if FSP_USE_REPO
help
Expand Down
18 changes: 14 additions & 4 deletions src/drivers/intel/fsp2_0/include/fsp/soc_binding.h
View file
Expand Up @@ -17,6 +17,20 @@
#include <stddef.h>

#pragma pack(push)

/**
* These includes are required to include headers that are missing in
* the FSP headers. Import order matter for the correct PiHob definition
* to be found.
*/
#if CONFIG_UDK_VERSION >= CONFIG_UDK_2017_VERSION
#include <PiPei.h>
#include <Ppi/MpServices.h>
#include <Uefi/UefiMultiPhase.h>
#include <Pi/PiBootMode.h>
#include <Pi/PiHob.h>
#endif

/*
* This file is a implementation specific header. i.e. different
* FSP implementations for different chipsets.
Expand All @@ -28,10 +42,6 @@
#include <FirmwareVersionInfoHob.h>
#endif

#if CONFIG_UDK_VERSION >= CONFIG_UDK_2017_VERSION
#include <PiPei.h>
#include <Ppi/MpServices.h>
#endif

#pragma pack(pop)

Expand Down
2 changes: 1 addition & 1 deletion src/drivers/intel/gma/edid.c
View file
Expand Up @@ -103,7 +103,7 @@ void intel_gmbus_read_edid(u8 *mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size)

printk (BIOS_SPEW, "EDID:\n");
for (i = 0; i < 128; i++) {
printk (BIOS_SPEW, "%02x ", edid[i]);
printk(BIOS_SPEW, " %02x", edid[i]);
if ((i & 0xf) == 0xf)
printk (BIOS_SPEW, "\n");
}
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/intel/gma/int15.c
View file
Expand Up @@ -33,7 +33,7 @@ int intel_vga_int15_handler(void)
* bit 2 = Graphics Stretching
* bit 1 = Text Stretching
* bit 0 = Centering (do not set with bit1 or bit2)
* 0 = video bios default
* 0 = video BIOS default
*/
X86_AX = 0x005f;
X86_CX = pfit;
Expand Down
12 changes: 12 additions & 0 deletions src/drivers/net/chip.h
View file
Expand Up @@ -15,10 +15,22 @@
#define __DRIVERS_R8168_CHIP_H__

#include <stdint.h>
#include <arch/acpi_device.h>

struct drivers_net_config {
uint16_t customized_leds;
unsigned int wake; /* Wake pin for ACPI _PRW */

/* Does the device have a power resource? */
bool has_power_resource;

/* GPIO used to stop operation of device. */
struct acpi_gpio stop_gpio;
/* Delay to be inserted after disabling stop. */
unsigned int stop_delay_ms;
/* Delay to be inserted after enabling stop. */
unsigned int stop_off_delay_ms;

/*
* There maybe many NIC cards in a system.
* This parameter is for driver to identify what
Expand Down
10 changes: 10 additions & 0 deletions src/drivers/net/r8168.c
View file
Expand Up @@ -317,6 +317,16 @@ static void r8168_net_fill_ssdt(struct device *dev)
if (dev->chip_ops)
acpigen_write_name_string("_DDN", dev->chip_ops->name);

/* Power Resource */
if (config->has_power_resource) {
const struct acpi_power_res_params power_res_params = {
.stop_gpio = &config->stop_gpio,
.stop_delay_ms = config->stop_delay_ms,
.stop_off_delay_ms = config->stop_off_delay_ms
};
acpi_device_add_power_res(&power_res_params);
}

/* Address */
address = PCI_SLOT(dev->path.pci.devfn) & 0xffff;
address <<= 16;
Expand Down
4 changes: 2 additions & 2 deletions src/drivers/pc80/rtc/mc146818rtc.c
View file
Expand Up @@ -160,7 +160,7 @@ static void cmos_init_vbnv(bool invalid)
occurred with !CONFIG_USE_OPTION_TABLE. However, __cmos_init() may
clear vbnv data for other internal reasons. For that, always back up
the vbnv contents and conditionally save them when __cmos_init()
indicates cmos was cleared. */
indicates CMOS was cleared. */
read_vbnv_cmos(vbnv);

if (__cmos_init(invalid))
Expand Down Expand Up @@ -204,7 +204,7 @@ void cmos_check_update_date(void)
year = cmos_read(RTC_CLK_YEAR);

/*
* TODO: If century is 0xFF, 100% that the cmos is cleared.
* TODO: If century is 0xFF, 100% that the CMOS is cleared.
* Other than that, so far rtc_year is the only entry to check
* if the date is valid.
*/
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/pc80/rtc/option.c
View file
Expand Up @@ -26,7 +26,7 @@

/*
* This routine returns the value of the requested bits.
* input bit = bit count from the beginning of the cmos image
* input bit = bit count from the beginning of the CMOS image
* length = number of bits to include in the value
* ret = a character pointer to where the value is to be returned
* returns CB_SUCCESS = successful, cb_err code if an error occurred
Expand Down
50 changes: 25 additions & 25 deletions src/drivers/spi/adesto.c
View file
Expand Up @@ -41,63 +41,63 @@

static const struct spi_flash_part_id flash_table[] = {
{
.id = 0x4218,
.name = "AT25SL128A",
/* AT25SL128A */
.id[0] = 0x4218,
.nr_sectors_shift = 12,
},
{
.id = 0x4501,
.name = "AT25DF081A", /* Yes, 81A id < 81 */
/* AT25DF081A Yes, 81A id < 81 */
.id[0] = 0x4501,
.nr_sectors_shift = 8,
},
{
.id = 0x4502,
.name = "AT25DF081",
/* AT25DF081 */
.id[0] = 0x4502,
.nr_sectors_shift = 8,
},
{
.id = 0x4602,
.name = "AT25DF161",
/* AT25DF161 */
.id[0] = 0x4602,
.nr_sectors_shift = 9,
},
{
.id = 0x4603,
.name = "AT25DL161",
/* AT25DL161 */
.id[0] = 0x4603,
.nr_sectors_shift = 9,
},
{
.id = 0x4700,
.name = "AT25DF321",
/* AT25DF321 */
.id[0] = 0x4700,
.nr_sectors_shift = 10,
},
{
.id = 0x4701,
.name = "AT25DF321A",
/* AT25DF321A */
.id[0] = 0x4701,
.nr_sectors_shift = 10,
},
{
.id = 0x4800,
.name = "AT25DF641",
/* AT25DF641 */
.id[0] = 0x4800,
.nr_sectors_shift = 11,
},
{
.id = 0x8501,
.name = "AT25SF081",
/* AT25SF081 */
.id[0] = 0x8501,
.nr_sectors_shift = 8,
},
{
.id = 0x8600,
.name = "AT25DQ161",
/* AT25DQ161 */
.id[0] = 0x8600,
.nr_sectors_shift = 9,
},
{
.id = 0x8601,
.name = "AT25SF161",
/* AT25SF161 */
.id[0] = 0x8601,
.nr_sectors_shift = 9,
},
{
.id = 0x8700,
.name = "AT25DQ321",
/* AT25DQ321 */
.id[0] = 0x8700,
.nr_sectors_shift = 10,
},
};
Expand All @@ -106,7 +106,7 @@ const struct spi_flash_vendor_info spi_flash_adesto_vi = {
.id = VENDOR_ID_ADESTO,
.page_size_shift = 8,
.sector_size_kib_shift = 2,
.match_id_mask = 0xffff,
.match_id_mask[0] = 0xffff,
.ids = flash_table,
.nr_part_ids = ARRAY_SIZE(flash_table),
.desc = &spi_flash_pp_0x20_sector_desc,
Expand Down
38 changes: 19 additions & 19 deletions src/drivers/spi/amic.c
View file
Expand Up @@ -36,48 +36,48 @@

static const struct spi_flash_part_id flash_table[] = {
{
.id = 0x2015,
.name = "A25L16PU",
/* A25L16PU */
.id[0] = 0x2015,
.nr_sectors_shift = 9,
},
{
.id = 0x2025,
.name = "A25L16PT",
/* A25L16PT */
.id[0] = 0x2025,
.nr_sectors_shift = 9,
},
{
.id = 0x3014,
.name = "A25L080",
/* A25L080 */
.id[0] = 0x3014,
.nr_sectors_shift = 8,
},
{
.id = 0x3015,
.name = "A25L016",
/* A25L016 */
.id[0] = 0x3015,
.nr_sectors_shift = 9,
},
{
.id = 0x3016,
.name = "A25L032",
/* A25L032 */
.id[0] = 0x3016,
.nr_sectors_shift = 10,
},
{
.id = 0x4014,
.name = "A25LQ080",
/* A25LQ080 */
.id[0] = 0x4014,
.nr_sectors_shift = 8,
},
{
.id = 0x4015,
.name = "A25LQ16",
/* A25LQ16 */
.id[0] = 0x4015,
.nr_sectors_shift = 9,
},
{
.id = 0x4016,
.name = "A25LQ032",
/* A25LQ032 */
.id[0] = 0x4016,
.nr_sectors_shift = 10,
},
{
.id = 0x4017,
.name = "A25LQ64",
/* A25LQ64 */
.id[0] = 0x4017,
.nr_sectors_shift = 11,
},
};
Expand All @@ -86,7 +86,7 @@ const struct spi_flash_vendor_info spi_flash_amic_vi = {
.id = VENDOR_ID_AMIC,
.page_size_shift = 8,
.sector_size_kib_shift = 2,
.match_id_mask = 0xffff,
.match_id_mask[0] = 0xffff,
.ids = flash_table,
.nr_part_ids = ARRAY_SIZE(flash_table),
.desc = &spi_flash_pp_0x20_sector_desc,
Expand Down
30 changes: 15 additions & 15 deletions src/drivers/spi/atmel.c
View file
Expand Up @@ -36,38 +36,38 @@

static const struct spi_flash_part_id flash_table[] = {
{
.id = 0x3015,
.name = "AT25X16",
/* AT25X16 */
.id[0] = 0x3015,
.nr_sectors_shift = 9,
},
{
.id = 0x47,
.name = "AT25DF32",
/* AT25DF32 */
.id[0] = 0x47,
.nr_sectors_shift = 10,
},
{
.id = 0x3017,
.name = "AT25X64",
/* AT25X64 */
.id[0] = 0x3017,
.nr_sectors_shift = 11,
},
{
.id = 0x4015,
.name = "AT25Q16",
/* AT25Q16 */
.id[0] = 0x4015,
.nr_sectors_shift = 9,
},
{
.id = 0x4016,
.name = "AT25Q32",
/* AT25Q32 */
.id[0] = 0x4016,
.nr_sectors_shift = 10,
},
{
.id = 0x4017,
.name = "AT25Q64",
/* AT25Q64 */
.id[0] = 0x4017,
.nr_sectors_shift = 11,
},
{
.id = 0x4018,
.name = "AT25Q128",
/* AT25Q128 */
.id[0] = 0x4018,
.nr_sectors_shift = 12,
},
};
Expand All @@ -76,7 +76,7 @@ const struct spi_flash_vendor_info spi_flash_atmel_vi = {
.id = VENDOR_ID_ATMEL,
.page_size_shift = 8,
.sector_size_kib_shift = 2,
.match_id_mask = 0xffff,
.match_id_mask[0] = 0xffff,
.ids = flash_table,
.nr_part_ids = ARRAY_SIZE(flash_table),
.desc = &spi_flash_pp_0x20_sector_desc,
Expand Down
86 changes: 43 additions & 43 deletions src/drivers/spi/eon.c
View file
Expand Up @@ -57,108 +57,108 @@

static const struct spi_flash_part_id flash_table[] = {
{
.id = EON_ID_EN25B80,
.name = "EN25B80",
/* EN25B80 */
.id[0] = EON_ID_EN25B80,
.nr_sectors_shift = 8,
},
{
.id = EON_ID_EN25B16,
.name = "EN25B16",
/* EN25B16 */
.id[0] = EON_ID_EN25B16,
.nr_sectors_shift = 9,
},
{
.id = EON_ID_EN25B32,
.name = "EN25B32",
/* EN25B32 */
.id[0] = EON_ID_EN25B32,
.nr_sectors_shift = 10,
},
{
.id = EON_ID_EN25B64,
.name = "EN25B64",
/* EN25B64 */
.id[0] = EON_ID_EN25B64,
.nr_sectors_shift = 11,
},
{
.id = EON_ID_EN25F80,
.name = "EN25F80",
/* EN25F80 */
.id[0] = EON_ID_EN25F80,
.nr_sectors_shift = 8,
},
{
.id = EON_ID_EN25F16,
.name = "EN25F16",
/* EN25F16 */
.id[0] = EON_ID_EN25F16,
.nr_sectors_shift = 9,
},
{
.id = EON_ID_EN25F32,
.name = "EN25F32",
/* EN25F32 */
.id[0] = EON_ID_EN25F32,
.nr_sectors_shift = 10,
},
{
.id = EON_ID_EN25F64,
.name = "EN25F64",
/* EN25F64 */
.id[0] = EON_ID_EN25F64,
.nr_sectors_shift = 11,
},
{
.id = EON_ID_EN25Q80,
.name = "EN25Q80(A)",
/* EN25Q80(A) */
.id[0] = EON_ID_EN25Q80,
.nr_sectors_shift = 8,
},
{
.id = EON_ID_EN25Q16,
.name = "EN25Q16(D16)",
/* EN25Q16(D16) */
.id[0] = EON_ID_EN25Q16,
.nr_sectors_shift = 9,
},
{
.id = EON_ID_EN25Q32,
.name = "EN25Q32(A/B)",
/* EN25Q32(A/B) */
.id[0] = EON_ID_EN25Q32,
.nr_sectors_shift = 10,
},
{
.id = EON_ID_EN25Q64,
.name = "EN25Q64",
/* EN25Q64 */
.id[0] = EON_ID_EN25Q64,
.nr_sectors_shift = 11,
},
{
.id = EON_ID_EN25Q128,
.name = "EN25Q128",
/* EN25Q128 */
.id[0] = EON_ID_EN25Q128,
.nr_sectors_shift = 12,
},
{
.id = EON_ID_EN25QH16,
.name = "EN25QH16",
/* EN25QH16 */
.id[0] = EON_ID_EN25QH16,
.nr_sectors_shift = 9,
},
{
.id = EON_ID_EN25QH32,
.name = "EN25QH32",
/* EN25QH32 */
.id[0] = EON_ID_EN25QH32,
.nr_sectors_shift = 10,
},
{
.id = EON_ID_EN25QH64,
.name = "EN25QH64",
/* EN25QH64 */
.id[0] = EON_ID_EN25QH64,
.nr_sectors_shift = 11,
},
{
.id = EON_ID_EN25QH128,
.name = "EN25QH128",
/* EN25QH128 */
.id[0] = EON_ID_EN25QH128,
.nr_sectors_shift = 12,
},
{
.id = EON_ID_EN25S80,
.name = "EN25S80",
/* EN25S80 */
.id[0] = EON_ID_EN25S80,
.nr_sectors_shift = 8,
},
{
.id = EON_ID_EN25S16,
.name = "EN25S16",
/* EN25S16 */
.id[0] = EON_ID_EN25S16,
.nr_sectors_shift = 9,
},
{
.id = EON_ID_EN25S32,
.name = "EN25S32",
/* EN25S32 */
.id[0] = EON_ID_EN25S32,
.nr_sectors_shift = 10,
},
{
.id = EON_ID_EN25S64,
.name = "EN25S64",
/* EN25S64 */
.id[0] = EON_ID_EN25S64,
.nr_sectors_shift = 11,
},
};
Expand All @@ -167,7 +167,7 @@ const struct spi_flash_vendor_info spi_flash_eon_vi = {
.id = VENDOR_ID_EON,
.page_size_shift = 8,
.sector_size_kib_shift = 2,
.match_id_mask = 0xffff,
.match_id_mask[0] = 0xffff,
.ids = flash_table,
.nr_part_ids = ARRAY_SIZE(flash_table),
.desc = &spi_flash_pp_0x20_sector_desc,
Expand Down
54 changes: 27 additions & 27 deletions src/drivers/spi/gigadevice.c
View file
Expand Up @@ -36,79 +36,79 @@

static const struct spi_flash_part_id flash_table[] = {
{
.id = 0x3114,
.name = "GD25T80",
/* GD25T80 */
.id[0] = 0x3114,
.nr_sectors_shift = 8,
},
{
.id = 0x4014,
.name = "GD25Q80",
/* GD25Q80 */
.id[0] = 0x4014,
.nr_sectors_shift = 8,
.fast_read_dual_output_support = 1,
}, /* also GD25Q80B */
{
.id = 0x4015,
.name = "GD25Q16",
/* GD25Q16 */
.id[0] = 0x4015,
.nr_sectors_shift = 9,
.fast_read_dual_output_support = 1,
}, /* also GD25Q16B */
{
.id = 0x4016,
.name = "GD25Q32B",
/* GD25Q32B */
.id[0] = 0x4016,
.nr_sectors_shift = 10,
.fast_read_dual_output_support = 1,
}, /* also GD25Q32B */
{
.id = 0x4017,
.name = "GD25Q64",
/* GD25Q64 */
.id[0] = 0x4017,
.nr_sectors_shift = 11,
.fast_read_dual_output_support = 1,
}, /* also GD25Q64B, GD25B64C */
{
.id = 0x4018,
.name = "GD25Q128",
/* GD25Q128 */
.id[0] = 0x4018,
.nr_sectors_shift = 12,
.fast_read_dual_output_support = 1,
}, /* also GD25Q128B */
{
.id = 0x4214,
.name = "GD25VQ80C",
/* GD25VQ80C */
.id[0] = 0x4214,
.nr_sectors_shift = 8,
.fast_read_dual_output_support = 1,
},
{
.id = 0x4215,
.name = "GD25VQ16C",
/* GD25VQ16C */
.id[0] = 0x4215,
.nr_sectors_shift = 9,
.fast_read_dual_output_support = 1,
},
{
.id = 0x6014,
.name = "GD25LQ80",
/* GD25LQ80 */
.id[0] = 0x6014,
.nr_sectors_shift = 8,
.fast_read_dual_output_support = 1,
},
{
.id = 0x6015,
.name = "GD25LQ16",
/* GD25LQ16 */
.id[0] = 0x6015,
.nr_sectors_shift = 9,
.fast_read_dual_output_support = 1,
},
{
.id = 0x6016,
.name = "GD25LQ32",
/* GD25LQ32 */
.id[0] = 0x6016,
.nr_sectors_shift = 10,
.fast_read_dual_output_support = 1,
},
{
.id = 0x6017,
.name = "GD25LQ64C",
/* GD25LQ64C */
.id[0] = 0x6017,
.nr_sectors_shift = 11,
.fast_read_dual_output_support = 1,
}, /* also GD25LB64C */
{
.id = 0x6018,
.name = "GD25LQ128",
/* GD25LQ128 */
.id[0] = 0x6018,
.nr_sectors_shift = 12,
.fast_read_dual_output_support = 1,
},
Expand All @@ -118,7 +118,7 @@ const struct spi_flash_vendor_info spi_flash_gigadevice_vi = {
.id = VENDOR_ID_GIGADEVICE,
.page_size_shift = 8,
.sector_size_kib_shift = 2,
.match_id_mask = 0xffff,
.match_id_mask[0] = 0xffff,
.ids = flash_table,
.nr_part_ids = ARRAY_SIZE(flash_table),
.desc = &spi_flash_pp_0x20_sector_desc,
Expand Down
78 changes: 39 additions & 39 deletions src/drivers/spi/macronix.c
View file
Expand Up @@ -38,98 +38,98 @@

static const struct spi_flash_part_id flash_table[] = {
{
.id = 0x2014,
.name = "MX25L8005",
/* MX25L8005 */
.id[0] = 0x2014,
.nr_sectors_shift = 8,
},
{
.id = 0x2015,
.name = "MX25L1605D",
/* MX25L1605D */
.id[0] = 0x2015,
.nr_sectors_shift = 9,
},
{
.id = 0x2016,
.name = "MX25L3205D",
/* MX25L3205D */
.id[0] = 0x2016,
.nr_sectors_shift = 10,
},
{
.id = 0x2017,
.name = "MX25L6405D",
/* MX25L6405D */
.id[0] = 0x2017,
.nr_sectors_shift = 11,
},
{
.id = 0x2018,
.name = "MX25L12805D",
/* MX25L12805D */
.id[0] = 0x2018,
.nr_sectors_shift = 12,
},
{
.id = 0x2019,
.name = "MX25L25635F",
/* MX25L25635F */
.id[0] = 0x2019,
.nr_sectors_shift = 13,
},
{
.id = 0x201a,
.name = "MX66L51235F",
/* MX66L51235F */
.id[0] = 0x201a,
.nr_sectors_shift = 14,
},
{
.id = 0x2415,
.name = "MX25L1635D",
/* MX25L1635D */
.id[0] = 0x2415,
.nr_sectors_shift = 9,
},
{
.id = 0x2515,
.name = "MX25L1635E",
/* MX25L1635E */
.id[0] = 0x2515,
.nr_sectors_shift = 9,
},
{
.id = 0x2534,
.name = "MX25U8032E",
/* MX25U8032E */
.id[0] = 0x2534,
.nr_sectors_shift = 8,
},
{
.id = 0x2535,
.name = "MX25U1635E",
/* MX25U1635E */
.id[0] = 0x2535,
.nr_sectors_shift = 9,
},
{
.id = 0x2536,
.name = "MX25U3235E",
/* MX25U3235E */
.id[0] = 0x2536,
.nr_sectors_shift = 10,
},
{
.id = 0x2537,
.name = "MX25U6435F",
/* MX25U6435F */
.id[0] = 0x2537,
.nr_sectors_shift = 11,
},
{
.id = 0x2538,
.name = "MX25U12835F",
/* MX25U12835F */
.id[0] = 0x2538,
.nr_sectors_shift = 12,
},
{
.id = 0x2539,
.name = "MX25U25635F",
/* MX25U25635F */
.id[0] = 0x2539,
.nr_sectors_shift = 13,
},
{
.id = 0x253a,
.name = "MX25U51245G",
/* MX25U51245G */
.id[0] = 0x253a,
.nr_sectors_shift = 14,
},
{
.id = 0x2618,
.name = "MX25L12855E",
/* MX25L12855E */
.id[0] = 0x2618,
.nr_sectors_shift = 12,
},
{
.id = 0x5e16,
.name = "MX25L3235D", /* MX25L3225D/MX25L3236D/MX25L3237D */
/* MX25L3235D/MX25L3225D/MX25L3236D/MX25L3237D */
.id[0] = 0x5e16,
.nr_sectors_shift = 10,
},
{
.id = 0x9517,
.name = "MX25L6495F",
/* MX25L6495F */
.id[0] = 0x9517,
.nr_sectors_shift = 11,
},
};
Expand All @@ -138,7 +138,7 @@ const struct spi_flash_vendor_info spi_flash_macronix_vi = {
.id = VENDOR_ID_MACRONIX,
.page_size_shift = 8,
.sector_size_kib_shift = 2,
.match_id_mask = 0xffff,
.match_id_mask[0] = 0xffff,
.ids = flash_table,
.nr_part_ids = ARRAY_SIZE(flash_table),
.desc = &spi_flash_pp_0x20_sector_desc,
Expand Down
65 changes: 36 additions & 29 deletions src/drivers/spi/spansion.c
View file
Expand Up @@ -51,74 +51,79 @@

static const struct spi_flash_part_id flash_table_ext[] = {
{
.id = SPSN_ID_S25FL008A,
.name = "S25FL008A",
/* S25FL008A */
.id[0] = SPSN_ID_S25FL008A,
.nr_sectors_shift = 4,
},
{
.id = SPSN_ID_S25FL016A,
.name = "S25FL016A",
/* S25FL016A */
.id[0] = SPSN_ID_S25FL016A,
.nr_sectors_shift = 5,
},
{
.id = SPSN_ID_S25FL032A,
.name = "S25FL032A",
/* S25FL032A */
.id[0] = SPSN_ID_S25FL032A,
.nr_sectors_shift = 6,
},
{
.id = SPSN_ID_S25FL064A,
.name = "S25FL064A",
/* S25FL064A */
.id[0] = SPSN_ID_S25FL064A,
.nr_sectors_shift = 7,
},
{
.id = (SPSN_EXT_ID_S25FL128P_64KB << 16) | SPSN_ID_S25FL128P,
.name = "S25FL128P_64K",
/* S25FL128P_64K */
.id[0] = SPSN_ID_S25FL128P,
.id[1] = SPSN_EXT_ID_S25FL128P_64KB,
.nr_sectors_shift = 8,
},
{
.id = (SPSN_EXT_ID_S25FLXXS_64KB << 16) | SPSN_ID_S25FL128S,
.name = "S25FL128S_256K",
/* S25FL128S_256K */
.id[0] = SPSN_ID_S25FL128S,
.id[1] = SPSN_EXT_ID_S25FLXXS_64KB,
.nr_sectors_shift = 9,
},
{
.id = (SPSN_EXT_ID_S25FL032P << 16) | SPSN_ID_S25FL032A,
.name = "S25FL032P",
/* S25FL032P */
.id[0] = SPSN_ID_S25FL032A,
.id[1] = SPSN_EXT_ID_S25FL032P,
.nr_sectors_shift = 6,
},
{
.id = (SPSN_EXT_ID_S25FLXXS_64KB << 16) | SPSN_ID_S25FL128P,
.name = "S25FS128S",
/* S25FS128S */
.id[0] = SPSN_ID_S25FL128P,
.id[1] = SPSN_EXT_ID_S25FLXXS_64KB,
.nr_sectors_shift = 8,
},
};

static const struct spi_flash_part_id flash_table_256k_sector[] = {
{
.id = (SPSN_EXT_ID_S25FL128P_256KB << 16) | SPSN_ID_S25FL128P,
.name = "S25FL128P_256K",
/* S25FL128P_256K */
.id[0] = SPSN_ID_S25FL128P,
.id[1] = SPSN_EXT_ID_S25FL128P_256KB,
.nr_sectors_shift = 6,
},
};

static const struct spi_flash_part_id flash_table[] = {
{
.id = SPSN_ID_S25FL208K,
.name = "S25FL208K",
/* S25FL208K */
.id[0] = SPSN_ID_S25FL208K,
.nr_sectors_shift = 4,
},
{
.id = SPSN_ID_S25FL116K,
.name = "S25FL116K_16M",
/* S25FL116K_16M */
.id[0] = SPSN_ID_S25FL116K,
.nr_sectors_shift = 5,
},
{
.id = SPSN_ID_S25FL132K,
.name = "S25FL132K",
/* S25FL132K */
.id[0] = SPSN_ID_S25FL132K,
.nr_sectors_shift = 6,
},
{
.id = SPSN_ID_S25FL164K,
.name = "S25FL164K",
/* S25FL164K */
.id[0] = SPSN_ID_S25FL164K,
.nr_sectors_shift = 7,
},
};
Expand All @@ -127,7 +132,8 @@ const struct spi_flash_vendor_info spi_flash_spansion_ext1_vi = {
.id = VENDOR_ID_SPANSION,
.page_size_shift = 8,
.sector_size_kib_shift = 6,
.match_id_mask = 0xffffffff,
.match_id_mask[0] = 0xffff,
.match_id_mask[1] = 0xffff,
.ids = flash_table_ext,
.nr_part_ids = ARRAY_SIZE(flash_table_ext),
.desc = &spi_flash_pp_0xd8_sector_desc,
Expand All @@ -137,7 +143,8 @@ const struct spi_flash_vendor_info spi_flash_spansion_ext2_vi = {
.id = VENDOR_ID_SPANSION,
.page_size_shift = 8,
.sector_size_kib_shift = 8,
.match_id_mask = 0xffffffff,
.match_id_mask[0] = 0xffff,
.match_id_mask[1] = 0xffff,
.ids = flash_table_256k_sector,
.nr_part_ids = ARRAY_SIZE(flash_table_256k_sector),
.desc = &spi_flash_pp_0xd8_sector_desc,
Expand All @@ -147,7 +154,7 @@ const struct spi_flash_vendor_info spi_flash_spansion_vi = {
.id = VENDOR_ID_SPANSION,
.page_size_shift = 8,
.sector_size_kib_shift = 6,
.match_id_mask = 0xffff,
.match_id_mask[0] = 0xffff,
.ids = flash_table,
.nr_part_ids = ARRAY_SIZE(flash_table),
.desc = &spi_flash_pp_0xd8_sector_desc,
Expand Down
25 changes: 15 additions & 10 deletions src/drivers/spi/spi_flash.c
View file
Expand Up @@ -355,8 +355,7 @@ static int fill_spi_flash(const struct spi_slave *spi, struct spi_flash *flash,
{
memcpy(&flash->spi, spi, sizeof(*spi));
flash->vendor = vi->id;
flash->model = part->id;
flash->name = part->name;
flash->model = part->id[0];

flash->page_size = 1U << vi->page_size_shift;
flash->sector_size = (1U << vi->sector_size_kib_shift) * KiB;
Expand All @@ -379,22 +378,27 @@ static int fill_spi_flash(const struct spi_slave *spi, struct spi_flash *flash,
}

static const struct spi_flash_part_id *find_part(const struct spi_flash_vendor_info *vi,
uint32_t id)
uint16_t id[2])
{
size_t i;
const uint16_t lid[2] = {
[0] = id[0] & vi->match_id_mask[0],
[1] = id[1] & vi->match_id_mask[1],
};


for (i = 0; i < vi->nr_part_ids; i++) {
const struct spi_flash_part_id *part = &vi->ids[i];

if (part->id == id)
if (part->id[0] == lid[0] && part->id[1] == lid[1])
return part;
}

return NULL;
}

static int find_match(const struct spi_slave *spi, struct spi_flash *flash,
uint8_t manuf_id, uint32_t id)
uint8_t manuf_id, uint16_t id[2])
{
int i;

Expand All @@ -407,7 +411,7 @@ static int find_match(const struct spi_slave *spi, struct spi_flash *flash,
if (manuf_id != vi->id)
continue;

part = find_part(vi, id & vi->match_id_mask);
part = find_part(vi, id);

if (part == NULL)
continue;
Expand All @@ -424,7 +428,7 @@ int spi_flash_generic_probe(const struct spi_slave *spi,
int ret, i;
u8 idcode[IDCODE_LEN];
u8 manuf_id;
u32 id;
u16 id[2];

/* Read the ID codes */
ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
Expand All @@ -450,7 +454,8 @@ int spi_flash_generic_probe(const struct spi_slave *spi,
manuf_id = idcode[0];
}

id = (idcode[3] << 24) | (idcode[4] << 16) | (idcode[1] << 8) | idcode[2];
id[0] = (idcode[1] << 8) | idcode[2];
id[1] = (idcode[3] << 8) | idcode[4];

return find_match(spi, flash, manuf_id, id);
}
Expand Down Expand Up @@ -483,8 +488,8 @@ int spi_flash_probe(unsigned int bus, unsigned int cs, struct spi_flash *flash)
if (flash->flags.dual_spi && spi.ctrlr->xfer_dual)
mode_string = " (Dual SPI mode)";
printk(BIOS_INFO,
"SF: Detected %s with sector size 0x%x, total 0x%x%s\n",
flash->name, flash->sector_size, flash->size, mode_string);
"SF: Detected %02x %04x with sector size 0x%x, total 0x%x%s\n",
flash->vendor, flash->model, flash->sector_size, flash->size, mode_string);
if (bus == CONFIG_BOOT_DEVICE_SPI_FLASH_BUS
&& flash->size != CONFIG_ROM_SIZE) {
printk(BIOS_ERR, "SF size 0x%x does not correspond to"
Expand Down
12 changes: 7 additions & 5 deletions src/drivers/spi/spi_flash_internal.h
View file
Expand Up @@ -73,10 +73,12 @@ int spi_flash_cmd_read(const struct spi_flash *flash, u32 offset, size_t len, vo
int stmicro_release_deep_sleep_identify(const struct spi_slave *spi, u8 *idcode);

struct spi_flash_part_id {
/* rdid command constructs a 32-bit id using the following method
* for matching: 31 | id[3] | id[4] | id[1] | id[2] | 0 */
uint32_t id;
const char *name;
/* rdid command constructs 2x 16-bit id using the following method
* for matching after reading 5 bytes (1st byte is manuf id):
* id[0] = (id[1] << 8) | id[2]
* id[1] = (id[3] << 8) | id[4]
*/
uint16_t id[2];
/* Log based 2 total number of sectors. */
uint16_t nr_sectors_shift: 4;
uint16_t fast_read_dual_output_support : 1;
Expand Down Expand Up @@ -104,7 +106,7 @@ struct spi_flash_vendor_info {
uint8_t sector_size_kib_shift : 4;
uint16_t nr_part_ids;
const struct spi_flash_part_id *ids;
uint32_t match_id_mask; /* matching bytes of the id for this set*/
uint16_t match_id_mask[2]; /* matching bytes of the id for this set*/
const struct spi_flash_ops_descriptor *desc;
const struct spi_flash_protection_ops *prot_ops;
/* Returns 0 on success. !0 otherwise. */
Expand Down
52 changes: 26 additions & 26 deletions src/drivers/spi/sst.c
View file
Expand Up @@ -46,56 +46,56 @@

static const struct spi_flash_part_id flash_table_ai[] = {
{
.id = 0x8d,
.name = "SST25VF040B",
/* SST25VF040B */
.id[0] = 0x8d,
.nr_sectors_shift = 7,
},{
.id = 0x8e,
.name = "SST25VF080B",
/* SST25VF080B */
.id[0] = 0x8e,
.nr_sectors_shift = 8,
},{
.id = 0x80,
.name = "SST25VF080",
/* SST25VF080 */
.id[0] = 0x80,
.nr_sectors_shift = 8,
},{
.id = 0x41,
.name = "SST25VF016B",
/* SST25VF016B */
.id[0] = 0x41,
.nr_sectors_shift = 9,
},{
.id = 0x4a,
.name = "SST25VF032B",
/* SST25VF032B */
.id[0] = 0x4a,
.nr_sectors_shift = 10,
},{
.id = 0x01,
.name = "SST25WF512",
/* SST25WF512 */
.id[0] = 0x01,
.nr_sectors_shift = 4,
},{
.id = 0x02,
.name = "SST25WF010",
/* SST25WF010 */
.id[0] = 0x02,
.nr_sectors_shift = 5,
},{
.id = 0x03,
.name = "SST25WF020",
/* SST25WF020 */
.id[0] = 0x03,
.nr_sectors_shift = 6,
},{
.id = 0x04,
.name = "SST25WF040",
/* SST25WF040 */
.id[0] = 0x04,
.nr_sectors_shift = 7,
},{
.id = 0x05,
.name = "SST25WF080",
/* SST25WF080 */
.id[0] = 0x05,
.nr_sectors_shift = 8,
},{
.id = 0x14,
.name = "SST25WF080B",
/* SST25WF080B */
.id[0] = 0x14,
.nr_sectors_shift = 8,
},
};

static const struct spi_flash_part_id flash_table_pp256[] = {
{
.id = 0x4b,
.name = "SST25VF064C",
/* SST25VF064C */
.id[0] = 0x4b,
.nr_sectors_shift = 11,
},
};
Expand Down Expand Up @@ -254,7 +254,7 @@ static const struct spi_flash_ops_descriptor descai = {
const struct spi_flash_vendor_info spi_flash_sst_ai_vi = {
.id = VENDOR_ID_SST,
.sector_size_kib_shift = 2,
.match_id_mask = 0xff,
.match_id_mask[0] = 0xff,
.ids = flash_table_ai,
.nr_part_ids = ARRAY_SIZE(flash_table_ai),
.desc = &descai,
Expand All @@ -265,7 +265,7 @@ const struct spi_flash_vendor_info spi_flash_sst_vi = {
.id = VENDOR_ID_SST,
.page_size_shift = 8,
.sector_size_kib_shift = 2,
.match_id_mask = 0xff,
.match_id_mask[0] = 0xff,
.ids = flash_table_pp256,
.nr_part_ids = ARRAY_SIZE(flash_table_pp256),
.desc = &spi_flash_pp_0x20_sector_desc,
Expand Down
112 changes: 56 additions & 56 deletions src/drivers/spi/stmicro.c
View file
Expand Up @@ -66,142 +66,142 @@

static const struct spi_flash_part_id flash_table_se32k[] = {
{
.id = STM_ID_M25P10,
.name = "M25P10",
/* M25P10 */
.id[0] = STM_ID_M25P10,
.nr_sectors_shift = 2,
},
};

static const struct spi_flash_part_id flash_table_se64k[] = {
{
.id = STM_ID_M25P16,
.name = "M25P16",
/* M25P16 */
.id[0] = STM_ID_M25P16,
.nr_sectors_shift = 5,
},
{
.id = STM_ID_M25P20,
.name = "M25P20",
/* M25P20 */
.id[0] = STM_ID_M25P20,
.nr_sectors_shift = 2,
},
{
.id = STM_ID_M25P32,
.name = "M25P32",
/* M25P32 */
.id[0] = STM_ID_M25P32,
.nr_sectors_shift = 6,
},
{
.id = STM_ID_M25P40,
.name = "M25P40",
/* M25P40 */
.id[0] = STM_ID_M25P40,
.nr_sectors_shift = 3,
},
{
.id = STM_ID_M25P64,
.name = "M25P64",
/* M25P64 */
.id[0] = STM_ID_M25P64,
.nr_sectors_shift = 7,
},
{
.id = STM_ID_M25P80,
.name = "M25P80",
/* M25P80 */
.id[0] = STM_ID_M25P80,
.nr_sectors_shift = 4,
},
{
.id = STM_ID_M25PX80,
.name = "M25PX80",
/* M25PX80 */
.id[0] = STM_ID_M25PX80,
.nr_sectors_shift = 4,
},
{
.id = STM_ID_M25PX16,
.name = "M25PX16",
/* M25PX16 */
.id[0] = STM_ID_M25PX16,
.nr_sectors_shift = 5,
},
{
.id = STM_ID_M25PX32,
.name = "M25PX32",
/* M25PX32 */
.id[0] = STM_ID_M25PX32,
.nr_sectors_shift = 6,
},
{
.id = STM_ID_M25PX64,
.name = "M25PX64",
/* M25PX64 */
.id[0] = STM_ID_M25PX64,
.nr_sectors_shift = 7,
},
{
.id = STM_ID_M25PE80,
.name = "M25PE80",
/* M25PE80 */
.id[0] = STM_ID_M25PE80,
.nr_sectors_shift = 4,
},
{
.id = STM_ID_M25PE16,
.name = "M25PE16",
/* M25PE16 */
.id[0] = STM_ID_M25PE16,
.nr_sectors_shift = 5,
},
{
.id = STM_ID_M25PE32,
.name = "M25PE32",
/* M25PE32 */
.id[0] = STM_ID_M25PE32,
.nr_sectors_shift = 6,
},
{
.id = STM_ID_M25PE64,
.name = "M25PE64",
/* M25PE64 */
.id[0] = STM_ID_M25PE64,
.nr_sectors_shift = 7,
},
};

static const struct spi_flash_part_id flash_table_se256k[] = {
{
.id = STM_ID_M25P128,
.name = "M25P128",
/* M25P128 */
.id[0] = STM_ID_M25P128,
.nr_sectors_shift = 6,
},
};

static const struct spi_flash_part_id flash_table_sse[] = {
{
.id = STM_ID_N25Q016__3E,
.name = "N25Q016..3E",
/* N25Q016..3E */
.id[0] = STM_ID_N25Q016__3E,
.nr_sectors_shift = 9,
},
{
.id = STM_ID_N25Q032__3E,
.name = "N25Q032..3E",
/* N25Q032..3E */
.id[0] = STM_ID_N25Q032__3E,
.nr_sectors_shift = 10,
},
{
.id = STM_ID_N25Q064__3E,
.name = "N25Q064..3E",
/* N25Q064..3E */
.id[0] = STM_ID_N25Q064__3E,
.nr_sectors_shift = 11,
},
{
.id = STM_ID_N25Q128__3E,
.name = "N25Q128..3E",
/* N25Q128..3E */
.id[0] = STM_ID_N25Q128__3E,
.nr_sectors_shift = 12,
},
{
.id = STM_ID_N25Q256__3E,
.name = "N25Q256..3E",
/* N25Q256..3E */
.id[0] = STM_ID_N25Q256__3E,
.nr_sectors_shift = 13,
},
{
.id = STM_ID_N25Q016__1E,
.name = "N25Q016..1E",
/* N25Q016..1E */
.id[0] = STM_ID_N25Q016__1E,
.nr_sectors_shift = 9,
},
{
.id = STM_ID_N25Q032__1E,
.name = "N25Q032..1E",
/* N25Q032..1E */
.id[0] = STM_ID_N25Q032__1E,
.nr_sectors_shift = 10,
},
{
.id = STM_ID_N25Q064__1E,
.name = "N25Q064..1E",
/* N25Q064..1E */
.id[0] = STM_ID_N25Q064__1E,
.nr_sectors_shift = 11,
},
{
.id = STM_ID_N25Q128__1E,
.name = "N25Q128..1E",
/* N25Q128..1E */
.id[0] = STM_ID_N25Q128__1E,
.nr_sectors_shift = 12,
},
{
.id = STM_ID_N25Q256__1E,
.name = "N25Q256..1E",
/* N25Q256..1E */
.id[0] = STM_ID_N25Q256__1E,
.nr_sectors_shift = 13,
},
};
Expand All @@ -228,7 +228,7 @@ const struct spi_flash_vendor_info spi_flash_stmicro1_vi = {
.id = VENDOR_ID_STMICRO,
.page_size_shift = 8,
.sector_size_kib_shift = 5,
.match_id_mask = 0xffff,
.match_id_mask[0] = 0xffff,
.ids = flash_table_se32k,
.nr_part_ids = ARRAY_SIZE(flash_table_se32k),
.desc = &spi_flash_pp_0xd8_sector_desc,
Expand All @@ -238,7 +238,7 @@ const struct spi_flash_vendor_info spi_flash_stmicro2_vi = {
.id = VENDOR_ID_STMICRO,
.page_size_shift = 8,
.sector_size_kib_shift = 6,
.match_id_mask = 0xffff,
.match_id_mask[0] = 0xffff,
.ids = flash_table_se64k,
.nr_part_ids = ARRAY_SIZE(flash_table_se64k),
.desc = &spi_flash_pp_0xd8_sector_desc,
Expand All @@ -248,7 +248,7 @@ const struct spi_flash_vendor_info spi_flash_stmicro3_vi = {
.id = VENDOR_ID_STMICRO,
.page_size_shift = 8,
.sector_size_kib_shift = 8,
.match_id_mask = 0xffff,
.match_id_mask[0] = 0xffff,
.ids = flash_table_se256k,
.nr_part_ids = ARRAY_SIZE(flash_table_se256k),
.desc = &spi_flash_pp_0xd8_sector_desc,
Expand All @@ -258,7 +258,7 @@ const struct spi_flash_vendor_info spi_flash_stmicro4_vi = {
.id = VENDOR_ID_STMICRO,
.page_size_shift = 8,
.sector_size_kib_shift = 2,
.match_id_mask = 0xffff,
.match_id_mask[0] = 0xffff,
.ids = flash_table_sse,
.nr_part_ids = ARRAY_SIZE(flash_table_sse),
.desc = &spi_flash_pp_0x20_sector_desc,
Expand Down
82 changes: 41 additions & 41 deletions src/drivers/spi/winbond.c
View file
Expand Up @@ -81,141 +81,141 @@ struct status_regs {

static const struct spi_flash_part_id flash_table[] = {
{
.id = 0x2014,
.name = "W25P80",
/* W25P80 */
.id[0] = 0x2014,
.nr_sectors_shift = 8,
},
{
.id = 0x2015,
.name = "W25P16",
/* W25P16 */
.id[0] = 0x2015,
.nr_sectors_shift = 9,
},
{
.id = 0x2016,
.name = "W25P32",
/* W25P32 */
.id[0] = 0x2016,
.nr_sectors_shift = 10,
},
{
.id = 0x3014,
.name = "W25X80",
/* W25X80 */
.id[0] = 0x3014,
.nr_sectors_shift = 8,
.fast_read_dual_output_support = 1,
},
{
.id = 0x3015,
.name = "W25X16",
/* W25X16 */
.id[0] = 0x3015,
.nr_sectors_shift = 9,
.fast_read_dual_output_support = 1,
},
{
.id = 0x3016,
.name = "W25X32",
/* W25X32 */
.id[0] = 0x3016,
.nr_sectors_shift = 10,
.fast_read_dual_output_support = 1,
},
{
.id = 0x3017,
.name = "W25X64",
/* W25X64 */
.id[0] = 0x3017,
.nr_sectors_shift = 11,
.fast_read_dual_output_support = 1,
},
{
.id = 0x4014,
.name = "W25Q80_V",
/* W25Q80_V */
.id[0] = 0x4014,
.nr_sectors_shift = 8,
.fast_read_dual_output_support = 1,
},
{
.id = 0x4015,
.name = "W25Q16_V",
/* W25Q16_V */
.id[0] = 0x4015,
.nr_sectors_shift = 9,
.fast_read_dual_output_support = 1,
.protection_granularity_shift = 16,
.bp_bits = 3,
},
{
.id = 0x6015,
.name = "W25Q16DW",
/* W25Q16DW */
.id[0] = 0x6015,
.nr_sectors_shift = 9,
.fast_read_dual_output_support = 1,
.protection_granularity_shift = 16,
.bp_bits = 3,
},
{
.id = 0x4016,
.name = "W25Q32_V",
/* W25Q32_V */
.id[0] = 0x4016,
.nr_sectors_shift = 10,
.fast_read_dual_output_support = 1,
.protection_granularity_shift = 16,
.bp_bits = 3,
},
{
.id = 0x6016,
.name = "W25Q32DW",
/* W25Q32DW */
.id[0] = 0x6016,
.nr_sectors_shift = 10,
.fast_read_dual_output_support = 1,
.protection_granularity_shift = 16,
.bp_bits = 3,
},
{
.id = 0x4017,
.name = "W25Q64_V",
/* W25Q64_V */
.id[0] = 0x4017,
.nr_sectors_shift = 11,
.fast_read_dual_output_support = 1,
.protection_granularity_shift = 17,
.bp_bits = 3,
},
{
.id = 0x6017,
.name = "W25Q64DW",
/* W25Q64DW */
.id[0] = 0x6017,
.nr_sectors_shift = 11,
.fast_read_dual_output_support = 1,
.protection_granularity_shift = 17,
.bp_bits = 3,
},
{
.id = 0x4018,
.name = "W25Q128_V",
/* W25Q128_V */
.id[0] = 0x4018,
.nr_sectors_shift = 12,
.fast_read_dual_output_support = 1,
.protection_granularity_shift = 18,
.bp_bits = 3,
},
{
.id = 0x6018,
.name = "W25Q128FW",
/* W25Q128FW */
.id[0] = 0x6018,
.nr_sectors_shift = 12,
.fast_read_dual_output_support = 1,
.protection_granularity_shift = 18,
.bp_bits = 3,
},
{
.id = 0x7018,
.name = "W25Q128J",
/* W25Q128J */
.id[0] = 0x7018,
.nr_sectors_shift = 12,
.fast_read_dual_output_support = 1,
.protection_granularity_shift = 18,
.bp_bits = 3,
},
{
.id = 0x8018,
.name = "W25Q128JW",
/* W25Q128JW */
.id[0] = 0x8018,
.nr_sectors_shift = 12,
.fast_read_dual_output_support = 1,
.protection_granularity_shift = 18,
.bp_bits = 3,
},
{
.id = 0x4019,
.name = "W25Q256_V",
/* W25Q256_V */
.id[0] = 0x4019,
.nr_sectors_shift = 13,
.fast_read_dual_output_support = 1,
.protection_granularity_shift = 16,
.bp_bits = 4,
},
{
.id = 0x7019,
.name = "W25Q256J",
/* W25Q256J */
.id[0] = 0x7019,
.nr_sectors_shift = 13,
.fast_read_dual_output_support = 1,
.protection_granularity_shift = 16,
Expand Down Expand Up @@ -625,7 +625,7 @@ const struct spi_flash_vendor_info spi_flash_winbond_vi = {
.id = VENDOR_ID_WINBOND,
.page_size_shift = 8,
.sector_size_kib_shift = 2,
.match_id_mask = 0xffff,
.match_id_mask[0] = 0xffff,
.ids = flash_table,
.nr_part_ids = ARRAY_SIZE(flash_table),
.desc = &spi_flash_winbond_desc,
Expand Down
1 change: 1 addition & 0 deletions src/ec/google/chromeec/Makefile.inc
View file
Expand Up @@ -24,6 +24,7 @@ verstage-y += ec.c crosec_proto.c vstore.c
verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c
verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
verstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ec_chip.c

ramstage-$(CONFIG_VBOOT) += vboot_storage.c
smm-$(CONFIG_VBOOT) += vboot_storage.c
Expand Down
121 changes: 81 additions & 40 deletions src/ec/google/chromeec/ec.c
View file
Expand Up @@ -15,21 +15,21 @@

#include <stdint.h>
#include <string.h>
#include <cbmem.h>
#include <console/console.h>
#include <assert.h>
#include <bootmode.h>
#include <bootstate.h>
#include <cbmem.h>
#include <console/console.h>
#include <delay.h>
#include <device/device.h>
#include <device/path.h>
#include <elog.h>
#include <rtc.h>
#include <stdlib.h>
#include <security/vboot/vboot_common.h>
#include <stdlib.h>
#include <timer.h>

#include "chip.h"
#include "ec.h"
#include "ec_commands.h"

#define INVALID_HCMD 0xFF

Expand Down Expand Up @@ -79,41 +79,6 @@ static const struct {
},
};

void log_recovery_mode_switch(void)
{
uint64_t *events;

if (cbmem_find(CBMEM_ID_EC_HOSTEVENT))
return;

events = cbmem_add(CBMEM_ID_EC_HOSTEVENT, sizeof(*events));
if (!events)
return;

*events = google_chromeec_get_events_b();
}

static void google_chromeec_elog_add_recovery_event(void *unused)
{
uint64_t *events = cbmem_find(CBMEM_ID_EC_HOSTEVENT);
uint8_t event_byte = EC_HOST_EVENT_KEYBOARD_RECOVERY;

if (!events)
return;

if (!(*events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)))
return;

if (*events &
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT))
event_byte = EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT;

elog_add_event_byte(ELOG_TYPE_EC_EVENT, event_byte);
}

BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY,
google_chromeec_elog_add_recovery_event, NULL);

uint8_t google_chromeec_calc_checksum(const uint8_t *data, int size)
{
int csum;
Expand Down Expand Up @@ -1419,6 +1384,57 @@ enum ec_current_image google_chromeec_get_current_image(void)
return ec_image_type;
}

int google_chromeec_get_num_pd_ports(int *num_ports)
{
struct ec_response_charge_port_count resp = {};
struct chromeec_command cmd = {
.cmd_code = EC_CMD_CHARGE_PORT_COUNT,
.cmd_version = 0,
.cmd_data_out = &resp,
.cmd_size_in = 0,
.cmd_size_out = sizeof(resp),
.cmd_dev_index = 0,
};
int rv;

rv = google_chromeec_command(&cmd);
if (rv)
return rv;

*num_ports = resp.port_count;
return 0;
}

int google_chromeec_get_pd_port_caps(int port,
struct usb_pd_port_caps *port_caps)
{
struct ec_params_get_pd_port_caps params = {
.port = port,
};
struct ec_response_get_pd_port_caps resp = {};
struct chromeec_command cmd = {
.cmd_code = EC_CMD_GET_PD_PORT_CAPS,
.cmd_version = 0,
.cmd_data_in = &params,
.cmd_size_in = sizeof(params),
.cmd_data_out = &resp,
.cmd_size_out = sizeof(resp),
.cmd_dev_index = 0,
};
int rv;

rv = google_chromeec_command(&cmd);
if (rv)
return rv;

port_caps->power_role_cap = resp.pd_power_role_cap;
port_caps->try_power_role_cap = resp.pd_try_power_role_cap;
port_caps->data_role_cap = resp.pd_data_role_cap;
port_caps->port_location = resp.pd_port_location;

return 0;
}

void google_chromeec_init(void)
{
google_chromeec_log_uptimeinfo();
Expand Down Expand Up @@ -1509,3 +1525,28 @@ int google_chromeec_wait_for_displayport(long timeout)

return 1;
}

#if CONFIG(HAVE_ACPI_TABLES) && !DEVTREE_EARLY
static struct device_operations ec_chromeec_ops = {
.acpi_name = google_chromeec_acpi_name,
.acpi_fill_ssdt_generator = google_chromeec_fill_ssdt_generator,
};
#endif

/* ec_lpc, ec_spi, or ec_i2c can override this */
__weak void google_ec_enable_extra(struct device *dev)
{
}

static void google_chromeec_enable(struct device *dev)
{
#if CONFIG(HAVE_ACPI_TABLES) && !DEVTREE_EARLY
dev->ops = &ec_chromeec_ops;
#endif
google_ec_enable_extra(dev);
}

struct chip_operations ec_google_chromeec_ops = {
CHIP_NAME("Google Chrome EC")
.enable_dev = google_chromeec_enable
};
53 changes: 53 additions & 0 deletions src/ec/google/chromeec/ec.h
View file
Expand Up @@ -18,6 +18,7 @@
#ifndef _EC_GOOGLE_CHROMEEC_EC_H
#define _EC_GOOGLE_CHROMEEC_EC_H
#include <types.h>
#include <device/device.h>
#include "ec_commands.h"

/* Fill in base and size of the IO port resources used. */
Expand Down Expand Up @@ -299,4 +300,56 @@ int google_chromeec_get_protocol_info(
*/
int google_chromeec_get_cmd_versions(int command, uint32_t *pmask);

/**
* Get number of PD-capable USB ports from EC.
*
* @param *num_ports If successful, num_ports is the number
* of PD-capable USB ports according to the EC.
* @return 0 on success, -1 on error
*/
int google_chromeec_get_num_pd_ports(int *num_ports);

/* Structure representing the capabilities of a USB-PD port */
struct usb_pd_port_caps {
enum ec_pd_power_role_caps power_role_cap;
enum ec_pd_try_power_role_caps try_power_role_cap;
enum ec_pd_data_role_caps data_role_cap;
enum ec_pd_port_location port_location;
};

/**
* Get role-based capabilities for a USB-PD port
*
* @param port Which port to get information about
* @param *power_role_cap The power-role capabillity of the port
* @param *try_power_role_cap The Try-power-role capability of the port
* @param *data_role_cap The data role capability of the port
* @param *port_location Location of the port on the device
* @return 0 on success, -1 on error
*/
int google_chromeec_get_pd_port_caps(int port,
struct usb_pd_port_caps *port_caps);

#if CONFIG(HAVE_ACPI_TABLES)
/**
* Writes USB Type-C PD related information to the SSDT
*
* @param dev EC device
*/
void google_chromeec_fill_ssdt_generator(struct device *dev);

/**
* Returns the ACPI name for the EC device.
*
* @param dev EC device
*/
const char *google_chromeec_acpi_name(const struct device *dev);

#endif /* HAVE_ACPI_TABLES */

/*
* Allows bus-specific EC code to perform actions when the device is enabled.
*/
void google_ec_enable_extra(struct device *dev);

#endif /* _EC_GOOGLE_CHROMEEC_EC_H */
228 changes: 228 additions & 0 deletions src/ec/google/chromeec/ec_chip.c
View file
@@ -0,0 +1,228 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2020 The coreboot project Authors.
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/

#include <arch/acpi.h>
#include <arch/acpi_device.h>
#include <arch/acpigen.h>
#include <console/console.h>
#include <drivers/usb/acpi/chip.h>
#include <stdlib.h>

#include "chip.h"
#include "ec.h"
#include "ec_commands.h"

#define GOOGLE_CHROMEEC_USBC_DEVICE_HID "GOOG0014"
#define GOOGLE_CHROMEEC_USBC_DEVICE_NAME "USBC"

const char *google_chromeec_acpi_name(const struct device *dev)
{
return "EC0";
}

static const char *power_role_to_str(enum ec_pd_power_role_caps power_role)
{
switch (power_role) {
case EC_PD_POWER_ROLE_SOURCE:
return "source";
case EC_PD_POWER_ROLE_SINK:
return "sink";
case EC_PD_POWER_ROLE_DUAL:
return "dual";
default:
return "unknown";
}
}

static const char *try_power_role_to_str(enum ec_pd_try_power_role_caps try_power_role)
{
switch (try_power_role) {
case EC_PD_TRY_POWER_ROLE_NONE:
/*
* This should never get returned; if there is no try-power role for a device,
* then the try-power-role field is not added to the DSD. Thus, this is just
* for completeness.
*/
return "none";
case EC_PD_TRY_POWER_ROLE_SINK:
return "sink";
case EC_PD_TRY_POWER_ROLE_SOURCE:
return "source";
default:
return "unknown";
}
}

static const char *data_role_to_str(enum ec_pd_data_role_caps data_role)
{
switch (data_role) {
case EC_PD_DATA_ROLE_DFP:
return "host";
case EC_PD_DATA_ROLE_UFP:
return "device";
case EC_PD_DATA_ROLE_DUAL:
return "dual";
default:
return "unknown";
}
}

/*
* Apparently these are supposed to be uppercase, in contrast to the other
* lowercase fields.
*/
static const char *port_location_to_str(enum ec_pd_port_location port_location)
{
switch (port_location) {
case EC_PD_PORT_LOCATION_LEFT:
return "LEFT";
case EC_PD_PORT_LOCATION_RIGHT:
return "RIGHT";
case EC_PD_PORT_LOCATION_BACK:
return "BACK";
case EC_PD_PORT_LOCATION_FRONT:
return "FRONT";
case EC_PD_PORT_LOCATION_LEFT_FRONT:
return "LEFT_FRONT";
case EC_PD_PORT_LOCATION_LEFT_BACK:
return "LEFT_BACK";
case EC_PD_PORT_LOCATION_RIGHT_FRONT:
return "RIGHT_FRONT";
case EC_PD_PORT_LOCATION_RIGHT_BACK:
return "RIGHT_BACK";
case EC_PD_PORT_LOCATION_BACK_LEFT:
return "BACK_LEFT";
case EC_PD_PORT_LOCATION_BACK_RIGHT:
return "BACK_RIGHT";
case EC_PD_PORT_LOCATION_UNKNOWN: /* intentional fallthrough */
default:
return "UNKNOWN";
}
}

/* Add port capabilities as DP properties */
static void add_port_caps(struct acpi_dp *dsd, const struct usb_pd_port_caps *port_caps)
{
acpi_dp_add_string(dsd, "power-role", power_role_to_str(port_caps->power_role_cap));

if (port_caps->try_power_role_cap != EC_PD_TRY_POWER_ROLE_NONE)
acpi_dp_add_string(dsd, "try-power-role",
try_power_role_to_str(port_caps->try_power_role_cap));

acpi_dp_add_string(dsd, "data-role", data_role_to_str(port_caps->data_role_cap));
acpi_dp_add_string(dsd, "port-location", port_location_to_str(
port_caps->port_location));
}

/*
* Helper for fill_ssdt_generator. This adds references to the USB
* port objects so that the consumer of this information can know
* whether the port supports USB2 and/or USB3.
*/
static void add_usb_port_references(struct acpi_dp *dsd, int port_number)
{
static const char usb2_port[] = "usb2-port";
static const char usb3_port[] = "usb3-port";
struct device *port = NULL;
const char *path;
const char *usb_port_type;
struct drivers_usb_acpi_config *config;

/*
* Unfortunately, the acpi_dp_* API doesn't write out the data immediately, thus we need
* different storage areas for all of the strings, so strdup() is used for that. It is
* safe to use strdup() here, because the strings are generated at build-time and are
* guaranteed to be NUL-terminated (they come from the devicetree).
*/
while ((port = dev_find_path(port, DEVICE_PATH_USB)) != NULL) {
if (!port->enabled || port->path.type != DEVICE_PATH_USB)
continue;

/* Looking for USB 2 & 3 port devices only */
if (port->path.usb.port_type == 2)
usb_port_type = usb2_port;
else if (port->path.usb.port_type == 3)
usb_port_type = usb3_port;
else
continue;

config = port->chip_info;

/*
* Look at only USB Type-C ports, making sure they match the
* port number we're looking for (the 'token' field in 'group').
* Also note that 'port_number' is 0-based, whereas the 'token'
* field is 1-based.
*/
if ((config->type != UPC_TYPE_C_USB2_ONLY) &&
(config->type != UPC_TYPE_C_USB2_SS_SWITCH) &&
(config->type != UPC_TYPE_C_USB2_SS))
continue;

if (config->group.token != (port_number + 1))
continue;

path = acpi_device_path(port);
if (path) {
path = strdup(path);
if (!path)
continue;

acpi_dp_add_reference(dsd, usb_port_type, path);
}
}
}

static void fill_ssdt_typec_device(struct device *dev)
{
struct usb_pd_port_caps port_caps;
char con_name[] = "CONx";
struct acpi_dp *dsd;
int num_ports;
int rv;
int i;

rv = google_chromeec_get_num_pd_ports(&num_ports);
if (rv)
return;

acpigen_write_device(GOOGLE_CHROMEEC_USBC_DEVICE_NAME);
acpigen_write_name_string("_HID", GOOGLE_CHROMEEC_USBC_DEVICE_HID);
acpigen_write_name_string("_DDN", "ChromeOS EC Embedded Controller "
"USB Type-C Control");

for (i = 0; i < num_ports; ++i) {
rv = google_chromeec_get_pd_port_caps(i, &port_caps);
if (rv)
continue;

con_name[3] = (char)i + '0';
acpigen_write_device(con_name);
acpigen_write_name_integer("_ADR", i);

/* _DSD, Device-Specific Data */
dsd = acpi_dp_new_table("_DSD");

acpi_dp_add_integer(dsd, "port-number", i);
add_port_caps(dsd, &port_caps);
add_usb_port_references(dsd, i);

acpi_dp_write(dsd);
acpigen_pop_len(); /* Device CONx */
}

acpigen_pop_len(); /* Device GOOGLE_CHROMEEC_USBC_DEVICE_NAME */
}

void google_chromeec_fill_ssdt_generator(struct device *dev)
{
/* Reference the existing device's scope */
acpigen_write_scope(acpi_device_path(dev));
fill_ssdt_typec_device(dev);
acpigen_pop_len(); /* Scope */
}
68 changes: 68 additions & 0 deletions src/ec/google/chromeec/ec_commands.h
View file
Expand Up @@ -5852,6 +5852,74 @@ struct ec_response_locate_chip {
*/
#define EC_CMD_REBOOT_AP_ON_G3 0x0127

/*****************************************************************************/
/* Get PD port capabilities
*
* Returns the following static *capabilities* of the given port:
* 1) Power role: source, sink, or dual. It is not anticipated that
* future CrOS devices would ever be only a source, so the options are
* sink or dual.
* 2) Try-power role: source, sink, or none (practically speaking, I don't
* believe any CrOS device would support Try.SNK, so this would be source
* or none).
* 3) Data role: dfp, ufp, or dual. This will probably only be DFP or dual
* for CrOS devices.
*/
#define EC_CMD_GET_PD_PORT_CAPS 0x0128

enum ec_pd_power_role_caps {
EC_PD_POWER_ROLE_SOURCE = 0,
EC_PD_POWER_ROLE_SINK = 1,
EC_PD_POWER_ROLE_DUAL = 2,
};

enum ec_pd_try_power_role_caps {
EC_PD_TRY_POWER_ROLE_NONE = 0,
EC_PD_TRY_POWER_ROLE_SINK = 1,
EC_PD_TRY_POWER_ROLE_SOURCE = 2,
};

enum ec_pd_data_role_caps {
EC_PD_DATA_ROLE_DFP = 0,
EC_PD_DATA_ROLE_UFP = 1,
EC_PD_DATA_ROLE_DUAL = 2,
};

/* From: power_manager/power_supply_properties.proto */
enum ec_pd_port_location {
/* The location of the port is unknown, or there's only one port. */
EC_PD_PORT_LOCATION_UNKNOWN = 0,

/*
* Various positions on the device. The first word describes the side of
* the device where the port is located while the second clarifies the
* position. For example, LEFT_BACK means the farthest-back port on the
* left side, while BACK_LEFT means the leftmost port on the back of the
* device.
*/
EC_PD_PORT_LOCATION_LEFT = 1,
EC_PD_PORT_LOCATION_RIGHT = 2,
EC_PD_PORT_LOCATION_BACK = 3,
EC_PD_PORT_LOCATION_FRONT = 4,
EC_PD_PORT_LOCATION_LEFT_FRONT = 5,
EC_PD_PORT_LOCATION_LEFT_BACK = 6,
EC_PD_PORT_LOCATION_RIGHT_FRONT = 7,
EC_PD_PORT_LOCATION_RIGHT_BACK = 8,
EC_PD_PORT_LOCATION_BACK_LEFT = 9,
EC_PD_PORT_LOCATION_BACK_RIGHT = 10,
};

struct ec_params_get_pd_port_caps {
uint8_t port; /* Which port to interrogate */
} __ec_align1;

struct ec_response_get_pd_port_caps {
uint8_t pd_power_role_cap; /* enum ec_pd_power_role_caps */
uint8_t pd_try_power_role_cap; /* enum ec_pd_try_power_role_caps */
uint8_t pd_data_role_cap; /* enum ec_pd_data_role_caps */
uint8_t pd_port_location; /* enum ec_pd_port_location */
} __ec_align1;

/*****************************************************************************/
/* The command range 0x200-0x2FF is reserved for Rotor. */

Expand Down
7 changes: 1 addition & 6 deletions src/ec/google/chromeec/ec_lpc.c
View file
Expand Up @@ -458,16 +458,11 @@ static struct pnp_info pnp_dev_info[] = {
{ NULL, 0, 0, 0, }
};

static void enable_dev(struct device *dev)
void google_ec_enable_extra(struct device *dev)
{
pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}

struct chip_operations ec_google_chromeec_ops = {
CHIP_NAME("Google Chrome EC")
.enable_dev = enable_dev,
};

static int google_chromeec_data_ready(u16 port)
{
return google_chromeec_status_check(port, EC_LPC_CMDR_DATA,
Expand Down
30 changes: 17 additions & 13 deletions src/ec/google/chromeec/switches.c
View file
Expand Up @@ -14,8 +14,8 @@
*/

#include <bootmode.h>
#include <cbmem.h>
#include <ec/google/chromeec/ec.h>
#include <elog.h>

#if CONFIG(EC_GOOGLE_CHROMEEC_LPC)
int get_lid_switch(void)
Expand All @@ -41,29 +41,33 @@ int get_recovery_mode_switch(void)

int get_recovery_mode_retrain_switch(void)
{
uint64_t events;
const uint64_t mask =
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT);

/*
* Check if the EC has posted the keyboard recovery event with memory
* retrain.
*/
events = google_chromeec_get_events_b();
return !!(google_chromeec_get_events_b() &
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT));
}

if (cbmem_possibly_online()) {
const uint64_t *events_save;
static void elog_add_recovery_mode_switch_event(void)
{
uint64_t events = google_chromeec_get_events_b();
uint8_t event_byte = EC_HOST_EVENT_KEYBOARD_RECOVERY;

if (!(events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)))
return;

events_save = cbmem_find(CBMEM_ID_EC_HOSTEVENT);
if (events_save != NULL)
events |= *events_save;
}
if (events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT))
event_byte = EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT;

return !!(events & mask);
elog_add_event_byte(ELOG_TYPE_EC_EVENT, event_byte);
}

int clear_recovery_mode_switch(void)
{
/* Log elog event before clearing */
elog_add_recovery_mode_switch_event();

/* Clear all host event bits requesting recovery mode. */
return google_chromeec_clear_events_b(
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) |
Expand Down
15 changes: 15 additions & 0 deletions src/ec/google/wilco/chip.c
View file
Expand Up @@ -16,10 +16,13 @@
#include <arch/acpi.h>
#include <arch/acpi_device.h>
#include <arch/acpigen.h>
#include <arch/cpu.h>
#include <bootstate.h>
#include <cbmem.h>
#include <console/console.h>
#include <device/pnp.h>
#include <ec/acpi/ec.h>
#include <intelblocks/cpulib.h>
#include <pc80/keyboard.h>
#include <stdint.h>

Expand Down Expand Up @@ -124,6 +127,14 @@ static void wilco_ec_resume(void *unused)
}
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, wilco_ec_resume, NULL);

static int wilco_set_cpu_id(void)
{
uint32_t cpu_phy_cores, cpu_virtual_cores;

cpu_read_topology(&cpu_phy_cores, &cpu_virtual_cores);
return wilco_ec_set_cpuid(cpu_get_cpuid(), cpu_phy_cores, 0);
}

static void wilco_ec_init(struct device *dev)
{
if (!dev->enabled)
Expand Down Expand Up @@ -153,6 +164,10 @@ static void wilco_ec_init(struct device *dev)

/* Turn on camera power */
wilco_ec_send(KB_CAMERA, CAMERA_ON);

/* Set cpu id and phy cores */
if (wilco_set_cpu_id())
printk(BIOS_ERR, "EC: use default cpu power table\n");
}

static void wilco_ec_resource(struct device *dev, int index,
Expand Down
21 changes: 21 additions & 0 deletions src/ec/lenovo/h8/acpi/ec.asl
View file
Expand Up @@ -195,6 +195,26 @@ Device(EC)
^HKEY.RHK (0x01)
}

/*
* Alternative layout (like in the Thinkpad X1 Carbon 1st generation):
* * Fn-F2 (_Q11) -> not mapped
* * Fn-F3 (_Q12) -> scancode 0x01 (KEY_COFFEE)
*
* Default layout (like in the Thinkpad X220):
* * Fn-F2 (_Q11) -> scancode 0x01 (KEY_COFFEE)
* * Fn-F3 (_Q12) -> scancode 0x02 (KEY_BATTERY)
*/
#ifdef EC_LENOVO_H8_ALT_FN_F2F3_LAYOUT
Method (_Q11, 0, NotSerialized)
{
// Not mapped
}

Method (_Q12, 0, NotSerialized)
{
^HKEY.RHK (0x02)
}
#else
Method (_Q11, 0, NotSerialized)
{
^HKEY.RHK (0x02)
Expand All @@ -204,6 +224,7 @@ Device(EC)
{
^HKEY.RHK (0x03)
}
#endif

Method (_Q64, 0, NotSerialized)
{
Expand Down
24 changes: 23 additions & 1 deletion src/ec/purism/librem/acpi/ec.asl
View file
Expand Up @@ -52,7 +52,9 @@ Device (EC)
OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF)
Field (ERAM, ByteAcc, Lock, Preserve)
{
Offset (0x15),
Offset (0x13),
RTMP, 8,
, 8,
BSTS, 2, /* Battery Status */
, 3,
BTEX, 1, /* Battery Present */
Expand Down Expand Up @@ -231,3 +233,23 @@ Device (EC)
#include "ac.asl"
#include "battery.asl"
}

Scope (\_TZ)
{
ThermalZone (TZ0)
{
/* _TMP: Temperature */
Method (_TMP, 0, Serialized)
{
Local0 = (0x0AAC + (\_SB.PCI0.LPCB.EC.RTMP * 0x0A))
Return (Local0)
}

/* _CRT: Critical Temperature */
Method (_CRT, 0, Serialized)
{
/* defined in board ec.asl */
Return (CRIT_TEMP)
}
}
}
1 change: 0 additions & 1 deletion src/include/bootmode.h
View file
Expand Up @@ -22,7 +22,6 @@ int get_write_protect_state(void);
int get_recovery_mode_switch(void);
int get_recovery_mode_retrain_switch(void);
int clear_recovery_mode_switch(void);
void log_recovery_mode_switch(void);
int get_wipeout_mode_switch(void);
int get_lid_switch(void);

Expand Down
11 changes: 11 additions & 0 deletions src/include/cpu/x86/msr.h
View file
Expand Up @@ -16,6 +16,7 @@
/* Page attribute type MSR */
#define TSC_MSR 0x10
#define IA32_PLATFORM_ID 0x17
#define IA32_APIC_BASE_MSR_INDEX 0x1B
#define IA32_FEATURE_CONTROL 0x3a
#define FEATURE_CONTROL_LOCK_BIT (1 << 0)
#define FEATURE_ENABLE_VMX (1 << 2)
Expand All @@ -30,6 +31,10 @@
#define IA32_BIOS_SIGN_ID 0x8b
#define IA32_MPERF 0xe7
#define IA32_APERF 0xe8
/* STM */
#define IA32_SMM_MONITOR_CTL_MSR 0x9B
#define SMBASE_RO_MSR 0x98
#define IA32_SMM_MONITOR_VALID (1 << 0)
#define IA32_MCG_CAP 0x179
#define MCG_CTL_P (1 << 3)
#define MCA_BANKS_MASK 0xff
Expand All @@ -45,6 +50,9 @@
#define ENERGY_POLICY_POWERSAVE 15
#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
#define IA32_PLATFORM_DCA_CAP 0x1f8
#define SMRR_PHYSBASE_MSR 0x1F2
#define SMRR_PHYSMASK_MSR 0x1F3
#define IA32_PLATFORM_DCA_CAP 0x1f8
#define IA32_PAT 0x277
#define IA32_MC0_CTL 0x400
#define IA32_MC0_STATUS 0x401
Expand All @@ -65,6 +73,9 @@
#define MCA_STATUS_LO_ERRCODE_EXT_SH 16
#define MCA_STATUS_LO_ERRCODE_EXT_MASK (0x3f << MCA_STATUS_LO_ERRCODE_EXT_SH)
#define MCA_STATUS_LO_ERRCODE_MASK (0xffff << 0)
#define IA32_VMX_BASIC_MSR 0x480
#define VMX_BASIC_HI_DUAL_MONITOR (1UL << (49 - 32))
#define IA32_VMX_MISC_MSR 0x485
#define MC0_ADDR 0x402
#define MC0_MISC 0x403
#define MC0_CTL_MASK 0xC0010044
Expand Down
3 changes: 3 additions & 0 deletions src/include/cpu/x86/smm.h
View file
Expand Up @@ -64,6 +64,9 @@ extern unsigned char _binary_smm_end[];
struct smm_runtime {
u32 smbase;
u32 save_state_size;
u32 num_cpus;
/* STM's 32bit entry into SMI handler */
u32 start32_offset;
/* The apic_id_to_cpu provides a mapping from APIC id to CPU number.
* The CPU number is indicated by the index into the array by matching
* the default APIC id and value at the index. The stub loader
Expand Down
6 changes: 5 additions & 1 deletion src/include/device/device.h
View file
Expand Up @@ -119,8 +119,12 @@ struct device {
unsigned int initialized : 1; /* 1 if we have initialized the device */
unsigned int on_mainboard : 1;
unsigned int disable_pcie_aspm : 1;
unsigned int hidden : 1; /* set if we should hide from UI */
/* set if we should hide from UI */
unsigned int hidden : 1;
/* set if this device is used even in minimum PCI cases */
unsigned int mandatory : 1;
u8 command;
uint16_t hotplug_buses; /* Number of hotplug buses to allocate */

/* Base registers for this device. I/O, MEM and Expansion ROM */
DEVTREE_CONST struct resource *resource_list;
Expand Down
1 change: 1 addition & 0 deletions src/include/device/pci_def.h
View file
Expand Up @@ -435,6 +435,7 @@
#define PCI_EXP_LNKSTA_LT 0x800 /* Link Training */
#define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */
#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
#define PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */
#define PCI_EXP_SLTCTL 24 /* Slot Control */
#define PCI_EXP_SLTSTA 26 /* Slot Status */
#define PCI_EXP_RTCTL 28 /* Root Control */
Expand Down
78 changes: 44 additions & 34 deletions src/include/device/pci_ids.h
View file
Expand Up @@ -2809,8 +2809,6 @@
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_24 0xA09D
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_25 0xA09E
#define PCI_DEVICE_ID_INTEL_TGP_ESPI_26 0xA09F
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_1 0x3887
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_ESPI_2 0x4d80
#define PCI_DEVICE_ID_INTEL_MCC_ESPI_0 0x4b00
#define PCI_DEVICE_ID_INTEL_MCC_ESPI_1 0x4b04
#define PCI_DEVICE_ID_INTEL_MCC_BASE_ESPI 0x4b03
Expand All @@ -2819,6 +2817,7 @@
#define PCI_DEVICE_ID_INTEL_MCC_ESPI_2 0x4b05
#define PCI_DEVICE_ID_INTEL_MCC_ESPI_3 0x4b06
#define PCI_DEVICE_ID_INTEL_MCC_ESPI_4 0x4b07
#define PCI_DEVICE_ID_INTEL_JSP_SUPER_ESPI 0X4d87

/* Intel PCIE device ids */
#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10
Expand Down Expand Up @@ -3014,6 +3013,7 @@
#define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP14 0x02b5
#define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP15 0x02b6
#define PCI_DEVICE_ID_INTEL_CMP_LP_PCIE_RP16 0x02b7

#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP1 0x06b8
#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP2 0x06b9
#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP3 0x06ba
Expand All @@ -3038,14 +3038,15 @@
#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP22 0x06ad
#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP23 0x06ae
#define PCI_DEVICE_ID_INTEL_CMP_H_PCIE_RP24 0x06af
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP1 0x38b8
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP2 0x38b9
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP3 0x38ba
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP4 0x38bb
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP5 0x38bc
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP6 0x38bd
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP7 0x38be
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PCIE_RP8 0x38bf

#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP1 0x4db8
#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP2 0x4db9
#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP3 0x4dba
#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP4 0x4dbb
#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP5 0x4dbc
#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP6 0x4dbd
#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP7 0x4dbe
#define PCI_DEVICE_ID_INTEL_JSP_PCIE_RP8 0x4dbf

#define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP1 0x4b38
#define PCI_DEVICE_ID_INTEL_MCC_PCIE_RP2 0x4b39
Expand Down Expand Up @@ -3089,8 +3090,9 @@
#define PCI_DEVICE_ID_INTEL_TGP_SATA 0xa0d5
#define PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA 0xa0d7
#define PCI_DEVICE_ID_INTEL_TGP_COMPAT_SATA 0x282a
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SATA 0x38d3
#define PCI_DEVICE_ID_INTEL_MCC_AHCI_SATA 0x4b60
#define PCI_DEVICE_ID_INTEL_JSP_SATA_1 0x4dd2
#define PCI_DEVICE_ID_INTEL_JSP_SATA_2 0x4dd3

/* Intel PMC device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21
Expand All @@ -3106,8 +3108,8 @@
#define PCI_DEVICE_ID_INTEL_CMP_PMC 0x02a1
#define PCI_DEVICE_ID_INTEL_CMP_H_PMC 0x06a1
#define PCI_DEVICE_ID_INTEL_TGP_PMC 0xa0a1
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_PMC 0x38a1
#define PCI_DEVICE_ID_INTEL_MCC_PMC 0x4b21
#define PCI_DEVICE_ID_INTEL_JSP_PMC 0x4da1

/* Intel I2C device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_I2C0 0x9d60
Expand Down Expand Up @@ -3178,12 +3180,13 @@
#define PCI_DEVICE_ID_INTEL_MCC_I2C5 0x4b4c
#define PCI_DEVICE_ID_INTEL_MCC_I2C6 0x4b44
#define PCI_DEVICE_ID_INTEL_MCC_I2C7 0x4b45
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C0 0x38e8
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C1 0x38e9
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C2 0x38ea
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C3 0x38eb
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C4 0x38c5
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_I2C5 0x38c6

#define PCI_DEVICE_ID_INTEL_JSP_I2C0 0x4de8
#define PCI_DEVICE_ID_INTEL_JSP_I2C1 0x4de9
#define PCI_DEVICE_ID_INTEL_JSP_I2C2 0x4dea
#define PCI_DEVICE_ID_INTEL_JSP_I2C3 0x4deb
#define PCI_DEVICE_ID_INTEL_JSP_I2C4 0x4dc5
#define PCI_DEVICE_ID_INTEL_JSP_I2C5 0x4dc6

/* Intel UART device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_UART0 0x9d27
Expand Down Expand Up @@ -3224,9 +3227,9 @@
#define PCI_DEVICE_ID_INTEL_MCC_UART0 0x4b28
#define PCI_DEVICE_ID_INTEL_MCC_UART1 0x4b29
#define PCI_DEVICE_ID_INTEL_MCC_UART2 0x4b4d
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART0 0x38a8
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART1 0x38a9
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_UART2 0x38c7
#define PCI_DEVICE_ID_INTEL_JSP_UART0 0x4da8
#define PCI_DEVICE_ID_INTEL_JSP_UART1 0x4da9
#define PCI_DEVICE_ID_INTEL_JSP_UART2 0x4dc7

/* Intel SPI device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_SPI1 0x9d24
Expand Down Expand Up @@ -3273,10 +3276,10 @@
#define PCI_DEVICE_ID_INTEL_MCC_GSPI0 0x4b2a
#define PCI_DEVICE_ID_INTEL_MCC_GSPI1 0x4b2b
#define PCI_DEVICE_ID_INTEL_MCC_GSPI2 0x4b37
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI0 0x38aa
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI1 0x38ab
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SPI2 0x38fb
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_HWSEQ_SPI 0x38a4
#define PCI_DEVICE_ID_INTEL_JSP_SPI0 0x4daa
#define PCI_DEVICE_ID_INTEL_JSP_SPI1 0x4dab
#define PCI_DEVICE_ID_INTEL_JSP_SPI2 0x4dfb
#define PCI_DEVICE_ID_INTEL_JSP_HWSEQ_SPI 0x4da4

/* Intel IGD device Ids */
#define PCI_DEVICE_ID_INTEL_SKL_GT1F_DT2 0x1902
Expand Down Expand Up @@ -3387,7 +3390,8 @@
#define PCI_DEVICE_ID_INTEL_EHL_GT2_2 0x4550
#define PCI_DEVICE_ID_INTEL_EHL_GT1_3 0x4571
#define PCI_DEVICE_ID_INTEL_EHL_GT2_3 0x4570
#define PCI_DEVICE_ID_INTEL_JSL_PRE_PROD_GT0 0x4569
#define PCI_DEVICE_ID_INTEL_JSL_GT1 0x4E51
#define PCI_DEVICE_ID_INTEL_JSL_GT2 0x4E71

/* Intel Northbridge Ids */
#define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0
Expand Down Expand Up @@ -3445,10 +3449,11 @@
#define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44
#define PCI_DEVICE_ID_INTEL_TGL_ID_U 0x9A14
#define PCI_DEVICE_ID_INTEL_TGL_ID_U_1 0x9A12
#define PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2 0x9A04
#define PCI_DEVICE_ID_INTEL_TGL_ID_Y 0x9A10
#define PCI_DEVICE_ID_INTEL_JSL_PRE_PROD 0x4e2a
#define PCI_DEVICE_ID_INTEL_JSL_EHL 0x4532
#define PCI_DEVICE_ID_INTEL_EHL_ID_1 0x4510
#define PCI_DEVICE_ID_INTEL_JSL_ID_1 0x4e22

/* Intel SMBUS device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23
Expand All @@ -3461,8 +3466,8 @@
#define PCI_DEVICE_ID_INTEL_CMP_SMBUS 0x02a3
#define PCI_DEVICE_ID_INTEL_CMP_H_SMBUS 0x06a3
#define PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS 0xa0a3
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SMBUS 0x38a3
#define PCI_DEVICE_ID_INTEL_MCC_SMBUS 0x4b23
#define PCI_DEVICE_ID_INTEL_JSP_SMBUS 0x4da3

/* Intel XHCI device Ids */
#define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
Expand All @@ -3478,8 +3483,8 @@
#define PCI_DEVICE_ID_INTEL_CMP_LP_XHCI 0x02ed
#define PCI_DEVICE_ID_INTEL_CMP_H_XHCI 0x06ed
#define PCI_DEVICE_ID_INTEL_TGP_LP_XHCI 0xa0ed
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_XHCI 0x38ed
#define PCI_DEVICE_ID_INTEL_MCC_XHCI 0x4b7d
#define PCI_DEVICE_ID_INTEL_JSP_XHCI 0x4ded

/* Intel P2SB device Ids */
#define PCI_DEVICE_ID_INTEL_APL_P2SB 0x5a92
Expand All @@ -3495,8 +3500,8 @@
#define PCI_DEVICE_ID_INTEL_CMP_P2SB 0x02a0
#define PCI_DEVICE_ID_INTEL_CMP_H_P2SB 0x06a0
#define PCI_DEVICE_ID_INTEL_TGL_P2SB 0xa0a0
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_P2SB 0x38a0
#define PCI_DEVICE_ID_INTEL_EHL_P2SB 0x4b20
#define PCI_DEVICE_ID_INTEL_JSP_P2SB 0x4da0

/* Intel SRAM device Ids */
#define PCI_DEVICE_ID_INTEL_APL_SRAM 0x5aec
Expand All @@ -3507,8 +3512,8 @@
#define PCI_DEVICE_ID_INTEL_CMP_SRAM 0x02ef
#define PCI_DEVICE_ID_INTEL_CMP_H_SRAM 0x06ef
#define PCI_DEVICE_ID_INTEL_TGL_SRAM 0xa0ef
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SRAM 0x38ef
#define PCI_DEVICE_ID_INTEL_MCC_SRAM 0x4b7f
#define PCI_DEVICE_ID_INTEL_JSP_SRAM 0x4def

/* Intel AUDIO device Ids */
#define PCI_DEVICE_ID_INTEL_APL_AUDIO 0x5a98
Expand All @@ -3525,8 +3530,8 @@
#define PCI_DEVICE_ID_INTEL_CMP_H_AUDIO 0x06c8
#define PCI_DEVICE_ID_INTEL_BSW_AUDIO 0x2284
#define PCI_DEVICE_ID_INTEL_TGL_AUDIO 0xa0c8
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_AUDIO 0x38c8
#define PCI_DEVICE_ID_INTEL_MCC_AUDIO 0x4b55
#define PCI_DEVICE_ID_INTEL_JSP_AUDIO 0x4dc8

/* Intel HECI/ME device Ids */
#define PCI_DEVICE_ID_INTEL_APL_CSE0 0x5a9a
Expand All @@ -3544,11 +3549,14 @@
#define PCI_DEVICE_ID_INTEL_CMP_CSE0 0x02e0
#define PCI_DEVICE_ID_INTEL_CMP_H_CSE0 0x06e0
#define PCI_DEVICE_ID_INTEL_TGL_CSE0 0xa0e0
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_CSE0 0x38e0
#define PCI_DEVICE_ID_INTEL_MCC_CSE0 0x4b70
#define PCI_DEVICE_ID_INTEL_MCC_CSE1 0x4b71
#define PCI_DEVICE_ID_INTEL_MCC_CSE2 0x4b74
#define PCI_DEVICE_ID_INTEL_MCC_CSE3 0x4b75
#define PCI_DEVICE_ID_INTEL_JSP_CSE0 0x4de0
#define PCI_DEVICE_ID_INTEL_JSP_CSE1 0x4de1
#define PCI_DEVICE_ID_INTEL_JSP_CSE2 0x4de4
#define PCI_DEVICE_ID_INTEL_JSP_CSE3 0x4de5

/* Intel XDCI device Ids */
#define PCI_DEVICE_ID_INTEL_APL_XDCI 0x5aaa
Expand All @@ -3561,6 +3569,7 @@
#define PCI_DEVICE_ID_INTEL_CMP_H_XDCI 0x06ee
#define PCI_DEVICE_ID_INTEL_TGP_LP_XDCI 0xa0ee
#define PCI_DEVICE_ID_INTEL_MCC_XDCI 0x4b7e
#define PCI_DEVICE_ID_INTEL_JSP_XDCI 0x4dee

/* Intel SD device Ids */
#define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca
Expand All @@ -3571,12 +3580,13 @@
#define PCI_DEVICE_ID_INTEL_ICL_SD 0x34f8
#define PCI_DEVICE_ID_INTEL_CMP_SD 0x02f5
#define PCI_DEVICE_ID_INTEL_CMP_H_SD 0x06f5
#define PCI_DEVICE_ID_INTEL_JSP_PRE_PROD_SD 0x38f8
#define PCI_DEVICE_ID_INTEL_MCC_SD 0x4b48
#define PCI_DEVICE_ID_INTEL_JSP_SD 0x4df8

/* Intel EMMC device Ids */
#define PCI_DEVICE_ID_INTEL_SKL_EMMC 0x9d2b
#define PCI_DEVICE_ID_INTEL_CMP_EMMC 0x02c4
#define PCI_DEVICE_ID_INTEL_JSP_EMMC 0x4dc4

/* Intel WIFI Ids */
#define PCI_DEVICE_ID_1000_SERIES_WIFI 0x0084
Expand Down
6 changes: 6 additions & 0 deletions src/include/device/pciexp.h
View file
Expand Up @@ -26,5 +26,11 @@ void pciexp_scan_bridge(struct device *dev);

extern struct device_operations default_pciexp_ops_bus;

#if CONFIG(PCIEXP_HOTPLUG)
void pciexp_hotplug_scan_bridge(struct device *dev);

extern struct device_operations default_pciexp_hotplug_ops_bus;
#endif /* CONFIG(PCIEXP_HOTPLUG) */

unsigned int pciexp_find_extended_cap(struct device *dev, unsigned int cap);
#endif /* DEVICE_PCIEXP_H */
1 change: 0 additions & 1 deletion src/include/spi_flash.h
View file
Expand Up @@ -106,7 +106,6 @@ struct spi_flash {
};
} flags;
u16 model;
const char *name;
u32 size;
u32 sector_size;
u32 page_size;
Expand Down
4 changes: 0 additions & 4 deletions src/include/stdint.h
View file
Expand Up @@ -14,10 +14,6 @@
#ifndef STDINT_H
#define STDINT_H

/* romcc does not support long long, _Static_assert, or _Bool, so we must ifdef that code out.
Also, GCC can provide its own implementation of stdint.h, so in theory we could use that
instead of this custom file once romcc is no more. */

/* Fixed width integer types */
typedef signed char int8_t;
typedef unsigned char uint8_t;
Expand Down
2 changes: 1 addition & 1 deletion src/lib/coreboot_table.c
View file
Expand Up @@ -505,7 +505,7 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end)
* lb_record...
*/
memcpy(rec_dest, option_table, option_table->size);
/* Create cmos checksum entry in coreboot table */
/* Create CMOS checksum entry in coreboot table */
lb_cmos_checksum(head);
} else {
printk(BIOS_ERR,
Expand Down
6 changes: 3 additions & 3 deletions src/lib/edid.c
View file
Expand Up @@ -573,7 +573,7 @@ detailed_block(struct edid *result_edid, unsigned char *x, int in_extension,
"Detailed mode (IN HEX): Clock %d KHz, %x mm x %x mm\n"
" %04x %04x %04x %04x hborder %x\n"
" %04x %04x %04x %04x vborder %x\n"
" %chsync %cvsync%s%s %s\n",
" %chsync %cvsync%s%s%s\n",
out->mode.pixel_clock,
extra_info.x_mm,
extra_info.y_mm,
Expand Down Expand Up @@ -1138,8 +1138,6 @@ int decode_edid(unsigned char *edid, int size, struct edid *out)
.conformant = EDID_CONFORMANT,
};

memset(out, 0, sizeof(*out));

if (!edid) {
printk(BIOS_ERR, "No EDID found\n");
return EDID_ABSENT;
Expand All @@ -1152,6 +1150,8 @@ int decode_edid(unsigned char *edid, int size, struct edid *out)
return EDID_ABSENT;
}

memset(out, 0, sizeof(*out));

if (manufacturer_name(edid + 0x08, out->manufacturer_name))
c.manufacturer_name_well_formed = 1;

Expand Down
5 changes: 5 additions & 0 deletions src/lib/lzma.c
View file
Expand Up @@ -29,6 +29,11 @@ size_t ulzman(const void *src, size_t srcn, void *dst, size_t dstn)
MAYBE_STATIC_BSS unsigned char scratchpad[15980];
const unsigned char *cp;

if (srcn < data_offset) {
printk(BIOS_WARNING, "lzma: Input too small.\n");
return 0;
}

memcpy(properties, src, LZMA_PROPERTIES_SIZE);
/* The outSize in LZMA stream is a 64bit integer stored in little-endian
* (ref: lzma.cc@LZMACompress: put_64). To prevent accessing by
Expand Down