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|
@@ -3,8 +3,3 @@ config IPMI_OCP | |
| default n | ||
| help | ||
| This implements OCP specific IPMI command | ||
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| @@ -0,0 +1,2 @@ | ||
| config DRIVERS_SOUNDWIRE_ALC1308 | ||
| bool |
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| @@ -0,0 +1 @@ | ||
| ramstage-$(CONFIG_DRIVERS_SOUNDWIRE_ALC1308) += alc1308.c |
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| @@ -0,0 +1,151 @@ | ||
| /* SPDX-License-Identifier: GPL-2.0-only */ | ||
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| #include <acpi/acpigen.h> | ||
| #include <acpi/acpi_device.h> | ||
| #include <acpi/acpi_soundwire.h> | ||
| #include <device/device.h> | ||
| #include <device/path.h> | ||
| #include <device/mipi_ids.h> | ||
| #include <device/soundwire.h> | ||
| #include <stdio.h> | ||
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| #include "chip.h" | ||
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| static struct soundwire_address alc1308_address = { | ||
| .version = SOUNDWIRE_VERSION_1_1, | ||
| .manufacturer_id = MIPI_MFG_ID_REALTEK, | ||
| .part_id = MIPI_DEV_ID_REALTEK_ALC1308, | ||
| .class = MIPI_CLASS_NONE | ||
| }; | ||
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||
| static struct soundwire_slave alc1308_slave = { | ||
| .wake_up_unavailable = false, | ||
| .test_mode_supported = false, | ||
| .clock_stop_mode1_supported = true, | ||
| .simplified_clockstopprepare_sm_supported = true, | ||
| .clockstopprepare_hard_reset_behavior = false, | ||
| .highPHY_capable = false, | ||
| .paging_supported = false, | ||
| .bank_delay_supported = false, | ||
| .port15_read_behavior = false, | ||
| .source_port_list = SOUNDWIRE_PORT(2) | SOUNDWIRE_PORT(4), | ||
| .sink_port_list = SOUNDWIRE_PORT(1) | ||
| }; | ||
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| static struct soundwire_audio_mode alc1308_audio_mode = { | ||
| /* Bus frequency must be 1/2/4/8 divider of supported input frequencies. */ | ||
| .bus_frequency_configs_count = 12, | ||
| .bus_frequency_configs = { | ||
| 9600 * KHz, 4800 * KHz, 2400 * KHz, 1200 * KHz, /* 9.6 MHz */ | ||
| 12000 * KHz, 6000 * KHz, 3000 * KHz, 1500 * KHz, /* 12 MHz */ | ||
| 12288 * KHz, 6144 * KHz, 3072 * KHz, 1536 * KHz /* 12.288 MHz */ | ||
| }, | ||
| /* Support 16 KHz to 96 KHz sampling frequency */ | ||
| .sampling_frequency_configs_count = 8, | ||
| .sampling_frequency_configs = { | ||
| 16 * KHz, | ||
| 22.05 * KHz, | ||
| 24 * KHz, | ||
| 32 * KHz, | ||
| 44.1 * KHz, | ||
| 48 * KHz, | ||
| 88.2 * KHz, | ||
| 96 * KHz, | ||
| }, | ||
| .prepare_channel_behavior = CHANNEL_PREPARE_ANY_FREQUENCY | ||
| }; | ||
|
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| static struct soundwire_dpn alc1308_dp1 = { | ||
| .port_wordlength_configs_count = 1, | ||
| .port_wordlength_configs = { 32 }, | ||
| .data_port_type = FULL_DATA_PORT, | ||
| .max_grouping_supported = BLOCK_GROUP_COUNT_1, | ||
| .simplified_channelprepare_sm = false, | ||
| .imp_def_dpn_interrupts_supported = 0, | ||
| .min_channel_number = 1, | ||
| .max_channel_number = 2, | ||
| .modes_supported = MODE_ISOCHRONOUS | MODE_TX_CONTROLLED | | ||
| MODE_RX_CONTROLLED | MODE_FULL_ASYNCHRONOUS, | ||
| .block_packing_mode = true, | ||
| .port_audio_mode_count = 1, | ||
| .port_audio_mode_list = { 0 } | ||
| }; | ||
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| static const struct soundwire_codec alc1308_codec = { | ||
| .slave = &alc1308_slave, | ||
| .audio_mode = { &alc1308_audio_mode }, | ||
| .dpn = { | ||
| { | ||
| /* Data Input for Speaker Path */ | ||
| .port = 1, | ||
| .sink = &alc1308_dp1 | ||
| }, | ||
| { | ||
| /* Data out for I.V sensing */ | ||
| .port = 2, | ||
| .source = &alc1308_dp1 | ||
| }, | ||
| { | ||
| /* Data out for I.V sensing */ | ||
| .port = 4, | ||
| .source = &alc1308_dp1 | ||
| } | ||
| } | ||
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| }; | ||
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| static void soundwire_alc1308_fill_ssdt(const struct device *dev) | ||
| { | ||
| struct drivers_soundwire_alc1308_config *config = dev->chip_info; | ||
| const char *scope = acpi_device_scope(dev); | ||
| struct acpi_dp *dsd; | ||
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| if (!dev->enabled || !scope) | ||
| return; | ||
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| acpigen_write_scope(scope); | ||
| acpigen_write_device(acpi_device_name(dev)); | ||
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| /* Set codec address IDs. */ | ||
| alc1308_address.link_id = dev->path.generic.id; | ||
| alc1308_address.unique_id = dev->path.generic.subid; | ||
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| acpigen_write_ADR_soundwire_device(&alc1308_address); | ||
| acpigen_write_name_string("_DDN", config->desc ? : dev->chip_ops->name); | ||
| acpigen_write_STA(acpi_device_status(dev)); | ||
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| dsd = acpi_dp_new_table("_DSD"); | ||
| soundwire_gen_codec(dsd, &alc1308_codec, NULL); | ||
| acpi_dp_write(dsd); | ||
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| acpigen_pop_len(); /* Device */ | ||
| acpigen_pop_len(); /* Scope */ | ||
| } | ||
|
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| static const char *soundwire_alc1308_acpi_name(const struct device *dev) | ||
| { | ||
| struct drivers_soundwire_alc1308_config *config = dev->chip_info; | ||
| static char name[5]; | ||
|
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| if (config->name) | ||
| return config->name; | ||
| snprintf(name, sizeof(name), "SW%1X%1X", dev->path.generic.id, dev->path.generic.subid); | ||
| return name; | ||
| } | ||
|
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| static struct device_operations soundwire_alc1308_ops = { | ||
| .read_resources = noop_read_resources, | ||
| .set_resources = noop_set_resources, | ||
| .acpi_name = soundwire_alc1308_acpi_name, | ||
| .acpi_fill_ssdt = soundwire_alc1308_fill_ssdt, | ||
| }; | ||
|
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| static void soundwire_alc1308_enable(struct device *dev) | ||
| { | ||
| dev->ops = &soundwire_alc1308_ops; | ||
| } | ||
|
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| struct chip_operations drivers_soundwire_alc1308_ops = { | ||
| CHIP_NAME("Realtek ALC1308 SoundWire Codec") | ||
| .enable_dev = soundwire_alc1308_enable | ||
| }; |
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| @@ -0,0 +1,11 @@ | ||
| /* SPDX-License-Identifier: GPL-2.0-only */ | ||
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| #ifndef __DRIVERS_SOUNDWIRE_ALC1308_CHIP_H__ | ||
| #define __DRIVERS_SOUNDWIRE_ALC1308_CHIP_H__ | ||
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| struct drivers_soundwire_alc1308_config { | ||
| const char *name; | ||
| const char *desc; | ||
| }; | ||
|
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| #endif /* __DRIVERS_SOUNDWIRE_ALC1308_CHIP_H__ */ |
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| @@ -0,0 +1,17 @@ | ||
| /* SPDX-License-Identifier: GPL-2.0-only */ | ||
|
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| #ifndef ACPIGEN_PCI_H | ||
| #define ACPIGEN_PCI_H | ||
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| #include <device/device.h> | ||
| #include <device/pci_def.h> | ||
| #include <device/pci_type.h> | ||
|
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| void acpigen_write_ADR_pci_devfn(pci_devfn_t devfn); | ||
| void acpigen_write_ADR_pci_device(const struct device *dev); | ||
|
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| void acpigen_write_PRT_GSI_entry(unsigned int pci_dev, unsigned int acpi_pin, unsigned int gsi); | ||
| void acpigen_write_PRT_source_entry(unsigned int pci_dev, unsigned int acpi_pin, | ||
| const char *source_path, unsigned int index); | ||
|
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| #endif /* ACPIGEN_PCI_H */ |
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|---|---|---|
| @@ -1,6 +1,5 @@ | ||
| FLASH@0xFF000000 16M { | ||
| BIOS { | ||
| RW_MRC_CACHE 64K | ||
| FMAP 4K | ||
| COREBOOT(CBFS) | ||
|
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|---|---|---|
| @@ -0,0 +1,26 @@ | ||
| /* SPDX-License-Identifier: GPL-2.0-or-later */ | ||
|
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| #include <boot/coreboot_tables.h> | ||
| #include <gpio.h> | ||
| #include <vendorcode/google/chromeos/chromeos.h> | ||
|
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| void fill_lb_gpios(struct lb_gpios *gpios) | ||
| { | ||
| struct lb_gpio chromeos_gpios[] = {}; | ||
| lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); | ||
| } | ||
|
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| int get_write_protect_state(void) | ||
| { | ||
| /* Majolica doesn't have a write protect pin */ | ||
| return 0; | ||
| } | ||
|
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| static const struct cros_gpio cros_gpios[] = { | ||
| /* No ChromeOS GPIOs */ | ||
| }; | ||
|
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| void mainboard_chromeos_acpi_generate(void) | ||
| { | ||
| chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); | ||
| } |
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| @@ -1,8 +1,71 @@ | ||
| # SPDX-License-Identifier: GPL-2.0-only | ||
|
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| chip soc/amd/cezanne | ||
| register "common_config.espi_config" = "{ | ||
| .std_io_decode_bitmap = ESPI_DECODE_IO_0X60_0X64_EN | ESPI_DECODE_IO_0x80_EN | ||
| | ESPI_DECODE_IO_0X2E_0X2F_EN, | ||
| .io_mode = ESPI_IO_MODE_QUAD, | ||
| .op_freq_mhz = ESPI_OP_FREQ_16_MHZ, | ||
| .crc_check_enable = 1, | ||
| .dedicated_alert_pin = 1, | ||
| .periph_ch_en = 1, | ||
| .vw_ch_en = 1, | ||
| .oob_ch_en = 1, | ||
| .flash_ch_en = 0, | ||
| }" | ||
|
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| device domain 0 on | ||
| device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A | ||
| device ref gfx on end # Internal GPU (GFX) | ||
| device ref xhci_0 on # USB 3.1 (USB0) | ||
| chip drivers/usb/acpi | ||
| device ref xhci_0_root_hub on | ||
| chip drivers/usb/acpi | ||
| device ref usb3_port0 on end | ||
| end | ||
| chip drivers/usb/acpi | ||
| device ref usb3_port1 on end | ||
| end | ||
| chip drivers/usb/acpi | ||
| device ref usb2_port0 on end | ||
| end | ||
| chip drivers/usb/acpi | ||
| device ref usb2_port1 on end | ||
| end | ||
| chip drivers/usb/acpi | ||
| device ref usb2_port2 on end | ||
| end | ||
| chip drivers/usb/acpi | ||
| device ref usb2_port3 on end | ||
| end | ||
| end | ||
| end | ||
| end | ||
| device ref xhci_1 on # USB 3.1 (USB1) | ||
| chip drivers/usb/acpi | ||
| device ref xhci_1_root_hub on | ||
| chip drivers/usb/acpi | ||
| device ref usb3_port4 on end | ||
| end | ||
| chip drivers/usb/acpi | ||
| device ref usb3_port5 on end | ||
| end | ||
| chip drivers/usb/acpi | ||
| device ref usb2_port4 on end | ||
| end | ||
| chip drivers/usb/acpi | ||
| device ref usb2_port5 on end | ||
| end | ||
| chip drivers/usb/acpi | ||
| device ref usb2_port6 on end | ||
| end | ||
| chip drivers/usb/acpi | ||
| device ref usb2_port7 on end | ||
| end | ||
| end | ||
| end | ||
| end | ||
| end | ||
| end | ||
|
|
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| end |