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2 changes: 1 addition & 1 deletion Documentation/getting_started/architecture.md
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Expand Up @@ -10,7 +10,7 @@ coreboot consists of multiple stages that are compiled as separate binaries and
are inserted into the CBFS with custom compression. The bootblock usually doesn't
have compression while the ramstage and payload are compressed with LZMA.

Each stage loads the next stage a given address (possibly decompressing it).
Each stage loads the next stage at given address (possibly decompressing it).

Some stages are relocatable and can be placed anywhere in DRAM. Those stages are
usually cached in CBMEM for faster loading times on ACPI S3 resume.
Expand Down
17 changes: 17 additions & 0 deletions Documentation/getting_started/gerrit_guidelines.md
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Expand Up @@ -254,6 +254,23 @@ commit message itself:
The script 'util/gitconfig/rebase.sh' can be used to help automate this.
Other tags such as 'Commit-Queue' can simply be removed.

* Check if there's documentation that needs to be updated to remain current
after your change. If there's no documentation for the part of coreboot
you're working on, consider adding some.

* When contributing a significant change to core parts of the code base (such
as the boot state machine or the resource allocator), or when introducing
a new way of doing something that you think is worthwhile to apply across
the tree (e.g. board variants), please bring up your design on the [mailing
list](../community/forums.md). When changing behavior substantially, an
explanation of what changes and why may be useful to have, either in the
commit message or, if the discussion of the subject matter needs way more
space, in the documentation. Since "what we did in the past and why it isn't
appropriate anymore" isn't the most useful reading several years down the road,
such a description could be put into the release notes for the next version
(that you can find in Documentation/releases/) where it will inform people
now without cluttering up the regular documentation, and also gives a nice
shout-out to your contribution by the next release.

Expectations contributors should have
-------------------------------------
Expand Down
27 changes: 22 additions & 5 deletions Documentation/gfx/libgfxinit.md
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Expand Up @@ -88,11 +88,28 @@ know through which interface the EDID can be queried:
select GFX_GMA_ANALOG_I2C_HDMI_C # or
select GFX_GMA_ANALOG_I2C_HDMI_D

Beside Kconfig options, *libgfxinit* needs to know which ports are
implemented on a board and should be probed for displays. The mapping
between the physical ports and these entries depends on the hardware
implementation and can be recovered by testing or studying the output
of `intelvbttool` or `intel_vbt_decode`.
*libgfxinit* needs to know which ports are implemented on a board
and should be probed for displays. There are two mechanisms to
constrain the list of ports to probe, 1. port presence straps on
the mainboard, and 2. a list of ports provided by *coreboot* (see
below).

Presence straps are configured via the state of certains pins of
the chipset at reset time. They are documented in the chipset's
datasheets. By default, *libgfxinit* honors these straps for
safety. However, some boards don't implement the straps correctly.
If ports are not strapped as implemented by error, one can select
an option to ignore the straps:

select GFX_GMA_IGNORE_PRESENCE_STRAPS

In the opposite case, that ports are strapped as implemented,
but are actually unconnected, one has to make sure that the
list of ports in *coreboot* omits them.

The mapping between the physical ports and these entries depends on
the hardware implementation and can be recovered by testing or
studying the output of `intelvbttool` or `intel_vbt_decode`.
Each board has to implement the package `GMA.Mainboard` with a list:

ports : HW.GFX.GMA.Display_Probing.Port_List;
Expand Down
1 change: 1 addition & 0 deletions Documentation/index.md
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Expand Up @@ -164,6 +164,7 @@ Contents:
* [Tutorial](tutorial/index.md)
* [Coding Style](coding_style.md)
* [Project Ideas](contributing/project_ideas.md)
* [Documentation Ideas](contributing/documentation_ideas.md)
* [Code of Conduct](community/code_of_conduct.md)
* [Community forums](community/forums.md)
* [Project services](community/services.md)
Expand Down
13 changes: 7 additions & 6 deletions Documentation/mainboard/51nb/x210.md
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Expand Up @@ -4,20 +4,21 @@

EC firmware is included in the SPI image. To extract it, run:

``
```
dd bs=64K skip=32 count=1 if=bios.rom of=ec.bin
``
```

and ensure that you have a file that includes the string "Insyde Software Corp"
and ensure that you have a file that includes the string "Insyde Software Corp".

## Flashing instructions

This can be performed using the internal SPI controller, even when flashing
from stock firmware. Use flashrom -p internal and follow the appropriate
from stock firmware. Use `flashrom -p internal` and follow the appropriate
flashrom instructions to force it. Alternatively, external flashing has been
tested with Dediprog SF100 and SF600 and using a Beaglebone Black. The flash
is located on the upper side of the motherboard, below the keyboard
connector. It is circled in red here:

![](x210.jpg)

## Flashing a subset of the ROM
Expand All @@ -32,14 +33,14 @@ create a layout file with the following content:
00210000:007fffff main
```

and run flashrom with the "--layout rom.layout --image main" arguments. This
and run flashrom with the `--layout rom.layout --image main` arguments. This
will flash the main firmware without overwriting the existing EC or ME
firmware.

## Working

All hardware features are believed to be working, although the SD reader is
untested. Note that certain hotkeys don't work (including the Thinkvantage
untested. Note that certain hotkeys don't work (including the ThinkVantage
button) - this is a limitation of the EC firmware, and these keys also
generate no events under the stock vendor firmware.

Binary file added Documentation/mainboard/dell/optiplex_9010.jpg
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147 changes: 147 additions & 0 deletions Documentation/mainboard/dell/optiplex_9010.md
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@@ -0,0 +1,147 @@
# Dell OptiPlex 9010

This page describes how to run coreboot on Dell OptiPlex 9010 SFF.

![](optiplex_9010.jpg)

## Technology

```eval_rst
+------------+---------------------------------------------------------------+
| CPU | Intel Core 2nd Gen (Sandybridge) or 3rd Gen (Ivybridge) |
+------------+---------------------------------------------------------------+
| DRAM | Up to 4 DIMM slots, up to 32GB 1600MHz non-ECC DDR3 SDRAM |
+------------+---------------------------------------------------------------+
| Chipset | Intel Q77 Express |
+------------+---------------------------------------------------------------+
| Super I/O | SMSC SCH5545 (or SCH5544) with Environmental Controller |
+------------+---------------------------------------------------------------+
| TPM | ST Microelectronics ST33ZP24 |
+------------+---------------------------------------------------------------+
| Boot | From USB, SATA, NVMe (using PCIe x4 expansion card) |
+------------+---------------------------------------------------------------+
| Power | 200W-275W PSU |
+------------+---------------------------------------------------------------+
```

More specifications on [Dell OptiPlex 9010 specifications].

## Required proprietary blobs

```eval_rst
+------------------+---------------------------------+---------------------+
| Binary file | Apply | Required / Optional |
+==================+=================================+=====================+
| smsc_sch5545.bin | SMSC SCH5545 EC | Optional |
+------------------+---------------------------------+---------------------+
| microcode | CPU microcode | Required |
+------------------+---------------------------------+---------------------+
```

Microcode updates are automatically included into the coreboot image by build
system from the `3rdparty/intel-microcode` submodule.

SMSC SC5545 EC firmware is optional, however lack of the binary will result in
EC malfunction after power failure and fans running at full speed. The blob can
be extracted from original firmware. It should be located under a file with
GUID D386BEB8-4B54-4E69-94F5-06091F67E0D3, raw section. The file begins with a
signature `SMSCUBIM`. The easiest way to do this is to use [UEFITool] and
`Extract body` option on the raw section of the file.

## Flashing coreboot

```eval_rst
+---------------------+--------------------------+
| Type | Value |
+=====================+==========================+
| Socketed flash | no |
+---------------------+--------------------------+
| Model | MX25L6406E/MX25L3206E |
+---------------------+--------------------------+
| Size | 8 + 4 MiB |
+---------------------+--------------------------+
| Package | SOIC-16 + SOIC-8 |
+---------------------+--------------------------+
| Write protection | chipset PRR |
+---------------------+--------------------------+
| Dual BIOS feature | no |
+---------------------+--------------------------+
| Internal flashing | yes |
+---------------------+--------------------------+
```

### Internal programming

The SPI flash can be accessed using [flashrom].

flashrom -p internal -w coreboot.rom --ifd -i bios

Internal programming will not work when migrating from original UEFI firmware.
One will have to short the SERVICE_MODE jumper to enable HMRFPO and then boot
the machine to flash it.

### External programming

The external access to flash chip is available through standard SOP-8 clip
and/or SOP-16 clip on the right side of the CPU fan (marked on the board
image). The voltage of SPI flash is 3.3V.

There are no restrictions as to the programmer device. It is only recommended
to flash firmware without supplying power. There are no diodes connected to the
flash chips. External programming can be performed, for example using OrangePi
and Armbian. You can use linux_spi driver which provides communication with SPI
devices. Example command to program SPI flash with OrangePi using linux_spi:

flashrom -w coreboot.rom -p linux_spi:dev=/dev/spidev1.0,spispeed=16000

## Schematics

There are no schematics for SFF, but if one looks for MT/DT schematics, they
can be found publicly. Most of the schematics should match the SFF (although
MT/DT has additional PCIe and PCI slot).

## Known issues

- There seems to be a problem with DRAM clearing on reboot. The SSKPD register
still contains 0xCAFE which leads to reset loop.

## Untested

Not all mainboard's peripherals and functions were tested because of lack of
the cables or not being populated on the board case.

- Internal USB 2.0 header
- Wake from S3 using serial port
- Wake-on-Lan from ACPI S4/S5

## Working

- USB 3.0 and 2.0 rear and front ports (SeaBIOS and Linux 4.19)
- Gigabit Ethernet
- VGA and 2x DP port using libgfxinit
- flashrom
- PCIe x1 WiFi in PCIe x4 slot
- NVMe PCIe x4 using PCIe x4 expansion card
- PCIe x16 PEG port using Dell Radeon HD 7570
- SATA ports (SATA disks and DVD)
- Super I/O serial port 0 (RS232 DB9 connector on the rear side)
- SMBus (reading SPD from DIMMs)
- CPU initialization using Intel i7-3770
- Sandy Bridge/Ivy Bridge native RAM initialization
- SeaBIOS payload (version rel-1.13.0)
- PS/2 keyboard and mouse (including wake support)
- LPC debug header (requires soldering of the pin header and shorting RF24 for
LPC clock)
- USB debug dongle (the most bottom USB 2.0 port under RJ45 on the read side)
- SMSC SCH5545 Super I/O initialization
- SMSC SCH5545 EC initialization and firmware update
- SMSC SCH5545 EC automatic fan control
- TPM 1.2
- Booting Debian 10, Ubuntu 18.04, QubesOS R4.01
- Boot with cleaned ME
- Intruder detection
- Wake-on-Lan from ACPI S3

[flashrom]: https://flashrom.org/Flashrom
[Dell OptiPlex 9010 specifications]: https://www.dell.com/downloads/global/products/optix/en/dell_optiplex_9010_spec_sheet.pdf
[UEFITool]: https://github.com/LongSoft/UEFITool
5 changes: 5 additions & 0 deletions Documentation/mainboard/index.md
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Expand Up @@ -26,6 +26,10 @@ This section contains documentation about coreboot on specific mainboards.

- [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)

## Dell

- [OptiPlex 9010 SFF](dell/optiplex_9010.md)

## Emulation

The boards in this section are not real mainboards, but emulators.
Expand Down Expand Up @@ -74,6 +78,7 @@ The boards in this section are not real mainboards, but emulators.
- [R60](lenovo/r60.md)
- [T4xx common](lenovo/t4xx_series.md)
- [X2xx common](lenovo/x2xx_series.md)
- [vboot](lenovo/vboot.md)

### Arrandale series

Expand Down
1 change: 1 addition & 0 deletions Documentation/mainboard/lenovo/Sandy_Bridge_series.md
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Expand Up @@ -67,3 +67,4 @@ the remaining space for the `bios` partition.

[me_cleaner]: ../../northbridge/intel/sandybridge/me_cleaner.md
[external programmer]: ../../flash_tutorial/index.md
[flashing tutorial]: ../../flash_tutorial/index.md
38 changes: 38 additions & 0 deletions Documentation/mainboard/lenovo/vboot.md
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@@ -0,0 +1,38 @@
# Using coreboot's verified boot on Lenovo devices

By default a single instance of coreboot is present in the firmware flash,
no verification is done and the flash is not write-protected, so as to allow
firmware updates from the OS.
The verified boot mechanism also called [vboot] allows secure firmware
updates using an A/B partitioning scheme once enabled.

## Enabling vboot
You can enable [vboot] in Kconfig's *Security* section. Besides a verified
boot you can also enable a measured boot by setting
`CONFIG_VBOOT_MEASURED_BOOT`. Both options need a working TPM, which is
present on all recent Lenovo devices.

## Updating and recovery
As the A/B partition is writeable you can still update them from the OS.
By using the [vboot] mechanism you store a copy of coreboot in the `RO`
partition that acts as failsafe in case the regular firmware update, that
goes to the `A` or `B` partition fails.

**Note:** The `RO` partition isn't write-protected by default, therefore you
have to enable the protection in the security Kconfig menu by yourself.

On *Lenovo* devices you can enable the *Fn* key as recovery mode switch, by
enabling `CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW`.
Holding the *Fn* at boot will then switch to the recovery image, allowing
to boot and flash a working image to the A/B partition.

## 8 MiB ROM limitation
*Lenovo* devices with 8 MiB ROM only have a `RO`+`A` partition enabled in the
default FMAP. They are missing the `B` partition, due to size constaints.
You can still provide your own FMAP if you need `RO`+`A`+`B` partitions.

## CMOS
[vboot] on *Lenovo* devices uses the CMOS to store configuration data, like
boot failures and the last successfully booted partition.

[vboot]: ../../security/vboot/index.md
16 changes: 1 addition & 15 deletions Documentation/mainboard_io_trap_handler_sample.c
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@@ -1,18 +1,4 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008-2009 coresystems GmbH
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */

#include <arch/io.h>
#include <console/console.h>
Expand Down
3 changes: 3 additions & 0 deletions Documentation/releases/checklist.md
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Expand Up @@ -67,6 +67,9 @@ be more frequent than was needed, so we scaled it back to twice a year.
ask for testing.
- [ ] Test the commit selected for release.
- [ ] Update release notes with actual commit id, push to repo.
- [ ] Create new release notes doc template for the next version.
- [ ] Fill in the release date, remove "Upcoming release" and other filler
from the current release notes.
- [ ] Run release script.
- [ ] Run vboot_list script.
- [ ] Test the release from the actual release tarballs.
Expand Down
2 changes: 1 addition & 1 deletion Documentation/releases/coreboot-4.11-relnotes.md
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Expand Up @@ -175,7 +175,7 @@ of becoming more generally useful.
Payload integration has been updated, coreinfo learned to cope with
UPPER CASE commands and libpayload knows how to deal with USB3 hubs.

### Added VBOOT support to the following platforms:
### Added vboot support to the following platforms:

* intel/gm45
* intel/nehalem
Expand Down
105 changes: 90 additions & 15 deletions Documentation/releases/coreboot-4.12-relnotes.md
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@@ -1,20 +1,79 @@
Upcoming release - coreboot 4.12
================================
coreboot 4.12
=============

The 4.12 release is planned for April 2020
coreboot 4.12 was released on May 12th, 2020.

Update this document with changes that should be in the release
notes.
* Please use Markdown.
* See the past few release notes for the general format.
* The chip and board additions and removals will be updated right
before the release, so those do not need to be added.
Since 4.11 there were 2692 new commits by over 190 developers and of
these, 59 contributed for the first time, which is quite an amazing
increase.

Thank you to all developers who again helped made coreboot better
than ever, and a big welcome to our new contributors!

Maintainers
-----------

This release saw some activity on the MAINTAINERS file, showing more
persons, teams and companies declare publicly that they intend to
take care of mainboards and subsystems.

To all new maintainers, thanks a lot!

Documentation
-------------

Our documentation efforts in the code tree are picking up steam, with
some 70 commits in that general area. Everything from typo fixes to
documenting mainboard support or coreboot APIs.

There's still room to improve, but the contributions are getting more
and better.

Hardware support
----------------

The removals due to the announced deprecations as well as the
deduplication of boards into variants skew the stats a bit, so at
a top level view this is a rare coreboot release in that it removes
more boards (51) than it adds (49).

After accounting for the variant moves the numbers in favor of more
hardware supported than the previous version. Besides a whole lot
of Chrome OS devices (again), this release features a whole bunch
of retrofits for devices originally shipping with non-coreboot OEM
firmware, but also support for devices that come with coreboot right
out of the box.

For that, a shout out to System76, Protectli, Libretrend and the
Open Compute Project!

Cleanup
--------

We simplified the header that comes at the top of every file:
Instead of a lengthy reference to the license any given file
is under, or even the license text itself, we opted for simple
[SPDX](https://www.spdx.org) identifiers.

Since people also handled copyright lines differently, we now opt for
collecting authors in AUTHORS and let git history tell the whole story.

While at it, the content-free "This file is part of this-and-that
project" header was also dropped.

Besides that, there has also been more work to sort out the headers
we include across the tree to minimize the code impacting every
compilation unit.

Now that our board-variant mechanism matured, many boards that were
individual models so far were converted into variants, making it
easier to maintain families of devices.

Deprecations
------------

For the 4.12 release a few features on x86 became mandatory. These are
relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK.
relocatable ramstage, postcar stage and C\_ENVIRONMENT\_BOOTBLOCK.

### Relocatable ramstage

Expand Down Expand Up @@ -53,9 +112,8 @@ regions.
The following platforms did not implement those feature are dropped
from master to allow the master branch to move on:
- AMDFAM10
- all FSP1.0 platforms: BROADWELL_DE, FSP_BAYTRAIL, RANGELEY
- all FSP1.0 platforms: BROADWELL\_DE, FSP\_BAYTRAIL, RANGELEY
- VIA VX900
- TODO (AMD?)

In particular on FSP1.0 it is impossible to implement POSTCAR stage.
The reason is that FSP1.0 relocates the CAR region to the HOB before
Expand All @@ -67,7 +125,7 @@ there. This solution is deemed too hacky. Maybe a lesson can be
learned from this: blobs should not interfere with the execution
environment, as this makes proper integration much harder.

### 4.11_branch
### 4.11\_branch

Given that some platforms supported by FSP1.0 are being produced and
popular, the 4.11 release was made into a branch in which further
Expand All @@ -78,6 +136,23 @@ Significant changes

### SMMSTORE is now production ready

See [smmstore](../drivers/smmstore.md) for the documentation on the API.
See [smmstore](../drivers/smmstore.md) for the documentation on
the API, but note that there will be an update to it featuring a
much-improved but incompatible API.

### Unit testing infrastructure

Unit testing of coreboot is now possible in a more structured way, with new
build subsystem and adoption of [Cmocka](https://cmocka.org/) framework. Tree
has new directory `tests/`, which comprises infrastructure and examples of unit
tests. See
[Unit testing coreboot](../technotes/2020-03-unit-testing-coreboot.md) for the
design document.

Final Notes
-----------

### Add significant changes here
Your favorite new feature or supported board didn't make it to the
release notes? They're maintained collaboratively in the coreboot
tree, so when you land something noteworthy don't be shy, contribute
to the upcoming release's document in Documentation/releases!
16 changes: 16 additions & 0 deletions Documentation/releases/coreboot-4.13-relnotes.md
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@@ -0,0 +1,16 @@
Upcoming release - coreboot 4.13
================================

The 4.13 release is planned for November 2020.

Update this document with changes that should be in the release notes.

* Please use Markdown.
* See the past few release notes for the general format.
* The chip and board additions and removals will be updated right
before the release, so those do not need to be added.

Significant changes
-------------------

### Add significant changes here
2 changes: 1 addition & 1 deletion Documentation/releases/coreboot-4.5-relnotes.md
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Expand Up @@ -73,7 +73,7 @@ Areas with significant updates

### Vendorcode
* AMD (14 commits) - Cleanup, add libagesa.a builds, remove unused code.
* Google (22 commits) - VBoot2 updates and cleanup
* Google (22 commits) - vboot2 updates and cleanup
* Intel (86 commits) - Add Intel FSP 2.0, update Broadwell DE support

### Payloads (37 commits)
Expand Down
2 changes: 1 addition & 1 deletion Documentation/releases/coreboot-4.6-relnotes.md
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Expand Up @@ -180,7 +180,7 @@ SuperIO (12 commits)
* Add 2 new chips
* Consolidate code to use common routines

Vboot (23 commits)
vboot (23 commits)
* Add support for recovery hash space in TPM

RISC-V (25 commits)
Expand Down
2 changes: 1 addition & 1 deletion Documentation/releases/coreboot-4.8.1-relnotes.md
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Expand Up @@ -77,7 +77,7 @@ Security
--------
* Start of refactoring the TPM software stack
* Introduced coreboot security section in kconfig
* VBoot & TPM code moved into src/security
* vboot & TPM code moved into src/security

Intelmetool
-----------
Expand Down
3 changes: 2 additions & 1 deletion Documentation/releases/index.md
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Expand Up @@ -12,6 +12,7 @@ Release notes for previous releases
* [4.9 - December 2018](coreboot-4.9-relnotes.md)
* [4.10 - July 2019](coreboot-4.10-relnotes.md)
* [4.11 - November 2019](coreboot-4.11-relnotes.md)
* [4.12 - May 2020](coreboot-4.12-relnotes.md)

The checklist contains instructions to ensure that a release covers all
important things and provides a reliable format for tarballs, branch
Expand All @@ -23,4 +24,4 @@ Upcoming release
----------------

Please add to the release notes as changes are added:
* [4.12 - April 2020](coreboot-4.12-relnotes.md)
* [4.13 - November 2020](coreboot-4.13-relnotes.md)
2 changes: 1 addition & 1 deletion Documentation/security/vboot/index.md
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Expand Up @@ -196,7 +196,7 @@ not into the read/write coreboot file systems in *FW_MAIN_A* and *FW_MAIN_B*.
**VBOOT_ENABLE_CBFS_FALLBACK**

Normally coreboot will use the active read/write coreboot file system for all
of it's file access when VBOOT is active and is not in recovery mode.
of it's file access when vboot is active and is not in recovery mode.

When the `VBOOT_ENABLE_CBFS_FALLBACK` option is enabled the cbfs file system will
first try to locate a file in the active read/write file system. If the file
Expand Down
10 changes: 9 additions & 1 deletion Documentation/security/vboot/list_vboot.md
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@@ -1,4 +1,4 @@
# VBOOT enabled devices
# vboot-enabled devices

## Emulation
- QEMU x86 i440fx/piix4 (aka qemu -M pc)
Expand Down Expand Up @@ -33,6 +33,8 @@
- Ultima (Lenovo Yoga 11e G3)
- Wizpig
- Daisy (Samsung Chromebook (2012))
- Deltan
- Deltaur
- DragonEgg
- Drallion
- Eve (Google Pixelbook)
Expand All @@ -56,8 +58,10 @@
- Rainier
- Akemi
- Dratini
- Duffy
- Hatch
- Jinlon
- Kaisa
- Kohaku
- Kindred
- Helios
Expand All @@ -67,6 +71,7 @@
- Puff
- Helios_Diskswap
- Stryke
- Sushi
- Guado (ASUS Chromebox CN62)
- Jecht
- Rikku (Acer Chromebox CXI2)
Expand Down Expand Up @@ -135,6 +140,8 @@
- Storm (OnHub Router TGR1900)
- Stout (Lenovo Thinkpad X131e Chromebook)
- Trogdor
- Lazor
- Bubs
- Veyron_Jaq (Haier Chromebook 11)
- Veyron_Jerry (Hisense Chromebook 11)
- Veyron_Mighty (Haier Chromebook 11(edu))
Expand Down Expand Up @@ -199,6 +206,7 @@
- ThinkPad X1
- ThinkPad X230
- ThinkPad X230t
- ThinkPad X60 / X60s / X60t

## OpenCellular
- Elgon (GBCv2)
Expand Down
4 changes: 2 additions & 2 deletions Documentation/security/vboot/measured_boot.md
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Expand Up @@ -120,12 +120,12 @@ PCR-7 are left empty.
### PCR-0
_Hash:_ SHA1

_Description:_ Google VBoot GBB flags.
_Description:_ Google vboot GBB flags.

### PCR-1
_Hash:_ SHA1/SHA256

_Description:_ Google VBoot GBB HWID.
_Description:_ Google vboot GBB HWID.

### PCR-2
_Hash:_ SHA1/SHA256
Expand Down
45 changes: 45 additions & 0 deletions Documentation/soc/amd/family17h.md
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Expand Up @@ -237,6 +237,51 @@ Picasso's FSP is compatible with rev. 2.0 of the External Architecture
Specification. Deviations, e.g., no FSP-T support, shall be published
in an Integration Guide.

## APCB setup

APCBs are used to provide the PSP with SPD information and optionally a set of
GPIOs to use for selecting which SPD to load.

### Prebuilt
The picasso `Makefile` expects APCBs to be located in
`3rdparty/blobs/mainboard/$(MAINBOARDDIR)`. If you have a pre-built binary just
add the following to your mainboard's Makefile.

```
# i.e., 3rdparty/blobs/mainboard/amd/mandolin/APCB_mandolin.bin
APCB_SOURCES = mandolin
```

### Generating APCBs
If you have a template APCB file, the `apcb_edit` tool can be used to inject the
SPD and GPIOs used to select the correct slot. Entries should match this
pattern `{NAME}_x{1,2}`. There should be a matching SPD hex file in
`SPD_SOURCES_DIR` matching the pattern `{NAME}.spd.hex`.
The `_x{1,2}` suffix denotes single or dual channel. Up to 16 slots can be used.
If a slot is empty, the special empty keyword can be used. This will generate
an APCB with an empty SPD.

```
APCB_SOURCES = hynix-HMA851S6CJR6N-VK_x1 # 0b0000
APCB_SOURCES += hynix-HMAA1GS6CMR6N-VK_x2 # 0b0001
APCB_SOURCES += empty # 0b0010
APCB_SOURCES += samsung-K4A8G165WC-BCWE_x1 # 0b0011
```

#### APCB Board ID GPIO configuration.
The GPIOs determine which memory SPD will be used during boot.
```
# APCB_BOARD_ID_GPIO[0-3] = GPIO_NUMBER GPIO_IO_MUX GPIO_BANK_CTL
# GPIO_NUMBER: FCH GPIO number
# GPIO_IO_MUX: Value write to IOMUX to configure this GPIO
# GPIO_BANK_CTL: Value write to GPIOBankCtl[23:16] to configure this GPIO
APCB_BOARD_ID_GPIO0 = 121 1 0
APCB_BOARD_ID_GPIO1 = 120 1 0
APCB_BOARD_ID_GPIO2 = 131 3 0
APCB_BOARD_ID_GPIO3 = 116 1 0
```

## Footnotes

1. *AMD Platform Security Processor BIOS Architecture Design Guide
Expand Down
319 changes: 319 additions & 0 deletions Documentation/technotes/2020-03-unit-testing-coreboot.md
View file
@@ -0,0 +1,319 @@
# Unit testing coreboot

## Preface
First part of this document, Introduction, comprises disambiguation for what
unit testing is and what is not. This definition will be a basis for the whole
paper.

Next, Rationale, explains why to use unit testing and how coreboot specifically
may benefit from it.

This is followed by evaluation of different available free C unit test
frameworks. Firstly, collection of requirements is provided. Secondly, there is
a description of a few selected candidates. Finally, requirements are applied to
candidates to see if they might be a good fit.

Fourth part is a summary of evaluation, with proposal of unit test framework
for coreboot to be used.

Finally, Implementation proposal paragraph touches how build system and coreboot
codebase in general should be organized, in order to support unit testing. This
comprises couple of design considerations which need to be addressed.

## Introduction
A unit test is supposed to test a single unit of code in isolation. In C
language (in contrary to OOP) unit usually means a function. One may also
consider unit under test to be a single compilation unit which exposes some
API (set of functions). A function, talking to some external component can be
tested if this component can be mocked out.

In other words (looking from C compilation angle), there should be no extra
dependencies (executables) required beside unit under test and test harness in
order to compile unit test binary. Test harness, beside code examining a
routines, may comprise test framework implementation.

It is hard to apply this strict definition of unit test to firmware code in
practice, mostly due to constraints on speed of execution and size of final
executable. coreboot codebase often cannot be adjusted to be testable. Because
of this, coreboot unit testing subsystem should allow to include some additional
source object files beside unit under test. That being said, the default and
goal wherever possible, should be to isolate unit under test from other parts.

Unit testing is not an integration testing and it doesn't replace it. First of
all, integration tests cover larger set of components and interactions between
them. Positive integration test result gives more confidence than a positive
unit test does. Furthermore, unit tests are running on the build machine, while
integration tests usually are executed on the target (or simulator).

## Rationale
Considering above, what is the benefit of unit testing, especially keeping in
mind that coreboot is low-level firmware? Unit tests should be quick, thus may
be executed frequently during development process. It is much easier to build
and run a unit test on a build machine, than any integration test. This in turn
may be used by dev to gather extra confidence early during code development
process. Actually developer may even write unit tests earlier than the code -
see [TDD](https://en.wikipedia.org/wiki/Test-driven_development) concept.

That being said, unit testing embedded C code is a difficult task, due to
significant amount of dependencies on underlying hardware. Mocking can handle
some hardware dependencies. However, complex mocks make the unit test
susceptible to failing and can require significant development effort.

Writing unit tests for a code (both new and currently existing) may be favorable
for the code quality. It is not only about finding bugs, but in general - easily
testable code is a good code.

coreboot benefits the most from testing common libraries (lib/, commonlib/,
payloads/libpayload) and coreboot infrastructure (console/, device/, security/).

## Evaluation of unit testing frameworks

### Requirements
Requirements for unit testing frameworks:

* Easy to use
* Few dependencies

Standard C library is all we should need

* Isolation between tests
* Support for mocking
* Support for some machine parsable output
* Compiler similarity

Compiler for the host _must_ support the same language standards as the target
compiler. Ideally the same toolchain should be used for building firmware
executables and test binaries, however the host complier will be used to build
unit tests, whereas the coreboot toolchain will be used for building the
firmware executables. For some targets, the host compiler and the target
compiler could be the same, but this is not a requirement.

* Same language for tests and code

Unit tests will be written in C, because coreboot code is also written in C

### Desirables

* Easy to integrate with build system/build tools

Ideally JUnit-like XML output format for Jenkins

* Popularity is a plus

We want a larger community for a couple of reasons. Firstly, easier access to
people with knowledge and tutorials. Secondly, bug fixes for the top of tree
are more frequent and known issues are usually shorter in the pending state.
Last but not least, larger reviewer pool means better and easier upstream
improvements that we would like to submit.

* Extra features may be a plus
* Compatible license

This should not be a blocker, since test binaries are not distributed.
However ideally compatible with GPL.

* IDE integration

### Candidates
There is a lot of frameworks which allow unit testing C code
([list](https://en.wikipedia.org/wiki/List_of_unit_testing_frameworks#C) from
Wikipedia). While not all of them were evaluated, because that would take an
excessive amount of time, couple of them were selected based on the good
opinions among C devs, popularity and fitting above criteria.

* [SputUnit](https://www.use-strict.de/sput-unit-testing/)
* [GoogleTest](https://github.com/google/googletest)
* [Cmocka](https://cmocka.org/)
* [Unity](http://www.throwtheswitch.org/unity) (CMock, Ceedling)

We looked at several other test frameworks, but decided not to do a full evaluation
for various reasons such as functionality, size of the developer community, or
compatibility.

### Evaluation
* [SputUnit](https://www.use-strict.de/sput-unit-testing/)
* Pros
* No dependencies, one header file to include - that’s all
* Pure C
* Very easy to use
* BSD license
* Cons
* Main repo doesn’t have support for generating JUnit XML reports for
Jenkins to consume - this feature is available only on the fork from
SputUnit called “Sput_report”. It makes it niche in a niche, so there are
some reservations whether support for this will be satisfactory
* No support for mocks
* Not too popular
* No automatic test registration
* [GoogleTest](https://github.com/google/googletest)
* Pros
* Automatic test registration
* Support for different output formats (including XML for Jenkins)
* Good support, widely used, the biggest and the most active community out
of all frameworks that were investigated
* Available as a package in the most common distributions
* Test fixtures easily available
* Well documented
* Easy to integrate with an IDE
* BSD license
* Cons
* Requires C++11 compiler
* To make most out of it (use GMock) C++ knowledge is required
* [Cmocka](https://cmocka.org/)
* Pros
* Self-contained, autonomous framework
* Pure C
* API is well documented
* Multiple output formats (including XML for Jenkins)
* Available as a package in the most common distributions
* Used in some popular open source projects (libssh, OpenVPN, Samba)
* Test fixtures available
* Support for exception handling
* Cons
* No automatic test registration
* It will require some effort to make it work from within an IDE
* Apache 2.0 license (not compatible with GPLv2)
* [Unity](http://www.throwtheswitch.org/unity) (CMock, Ceedling)
* Pros
* Pure C (Unity testing framework itself, not test runner)
* Support for different output formats (including XML for Jenkins)
* There are some (rather easy) hints how to use this from an IDE (e.g. Eclipse)
* MIT license
* Cons
* Test runner (Ceedling) is not written in C - uses Ruby
* Mocking/Exception handling functionalities are actually separate tools
* No automatic test registration
* Not too popular

### Summary & framework proposal
After research, we propose using the Cmocka unit test framework. Cmocka fulfills
all stated evaluation criteria. It is rather easy to use, doesn’t have extra
dependencies, written fully in C, allows for tests fixtures and some popular
open source projects already are using it. Cmocka also includes support for
mocks.

Cmocka's limitations, such as the lack of automatic test registration, are
considered minor issues that will require only minimal additional work from a
developer. At the same time, it may be worth to propose improvement to Cmocka
community or simply apply some extra wrapper with demanded functionality.

## Implementation

### Framework as a submodule or external package
Unit test frameworks may be either compiled from source (from a git submodule
under 3rdparty/) or pre-compiled as a package. The second option seems to be
easier to maintain, while at the same time may bring some unwanted consequences
(different version across distributions, frequent changes in API). It makes sense
to initially experiment with packages and check how it works. If this will
cause any issues, then it is always possible to switch to submodule approach.

### Integration with build system
To get the most out of unit testing framework, it should be integrated with
Jenkins automation server. Verification of all unit tests for new changes may
improve code reliability to some extent.

### Build configuration (Kconfig)
While building unit under test object file, it is necessary to apply some
configuration (config) just like when building usual firmware. For simplicity,
there will be one default tests .config `qemu_x86_i440fx` for all unit tests. At
the same time, some tests may require running with different values of particular
config. This should be handled by adding extra header, included after config.h.
This header will comprise #undef of old CONFIG values and #define of the
required value. When unit testing will be integrated with Jenkins, it may be
preferred to use every available config for periodic builds.

### Directory structure
Tests should be kept separate from the code, while at the same time it must be
easy to match code with test harness.

We create new directory for test files ($(toplevel)/tests/) and mimic the
structure of src/ directory.

Test object files (test harness, unit under tests and any additional executables
are stored under build/tests/<test_name> directory.

Below example shows how directory structure is organized for the two test cases:
tests/lib/string-test and tests/device/i2c-test:

```bash
├── src
│ ├── lib
│ │ ├── string.c <- unit under test
│ │
│ ├── device
│ ├── i2c.c
│
├── tests
│ ├── include
│ │ ├── mocks <- mock headers, which replace original headers
│ │
│ ├── Makefile.inc <- top Makefile for unit tests subsystem
│ ├── lib
│ │ ├── Makefile.inc
│ │ ├── string-test.c <- test code for src/lib/string.c
│ │ │
│ ├── device
│ │ ├── Makefile.inc
│ ├── i2c-test.c
│
├── build
│ ├── tests <-all test-related executables
├── config.h <- default config used for tests builds
├── lib
│ ├── string-test <- all string-test executables
│ │ ├── run <- final test binary
│ │ ├── tests <- all test harness executables
│ │ ├── lib
│ │ ├── string-test.o <-test harness executable
│ │ ├── src <- unit under test and other src executables
│ │ ├── lib
│ │ ├── string.o <- unit under test executable
├── device
├── i2c-test
├── run
├── tests
│ ├── device
│ ├── i2c-test.o
├── src
├── device
├── i2c.o
```

### Adding new tests
For purpose of this description, let's assume that we want to add a new unit test
for src/device/i2c.c module. Since this module is rather simple, it will be enough
to have only one test module.

Firstly (assuming there is no tests/device/Makefile.inc file) we need to create
Makefile.inc in main unit test module directory. Inside this Makefile.inc, one
need to register new test and can specify multiple different attributes for it.

```bash
# Register new test, by adding its name to tests variable
tests-y += i2c-test

# All attributes are defined by <test_name>-<attribute> variables
# <test_name>-srcs is used to register all input files (test harness, unit under
# test and others) for this particular test. Remember to add relative paths.
i2c-test-srcs += tests/device/i2c-test.c
i2c-test-srcs += src/device/i2c.c

# We can define extra cflags for this particular test
i2c-test-cflags += -DSOME_DEFINE=1

# For mocking out external dependencies (functions which cannot be resolved by
# linker), it is possible to register a mock function. To register new mock, it
# is enough to add function-to-be-mocked name to <test_name>-mocks variable.
i2c-test-mocks += platform_i2c_transfer

# Similar to coreboot concept, unit tests also runs in the context of stages.
# By default all unit tests are compiled to be ramstage executables. If one want
# to overwrite this setting, there is <test_name>-stage variable available.
i2c-test-stage:= bootblock
```

### Writing new tests
Full description of how to write unit tests and Cmocka API description is out of
the scope of this document. There are other documents related to this
[Cmocka API](https://api.cmocka.org/) and
[Mocks](https://lwn.net/Articles/558106/).
1 change: 1 addition & 0 deletions Documentation/technotes/index.md
View file
Expand Up @@ -2,3 +2,4 @@

* [Dealing with Untrusted Input in SMM](2017-02-dealing-with-untrusted-input-in-smm.md)
* [Rebuilding coreboot image generation](2015-11-rebuilding-coreboot-image-generation.md)
* [Unit testing coreboot](2020-03-unit-testing-coreboot.md)
91 changes: 91 additions & 0 deletions LICENSES/retained-copyrights.txt
View file
@@ -0,0 +1,91 @@
Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
Copyright 2006-2012 Red Hat, Inc.
Copyright © 2006 Intel Corporation
Copyright 2010, Google Inc.
Copyright 2012, Google Inc.
Copyright © 2012 Intel Corporation
Copyright 2012 Red Hat Inc.
Copyright 2013 Google Inc.
Copyright 2014 Google Inc.
Copyright 2014 The Chromium OS Authors. All rights reserved.
Copyright 2015 Google Inc.
Copyright 2015, Google Inc.
Copyright 2016 Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Copyright 2016 The Chromium OS Authors. All rights reserved.
Copyright 2017-2019 Eltan B.V.
Copyright 2017 Google Inc.
Copyright 2018 Generated Code
Copyright 2018-present Facebook, Inc.
Copyright 2019 9Elements Agency GmbH <patrick.rudolph@9elements.com>
Copyright 2019 The Chromium OS Authors. All rights reserved.
Copyright (C) 2002 David S. Peterson. All rights reserved.
Copyright (c) 2003-2016 Cavium Inc. (support@cavium.com). All rights
Copyright (c) 2003-2017 Cavium Inc. (support@cavium.com). All rights
Copyright (c) 2004, 2008 IBM Corporation
Copyright (c) 2005 ASPEED Technology Inc.
Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2008, 2009 Pattrick Hueper <phueper@hueper.net>
Copyright (C) 2008 Advanced Micro Devices, Inc.
Copyright (c) 2008, Google Inc.
Copyright (C) 2008 Jordan Crouse <jordan@cosmicpenguin.net>
Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
Copyright (C) 2009-2010 coresystems GmbH
Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
Copyright (c) 2010-2017, The Regents of the University of California
Copyright (c) 2010, Code Aurora Forum. All rights reserved.
Copyright (C) 2010 coresystems GmbH
Copyright (c) 2010 Per Odlund <per.odlund@armagedon.se>
Copyright (c) 2010 The Chromium OS Authors. All rights reserved.
Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
Copyright (c) 2011-2012 The Linux Foundation. All rights reserved.
Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
Copyright (c) 2011 - 2014 The Linux Foundation. All rights reserved.
Copyright (c) 2011-2019 The Linux Foundation. All rights reserved.
Copyright (c) 2011, Google Inc.
Copyright (C) 2011 secunet Security Networks AG
Copyright (c) 2012 - 2013, 2015, 2019 The Linux Foundation.
Copyright (c) 2012 - 2013, 2015 The Linux Foundation. All rights reserved.
Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved.
Copyright (c) 2012-2013 The Linux Foundation. All rights reserved.
Copyright (c) 2012, 2016-2017 Advanced Micro Devices, Inc.
Copyright (c) 2012, 2016-2019 Advanced Micro Devices, Inc.
Copyright (c) 2012-2019 The Linux Foundation. All rights reserved.
Copyright (c) 2012-2019 The Linux Foundation. All rights reserved.*
Copyright (c) 2012, Code Aurora Forum. All rights reserved.
Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
Copyright (c) 2012 The Linux Foundation. All rights reserved.
Copyright (c) 2012 The Linux Foundation. All rights reserved.*
Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Copyright (c) 2013-2015 Intel Corporation.
Copyright (c) 2013-2017 Intel Corporation.
Copyright (C) 2013 Google Inc.
Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
Copyright (c) 2013 The Linux Foundation. All rights reserved.
Copyright (c) 2013, The Regents of the University of California (Regents).
Copyright (C) 2014 - 2015, 2019 The Linux Foundation. All rights reserved.
Copyright (C) 2014 - 2015 The Linux Foundation. All rights reserved.
Copyright (C) 2014 - 2016, 2019 The Linux Foundation. All rights reserved.
Copyright (C) 2014 - 2016 The Linux Foundation. All rights reserved.
Copyright (c) 2014 Google Inc.
Copyright (C) 2014 Google Inc.
Copyright (c) 2014 Google Inc. All rights reserved.
Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
Copyright (C) 2014 The Linux Foundation. All rights reserved.
Copyright (C) 2015-2016 Intel Corporation.
Copyright (C) 2015-2016, Intel Corporation
Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
Copyright (C) 2015 Google Inc.
Copyright (c) 2015, Intel Corporation. All rights reserved.
Copyright (c) 2015 The Chromium OS Authors. All rights reserved.
Copyright (C) 2015 The Linux Foundation. All rights reserved.
Copyright (c) 2015, The Linux Foundation. All rights reserved.
Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
Copyright (c) 2016, 2018, The Linux Foundation. All rights reserved.
Copyright (C) 2016 Google Inc.
Copyright (c) 2016, The Regents of the University of California (Regents).
Copyright (C) 2018-2019 Eltan B.V.
Copyright (C) 2018 - 2019 The Linux Foundation. All rights reserved.
Copyright (c) 2018 Eltan B.V.
Copyright (c) 2018, HardenedLinux.
Copyright (C) 2018, The Linux Foundation. All rights reserved.
Copyright Dave Airlie <airlied@redhat.com>
10 changes: 10 additions & 0 deletions MAINTAINERS
View file
Expand Up @@ -362,6 +362,16 @@ M: Wim Vervoorn <wvervoorn@eltan.com>
S: Maintained
F: src/mainboard/facebook/monolith/

OCP TIOGAPASS MAINBOARD
M: Jonathan Zhang <jonzhang@fb.com>
M: Reddy Chagam <anjaneya.chagam@intel.com>
M: Johnny Lin <Johnny_Lin@wiwynn.com>
M: Morgan Jang <Morgan_Jang@wiwynn.com>
M: Ryback Hung <<Ryback.Hung@quantatw.com>
M: Bryant Ou <Bryant.Ou@quantatw.com>
S: Maintained
F: src/mainboard/ocp/tiogapass

PORTWELL PQ-M107 MAINBOARD
M: Frans Hendriks <fhendriks@eltan.com>
M: Wim Vervoorn <wvervoorn@eltan.com>
Expand Down
51 changes: 20 additions & 31 deletions Makefile
View file
@@ -1,34 +1,4 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2008 Advanced Micro Devices, Inc.
## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
## Copyright (C) 2009-2010 coresystems GmbH
## Copyright (C) 2011 secunet Security Networks AG
##
## Redistribution and use in source and binary forms, with or without
## modification, are permitted provided that the following conditions
## are met:
## 1. Redistributions of source code must retain the above copyright
## notice, this list of conditions and the following disclaimer.
## 2. Redistributions in binary form must reproduce the above copyright
## notice, this list of conditions and the following disclaimer in the
## documentation and/or other materials provided with the distribution.
## 3. The name of the author may not be used to endorse or promote products
## derived from this software without specific prior written permission.
##
## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
## SUCH DAMAGE.
##
## SPDX-License-Identifier: BSD-3-Clause

ifneq ($(words $(CURDIR)),1)
$(error Error: Path to the main directory cannot contain spaces)
Expand Down Expand Up @@ -141,6 +111,14 @@ NOMKDIR:=1
endif
endif

ifneq ($(filter %-test %-tests,$(MAKECMDGOALS)),)
ifneq ($(filter-out %-test %-tests, $(MAKECMDGOALS)),)
$(error Cannot mix unit-tests targets with other targets)
endif
UNIT_TEST:=1
NOCOMPILE:=
endif

.xcompile: util/xcompile/xcompile
rm -f $@
$< $(XGCCPATH) > $@.tmp
Expand All @@ -159,7 +137,9 @@ real-all:
@exit 1
else

ifneq ($(UNIT_TEST),1)
include $(DOTCONFIG)
endif

# in addition to the dependency below, create the file if it doesn't exist
# to silence stupid warnings about a file that would be generated anyway.
Expand All @@ -177,7 +157,9 @@ ifneq ($(CONFIG_MMX),y)
CFLAGS_x86_32 += -mno-mmx
endif

ifneq ($(UNIT_TEST),1)
include toolchain.inc
endif

strip_quotes = $(strip $(subst ",,$(subst \",,$(1))))
# fix makefile syntax highlighting after strip macro \" "))
Expand Down Expand Up @@ -276,7 +258,14 @@ evaluate_subdirs= \
# collect all object files eligible for building
subdirs:=$(TOPLEVEL)
postinclude-hooks :=

# Don't iterate through Makefile.incs under src/ when building tests
ifneq ($(UNIT_TEST),1)
$(eval $(call evaluate_subdirs))
else
include $(TOPLEVEL)/tests/Makefile.inc
endif

ifeq ($(FAILBUILD),1)
$(error cannot continue build)
endif
Expand Down
28 changes: 14 additions & 14 deletions Makefile.inc
View file
@@ -1,17 +1,4 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2011 secunet Security Networks AG
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
# SPDX-License-Identifier: GPL-2.0-only

ifneq ($(NOCOMPILE),1)
GIT:=$(shell git -C "$(top)" rev-parse --git-dir 1>/dev/null 2>&1 \
Expand Down Expand Up @@ -575,6 +562,8 @@ $(AMDFWTOOL): $(top)/util/amdfwtool/amdfwtool.c
@printf " HOSTCC $(subst $(obj)/,,$(@))\n"
$(HOSTCC) $(HOSTCFLAGS) -DCONFIG_ROM_SIZE=$(CONFIG_ROM_SIZE) -o $@ $<

APCB_EDIT_TOOL:=$(top)/util/apcb/apcb_edit.py

CBOOTIMAGE:=$(objutil)/cbootimage/cbootimage

FUTILITY?=$(objutil)/futility/futility
Expand Down Expand Up @@ -609,6 +598,17 @@ bootblock-y+=$(DEVICETREE_STATIC_C)
postcar-y+=$(DEVICETREE_STATIC_C)
smm-y+=$(DEVICETREE_STATIC_C)

# Ensure static.c and static.h are created before any objects are compiled
ramstage-c-deps+=$(DEVICETREE_STATIC_C)
romstage-c-deps+=$(DEVICETREE_STATIC_C)
verstage-c-deps+=$(DEVICETREE_STATIC_C)
bootblock-c-deps+=$(DEVICETREE_STATIC_C)
postcar-c-deps+=$(DEVICETREE_STATIC_C)
smm-c-deps+=$(DEVICETREE_STATIC_C)

.PHONY: devicetree
devicetree: $(DEVICETREE_STATIC_C)

#######################################################################
# Clean up rules
clean-abuild:
Expand Down
9 changes: 9 additions & 0 deletions configs/config.dell_optiplex_9010_sff
View file
@@ -0,0 +1,9 @@
CONFIG_USE_OPTION_TABLE=y
CONFIG_USE_BLOBS=y
CONFIG_VENDOR_DELL=y
CONFIG_ONBOARD_VGA_IS_PRIMARY=y
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PCIEXP_CLK_PM=y
CONFIG_SEABIOS_PS2_TIMEOUT=3000
CONFIG_POST_DEVICE_LPC=y
CONFIG_HAVE_EM100_SUPPORT=y
4 changes: 2 additions & 2 deletions configs/config.pcengines_apu1
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.11.0.6"
CONFIG_LOCALVERSION="v4.12.0.1"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_NO_GFX_INIT=y
Expand All @@ -17,6 +17,6 @@ CONFIG_PXE_SCRIPT="payloads/external/iPXE/menu.ipxe"
CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
CONFIG_MEMTEST_REVISION=y
CONFIG_MEMTEST_REVISION_ID="3754fd440f4009b62244e0f95c56bbb12c2fffcb"
CONFIG_MEMTEST_REVISION_ID="0b756257276729c1a12bc1d95e7a1f044894bda2"
CONFIG_SORTBOOTORDER_REVISION=y
CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.18"
4 changes: 2 additions & 2 deletions configs/config.pcengines_apu2
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.11.0.6"
CONFIG_LOCALVERSION="v4.12.0.1"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU2=y
Expand All @@ -19,6 +19,6 @@ CONFIG_PXE_SCRIPT="payloads/external/iPXE/menu.ipxe"
CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
CONFIG_MEMTEST_REVISION=y
CONFIG_MEMTEST_REVISION_ID="0bd34c22604660e4283316331f3e7bf8a3863753"
CONFIG_MEMTEST_REVISION_ID="0b756257276729c1a12bc1d95e7a1f044894bda2"
CONFIG_SORTBOOTORDER_REVISION=y
CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.18"
4 changes: 2 additions & 2 deletions configs/config.pcengines_apu3
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.11.0.6"
CONFIG_LOCALVERSION="v4.12.0.1"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU3=y
Expand All @@ -18,6 +18,6 @@ CONFIG_PXE_SCRIPT="payloads/external/iPXE/menu.ipxe"
CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
CONFIG_MEMTEST_REVISION=y
CONFIG_MEMTEST_REVISION_ID="0bd34c22604660e4283316331f3e7bf8a3863753"
CONFIG_MEMTEST_REVISION_ID="0b756257276729c1a12bc1d95e7a1f044894bda2"
CONFIG_SORTBOOTORDER_REVISION=y
CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.18"
4 changes: 2 additions & 2 deletions configs/config.pcengines_apu4
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.11.0.6"
CONFIG_LOCALVERSION="v4.12.0.1"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU4=y
Expand All @@ -18,6 +18,6 @@ CONFIG_PXE_SCRIPT="payloads/external/iPXE/menu.ipxe"
CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
CONFIG_MEMTEST_REVISION=y
CONFIG_MEMTEST_REVISION_ID="0bd34c22604660e4283316331f3e7bf8a3863753"
CONFIG_MEMTEST_REVISION_ID="0b756257276729c1a12bc1d95e7a1f044894bda2"
CONFIG_SORTBOOTORDER_REVISION=y
CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.18"
4 changes: 2 additions & 2 deletions configs/config.pcengines_apu5
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.11.0.6"
CONFIG_LOCALVERSION="v4.12.0.1"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU5=y
Expand All @@ -19,6 +19,6 @@ CONFIG_PXE_SCRIPT="payloads/external/iPXE/menu.ipxe"
CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
CONFIG_MEMTEST_REVISION=y
CONFIG_MEMTEST_REVISION_ID="0bd34c22604660e4283316331f3e7bf8a3863753"
CONFIG_MEMTEST_REVISION_ID="0b756257276729c1a12bc1d95e7a1f044894bda2"
CONFIG_SORTBOOTORDER_REVISION=y
CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.18"
13 changes: 1 addition & 12 deletions gnat.adc
View file
@@ -1,15 +1,4 @@
--
-- This file is part of the coreboot project.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; version 2 of the License.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- SPDX-License-Identifier: GPL-2.0-only

pragma Restrictions (No_Access_Subprograms);
pragma Restrictions (No_Allocators);
Expand Down
11 changes: 1 addition & 10 deletions payloads/Makefile.inc
View file
@@ -1,17 +1,8 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2016 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## SPDX-License-Identifier: GPL-2.0-only

cbfs-files-$(CONFIG_COREINFO_SECONDARY_PAYLOAD) += img/coreinfo
img/coreinfo-file := payloads/coreinfo/build/coreinfo.elf
Expand Down
12 changes: 1 addition & 11 deletions payloads/coreinfo/Kconfig
View file
@@ -1,19 +1,9 @@
##
## This file is part of the coreinfo project.
##
## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## SPDX-License-Identifier: GPL-2.0-only

#
# For a description of the syntax of this configuration file,
# see http://lxr.linux.no/source/Documentation/kbuild/kconfig-language.txt.
#
Expand Down
11 changes: 1 addition & 10 deletions payloads/coreinfo/Makefile
View file
@@ -1,18 +1,9 @@
##
## This file is part of the coreinfo project.
##
## Copyright (C) 2008 Advanced Micro Devices, Inc.
## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## SPDX-License-Identifier: GPL-2.0-only

src := $(CURDIR)
srctree := $(src)
Expand Down
1 change: 0 additions & 1 deletion payloads/coreinfo/bootlog_module.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the coreinfo project.
*
* Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
*
Expand Down
1 change: 0 additions & 1 deletion payloads/coreinfo/cbfs_module.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the coreinfo project.
*
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
*
Expand Down
1 change: 0 additions & 1 deletion payloads/coreinfo/coreboot_module.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the coreinfo project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
Expand Down
1 change: 0 additions & 1 deletion payloads/coreinfo/coreinfo.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the coreinfo project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
Expand Down
1 change: 0 additions & 1 deletion payloads/coreinfo/coreinfo.h
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the coreinfo project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
Expand Down
1 change: 0 additions & 1 deletion payloads/coreinfo/cpuid.S
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the coreinfo project.
*
* It is derived from the x86info project, which is GPLv2-licensed.
*
Expand Down
1 change: 0 additions & 1 deletion payloads/coreinfo/cpuinfo_module.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the coreinfo project.
*
* It is derived from the x86info project, which is GPLv2-licensed.
*
Expand Down
1 change: 0 additions & 1 deletion payloads/coreinfo/multiboot_module.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the coreinfo project.
*
* Copyright (C) 2008 Jordan Crouse <jordan@cosmicpenguin.net>
*
Expand Down
1 change: 0 additions & 1 deletion payloads/coreinfo/nvram_module.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the coreinfo project.
*
* Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
*
Expand Down
1 change: 0 additions & 1 deletion payloads/coreinfo/pci_module.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the coreinfo project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
Expand Down
1 change: 0 additions & 1 deletion payloads/coreinfo/ramdump_module.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the coreinfo project.
*
* Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
*
Expand Down
1 change: 0 additions & 1 deletion payloads/coreinfo/timestamps_module.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the coreinfo project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
Expand Down
7 changes: 4 additions & 3 deletions payloads/external/GRUB2/Makefile
View file
Expand Up @@ -17,12 +17,13 @@ checkout:
echo " GIT GRUB2 $(NAME-y)"
test -d $(project_dir) || git clone $(project_git_repo) $(project_dir)
git -C $(project_dir) fetch
ifeq ("$(shell test -d $(project_dir) && \
(git -C $(project_dir) status --ignored=no --untracked-files=no --porcelain))",)
ifeq ($(shell test -d $(project_dir) && \
(git -C $(project_dir) status --ignored=no --untracked-files=no --porcelain)),)
git -C $(project_dir) checkout -f $(TAG-y)
else
echo "WARNING: index/tree not clean, skipping update / force checkout."
echo " Checkout manually with `git -C $(project_dir) checkout -f`."
echo " Checkout manually with "\
"\`git -C payloads/external/GRUB2/$(project_dir) checkout -f\`."
endif

grub2/build/config.h: $(CONFIG_DEP) | checkout
Expand Down
11 changes: 1 addition & 10 deletions payloads/external/LinuxBoot/Kconfig
View file
@@ -1,17 +1,8 @@
## This file is part of the coreboot project.
##
## Copyright (C) 2017 Facebook Inc.
## Copyright (C) 2018 9elements Cyber Security
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## SPDX-License-Identifier: GPL-2.0-only

if PAYLOAD_LINUXBOOT

Expand Down
11 changes: 1 addition & 10 deletions payloads/external/LinuxBoot/Kconfig.name
View file
@@ -1,16 +1,7 @@
## This file is part of the coreboot project.
##
## Copyright (C) 2017 Facebook Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## SPDX-License-Identifier: GPL-2.0-only

config PAYLOAD_LINUXBOOT
bool "LinuxBoot"
Expand Down
11 changes: 1 addition & 10 deletions payloads/external/LinuxBoot/Makefile
View file
@@ -1,17 +1,8 @@
## This file is part of the coreboot project.
##
## Copyright (C) 2017 Facebook Inc.
## Copyright (C) 2018 9elements Cyber Security
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## SPDX-License-Identifier: GPL-2.0-only

project_dir=linuxboot
kernel_dir=$(project_dir)/kernel
Expand Down
12 changes: 2 additions & 10 deletions payloads/external/LinuxBoot/targets/linux.mk
View file
@@ -1,17 +1,9 @@
## This file is part of the coreboot project.
##
## Copyright (C) 2017 Facebook Inc.
## Copyright (C) 2018 9elements Cyber Security
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## SPDX-License-Identifier: GPL-2.0-only

SHELL := /bin/bash

ARCH-$(CONFIG_LINUXBOOT_X86_64)=x86_64
Expand Down
11 changes: 1 addition & 10 deletions payloads/external/LinuxBoot/targets/u-root.mk
View file
@@ -1,17 +1,8 @@
## This file is part of the coreboot project.
##
## Copyright (C) 2017 Facebook Inc.
## Copyright (C) 2018 9elements Cyber Security
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## SPDX-License-Identifier: GPL-2.0-only

project_dir=$(shell pwd)/linuxboot
go_path_dir=$(project_dir)/go
Expand Down
16 changes: 4 additions & 12 deletions payloads/external/Makefile.inc
View file
@@ -1,22 +1,12 @@
################################################################################
##
## This file is part of the coreboot project.
##
## Copyright (C) 2009-2010 coresystems GmbH
## Copyright (C) 2015 Google Inc.
## Copyright (C) 2017 Facebook Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## SPDX-License-Identifier: GPL-2.0-only

######################################################################
# set up payload config and version files for later inclusion
ifeq ($(CONFIG_PAYLOAD_SEABIOS),y)
PAYLOAD_CONFIG=payloads/external/SeaBIOS/seabios/.config
Expand Down Expand Up @@ -102,7 +92,8 @@ payloads/external/SeaBIOS/seabios/out/bios.bin.elf: $(DOTCONFIG)
CONFIG_SEABIOS_DEBUG_LEVEL=$(CONFIG_SEABIOS_DEBUG_LEVEL) \
CONFIG_DRIVERS_UART_8250MEM_32=$(CONFIG_DRIVERS_UART_8250MEM_32) \
CONFIG_ENABLE_HSUART=$(CONFIG_ENABLE_HSUART) \
CONFIG_CONSOLE_UART_BASE_ADDRESS=$(CONFIG_CONSOLE_UART_BASE_ADDRESS)
CONFIG_CONSOLE_UART_BASE_ADDRESS=$(CONFIG_CONSOLE_UART_BASE_ADDRESS) \
CONFIG_SEABIOS_HARDWARE_IRQ=$(CONFIG_SEABIOS_HARDWARE_IRQ)

payloads/external/SeaBIOS/seabios/out/vgabios.bin: payloads/external/SeaBIOS/seabios/out/bios.bin.elf
payloads/external/SeaBIOS/seabios/.config: payloads/external/SeaBIOS/seabios/out/bios.bin.elf
Expand Down Expand Up @@ -329,6 +320,7 @@ payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG) $(PXE_CONFIG_SCRIPT)
CONFIG_SCRIPT=$(PXE_CONFIG_SCRIPT) \
CONFIG_HAS_SCRIPT=$(CONFIG_PXE_ADD_SCRIPT) \
CONFIG_PXE_NO_PROMT=$(CONFIG_PXE_NO_PROMT) \
CONFIG_PXE_HAS_HTTPS=$(CONFIG_PXE_HAS_HTTPS) \
MFLAGS= MAKEFLAGS=

# LinuxBoot
Expand Down
11 changes: 1 addition & 10 deletions payloads/external/Memtest86Plus/Makefile
View file
@@ -1,17 +1,8 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2016 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## SPDX-License-Identifier: GPL-2.0-only

TAG-$(CONFIG_MEMTEST_MASTER)=origin/master
NAME-$(CONFIG_MEMTEST_MASTER)=Master
Expand Down
10 changes: 10 additions & 0 deletions payloads/external/SeaBIOS/Kconfig
View file
Expand Up @@ -51,6 +51,16 @@ config SEABIOS_THREAD_OPTIONROMS
variations during option ROM code execution. It is not
known if all option ROMs will behave properly with this option.

config SEABIOS_HARDWARE_IRQ
prompt "Hardware Interrupts"
default y
bool
help
Program and support hardware interrupts using the i8259
programmable interrupt controller (PIC). Deselected by
boards which would otherwise hang at the boot menu (eg,
google/rambi).

config SEABIOS_VGA_COREBOOT
prompt "Include generated option rom that implements legacy VGA BIOS compatibility"
default y if !VENDOR_EMULATION
Expand Down
3 changes: 3 additions & 0 deletions payloads/external/SeaBIOS/Makefile
View file
Expand Up @@ -72,6 +72,9 @@ endif
ifneq ($(CONFIG_SEABIOS_DEBUG_LEVEL),-1)
echo "CONFIG_DEBUG_LEVEL=$(CONFIG_SEABIOS_DEBUG_LEVEL)" >> seabios/.config
endif
ifneq ($(CONFIG_SEABIOS_HARDWARE_IRQ),y)
echo "# CONFIG_HARDWARE_IRQ is not set" >> seabios/.config
endif
# This shows how to force a previously set .config option *off*
# echo "# CONFIG_SMBIOS is not set" >> seabios/.config
$(MAKE) -C seabios olddefconfig OUT=out/
Expand Down
11 changes: 1 addition & 10 deletions payloads/external/U-Boot/Makefile
View file
@@ -1,17 +1,8 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2015 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## SPDX-License-Identifier: GPL-2.0-only

# 2019-4 tag
STABLE_COMMIT_ID=3c99166441bf3ea325af2da83cfe65430b49c066
Expand Down
11 changes: 1 addition & 10 deletions payloads/external/Yabits/Makefile
View file
@@ -1,17 +1,8 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2016 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## SPDX-License-Identifier: GPL-2.0-only

TAG-$(CONFIG_YABITS_MASTER)=origin/master
NAME-$(CONFIG_YABITS_MASTER)=Master
Expand Down
19 changes: 9 additions & 10 deletions payloads/external/iPXE/Kconfig
View file
@@ -1,15 +1,6 @@
##
## This file is part of the coreboot project.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## SPDX-License-Identifier: GPL-2.0-only

config PXE
prompt "Add a PXE ROM"
Expand Down Expand Up @@ -126,5 +117,13 @@ config PXE_SCRIPT
Uses the ipxe script instead showing the prompt:
"Press Ctrl-B to start iPXE..."

config PXE_HAS_HTTPS
bool "Enable HTTPS protocol"
default y
depends on BUILD_IPXE
help
Enable HTTPS protocol, which allows you to encrypt all communication
with a web server and to verify the server's identity

endmenu
endif
15 changes: 5 additions & 10 deletions payloads/external/iPXE/Makefile
View file
@@ -1,17 +1,8 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2016 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## SPDX-License-Identifier: GPL-2.0-only

# 2019.3 - Last commit of March 2019
# When updating, change the name both here and in payloads/external/iPXE/Kconfig
Expand Down Expand Up @@ -84,6 +75,10 @@ ifeq ($(CONFIG_PXE_NO_PROMT),y)
sed 's|#define\s*BANNER_TIMEOUT.*|#define BANNER_TIMEOUT 0|' "$(project_dir)/src/config/general.h" > "$(project_dir)/src/config/general.h.tmp"
mv "$(project_dir)/src/config/general.h.tmp" "$(project_dir)/src/config/general.h"
endif
ifeq ($(CONFIG_PXE_HAS_HTTPS),y)
sed 's|.*DOWNLOAD_PROTO_HTTPS|#define DOWNLOAD_PROTO_HTTPS|g' "$(project_dir)/src/config/general.h" > "$(project_dir)/src/config/general.h.tmp"
mv "$(project_dir)/src/config/general.h.tmp" "$(project_dir)/src/config/general.h"
endif

build: config $(CONFIG_SCRIPT)
ifeq ($(CONFIG_HAS_SCRIPT),y)
Expand Down
2 changes: 0 additions & 2 deletions payloads/external/tianocore/Kconfig
View file
Expand Up @@ -83,7 +83,6 @@ config TIANOCORE_USE_8254_TIMER

config TIANOCORE_BOOTSPLASH_IMAGE
bool "Use a custom bootsplash image"
depends on TIANOCORE_COREBOOTPAYLOAD
help
Select this option if you have a bootsplash image that you would
like to be used. If this option is not selected, the default
Expand All @@ -92,7 +91,6 @@ config TIANOCORE_BOOTSPLASH_IMAGE
config TIANOCORE_BOOTSPLASH_FILE
string "Tianocore Bootsplash path and filename"
depends on TIANOCORE_BOOTSPLASH_IMAGE
depends on TIANOCORE_COREBOOTPAYLOAD
default "bootsplash.bmp"
help
The path and filename of the file to use as graphical bootsplash
Expand Down
26 changes: 10 additions & 16 deletions payloads/external/tianocore/Makefile
View file
@@ -1,17 +1,8 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2017 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## SPDX-License-Identifier: GPL-2.0-only

# force the shell to bash - the edksetup.sh script doesn't work with dash
export SHELL := env bash
Expand All @@ -25,10 +16,12 @@ upstream_git_repo=https://github.com/tianocore/edk2
# STABLE revision is 3mdeb's coreboot uefi (coreboot-4.7.x-uefi) branch
ifeq ($(CONFIG_TIANOCORE_UEFIPAYLOAD),y)
bootloader=UefiPayloadPkg
logo_pkg=MdeModulePkg
build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_MMCONF_BASE_ADDRESS) -DPS2_KEYBOARD_ENABLE
TAG=upstream/master
else
bootloader=CorebootPayloadPkg
logo_pkg=CorebootPayloadPkg
# STABLE revision is MrChromebox's coreboot framebuffer (coreboot_fb) branch
TAG=$(CONFIG_TIANOCORE_REVISION_ID)
endif
Expand Down Expand Up @@ -67,12 +60,13 @@ update: $(project_dir)
echo " $(TAG) is not a valid git reference"; \
exit 1; \
fi; \
if git describe --all --dirty | grep -qv dirty; then \
if git status --ignore-submodules=dirty | grep -qv clean; then \
echo " Checking out $(project_name) revision $(TAG)"; \
git checkout --detach $(TAG); \
else \
echo " Working directory not clean; will not overwrite"; \
fi
fi; \
git submodule update --init --recursive

checktools:
echo "Checking uuid-dev..."
Expand All @@ -88,13 +82,13 @@ checktools:
build: update checktools
unset CC; $(MAKE) -C $(project_dir)/BaseTools
echo " build $(project_name) $(TAG)"
if [ -n $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) ]; then \
if [ -n "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" ]; then \
echo " Copying custom bootsplash image"; \
case "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" in \
/*) cp $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
$(project_dir)/CorebootPayloadPkg/Logo/Logo.bmp;; \
$(project_dir)/$(logo_pkg)/Logo/Logo.bmp;; \
*) cp $(top)/$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
$(project_dir)/CorebootPayloadPkg/Logo/Logo.bmp;; \
$(project_dir)/$(logo_pkg)/Logo/Logo.bmp;; \
esac \
fi; \
cd $(project_dir); \
Expand All @@ -107,7 +101,7 @@ build: update checktools
fi; \
build $(BUILD_STR); \
mv $(project_dir)/Build/$(bootloader)*/*/FV/UEFIPAYLOAD.fd $(project_dir)/Build/UEFIPAYLOAD.fd; \
git checkout CorebootPayloadPkg/Logo/Logo.bmp > /dev/null 2>&1 || true
git checkout $(logo_pkg)/Logo/Logo.bmp > /dev/null 2>&1 || true

clean:
test -d $(project_dir) && (cd $(project_dir); rm -rf Build; rm -f Conf/tools_def.txt) || exit 0
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1 change: 0 additions & 1 deletion payloads/libpayload/Kconfig
View file
@@ -1,5 +1,4 @@
##
## This file is part of the libpayload project.
##
## Copyright (C) 2008 Advanced Micro Devices, Inc.
## Copyright (C) 2008 coresystems GmbH
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1 change: 0 additions & 1 deletion payloads/libpayload/Makefile
View file
@@ -1,5 +1,4 @@
##
## This file is part of the libpayload project.
##
## Copyright (C) 2008 Advanced Micro Devices, Inc.
## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
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1 change: 0 additions & 1 deletion payloads/libpayload/Makefile.inc
View file
@@ -1,5 +1,4 @@
##
## This file is part of the libpayload project.
##
## Copyright (C) 2008 Advanced Micro Devices, Inc.
## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm/Kconfig
View file
@@ -1,5 +1,4 @@
##
## This file is part of the libpayload project.
##
## Copyright (c) 2012 Google Inc.
##
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm/Makefile.inc
View file
@@ -1,5 +1,4 @@
##
## This file is part of the libpayload project.
##
## Copyright (C) 2008 Advanced Micro Devices, Inc.
##
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm/cache.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2013 Google Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm/coreboot.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
* Copyright (C) 2009 coresystems GmbH
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm/dummy_media.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2013 Google, Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm/eabi_compat.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2014 Google, Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm/exception.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright 2013 Google Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm/exception_asm.S
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright 2013 Google Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm/head.S
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm/libpayload.ldscript
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2013 Google, Inc.
* Copyright (C) 2008 Advanced Micro Devices, Inc.
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm/main.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm/sysinfo.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm/timer.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm/util.S
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2012 Google, Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm/virtual.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 coresystems GmbH
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm64/Kconfig
View file
@@ -1,5 +1,4 @@
##
## This file is part of the libpayload project.
##
## Copyright (c) 2012 Google Inc.
##
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm64/Makefile.inc
View file
@@ -1,5 +1,4 @@
##
## This file is part of the libpayload project.
##
## Copyright (C) 2008 Advanced Micro Devices, Inc.
##
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm64/cache.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2013 Google Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm64/coreboot.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
* Copyright (C) 2009 coresystems GmbH
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm64/dummy_media.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2013 Google, Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm64/exception.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright 2014 Google Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm64/exception_asm.S
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright 2014 Google Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm64/head.S
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm64/libpayload.ldscript
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2013 Google, Inc.
* Copyright (C) 2008 Advanced Micro Devices, Inc.
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm64/main.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm64/mmu.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm64/sysinfo.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm64/timer.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm64/util.S
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2012 Google, Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm64/virtual.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 coresystems GmbH
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/x86/Kconfig
View file
@@ -1,5 +1,4 @@
##
## This file is part of the libpayload project.
##
## Copyright (c) 2012 Google Inc.
##
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/x86/Makefile.inc
View file
@@ -1,5 +1,4 @@
##
## This file is part of the libpayload project.
##
## Copyright (C) 2008 Advanced Micro Devices, Inc.
##
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/x86/apic.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright 2018 Google LLC
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/x86/coreboot.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
* Copyright (C) 2009 coresystems GmbH
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/x86/delay.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2018 Google LLC
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/x86/exception.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright 2013 Google Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/x86/exception_asm.S
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright 2013 Google Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/x86/exec.S
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/x86/head.S
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
* Copyright (C) 2017 Patrick Rudolph <siro@das-labor.org>
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/x86/libpayload.ldscript
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/x86/main.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/x86/multiboot.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/x86/rom_media.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2013 Google, Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/x86/string.c
View file
@@ -1,6 +1,5 @@
/*
* Copyright (C) 1991,1992,1993,1997,1998,2003, 2005 Free Software Foundation, Inc.
* This file is part of the GNU C Library.
* Copyright (c) 2011 The Chromium OS Authors.
*
* This program is free software; you can redistribute it and/or
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/arch/x86/sysinfo.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/x86/timer.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/x86/util.S
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/arch/x86/virtual.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 coresystems GmbH
*
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1 change: 0 additions & 1 deletion payloads/libpayload/bin/lp.functions
View file
@@ -1,4 +1,3 @@
## This file is part of the libpayload project.
##
## Copyright (C) 2008 Advanced Micro Devices, Inc.
##
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/bin/lpas
View file
@@ -1,5 +1,4 @@
#!/bin/sh
## This file is part of the libpayload project.
##
## Copyright (C) 2008 Advanced Micro Devices, Inc.
##
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1 change: 0 additions & 1 deletion payloads/libpayload/bin/lpgcc
View file
@@ -1,5 +1,4 @@
#!/bin/sh
## This file is part of the libpayload project.
##
## Copyright (C) 2008 Advanced Micro Devices, Inc.
##
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/crypto/Makefile.inc
View file
@@ -1,5 +1,4 @@
##
## This file is part of the libpayload project.
##
## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
##
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1 change: 0 additions & 1 deletion payloads/libpayload/crypto/sha1.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* It has originally been taken from the OpenBSD project.
*/
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/curses/Makefile.inc
View file
@@ -1,5 +1,4 @@
##
## This file is part of the libpayload project.
##
## Copyright (C) 2008 Advanced Micro Devices, Inc.
##
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/curses/colors.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2008 Advanced Micro Devices, Inc.
Expand Down
2 changes: 0 additions & 2 deletions payloads/libpayload/curses/curses.h
View file
Expand Up @@ -1239,7 +1239,6 @@ NCURSES_EXPORT(int) vsscanf(const char *, const char *, va_list);

#define KEY_MAX 0777 /* Maximum key value is 0633 */
/*
* This file is part of ncurses, designed to be appended after curses.h.in
* (see that file for the relevant copyright).
*/
#ifdef _XOPEN_SOURCE_EXTENDED
Expand Down Expand Up @@ -1488,7 +1487,6 @@ extern NCURSES_EXPORT(const char *) _nc_viswibuf(const wint_t *);

#endif /* _XOPEN_SOURCE_EXTENDED */
/*
* This file is part of ncurses, designed to be appended after curses.h.in
* (see that file for the relevant copyright).
*/
/* $Id: curses.tail,v 1.14 2006/05/27 16:28:29 tom Exp $ */
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/curses/keyboard.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2008 Advanced Micro Devices, Inc.
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/curses/local.h
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
*
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1 change: 0 additions & 1 deletion payloads/libpayload/curses/tinycurses.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2008 Ulf Jordan <jordan@chalmers.se>
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/Makefile.inc
View file
@@ -1,5 +1,4 @@
##
## This file is part of the libpayload project.
##
## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
## Copyright (C) 2008 Advanced Micro Devices, Inc.
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/cbmem_console.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (c) 2012 Google Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/hid.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008-2010 coresystems GmbH
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/i8042/i8042.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Patrick Rudolph 2017 <siro@das-labor.org>
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/i8042/i8042.h
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright 2018 Google LLC
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/i8042/keyboard.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
* Copyright (C) 2017 Patrick Rudolph <siro@das-labor.org>
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/i8042/mouse.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2017 Patrick Rudolph <siro@das-labor.org>
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/mouse_cursor.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2017 Patrick Rudolph <siro@das-labor.org>
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/nvram.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2017 Patrick Rudolph <siro@das-labor.org>
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/options.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 coresystems GmbH
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/pci.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
* Copyright (C) 2008 coresystems GmbH
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/serial/8250.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
* Copyright (C) 2008 Ulf Jordan <jordan@chalmers.se>
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/serial/qcom_qupv3_serial.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
* Copyright (c) 2020 Qualcomm Technologies.
*
* Redistribution and use in source and binary forms, with or without
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/serial/serial.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
* Copyright (C) 2008 Ulf Jordan <jordan@chalmers.se>
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/speaker.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
*
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10 changes: 1 addition & 9 deletions payloads/libpayload/drivers/storage/Kconfig
View file
@@ -1,14 +1,6 @@
##
## This file is part of the coreboot project.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
## SPDX-License-Identifier: GPL-2.0-only

config STORAGE
bool "Support for storage devices"
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/storage/ahci.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2012 secunet Security Networks AG
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/storage/ahci_ata.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2012 secunet Security Networks AG
* Copyright (C) 2013 Edward O'Callaghan <eocallaghan@alterapraxis.com>
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/storage/ahci_atapi.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2012 secunet Security Networks AG
* Copyright (C) 2013 Edward O'Callaghan <eocallaghan@alterapraxis.com>
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/storage/ahci_common.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2012 secunet Security Networks AG
* Copyright (C) 2013 Edward O'Callaghan <eocallaghan@alterapraxis.com>
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/storage/ahci_private.h
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2012 secunet Security Networks AG
* Copyright (C) 2013 Edward O'Callaghan <eocallaghan@alterapraxis.com>
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/storage/ata.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2012 secunet Security Networks AG
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/storage/atapi.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2012 secunet Security Networks AG
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/storage/storage.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2012 secunet Security Networks AG
*
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10 changes: 1 addition & 9 deletions payloads/libpayload/drivers/timer/Kconfig
View file
@@ -1,14 +1,6 @@
##
## This file is part of the coreboot project.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
## SPDX-License-Identifier: GPL-2.0-only

choice
prompt "Timer driver"
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/timer/arm64_arch_timer.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/timer/generic.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright 2016 Google Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/timer/rdtsc.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/udc/chipidea.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2015 Google Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/udc/chipidea_priv.h
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2015 Google Inc.
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/udc/dwc2.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Rockchip Electronics
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/udc/dwc2_priv.h
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Rockchip Electronics
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/udc/udc.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2015 Google Inc.
*
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11 changes: 1 addition & 10 deletions payloads/libpayload/drivers/usb/Kconfig
View file
@@ -1,15 +1,6 @@
##
## This file is part of the coreboot project.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## SPDX-License-Identifier: GPL-2.0-only

config USB
bool "USB Support"
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/dwc2.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Rockchip Electronics
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/dwc2.h
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Rockchip Electronics
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/dwc2_private.h
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Rockchip Electronics
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/dwc2_rh.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Rockchip Electronics
*
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5 changes: 2 additions & 3 deletions payloads/libpayload/drivers/usb/ehci.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2010 coresystems GmbH
*
Expand Down Expand Up @@ -860,9 +859,9 @@ ehci_pci_init (pcidev_t addr)
hci_t *controller;
u32 reg_base;

u32 pci_command = pci_read_config32(addr, PCI_COMMAND);
u16 pci_command = pci_read_config16(addr, PCI_COMMAND);
pci_command = (pci_command | PCI_COMMAND_MEMORY) & ~PCI_COMMAND_IO ;
pci_write_config32(addr, PCI_COMMAND, pci_command);
pci_write_config16(addr, PCI_COMMAND, pci_command);

reg_base = pci_read_config32 (addr, USBBASE);

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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/ehci.h
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2010 coresystems GmbH
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/ehci_private.h
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2010 coresystems GmbH
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/ehci_rh.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2010 coresystems GmbH
*
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7 changes: 4 additions & 3 deletions payloads/libpayload/drivers/usb/generic_hub.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2013 secunet Security Networks AG
*
Expand Down Expand Up @@ -218,9 +217,11 @@ generic_hub_poll(usbdev_t *const dev)
if (!hub)
return;

if (hub->ops->hub_status_changed &&
hub->ops->hub_status_changed(dev) != 1)
if (!(dev->quirks & USB_QUIRK_HUB_NO_USBSTS_PCD) &&
hub->ops->hub_status_changed &&
hub->ops->hub_status_changed(dev) != 1) {
return;
}

int port;
for (port = 1; port <= hub->num_ports; ++port) {
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/generic_hub.h
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2013 secunet Security Networks AG
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/ohci.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2010 Patrick Georgi
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/ohci.h
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2010 Patrick Georgi
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/ohci_private.h
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2010 Patrick Georgi
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/ohci_rh.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2010 Patrick Georgi
*
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25 changes: 24 additions & 1 deletion payloads/libpayload/drivers/usb/quirks.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2010 coresystems GmbH
*
Expand Down Expand Up @@ -59,6 +58,30 @@ usb_quirks_t usb_quirks[] = {
*/
};

#if CONFIG(LP_USB_PCI)
usb_quirks_t pci_quirks[] = {
/* QEMU XHCI root hub does not implement port change detect */
{ 0x1b36, 0x000d, USB_QUIRK_HUB_NO_USBSTS_PCD, 0 },
};

u32 pci_quirk_check(pcidev_t controller)
{
int i;
u16 vendor = pci_read_config16(controller, REG_VENDOR_ID);
u16 device = pci_read_config16(controller, REG_DEVICE_ID);

for (i = 0; i < ARRAY_SIZE(pci_quirks); i++) {
if ((pci_quirks[i].vendor == vendor) &&
(pci_quirks[i].device == device)) {
printf("PCI quirks enabled: %08x\n", pci_quirks[i].quirks);
return pci_quirks[i].quirks;
}
}

return USB_QUIRK_NONE;
}
#endif

u32 usb_quirk_check(u16 vendor, u16 device)
{
int i;
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/uhci.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008-2010 coresystems GmbH
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/uhci.h
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008-2010 coresystems GmbH
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/uhci_private.h
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008-2010 coresystems GmbH
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/uhci_rh.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008-2010 coresystems GmbH
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/usb.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008-2010 coresystems GmbH
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/usb_dev.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 coresystems GmbH
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/usbhid.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008-2010 coresystems GmbH
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/usbhub.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2013 secunet Security Networks AG
*
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7 changes: 3 additions & 4 deletions payloads/libpayload/drivers/usb/usbinit.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008-2010 coresystems GmbH
*
Expand Down Expand Up @@ -62,11 +61,11 @@ static int usb_controller_initialize(int bus, int dev, int func)

/* enable busmaster */
if (devclass == 0xc03) {
u32 pci_command;
u16 pci_command;

pci_command = pci_read_config32(pci_device, PCI_COMMAND);
pci_command = pci_read_config16(pci_device, PCI_COMMAND);
pci_command |= PCI_COMMAND_MASTER;
pci_write_config32(pci_device, PCI_COMMAND, pci_command);
pci_write_config16(pci_device, PCI_COMMAND, pci_command);

usb_debug("%02x:%02x.%x %04x:%04x.%d ", bus, dev, func,
pciid >> 16, pciid & 0xFFFF, func);
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/usbmsc.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 coresystems GmbH
*
Expand Down
17 changes: 10 additions & 7 deletions payloads/libpayload/drivers/usb/xhci.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2010 Patrick Georgi
* Copyright (C) 2013 secunet Security Networks AG
Expand Down Expand Up @@ -185,20 +184,20 @@ xhci_init (unsigned long physical_bar)
goto _free_xhci;
}

memcpy(&xhci->capreg, phys_to_virt(physical_bar), sizeof(xhci->capreg));
xhci->capreg = phys_to_virt(physical_bar);
xhci->opreg = phys_to_virt(physical_bar) + CAP_GET(CAPLEN, xhci->capreg);
xhci->hcrreg = phys_to_virt(physical_bar) + xhci->capreg.rtsoff;
xhci->dbreg = phys_to_virt(physical_bar) + xhci->capreg.dboff;
xhci->hcrreg = phys_to_virt(physical_bar) + xhci->capreg->rtsoff;
xhci->dbreg = phys_to_virt(physical_bar) + xhci->capreg->dboff;

xhci_debug("regbase: 0x%"PRIx32"\n", physical_bar);
xhci_debug("caplen: 0x%"PRIx32"\n", CAP_GET(CAPLEN, xhci->capreg));
xhci_debug("rtsoff: 0x%"PRIx32"\n", xhci->capreg.rtsoff);
xhci_debug("dboff: 0x%"PRIx32"\n", xhci->capreg.dboff);
xhci_debug("rtsoff: 0x%"PRIx32"\n", xhci->capreg->rtsoff);
xhci_debug("dboff: 0x%"PRIx32"\n", xhci->capreg->dboff);

xhci_debug("hciversion: %"PRIx8".%"PRIx8"\n",
CAP_GET(CAPVER_HI, xhci->capreg), CAP_GET(CAPVER_LO, xhci->capreg));
if ((CAP_GET(CAPVER, xhci->capreg) < 0x96) ||
(CAP_GET(CAPVER, xhci->capreg) > 0x110)) {
(CAP_GET(CAPVER, xhci->capreg) > 0x120)) {
xhci_debug("Unsupported xHCI version\n");
goto _free_xhci;
}
Expand Down Expand Up @@ -314,9 +313,13 @@ xhci_pci_init (pcidev_t addr)

controller = xhci_init((unsigned long)reg_addr);
if (controller) {
xhci_t *xhci = controller->instance;
controller->pcidev = addr;

xhci_switch_ppt_ports(addr);

/* Set up any quirks for controller root hub */
xhci->roothub->quirks = pci_quirk_check(addr);
}

return controller;
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/xhci.h
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2010 Patrick Georgi
*
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/xhci_commands.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2013 secunet Security Networks AG
*
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/xhci_debug.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2013 secunet Security Networks AG
*
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/xhci_devconf.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2013 secunet Security Networks AG
*
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/xhci_events.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2013 secunet Security Networks AG
*
Expand Down
5 changes: 2 additions & 3 deletions payloads/libpayload/drivers/usb/xhci_private.h
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2010 Patrick Georgi
* Copyright (C) 2013 secunet Security Networks AG
Expand Down Expand Up @@ -364,7 +363,7 @@ typedef struct erst_entry {
#define CAP_CSZ_LEN 1

#define CAP_MASK(tok) MASK(CAP_##tok##_START, CAP_##tok##_LEN)
#define CAP_GET(tok, cap) (((cap).CAP_##tok##_FIELD & CAP_MASK(tok)) \
#define CAP_GET(tok, cap) (((cap)->CAP_##tok##_FIELD & CAP_MASK(tok)) \
>> CAP_##tok##_START)

#define CTXSIZE(xhci) (CAP_GET(CSZ, (xhci)->capreg) ? 64 : 32)
Expand All @@ -378,7 +377,7 @@ typedef struct xhci {
u32 hccparams;
u32 dboff;
u32 rtsoff;
} __packed capreg;
} __packed *capreg;

/* opreg is R/W is most places, so volatile access is necessary.
volatile means that the compiler seeks byte writes if possible,
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/xhci_rh.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2013 secunet Security Networks AG
*
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/video/bitmap.h
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2015 Google, Inc.
*
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/video/corebootfb.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
* Copyright (C) 2010 coresystems GmbH
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1 change: 0 additions & 1 deletion payloads/libpayload/drivers/video/font.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2017 Paul Kocialkowski <contact@paulk.fr>
*
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/video/font.h
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2017 Paul Kocialkowski <contact@paulk.fr>
*
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/video/font8x16.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* It has originally been taken from the HelenOS project
* (http://www.helenos.eu), and slightly modified for our purposes.
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/video/font8x16.h
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/video/geodelx.c
View file
@@ -1,5 +1,4 @@
/*
* This file is part of the libpayload project.
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
Expand Down