383 changes: 383 additions & 0 deletions payloads/external/LinuxBoot/arm64/defconfig
@@ -0,0 +1,383 @@
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_NO_HZ_IDLE=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_IRQ_TIME_ACCOUNTING=y
CONFIG_BSD_PROCESS_ACCT=y
CONFIG_BSD_PROCESS_ACCT_V3=y
CONFIG_NUMA_BALANCING=y
CONFIG_CGROUPS=y
CONFIG_MEMCG=y
CONFIG_BLK_CGROUP=y
CONFIG_DEBUG_BLK_CGROUP=y
CONFIG_CGROUP_SCHED=y
CONFIG_CGROUP_PIDS=y
CONFIG_CGROUP_RDMA=y
CONFIG_CGROUP_FREEZER=y
CONFIG_CPUSETS=y
CONFIG_CGROUP_DEVICE=y
CONFIG_CGROUP_CPUACCT=y
CONFIG_NAMESPACES=y
CONFIG_USER_NS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_KALLSYMS_ALL=y
CONFIG_EMBEDDED=y
# CONFIG_COMPAT_BRK is not set
CONFIG_JUMP_LABEL=y
CONFIG_CC_STACKPROTECTOR_NONE=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEBUG_FS is not set
CONFIG_PARTITION_ADVANCED=y
# CONFIG_IOSCHED_DEADLINE is not set
CONFIG_CFQ_GROUP_IOSCHED=y
# CONFIG_MQ_IOSCHED_DEADLINE is not set
# CONFIG_MQ_IOSCHED_KYBER is not set
CONFIG_ARCH_ACTIONS=y
CONFIG_ARCH_SUNXI=y
CONFIG_ARCH_ALPINE=y
CONFIG_ARCH_BCM2835=y
CONFIG_ARCH_BCM_IPROC=y
CONFIG_ARCH_BERLIN=y
CONFIG_ARCH_BRCMSTB=y
CONFIG_ARCH_EXYNOS=y
CONFIG_ARCH_LAYERSCAPE=y
CONFIG_ARCH_LG1K=y
CONFIG_ARCH_HISI=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_ARCH_MESON=y
CONFIG_ARCH_MVEBU=y
CONFIG_ARCH_QCOM=y
CONFIG_ARCH_REALTEK=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_ARCH_SEATTLE=y
CONFIG_ARCH_SYNQUACER=y
CONFIG_ARCH_RENESAS=y
CONFIG_ARCH_R8A7795=y
CONFIG_ARCH_R8A7796=y
CONFIG_ARCH_R8A77970=y
CONFIG_ARCH_R8A77995=y
CONFIG_ARCH_STRATIX10=y
CONFIG_ARCH_TEGRA=y
CONFIG_ARCH_SPRD=y
CONFIG_ARCH_THUNDER=y
CONFIG_ARCH_THUNDER2=y
CONFIG_ARCH_UNIPHIER=y
CONFIG_ARCH_VEXPRESS=y
CONFIG_ARCH_XGENE=y
CONFIG_ARCH_ZX=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_PCI=y
CONFIG_PCI_REALLOC_ENABLE_AUTO=y
CONFIG_PCI_IOV=y
CONFIG_PCI_PRI=y
CONFIG_PCI_PASID=y
CONFIG_HOTPLUG_PCI=y
CONFIG_PCI_HOST_GENERIC=y
CONFIG_PCI_XGENE=y
CONFIG_PCI_HOST_THUNDER_PEM=y
CONFIG_ARM64_VA_BITS_48=y
CONFIG_SCHED_MC=y
CONFIG_NR_CPUS=8
CONFIG_NUMA=y
CONFIG_PREEMPT=y
# CONFIG_COMPACTION is not set
CONFIG_KSM=y
CONFIG_CMA=y
CONFIG_SECCOMP=y
CONFIG_KEXEC=y
# CONFIG_EFI is not set
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
# CONFIG_BINFMT_SCRIPT is not set
CONFIG_CPU_IDLE=y
CONFIG_ARM_CPUIDLE=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_PACKET_DIAG=y
CONFIG_UNIX=y
CONFIG_TLS=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_ADVANCED_ROUTER=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
CONFIG_NET_IPIP=y
CONFIG_NET_IPGRE_DEMUX=y
CONFIG_SYN_COOKIES=y
CONFIG_TCP_CONG_ADVANCED=y
CONFIG_BRIDGE=y
CONFIG_VLAN_8021Q=y
CONFIG_NET_DEVLINK=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_EXTRA_FIRMWARE="cpt8x-mc-ae.out cpt8x-mc-se.out"
CONFIG_DMA_CMA=y
CONFIG_MTD=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_PLATFORM=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_CRYPTOLOOP=y
CONFIG_VIRTIO_BLK=y
CONFIG_BLK_DEV_NVME=y
CONFIG_NVME_MULTIPATH=y
CONFIG_NVME_FC=y
CONFIG_SRAM=y
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
CONFIG_CHR_DEV_SG=y
CONFIG_SCSI_SAS_LIBSAS=y
CONFIG_SCSI_VIRTIO=y
CONFIG_ATA=y
CONFIG_SATA_AHCI=y
CONFIG_SATA_AHCI_PLATFORM=y
# CONFIG_ATA_BMDMA is not set
CONFIG_MD=y
CONFIG_BLK_DEV_DM=y
CONFIG_DM_CRYPT=y
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_3COM is not set
# CONFIG_NET_VENDOR_ADAPTEC is not set
# CONFIG_NET_VENDOR_AGERE is not set
# CONFIG_NET_VENDOR_ALACRITECH is not set
# CONFIG_NET_VENDOR_ALTEON is not set
# CONFIG_NET_VENDOR_AMAZON is not set
# CONFIG_NET_VENDOR_AMD is not set
# CONFIG_NET_VENDOR_AQUANTIA is not set
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_VENDOR_ATHEROS is not set
# CONFIG_NET_CADENCE is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_BROCADE is not set
CONFIG_THUNDER_NIC_PF=y
CONFIG_THUNDER_NIC_VF=y
CONFIG_LIQUIDIO=y
CONFIG_LIQUIDIO_VF=y
# CONFIG_NET_VENDOR_CHELSIO is not set
# CONFIG_NET_VENDOR_CISCO is not set
# CONFIG_NET_VENDOR_DEC is not set
# CONFIG_NET_VENDOR_DLINK is not set
# CONFIG_NET_VENDOR_EMULEX is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_EXAR is not set
# CONFIG_NET_VENDOR_HISILICON is not set
# CONFIG_NET_VENDOR_HP is not set
# CONFIG_NET_VENDOR_HUAWEI is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MELLANOX is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_MYRI is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_NETRONOME is not set
# CONFIG_NET_VENDOR_NVIDIA is not set
# CONFIG_NET_VENDOR_OKI is not set
# CONFIG_NET_PACKET_ENGINE is not set
# CONFIG_NET_VENDOR_QLOGIC is not set
# CONFIG_NET_VENDOR_QUALCOMM is not set
# CONFIG_NET_VENDOR_REALTEK is not set
# CONFIG_NET_VENDOR_RENESAS is not set
# CONFIG_NET_VENDOR_RDC is not set
# CONFIG_NET_VENDOR_ROCKER is not set
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SILAN is not set
# CONFIG_NET_VENDOR_SIS is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_SUN is not set
# CONFIG_NET_VENDOR_TEHUTI is not set
# CONFIG_NET_VENDOR_TI is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
CONFIG_MDIO_OCTEON=y
CONFIG_AQUANTIA_PHY=y
CONFIG_MARVELL_PHY=y
CONFIG_VITESSE_PHY=y
# CONFIG_USB_NET_DRIVERS is not set
# CONFIG_WLAN is not set
CONFIG_INPUT_POLLDEV=y
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
CONFIG_KEYBOARD_CROS_EC=y
CONFIG_INPUT_MISC=y
# CONFIG_SERIO_SERPORT is not set
CONFIG_SERIO_AMBAKMI=y
CONFIG_LEGACY_PTY_COUNT=16
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_EXTENDED=y
CONFIG_SERIAL_8250_SHARE_IRQ=y
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIAL_8250_UNIPHIER=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_SERIAL_XILINX_PS_UART=y
CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
CONFIG_SERIAL_DEV_BUS=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_I2C_RK3X=y
CONFIG_I2C_UNIPHIER_F=y
CONFIG_I2C_THUNDERX=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_I2C_SLAVE=y
CONFIG_SPI=y
CONFIG_SPI_THUNDERX=y
# CONFIG_PINCTRL_UNIPHIER is not set
CONFIG_GPIO_DWAPB=y
CONFIG_GPIO_PL061=y
CONFIG_GPIO_THUNDERX=y
CONFIG_GPIO_UNIPHIER=y
CONFIG_GPIO_XGENE=y
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
CONFIG_GPIO_PCF857X=y
CONFIG_GPIO_MAX77620=y
CONFIG_POWER_RESET_XGENE=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_SYSCON_REBOOT_MODE=y
CONFIG_BATTERY_BQ27XXX=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_SOFT_WATCHDOG=y
CONFIG_XILINX_WATCHDOG=y
CONFIG_ZIIRAVE_WATCHDOG=y
CONFIG_ARM_SP805_WATCHDOG=y
CONFIG_ARM_SBSA_WATCHDOG=y
CONFIG_CADENCE_WATCHDOG=y
CONFIG_MAX77620_WATCHDOG=y
CONFIG_UNIPHIER_WATCHDOG=y
CONFIG_MFD_CROS_EC=y
CONFIG_MFD_CROS_EC_I2C=y
CONFIG_MFD_HI6421_PMIC=y
CONFIG_MFD_MAX77620=y
CONFIG_MFD_RK808=y
CONFIG_MFD_SEC_CORE=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_VGA_ARB is not set
CONFIG_FB=y
CONFIG_FB_ARMCLCD=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_HID_A4TECH=y
CONFIG_HID_APPLE=y
CONFIG_HID_BELKIN=y
CONFIG_HID_CHERRY=y
CONFIG_HID_CHICONY=y
CONFIG_HID_CYPRESS=y
CONFIG_HID_EZKEY=y
CONFIG_HID_ITE=y
CONFIG_HID_KENSINGTON=y
CONFIG_HID_LOGITECH=y
CONFIG_HID_MICROSOFT=y
CONFIG_HID_MONTEREY=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USB_ACM=y
CONFIG_USB_STORAGE=y
CONFIG_USB_UAS=y
CONFIG_USB_SERIAL=y
CONFIG_MMC=y
CONFIG_SDIO_UART=y
CONFIG_MMC_ARMMMCI=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_CAVIUM_THUNDERX=m
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_ISL1208=y
CONFIG_RTC_DRV_ISL12022=y
CONFIG_SYNC_FILE=y
CONFIG_VIRTIO_BALLOON=y
CONFIG_VIRTIO_MMIO=y
CONFIG_COMMON_CLK_RK808=y
CONFIG_COMMON_CLK_CS2000_CP=y
CONFIG_COMMON_CLK_S2MPS11=y
CONFIG_CLK_QORIQ=y
CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
CONFIG_ARM_SMMU=y
CONFIG_ARM_SMMU_V3=y
CONFIG_EXTCON_USB_GPIO=y
CONFIG_PHY_XGENE=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_GOOGLE_FIRMWARE=y
CONFIG_GOOGLE_COREBOOT_TABLE_OF=y
CONFIG_GOOGLE_MEMCONSOLE_COREBOOT=y
CONFIG_GOOGLE_VPD=y
CONFIG_EXT3_FS=y
CONFIG_XFS_FS=y
CONFIG_BTRFS_FS=y
CONFIG_F2FS_FS=y
CONFIG_FS_DAX=y
CONFIG_EXPORTFS_BLOCK_OPS=y
CONFIG_FANOTIFY=y
CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
CONFIG_ISO9660_FS=y
CONFIG_MSDOS_FS=y
CONFIG_VFAT_FS=y
CONFIG_FAT_DEFAULT_UTF8=y
CONFIG_NTFS_FS=y
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
# CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_PRINTK_TIME=y
CONFIG_MESSAGE_LOGLEVEL_DEFAULT=5
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_FS=y
CONFIG_MAGIC_SYSRQ=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
# CONFIG_FTRACE is not set
CONFIG_MEMTEST=y
# CONFIG_STRICT_DEVMEM is not set
CONFIG_KEYS=y
CONFIG_SECURITY=y
# CONFIG_INTEGRITY is not set
CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_ECDH=y
# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
CONFIG_CRYPTO_AUTHENC=y
CONFIG_CRYPTO_ECHAINIV=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_CMAC=y
CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_ARC4=y
CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_ANSI_CPRNG=y
# CONFIG_CRYPTO_DEV_VIRTIO is not set
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
CONFIG_X509_CERTIFICATE_PARSER=y
CONFIG_PKCS7_MESSAGE_PARSER=y
CONFIG_SYSTEM_TRUSTED_KEYRING=y
CONFIG_ARM64_CRYPTO=y
CONFIG_CRYPTO_SHA512_ARM64=y
CONFIG_CRYPTO_SHA1_ARM64_CE=y
CONFIG_CRYPTO_SHA2_ARM64_CE=y
CONFIG_CRYPTO_GHASH_ARM64_CE=y
CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
CONFIG_CRYPTO_CRC32_ARM64_CE=y
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
CONFIG_CRYPTO_CHACHA20_NEON=y
CONFIG_CRYPTO_AES_ARM64_BS=y
CONFIG_CRC_T10DIF=y
CONFIG_CRC_ITU_T=y
CONFIG_CRC7=y
74 changes: 74 additions & 0 deletions payloads/external/LinuxBoot/arm64/kernel_fdt_lzma.its
@@ -0,0 +1,74 @@
/*
* Simple U-Boot uImage source file containing a single kernel and FDT blob
*/

/dts-v1/;

/ {
description = "Simple image with single Linux kernel and FDT blob";
#address-cells = <1>;

images {
kernel {
description = "Vanilla Linux kernel";
data = /incbin/("vmlinux.bin.lzma");
type = "kernel";
arch = "arm64";
os = "linux";
compression = "lzma";
load = <0x80000>;
entry = <0x80000>;
hash-1 {
algo = "crc32";
};
hash-2 {
algo = "sha1";
};
hash-3 {
algo = "sha256";
};
};
fdt-1 {
description = "Flattened Device Tree blob";
data = /incbin/("target.dtb");
type = "flat_dt";
arch = "arm64";
compression = "none";
hash-1 {
algo = "crc32";
};
hash-2 {
algo = "sha1";
};
hash-3 {
algo = "sha256";
};
};
ramdisk-1 {
description = "Compressed Initramfs";
data = /incbin/("initramfs.cpio.xz");
type = "ramdisk";
arch = "arm64";
os = "linux";
compression = "none";
load = <00000000>;
entry = <00000000>;
hash-1 {
algo = "sha1";
};
hash-2 {
algo = "sha256";
};
};
};

configurations {
default = "conf-1";
conf-1 {
description = "Boot Linux kernel with FDT blob";
kernel = "kernel";
fdt = "fdt-1";
ramdisk = "ramdisk-1";
};
};
};
7 changes: 5 additions & 2 deletions payloads/external/LinuxBoot/targets/u-root.mk
Expand Up @@ -52,8 +52,11 @@ checkout: fetch
done;,true;) \
fi

$(project_dir)/initramfs.cpio.xz: checkout
cd $(uroot_dir); GOARCH=$(CONFIG_LINUXBOOT_ARCH) GOPATH=$(go_path_dir) go build u-root.go
$(uroot_dir)/u-root: $(uroot_dir)/u-root.go
echo " GO u-root"
cd $(uroot_dir); GOPATH=$(go_path_dir) go build u-root.go

$(project_dir)/initramfs.cpio.xz: checkout $(uroot_dir)/u-root
echo " MAKE u-root $(CONFIG_LINUXBOOT_UROOT_VERSION)"
ifneq ($(CONFIG_LINUXBOOT_UROOT_COMMANDS),)
ifneq ($(CONFIG_LINUXBOOT_UROOT_FILES),)
Expand Down
24 changes: 10 additions & 14 deletions payloads/external/Makefile.inc
Expand Up @@ -33,10 +33,14 @@ $(PAYLOAD_CONFIG): payloads/external/depthcharge/depthcharge/build/depthcharge.e
endif

ifeq ($(CONFIG_PAYLOAD_LINUXBOOT),y)
ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUXBOOT_KERNEL_COMMANDLINE))),)
ifeq ($(CONFIG_ARCH_X86),y)
ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUXBOOT_KERNEL_COMMANDLINE))),)
ADDITIONAL_PAYLOAD_CONFIG+=-C $(CONFIG_LINUXBOOT_KERNEL_COMMANDLINE)
endif
ADDITIONAL_PAYLOAD_CONFIG+=-I $(CONFIG_PAYLOAD_USERSPACE)
endif
ifneq ($(strip $(call strip_quotes,$(CONFIG_PAYLOAD_USERSPACE))),)
ADDITIONAL_PAYLOAD_CONFIG+=-I $(strip $(call strip_quotes,$(CONFIG_PAYLOAD_USERSPACE)))
endif
endif
endif

ifeq ($(CONFIG_PAYLOAD_LINUX),y)
Expand Down Expand Up @@ -320,16 +324,6 @@ payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG)

linuxboot:
$(MAKE) -C payloads/external/LinuxBoot \
HOSTCC="$(HOSTCC)" \
CC="$(HOSTCC)" \
GCC_CC_x86_32=$(GCC_CC_x86_32) \
GCC_CC_x86_64=$(GCC_CC_x86_64) \
GCC_CC_arm=$(GCC_CC_arm) \
GCC_CC_arm64=$(GCC_CC_arm64) \
OBJCOPY_x86_32=$(OBJCOPY_x86_32) \
OBJCOPY_x86_64=$(OBJCOPY_x86_64) \
OBJCOPY_arm=$(OBJCOPY_arm) \
OBJCOPY_arm64=$(OBJCOPY_arm64) \
CPUS=$(CPUS) \
CONFIG_LINUXBOOT_KERNEL_VERSION=$(CONFIG_LINUXBOOT_KERNEL_VERSION) \
CONFIG_LINUXBOOT_KERNEL_CONFIGFILE=$(CONFIG_LINUXBOOT_KERNEL_CONFIGFILE) \
Expand All @@ -338,7 +332,9 @@ linuxboot:
CONFIG_LINUXBOOT_UROOT_COMMANDS="$(CONFIG_LINUXBOOT_UROOT_COMMANDS)" \
CONFIG_LINUXBOOT_ARCH=$(CONFIG_LINUXBOOT_ARCH) \
CONFIG_LINUXBOOT_UROOT=$(CONFIG_LINUXBOOT_UROOT) \
CONFIG_LINUXBOOT_UROOT_FILES=$(CONFIG_LINUXBOOT_UROOT_FILES)
CONFIG_LINUXBOOT_UROOT_FILES=$(CONFIG_LINUXBOOT_UROOT_FILES) \
CONFIG_LINUXBOOT_DTB_FILE=$(CONFIG_LINUXBOOT_DTB_FILE)


payloads/external/LinuxBoot/linuxboot/kernel-image: linuxboot
payloads/external/LinuxBoot/linuxboot/initramfs.cpio.xz: linuxboot
Expand Down
2 changes: 1 addition & 1 deletion payloads/external/SeaBIOS/Kconfig
Expand Up @@ -5,7 +5,7 @@ choice
default SEABIOS_STABLE

config SEABIOS_STABLE
bool "1.11.1"
bool "1.11.2"
help
Stable SeaBIOS version
config SEABIOS_MASTER
Expand Down
2 changes: 1 addition & 1 deletion payloads/external/SeaBIOS/Makefile
@@ -1,5 +1,5 @@
TAG-$(CONFIG_SEABIOS_MASTER)=origin/master
TAG-$(CONFIG_SEABIOS_STABLE)=0551a4be2ce599fb60e478b4c15e06ab6587822c
TAG-$(CONFIG_SEABIOS_STABLE)=f9626ccb91e771f990fbb2da92e427a399d7d918
TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID)

project_git_repo=https://github.com/pcengines/seabios.git
Expand Down
2 changes: 1 addition & 1 deletion payloads/libpayload/Makefile
Expand Up @@ -147,7 +147,7 @@ READELF := $(READELF_$(ARCH-y))
STRIP := $(STRIP_$(ARCH-y))
AR := $(AR_$(ARCH-y))

CFLAGS += $(CFLAGS_$(ARCH-y))
CFLAGS += -std=gnu11 $(CFLAGS_$(ARCH-y))

ifneq ($(INNER_SCANBUILD),y)
ifeq ($(CONFIG_LP_COMPILER_LLVM_CLANG),y)
Expand Down
19 changes: 0 additions & 19 deletions payloads/libpayload/arch/arm64/gdb.c
Expand Up @@ -28,25 +28,6 @@ struct gdb_regs
u32 spsr;
} __packed;

static const u8 type_to_signal[] = {
[EXC_SYNC_SP0] = GDB_SIGTRAP,
[EXC_IRQ_SP0] = GDB_SIGSEGV,
[EXC_FIQ_SP0] = GDB_SIGSEGV,
[EXC_SERROR_SP0] = GDB_SIGSEGV,
[EXC_SYNC_SPX] = GDB_SIGTRAP,
[EXC_IRQ_SPX] = GDB_SIGSEGV,
[EXC_FIQ_SPX] = GDB_SIGSEGV,
[EXC_SERROR_SPX] = GDB_SIGSEGV,
[EXC_SYNC_ELX_64] = GDB_SIGTRAP,
[EXC_IRQ_ELX_64] = GDB_SIGSEGV,
[EXC_FIQ_ELX_64] = GDB_SIGSEGV,
[EXC_SERROR_ELX_64] = GDB_SIGSEGV,
[EXC_SYNC_ELX_32] = GDB_SIGTRAP,
[EXC_IRQ_ELX_32] = GDB_SIGSEGV,
[EXC_FIQ_ELX_32] = GDB_SIGSEGV,
[EXC_SERROR_ELX_32] = GDB_SIGSEGV
};

static int gdb_exception_hook(u32 type)
{
return -1;
Expand Down
9 changes: 9 additions & 0 deletions payloads/libpayload/drivers/usb/generic_hub.c
Expand Up @@ -157,6 +157,15 @@ generic_hub_attach_dev(usbdev_t *const dev, const int port)
if (hub->ops->reset_port) {
if (hub->ops->reset_port(dev, port) < 0)
return -1;

if (!hub->ops->port_connected(dev, port)) {
usb_debug(
"generic_hub: Port %d disconnected after "
"reset. Possibly upgraded, rescan required.\n",
port);
return 0;
}

/* after reset the port will be enabled automatically */
const int ret = generic_hub_wait_for_port(
/* time out after 1,000 * 10us = 10ms */
Expand Down
9 changes: 6 additions & 3 deletions payloads/libpayload/drivers/usb/xhci.c
Expand Up @@ -403,9 +403,12 @@ xhci_reinit (hci_t *controller)
xhci_post_command(xhci);

/* Wait for result in event ring */
xhci_wait_for_command_done(xhci, cmd, 1);
xhci_debug("Command ring is %srunning\n",
(xhci->opreg->crcr_lo & CRCR_CRR) ? "" : "not ");
int cc = xhci_wait_for_command_done(xhci, cmd, 1);

xhci_debug("Command ring is %srunning: cc: %d\n",
(xhci->opreg->crcr_lo & CRCR_CRR) ? "" : "not ", cc);
if (cc != CC_SUCCESS)
xhci_debug("noop command failed.\n");
}
#endif
}
Expand Down
50 changes: 25 additions & 25 deletions payloads/libpayload/drivers/usb/xhci_private.h
Expand Up @@ -325,16 +325,16 @@ typedef struct xhci {
/* capreg is read-only, so no need for volatile,
and thus 32bit accesses can be assumed. */
struct capreg {
u8 caplength;
u8 res1;
union {
u8 caplength; /* 0x00 */
u8 res1; /* 0x01 */
union { /* 0x02 */
u16 hciversion;
struct {
u8 hciver_lo;
u8 hciver_hi;
} __packed;
} __packed;
union {
union { /* 0x04 */
u32 hcsparams1;
struct {
unsigned long MaxSlots:7;
Expand All @@ -343,7 +343,7 @@ typedef struct xhci {
unsigned long MaxPorts:8;
} __packed;
} __packed;
union {
union { /* 0x08 */
u32 hcsparams2;
struct {
unsigned long IST:4;
Expand All @@ -354,15 +354,15 @@ typedef struct xhci {
unsigned long Max_Scratchpad_Bufs_Lo:5;
} __packed;
} __packed;
union {
union { /* 0x0C */
u32 hcsparams3;
struct {
unsigned long u1latency:8;
unsigned long:8;
unsigned long u2latency:16;
} __packed;
} __packed;
union {
union { /* 0x10 */
u32 hccparams;
struct {
unsigned long ac64:1;
Expand All @@ -378,42 +378,42 @@ typedef struct xhci {
unsigned long xECP:16;
} __packed;
} __packed;
u32 dboff;
u32 rtsoff;
u32 dboff; /* 0x14 */
u32 rtsoff; /* 0x18 */
} __packed *capreg;

/* opreg is R/W is most places, so volatile access is necessary.
volatile means that the compiler seeks byte writes if possible,
making bitfields unusable for MMIO register blocks. Yay C :-( */
volatile struct opreg {
u32 usbcmd;
u32 usbcmd; /* 0x00 */
#define USBCMD_RS (1 << 0)
#define USBCMD_HCRST (1 << 1)
#define USBCMD_INTE (1 << 2)
u32 usbsts;
u32 usbsts; /* 0x04 */
#define USBSTS_HCH (1 << 0)
#define USBSTS_HSE (1 << 2)
#define USBSTS_EINT (1 << 3)
#define USBSTS_PCD (1 << 4)
#define USBSTS_CNR (1 << 11)
#define USBSTS_PRSRV_MASK ((1 << 1) | 0xffffe000)
u32 pagesize;
u8 res1[0x13-0x0c+1];
u32 dnctrl;
u32 crcr_lo;
u32 crcr_hi;
u32 pagesize; /* 0x08 */
u8 res1[0x13-0x0c+1]; /* 0x0C */
u32 dnctrl; /* 0x14 */
u32 crcr_lo; /* 0x18 */
u32 crcr_hi; /* 0x1C */
#define CRCR_RCS (1 << 0)
#define CRCR_CS (1 << 1)
#define CRCR_CA (1 << 2)
#define CRCR_CRR (1 << 3)
u8 res2[0x2f-0x20+1];
u32 dcbaap_lo;
u32 dcbaap_hi;
u32 config;
u8 res2[0x2f-0x20+1]; /* 0x20 */
u32 dcbaap_lo; /* 0x30 */
u32 dcbaap_hi; /* 0x34 */
u32 config; /* 0x38 */
#define CONFIG_LP_MASK_MaxSlotsEn 0xff
u8 res3[0x3ff-0x3c+1];
u8 res3[0x3ff-0x3c+1]; /* 0x3C */
struct {
u32 portsc;
u32 portsc; /* 0x400 + 4 * port */
#define PORTSC_CCS (1 << 0)
#define PORTSC_PED (1 << 1)
// BIT 2 rsvdZ
Expand Down Expand Up @@ -443,9 +443,9 @@ typedef struct xhci {
#define PORTSC_DR (1 << 30)
#define PORTSC_WPR (1 << 31)
#define PORTSC_RW_MASK (PORTSC_PR | PORTSC_PLS_MASK | PORTSC_PP | PORTSC_PIC_MASK | PORTSC_LWS | PORTSC_WCE | PORTSC_WDE | PORTSC_WOE)
u32 portpmsc;
u32 portli;
u32 res;
u32 portpmsc; /* 0x404 + 4 * port */
u32 portli; /* 0x408 + 4 * port */
u32 res; /* 0x40C + 4 * port */
} __packed prs[];
} __packed *opreg;

Expand Down
2 changes: 1 addition & 1 deletion payloads/libpayload/drivers/usb/xhci_rh.c
Expand Up @@ -95,7 +95,7 @@ xhci_rh_port_speed(usbdev_t *const dev, const int port)
>> PORTSC_PORT_SPEED_START)
- 1;
} else {
return -1;
return UNKNOWN_SPEED;
}
}

Expand Down
6 changes: 5 additions & 1 deletion payloads/libpayload/include/usb/usb.h
Expand Up @@ -187,7 +187,11 @@ typedef struct {
} endpoint_t;

typedef enum {
FULL_SPEED = 0, LOW_SPEED = 1, HIGH_SPEED = 2, SUPER_SPEED = 3,
UNKNOWN_SPEED = -1,
FULL_SPEED = 0,
LOW_SPEED = 1,
HIGH_SPEED = 2,
SUPER_SPEED = 3,
} usb_speed;

struct usbdev {
Expand Down
18 changes: 18 additions & 0 deletions src/Kconfig
Expand Up @@ -1024,6 +1024,24 @@ config DEBUG_ADA_CODE
Add the compiler switch `-gnata` to compile code guarded by
`pragma Debug`.

config HAVE_EM100_SUPPORT
bool "Platform can support the Dediprog EM100 SPI emulator"
help
This is enabled by platforms which can support using the EM100.

config EM100
bool "Configure image for EM100 usage"
depends on HAVE_EM100_SUPPORT
help
The Dediprog EM100 SPI emulator allows fast loading of new SPI images
over USB. However it only supports a maximum SPI clock of 20MHz and
single data output. Enable this option to use a 20MHz SPI clock and
disable "Dual Output Fast Read" Support.

On AMD platforms this changes the SPI speed at run-time if the
mainboard code supports this. On supported Intel platforms this works
by changing the settings in the descriptor.bin file.

endmenu


Expand Down
14 changes: 8 additions & 6 deletions src/arch/riscv/Kconfig
Expand Up @@ -2,12 +2,14 @@ config ARCH_RISCV
bool
default n

config ARCH_RISCV_COMPRESSED
bool
default n
help
Enable this option if your RISC-V processor supports compressed
instructions (RVC). Currently, this enables RVC for all stages.
config RISCV_ARCH
string

config RISCV_ABI
string

config RISCV_CODEMODEL
string

config ARCH_BOOTBLOCK_RISCV
bool
Expand Down
20 changes: 11 additions & 9 deletions src/arch/riscv/Makefile.inc
Expand Up @@ -18,20 +18,21 @@
################################################################################
## RISC-V specific options
################################################################################
ifeq ($(CONFIG_ARCH_RISCV),y)

ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y)
check-ramstage-overlap-regions += stack
endif

riscv_arch = rv64imafd
riscv_flags = -I$(src)/arch/riscv/ -mcmodel=$(CONFIG_RISCV_CODEMODEL) -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI)

ifeq ($(CONFIG_ARCH_RISCV_COMPRESSED),y)
riscv_arch := $(riscv_arch)c
endif
riscv_asm_flags = -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI)

COMPILER_RT_bootblock = $(shell $(GCC_bootblock) $(riscv_flags) -print-libgcc-file-name)

riscv_flags = -I$(src)/arch/riscv/ -mcmodel=medany -march=$(riscv_arch)
COMPILER_RT_romstage = $(shell $(GCC_romstage) $(riscv_flags) -print-libgcc-file-name)

riscv_asm_flags = -march=$(riscv_arch)
COMPILER_RT_ramstage = $(shell $(GCC_ramstage) $(riscv_flags) -print-libgcc-file-name)

################################################################################
## bootblock
Expand Down Expand Up @@ -64,7 +65,7 @@ $(objcbfs)/bootblock.debug: $$(bootblock-objs)
bootblock-c-ccopts += $(riscv_flags)
bootblock-S-ccopts += $(riscv_asm_flags)

endif
endif #CONFIG_ARCH_BOOTBLOCK_RISCV

################################################################################
## romstage
Expand Down Expand Up @@ -92,7 +93,7 @@ $(objcbfs)/romstage.debug: $$(romstage-objs)
romstage-c-ccopts += $(riscv_flags)
romstage-S-ccopts += $(riscv_asm_flags)

endif
endif #CONFIG_ARCH_ROMSTAGE_RISCV

################################################################################
## ramstage
Expand Down Expand Up @@ -128,4 +129,5 @@ $(objcbfs)/ramstage.debug: $$(ramstage-objs)
ramstage-c-ccopts += $(riscv_flags)
ramstage-S-ccopts += $(riscv_asm_flags)

endif
endif #CONFIG_ARCH_RAMSTAGE_RISCV
endif #CONFIG_ARCH_RISCV
36 changes: 21 additions & 15 deletions src/arch/riscv/bootblock.S
Expand Up @@ -34,25 +34,26 @@ _start:
#
csrw mscratch, a1

# N.B. This only works on low 4G of the address space
# and the stack must be page-aligned.
la sp, _estack

# poison the stack
la t1, _stack
li t0, 0xdeadbeef
sd t0, 0(t1)
# initialize cache as ram
call cache_as_ram

# make room for HLS and initialize it
addi sp, sp, -HLS_SIZE
# initialize stack point for each hart
# and the stack must be page-aligned.
# 0xDEADBEEF used to check stack overflow
csrr a0, mhartid
la t0, _stack
slli t1, a0, RISCV_PGSHIFT
add t0, t0, t1
li t1, 0xDEADBEEF
sd t1, 0(t0)
li t1, RISCV_PGSIZE - HLS_SIZE
add sp, t0, t1

// Once again, the docs and toolchain disagree.
// Rather than get fancy I'll just lock this down
// until it all stabilizes.
//csrr a0, mhartid
csrr a0, 0xf14
# initialize hart-local storage
csrr a0, mhartid
call hls_init

# initialize entry of interrupt/exception
la t0, trap_entry
csrw mtvec, t0

Expand All @@ -62,3 +63,8 @@ _start:
# set up the mstatus register for VM
call mstatus_init
tail main

// These codes need to be implemented on a specific SoC.
.weak cache_as_ram
cache_as_ram:
ret
7 changes: 7 additions & 0 deletions src/arch/riscv/include/arch/cpu.h
Expand Up @@ -16,6 +16,8 @@
#ifndef __ARCH_CPU_H__
#define __ARCH_CPU_H__

#include <arch/encoding.h>

#define asmlinkage

#if !defined(__PRE_RAM__)
Expand Down Expand Up @@ -44,5 +46,10 @@ struct cpuinfo_riscv {

#endif

static inline int supports_extension(char ext)
{
return read_csr(misa) & (1 << (ext - 'A'));
}

struct cpu_info *cpu_info(void);
#endif /* __ARCH_CPU_H__ */
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2013, The Regents of the University of California (Regents).
* Copyright (c) 2018, HardenedLinux.
* All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
Expand Down Expand Up @@ -30,38 +31,58 @@

#include <arch/encoding.h>

typedef struct { volatile int counter; } atomic_t;

#define disable_irqsave() clear_csr(mstatus, MSTATUS_MIE)
#define enable_irqrestore(flags) set_csr(mstatus, (flags) & MSTATUS_MIE)

typedef struct { int lock; } spinlock_t;
#define SPINLOCK_INIT {0}

#define atomic_set(ptr, val) (*(volatile typeof(*(ptr)) *)(ptr) = val)
#define atomic_read(ptr) (*(volatile typeof(*(ptr)) *)(ptr))
#define atomic_set(v, val) ((v)->counter = (val))
#define atomic_read(v) ((v)->counter)

#ifdef PK_ENABLE_ATOMICS
# define atomic_add(ptr, inc) __sync_fetch_and_add(ptr, inc)
# define atomic_swap(ptr, swp) __sync_lock_test_and_set(ptr, swp)
# define atomic_cas(ptr, cmp, swp) __sync_val_compare_and_swap(ptr, cmp, swp)
#ifdef __riscv_atomic
# define atomic_add(v, inc) __sync_fetch_and_add(&((v)->counter), inc)
# define atomic_swap(v, swp) __sync_lock_test_and_set(&((v)->counter), swp)
# define atomic_cas(v, cmp, swp) __sync_val_compare_and_swap(&((v)->counter), \
cmp, swp)
# define atomic_inc(v) atomic_add(v, 1)
# define atomic_dec(v) atomic_add(v, -1)
#else
# define atomic_add(ptr, inc) ({ \
long flags = disable_irqsave(); \
typeof(ptr) res = *(volatile typeof(ptr))(ptr); \
*(volatile typeof(ptr))(ptr) = res + (inc); \
enable_irqrestore(flags); \
res; })
# define atomic_swap(ptr, swp) ({ \
long flags = disable_irqsave(); \
typeof(*ptr) res = *(volatile typeof(ptr))(ptr); \
*(volatile typeof(ptr))(ptr) = (swp); \
enable_irqrestore(flags); \
res; })
# define atomic_cas(ptr, cmp, swp) ({ \
long flags = disable_irqsave(); \
typeof(ptr) res = *(volatile typeof(ptr))(ptr); \
if (res == (cmp)) *(volatile typeof(ptr))(ptr) = (swp); \
enable_irqrestore(flags); \
res; })
#endif
static inline int atomic_add(atomic_t *v, int inc)
{
long flags = disable_irqsave();
int res = v->counter;
v->counter += inc;
enable_irqrestore(flags);
return res;
}

static inline int atomic_swap(atomic_t *v, int swp)
{
long flags = disable_irqsave();
int res = v->counter;
v->counter = swp;
enable_irqrestore(flags);
return res;
}

static inline int atomic_cas(atomic_t *v, int cmp, int swp)
{
long flags = disable_irqsave();
int res = v->counter;
v->counter = (res == cmp ? swp : res);
enable_irqrestore(flags);
return res;
}

static inline int atomic_inc(atomic_t *v)
{
return atomic_add(v, 1);
}

static inline int atomic_dec(atomic_t *v)
{
return atomic_add(v, -1);
}
#endif //__riscv_atomic

#endif
#endif //_RISCV_ATOMIC_H
12 changes: 12 additions & 0 deletions src/arch/riscv/include/arch/smp/spinlock.h
@@ -0,0 +1,12 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
1 change: 0 additions & 1 deletion src/arch/riscv/include/mcall.h
Expand Up @@ -26,7 +26,6 @@
#ifndef __ASSEMBLER__

#include <arch/encoding.h>
#include <atomic.h>
#include <stdint.h>

typedef struct {
Expand Down
1 change: 0 additions & 1 deletion src/arch/riscv/mcall.c
Expand Up @@ -27,7 +27,6 @@

#include <arch/barrier.h>
#include <arch/errno.h>
#include <atomic.h>
#include <console/console.h>
#include <mcall.h>
#include <string.h>
Expand Down
2 changes: 1 addition & 1 deletion src/arch/x86/cpu.c
Expand Up @@ -116,7 +116,7 @@ static struct {
{ X86_VENDOR_SIS, "SiS SiS SiS ", },
};

static const char * const x86_vendor_name[] = {
static const char *const x86_vendor_name[] = {
[X86_VENDOR_INTEL] = "Intel",
[X86_VENDOR_CYRIX] = "Cyrix",
[X86_VENDOR_AMD] = "AMD",
Expand Down
30 changes: 28 additions & 2 deletions src/arch/x86/smbios.c
Expand Up @@ -4,6 +4,7 @@
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>,
* Raptor Engineering
* Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
* Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
Expand Down Expand Up @@ -335,8 +336,6 @@ const char *__weak smbios_mainboard_bios_version(void)
{
if (strlen(CONFIG_LOCALVERSION))
return CONFIG_LOCALVERSION;
else if (strlen(coreboot_tag))
return coreboot_tag;
else
return coreboot_version;
}
Expand Down Expand Up @@ -631,6 +630,33 @@ static int smbios_write_type32(unsigned long *current, int handle)
return len;
}

int smbios_write_type38(unsigned long *current, int *handle,
const enum smbios_bmc_interface_type interface_type,
const u8 ipmi_rev, const u8 i2c_addr, const u8 nv_addr,
const u64 base_addr, const u8 base_modifier,
const u8 irq)
{
struct smbios_type38 *t = (struct smbios_type38 *)*current;
int len = sizeof(struct smbios_type38);

memset(t, 0, sizeof(struct smbios_type38));
t->type = SMBIOS_IPMI_DEVICE_INFORMATION;
t->handle = *handle;
t->length = len - 2;
t->interface_type = interface_type;
t->ipmi_rev = ipmi_rev;
t->i2c_slave_addr = i2c_addr;
t->nv_storage_addr = nv_addr;
t->base_address = base_addr;
t->base_address_modifier = base_modifier;
t->irq = irq;

*current += len;
*handle += 1;

return len;
}

int smbios_write_type41(unsigned long *current, int *handle,
const char *name, u8 instance, u16 segment,
u8 bus, u8 device, u8 function)
Expand Down
2 changes: 1 addition & 1 deletion src/commonlib/storage/mmc.c
Expand Up @@ -529,7 +529,7 @@ int mmc_set_partition(struct storage_media *media,
const char *mmc_partition_name(struct storage_media *media,
unsigned int partition_number)
{
static const char * const partition_name[8] = {
static const char *const partition_name[8] = {
"User", /* 0 */
"Boot 1", /* 1 */
"Boot 2", /* 2 */
Expand Down
2 changes: 1 addition & 1 deletion src/commonlib/storage/storage.c
Expand Up @@ -31,7 +31,7 @@
#define HEX_CAPACITY_MULTIPLIER 1024ULL

struct capacity {
const char * const units;
const char *const units;
uint64_t bytes;
};

Expand Down
2 changes: 1 addition & 1 deletion src/cpu/amd/car/post_cache_as_ram.c
Expand Up @@ -121,7 +121,7 @@ static void vErrata343(void)
wrmsr(BU_CFG2_MSR, msr);
}

asmlinkage void * post_cache_as_ram(void)
asmlinkage void *post_cache_as_ram(void)
{
uint32_t family = amd_fam1x_cpu_family();
int s3resume = 0;
Expand Down
4 changes: 2 additions & 2 deletions src/cpu/amd/family_10h-family_15h/init_cpus.c
Expand Up @@ -377,7 +377,7 @@ u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
uint32_t max_bsp_stack_region_size = CONFIG_DCACHE_BSP_STACK_SIZE + CONFIG_DCACHE_BSP_STACK_SLUSH;
uint32_t bsp_stack_region_upper_boundary = CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE;
uint32_t bsp_stack_region_lower_boundary = bsp_stack_region_upper_boundary - max_bsp_stack_region_size;
void * lower_stack_region_boundary = (void*)(bsp_stack_region_lower_boundary - max_ap_stack_region_size);
void *lower_stack_region_boundary = (void *)(bsp_stack_region_lower_boundary - max_ap_stack_region_size);
if (((void*)(sysinfo + 1)) > lower_stack_region_boundary)
printk(BIOS_WARNING,
"sysinfo extends into stack region (sysinfo range: [%p,%p] lower stack region boundary: %p)\n",
Expand Down Expand Up @@ -825,7 +825,7 @@ static void AMD_SetupPSIVID_d(u32 platform_type, u8 node)
*
* Returns the offset of the link register.
*/
static BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 * offset)
static BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 *offset)
{
u32 reg;
u32 val;
Expand Down
4 changes: 2 additions & 2 deletions src/cpu/amd/pi/romstage.c
Expand Up @@ -28,7 +28,7 @@ void asmlinkage early_all_cores(void)
amd_initmmio();
}

void * asmlinkage romstage_main(unsigned long bist)
void *asmlinkage romstage_main(unsigned long bist)
{
int s3resume = 0;
u8 initial_apic_id = cpuid_ebx(1) >> 24;
Expand All @@ -45,7 +45,7 @@ void * asmlinkage romstage_main(unsigned long bist)
stack_top += HIGH_ROMSTAGE_STACK_SIZE;

printk(BIOS_DEBUG, "Move CAR stack.\n");
return (void*)stack_top;
return (void *)stack_top;
}

void asmlinkage romstage_after_car(void)
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/intel/turbo/turbo.c
Expand Up @@ -42,7 +42,7 @@ static inline void set_global_turbo_state(int state)
}
#endif

static const char * const turbo_state_desc[] = {
static const char *const turbo_state_desc[] = {
[TURBO_UNKNOWN] = "unknown",
[TURBO_UNAVAILABLE] = "unavailable",
[TURBO_DISABLED] = "available but hidden",
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/via/nano/update_ucode.c
Expand Up @@ -61,7 +61,7 @@ static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode)
* Two's complement done over the entire file, including the header */
int i;
u32 check = 0;
u32 *raw = (void*) ucode;
u32 *raw = (void *) ucode;
for (i = 0; i < ((ucode->total_size) >> 2); i++) {
check += raw[i];
}
Expand Down
2 changes: 1 addition & 1 deletion src/device/device.c
Expand Up @@ -195,7 +195,7 @@ static resource_t round(resource_t val, unsigned long pow)
return val;
}

static const char * resource2str(struct resource *res)
static const char *resource2str(struct resource *res)
{
if (res->flags & IORESOURCE_IO)
return "io";
Expand Down
2 changes: 1 addition & 1 deletion src/device/oprom/include/x86emu/regs.h
Expand Up @@ -306,7 +306,7 @@ typedef struct {
unsigned long mem_base;
unsigned long mem_size;
unsigned long abseg;
void* private;
void *private;
X86EMU_regs x86;
} X86EMU_sysEnv;

Expand Down
32 changes: 16 additions & 16 deletions src/device/oprom/yabel/compat/of.h
Expand Up @@ -35,7 +35,7 @@
#ifndef OF_H
#define OF_H
#define p32 int
#define p32cast (int) (unsigned long) (void*)
#define p32cast (int) (unsigned long) (void *)

#define phandle_t p32
#define ihandle_t p32
Expand All @@ -50,27 +50,27 @@ typedef struct


phandle_t of_finddevice (const char *);
phandle_t of_peer (phandle_t);
phandle_t of_child (phandle_t);
phandle_t of_parent (phandle_t);
int of_getprop (phandle_t, const char *, void *, int);
void * of_call_method_3 (const char *, ihandle_t, int);
phandle_t of_peer(phandle_t);
phandle_t of_child(phandle_t);
phandle_t of_parent(phandle_t);
int of_getprop(phandle_t, const char *, void *, int);
void *of_call_method_3(const char *, ihandle_t, int);


ihandle_t of_open (const char *);
ihandle_t of_open(const char *);
void of_close(ihandle_t);
int of_read (ihandle_t , void*, int);
int of_write (ihandle_t, void*, int);
int of_seek (ihandle_t, int, int);
int of_read(ihandle_t, void *, int);
int of_write(ihandle_t, void *, int);
int of_seek(ihandle_t, int, int);

void * of_claim(void *, unsigned int , unsigned int );
void of_release(void *, unsigned int );
void *of_claim(void *, unsigned int, unsigned int);
void of_release(void *, unsigned int);

int of_yield(void);
void * of_set_callback(void *);
void *of_set_callback(void *);

int vpd_read(unsigned int , unsigned int , char *);
int vpd_write(unsigned int , unsigned int , char *);
int write_mm_log(char *, unsigned int , unsigned short );
int vpd_read(unsigned int, unsigned int, char *);
int vpd_write(unsigned int, unsigned int, char *);
int write_mm_log(char *, unsigned int, unsigned short);

#endif
2 changes: 1 addition & 1 deletion src/device/oprom/yabel/debug.c
Expand Up @@ -37,7 +37,7 @@
u32 debug_flags = 0;

void
dump(u8 * addr, u32 len)
dump(u8 *addr, u32 len)
{
printf("\n%s(%p, %x):\n", __func__, addr, len);
while (len) {
Expand Down
2 changes: 1 addition & 1 deletion src/device/oprom/yabel/debug.h
Expand Up @@ -130,6 +130,6 @@ static inline void set_ci(void) {};

#endif //DEBUG

void dump(u8 * addr, u32 len);
void dump(u8 *addr, u32 len);

#endif
2 changes: 1 addition & 1 deletion src/device/oprom/yabel/vbe.c
Expand Up @@ -321,7 +321,7 @@ vbe_set_color(u16 color_number, u32 color_value)
}

static u8
vbe_get_color(u16 color_number, u32 * color_value)
vbe_get_color(u16 color_number, u32 *color_value)
{
vbe_prepare();
// call VBE function 09h (Set/Get Palette Data Function)
Expand Down
68 changes: 68 additions & 0 deletions src/device/pci_device.c
Expand Up @@ -337,6 +337,74 @@ static void pci_get_rom_resource(struct device *dev, unsigned long index)
compact_resources(dev);
}

/**
* Given a device, read the size of the MSI-X table.
*
* @param dev Pointer to the device structure.
* @return MSI-X table size or 0 if not MSI-X capable device
*/
size_t pci_msix_table_size(struct device *dev)
{
const size_t pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
if (!pos)
return 0;

const u16 control = pci_read_config16(dev, pos + PCI_MSIX_FLAGS);
return (control & PCI_MSIX_FLAGS_QSIZE) + 1;
}

/**
* Given a device, return the table offset and bar the MSI-X tables resides in.
*
* @param dev Pointer to the device structure.
* @param offset Returned value gives the offset in bytes inside the PCI BAR.
* @param idx The returned value is the index of the PCI_BASE_ADDRESS register
* the MSI-X table is located in.
* @return Zero on success
*/
int pci_msix_table_bar(struct device *dev, u32 *offset, u8 *idx)
{
const size_t pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
if (!pos || !offset || !idx)
return 1;

*offset = pci_read_config32(dev, pos + PCI_MSIX_TABLE);
*idx = (u8)(*offset & PCI_MSIX_PBA_BIR);
*offset &= PCI_MSIX_PBA_OFFSET;

return 0;
}

/**
* Given a device, return a msix_entry pointer or NULL if no table was found.
*
* @param dev Pointer to the device structure.
*
* @return NULL on error
*/
struct msix_entry *pci_msix_get_table(struct device *dev)
{
struct resource *res;
u32 offset;
u8 idx;

if (pci_msix_table_bar(dev, &offset, &idx))
return NULL;

if (idx > 5)
return NULL;

res = probe_resource(dev, idx * 4 + PCI_BASE_ADDRESS_0);
if (!res || !res->base || offset >= res->size)
return NULL;

if ((res->flags & IORESOURCE_PCI64) &&
(uintptr_t)res->base != res->base)
return NULL;

return (struct msix_entry *)((uintptr_t)res->base + offset);
}

/**
* Read the base address registers for a given device.
*
Expand Down
9 changes: 6 additions & 3 deletions src/device/pnp_device.c
Expand Up @@ -386,10 +386,13 @@ void pnp_enable_devices(struct device *base_dev, struct device_operations *ops,
if (dev->ops)
continue;

if (info[i].ops == 0)
dev->ops = ops;
else
/* use LDN-specific ops override from corresponding pnp_info
entry if not NULL */
if (info[i].ops)
dev->ops = info[i].ops;
/* else use device ops */
else
dev->ops = ops;

get_resources(dev, &info[i]);
}
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/amd/agesa/oem_s3.c
Expand Up @@ -161,5 +161,5 @@ const void *OemS3Saved_MTRR_Storage(void)
if (!size)
return NULL;

return (void*)(pos + sizeof(UINT32));
return (void *)(pos + sizeof(UINT32));
}
2 changes: 1 addition & 1 deletion src/drivers/amd/agesa/romstage.c
Expand Up @@ -54,7 +54,7 @@ static void fill_sysinfo(struct sysinfo *cb)
agesa_set_interface(cb);
}

void * asmlinkage romstage_main(unsigned long bist)
void *asmlinkage romstage_main(unsigned long bist)
{
struct postcar_frame pcf;
struct sysinfo romstage_state;
Expand Down
10 changes: 5 additions & 5 deletions src/drivers/amd/agesa/state_machine.c
Expand Up @@ -53,7 +53,7 @@ static void agesa_locate_image(AMD_CONFIG_PARAMS *StdHeader)

image = LibAmdLocateImage(agesa, agesa + file_size, 4096,
ModuleIdentifier);
StdHeader->ImageBasePtr = (void*) image;
StdHeader->ImageBasePtr = (void *) image;
#endif
}

Expand All @@ -66,10 +66,10 @@ void agesa_set_interface(struct sysinfo *cb)
if (IS_ENABLED(CONFIG_CPU_AMD_AGESA_BINARY_PI)) {
agesa_locate_image(&cb->StdHeader);
AMD_IMAGE_HEADER *image =
(void*)(uintptr_t)cb->StdHeader.ImageBasePtr;
(void *)(uintptr_t)cb->StdHeader.ImageBasePtr;
ASSERT(image);
AMD_MODULE_HEADER *module =
(void*)(uintptr_t)image->ModuleInfoOffset;
(void *)(uintptr_t)image->ModuleInfoOffset;
ASSERT(module && module->ModuleDispatcher);
}
}
Expand All @@ -83,8 +83,8 @@ AGESA_STATUS module_dispatch(AGESA_STRUCT_NAME func,
dispatcher = AmdAgesaDispatcher;
#endif
#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_BINARY_PI)
AMD_IMAGE_HEADER *image = (void*)(uintptr_t)StdHeader->ImageBasePtr;
AMD_MODULE_HEADER *module = (void*)(uintptr_t)image->ModuleInfoOffset;
AMD_IMAGE_HEADER *image = (void *)(uintptr_t)StdHeader->ImageBasePtr;
AMD_MODULE_HEADER *module = (void *)(uintptr_t)image->ModuleInfoOffset;
dispatcher = module->ModuleDispatcher;
#endif

Expand Down
2 changes: 1 addition & 1 deletion src/drivers/aspeed/common/aspeed_coreboot.h
Expand Up @@ -73,7 +73,7 @@ struct drm_device {
};

static inline void *kzalloc(size_t size, int flags) {
void* ptr = malloc(size);
void *ptr = malloc(size);
memset(ptr, 0, size);
return ptr;
}
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/i2c/sx9310/sx9310.c
Expand Up @@ -22,7 +22,7 @@
#include <string.h>
#include "chip.h"

#define I2C_SX9310_ACPI_ID "SX9310"
#define I2C_SX9310_ACPI_ID "STH9310"
#define I2C_SX9310_ACPI_NAME "Semtech SX9310"

#define REGISTER(NAME) acpi_dp_add_integer(dsd, \
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/i2c/tpm/tpm.c
Expand Up @@ -65,7 +65,7 @@ enum i2c_chip_type {
UNKNOWN,
};

static const char * const chip_name[] = {
static const char *const chip_name[] = {
[SLB9635] = "slb9635tt",
[SLB9645] = "slb9645tt",
[UNKNOWN] = "unknown/fallback to slb9635",
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/intel/fsp1_0/fastboot_cache.c
Expand Up @@ -224,7 +224,7 @@ void update_mrc_cache(void *unused)

#endif /* !defined(__PRE_RAM__) */

void * find_and_set_fastboot_cache(void)
void *find_and_set_fastboot_cache(void)
{
struct mrc_data_container *mrc_cache = NULL;
if (((mrc_cache = find_current_mrc_cache()) == NULL) ||
Expand Down
13 changes: 7 additions & 6 deletions src/drivers/intel/fsp1_0/fsp_util.c
Expand Up @@ -75,7 +75,7 @@ void __attribute__((noreturn)) fsp_early_init (FSP_INFO_HEADER *fsp_ptr)
UPD_DATA_REGION fsp_upd_data;
#endif

memset((void*)&FspRtBuffer, 0, sizeof(FSP_INIT_RT_BUFFER));
memset((void *)&FspRtBuffer, 0, sizeof(FSP_INIT_RT_BUFFER));
FspRtBuffer.Common.StackTop = (u32 *)CONFIG_RAMTOP;
FspInitParams.NvsBufferPtr = NULL;

Expand All @@ -100,7 +100,7 @@ void __attribute__((noreturn)) fsp_early_init (FSP_INFO_HEADER *fsp_ptr)
}
#endif /* __PRE_RAM__ */

volatile u8 * find_fsp ()
volatile u8 *find_fsp()
{

#ifdef __PRE_RAM__
Expand Down Expand Up @@ -175,7 +175,7 @@ volatile u8 * find_fsp ()
* @param hob_list_ptr pointer to the start of the hob list
* @return pointer to saved CAR MEM or NULL if not found.
*/
void * find_saved_temp_mem(void *hob_list_ptr)
void *find_saved_temp_mem(void *hob_list_ptr)
{
EFI_GUID temp_hob_guid = FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID;
EFI_HOB_GUID_TYPE *saved_mem_hob =
Expand All @@ -194,7 +194,7 @@ void * find_saved_temp_mem(void *hob_list_ptr)
* @param hob_list_ptr pointer to the start of the hob list
* @return pointer to the start of the FSP reserved memory or NULL if not found.
*/
void * find_fsp_reserved_mem(void *hob_list_ptr)
void *find_fsp_reserved_mem(void *hob_list_ptr)
{
EFI_GUID fsp_reserved_guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID;
EFI_HOB_RESOURCE_DESCRIPTOR *fsp_reserved_mem =
Expand All @@ -221,7 +221,8 @@ void print_fsp_info(void) {
}

if (FspHobListPtr == NULL) {
FspHobListPtr = (void*)*((u32*) cbmem_find(CBMEM_ID_HOB_POINTER));
FspHobListPtr = (void *)*((u32 *)
cbmem_find(CBMEM_ID_HOB_POINTER));
}

printk(BIOS_SPEW,"fsp_header_ptr: %p\n", fsp_header_ptr);
Expand Down Expand Up @@ -294,7 +295,7 @@ int save_mrc_data(void *hob_start)
static void find_fsp_hob_update_mrc(void *unused)
{
/* Set the global HOB list pointer */
FspHobListPtr = (void*)*((u32*) cbmem_find(CBMEM_ID_HOB_POINTER));
FspHobListPtr = (void *)*((u32 *) cbmem_find(CBMEM_ID_HOB_POINTER));

if (!FspHobListPtr){
printk(BIOS_ERR, "ERROR: Could not find FSP HOB pointer in CBFS!\n");
Expand Down
16 changes: 8 additions & 8 deletions src/drivers/intel/fsp1_0/fsp_util.h
Expand Up @@ -22,10 +22,10 @@

#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
int save_mrc_data(void *hob_start);
void * find_and_set_fastboot_cache(void);
void *find_and_set_fastboot_cache(void);
#endif

volatile u8 * find_fsp(void);
volatile u8 *find_fsp(void);
void fsp_early_init(FSP_INFO_HEADER *fsp_info);
void FspNotify(u32 Phase);
void FspNotifyReturnPoint(EFI_STATUS Status, VOID *HobListPtr);
Expand All @@ -34,16 +34,16 @@ void print_fsp_info(void);
void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams,
FSP_INFO_HEADER *fsp_ptr);
void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr);
void * find_saved_temp_mem(void *hob_list_ptr);
void * find_fsp_reserved_mem(void *hob_list_ptr);
void *find_saved_temp_mem(void *hob_list_ptr);
void *find_fsp_reserved_mem(void *hob_list_ptr);

/* functions in hob.c */
void print_hob_mem_attributes(void *Hobptr);
void print_hob_type_structure(u16 Hobtype, void *Hoblistptr);
void print_hob_resource_attributes(void *Hobptr);
void print_guid_type_attributes(void *Hobptr);
const char * get_hob_type_string(void *Hobptr);
void * find_hob_by_guid(void *Hoblistptr, EFI_GUID *guid1);
const char *get_hob_type_string(void *Hobptr);
void *find_hob_by_guid(void *Hoblistptr, EFI_GUID *guid1);
uint8_t guids_are_equal(EFI_GUID *guid1, EFI_GUID *guid2);
void printguid(EFI_GUID *guid);

Expand Down Expand Up @@ -90,10 +90,10 @@ void update_mrc_cache(void *unused);
#define FSP_SIG 0x48505346 /* 'FSPH' */

#define ERROR_NO_FV_SIG 1
#define ERROR_NO_FFS_GUID 2
#define ERROR_NO_FFS_GUID 2
#define ERROR_NO_INFO_HEADER 3
#define ERROR_IMAGEBASE_MISMATCH 4
#define ERROR_INFO_HEAD_SIG_MISMATCH 5
#define ERROR_INFO_HEAD_SIG_MISMATCH 5
#define ERROR_FSP_SIG_MISMATCH 6

#ifndef __PRE_RAM__
Expand Down
10 changes: 5 additions & 5 deletions src/drivers/intel/fsp1_0/hob.c
Expand Up @@ -42,7 +42,7 @@ void print_hob_mem_attributes(void *Hobptr)
EFI_MEMORY_TYPE Hobmemtype = HobMemoryPtr->AllocDescriptor.MemoryType;
u64 Hobmemaddr = HobMemoryPtr->AllocDescriptor.MemoryBaseAddress;
u64 Hobmemlength = HobMemoryPtr->AllocDescriptor.MemoryLength;
const char * Hobmemtypenames[15];
const char *Hobmemtypenames[15];

Hobmemtypenames[0] = "EfiReservedMemoryType";
Hobmemtypenames[1] = "EfiLoaderCode";
Expand Down Expand Up @@ -104,7 +104,7 @@ void print_hob_resource_attributes(void *Hobptr)
(unsigned long)Hobresaddr, (unsigned long)Hobreslength);
}

const char * get_hob_type_string(void *Hobptr)
const char *get_hob_type_string(void *Hobptr)
{
EFI_HOB_GENERIC_HEADER *HobHeaderPtr = (EFI_HOB_GENERIC_HEADER *)Hobptr;
u16 Hobtype = HobHeaderPtr->HobType;
Expand Down Expand Up @@ -215,7 +215,7 @@ void print_hob_type_structure(u16 Hobtype, void *Hoblistptr)
* @param guid the GUID of the HOB entry to find
* @return pointer to the start of the requested HOB or NULL if not found.
*/
void * find_hob_by_guid(void *current_hob, EFI_GUID *guid)
void *find_hob_by_guid(void *current_hob, EFI_GUID *guid)
{
do {
switch (((EFI_HOB_GENERIC_HEADER *)current_hob)->HobType) {
Expand Down Expand Up @@ -255,8 +255,8 @@ void * find_hob_by_guid(void *current_hob, EFI_GUID *guid)
*/
uint8_t guids_are_equal(EFI_GUID *guid1, EFI_GUID *guid2)
{
uint64_t* guid_1 = (void *) guid1;
uint64_t* guid_2 = (void *) guid2;
uint64_t *guid_1 = (void *) guid1;
uint64_t *guid_2 = (void *) guid2;

if ((*(guid_1) != *(guid_2)) || (*(guid_1 + 1) != *(guid_2 + 1)))
return 0;
Expand Down
@@ -1,8 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Google Inc.
* Copyright (C) 2015 Intel Corporation
* Copyright (C) 2018 Facebook Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
Expand All @@ -14,20 +13,20 @@
* GNU General Public License for more details.
*/

#ifndef MAINBOARD_SPD_H
#define MAINBOARD_SPD_H
#ifndef _FSP2_0_MEMORY_INIT_H_
#define _FSP2_0_MEMORY_INIT_H_

#define SPD_LEN 256
#include <types.h>

#define SPD_DRAM_TYPE 2
#define SPD_DRAM_DDR3 0x0b
#define SPD_DRAM_LPDDR3 0xf1
#define SPD_DENSITY_BANKS 4
#define SPD_ADDRESSING 5
#define SPD_ORGANIZATION 7
#define SPD_BUS_DEV_WIDTH 8
#define SPD_PART_OFF 128
#define SPD_PART_LEN 18
#define SPD_MANU_OFF 148
/*
* Updates mrc cache hash if it differs.
*/
void mrc_cache_update_hash(const uint8_t *data, size_t size);

/*
* Verifies mrc cache hash which is stored somewhere.
* return 1 verification was successful and 0 for error.
*/
int mrc_cache_verify_hash(const uint8_t *data, size_t size);

#endif
#endif /* _FSP2_0_MEMORY_INIT_H_ */
105 changes: 6 additions & 99 deletions src/drivers/intel/fsp2_0/memory_init.c
Expand Up @@ -31,63 +31,10 @@
#include <string.h>
#include <symbols.h>
#include <timestamp.h>
#include <security/tpm/tspi.h>
#include <security/vboot/vboot_common.h>
#include <security/tpm/tspi.h>
#include <vb2_api.h>

static void mrc_cache_update_tpm_hash(const uint8_t *data, size_t size)
{
uint8_t data_hash[VB2_SHA256_DIGEST_SIZE];
static const uint8_t dead_hash[VB2_SHA256_DIGEST_SIZE] = {
0xba, 0xad, 0xda, 0x1a, /* BAADDA1A */
0xde, 0xad, 0xde, 0xad, /* DEADDEAD */
0xde, 0xad, 0xda, 0x1a, /* DEADDA1A */
0xba, 0xad, 0xba, 0xad, /* BAADBAAD */
0xba, 0xad, 0xda, 0x1a, /* BAADDA1A */
0xde, 0xad, 0xde, 0xad, /* DEADDEAD */
0xde, 0xad, 0xda, 0x1a, /* DEADDA1A */
0xba, 0xad, 0xba, 0xad, /* BAADBAAD */
};
const uint8_t *hash_ptr = data_hash;

/* We do not store normal mode data hash in TPM. */
if (!vboot_recovery_mode_enabled())
return;

/* Bail out early if no mrc hash space is supported in TPM. */
if (!IS_ENABLED(CONFIG_FSP2_0_USES_TPM_MRC_HASH))
return;

/* Initialize TPM driver. */
if (tlcl_lib_init() != VB2_SUCCESS) {
printk(BIOS_ERR, "MRC: TPM driver initialization failed.\n");
return;
}

/* Calculate hash of data generated by MRC. */
if (vb2_digest_buffer(data, size, VB2_HASH_SHA256, data_hash,
sizeof(data_hash))) {
printk(BIOS_ERR, "MRC: SHA-256 calculation failed for data. "
"Not updating TPM hash space.\n");
/*
* Since data is being updated in recovery cache, the hash
* currently stored in TPM recovery hash space is no longer
* valid. If we are not able to calculate hash of the data being
* updated, reset all the bits in TPM recovery hash space to
* pre-defined hash pattern.
*/
hash_ptr = dead_hash;
}

/* Write hash of data to TPM space. */
if (antirollback_write_space_rec_hash(hash_ptr, VB2_SHA256_DIGEST_SIZE)
!= TPM_SUCCESS) {
printk(BIOS_ERR, "MRC: Could not save hash to TPM.\n");
return;
}

printk(BIOS_INFO, "MRC: TPM MRC hash updated successfully.\n");
}
#include <fsp/memory_init.h>

static void save_memory_training_data(bool s3wake, uint32_t fsp_version)
{
Expand All @@ -113,7 +60,8 @@ static void save_memory_training_data(bool s3wake, uint32_t fsp_version)
mrc_data_size) < 0)
printk(BIOS_ERR, "Failed to stash MRC data\n");

mrc_cache_update_tpm_hash(mrc_data, mrc_data_size);
if (IS_ENABLED(CONFIG_FSP2_0_USES_TPM_MRC_HASH))
mrc_cache_update_hash(mrc_data, mrc_data_size);
}

static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version)
Expand Down Expand Up @@ -156,48 +104,6 @@ static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version)
tpm_setup(s3wake);
}

static int mrc_cache_verify_tpm_hash(const uint8_t *data, size_t size)
{
uint8_t data_hash[VB2_SHA256_DIGEST_SIZE];
uint8_t tpm_hash[VB2_SHA256_DIGEST_SIZE];

/* We do not store normal mode data hash in TPM. */
if (!vboot_recovery_mode_enabled())
return 1;

if (!IS_ENABLED(CONFIG_FSP2_0_USES_TPM_MRC_HASH))
return 1;

/* Calculate hash of data read from RECOVERY_MRC_CACHE. */
if (vb2_digest_buffer(data, size, VB2_HASH_SHA256, data_hash,
sizeof(data_hash))) {
printk(BIOS_ERR, "MRC: SHA-256 calculation failed for data.\n");
return 0;
}

/* Initialize TPM driver. */
if (tlcl_lib_init() != VB2_SUCCESS) {
printk(BIOS_ERR, "MRC: TPM driver initialization failed.\n");
return 0;
}

/* Read hash of MRC data saved in TPM. */
if (antirollback_read_space_rec_hash(tpm_hash, sizeof(tpm_hash))
!= TPM_SUCCESS) {
printk(BIOS_ERR, "MRC: Could not read hash from TPM.\n");
return 0;
}

if (memcmp(tpm_hash, data_hash, sizeof(tpm_hash))) {
printk(BIOS_ERR, "MRC: Hash comparison failed.\n");
return 0;
}

printk(BIOS_INFO, "MRC: Hash comparison successful. "
"Using data from RECOVERY_MRC_CACHE\n");
return 1;
}

static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version)
{
struct region_device rdev;
Expand Down Expand Up @@ -230,7 +136,8 @@ static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version)
if (data == NULL)
return;

if (!mrc_cache_verify_tpm_hash(data, region_device_sz(&rdev)))
if (IS_ENABLED(CONFIG_FSP2_0_USES_TPM_MRC_HASH) &&
!mrc_cache_verify_hash(data, region_device_sz(&rdev)))
return;

/* MRC cache found */
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/intel/gma/Kconfig
Expand Up @@ -95,7 +95,7 @@ config GFX_GMA_INTERNAL_IS_EDP

config GFX_GMA_INTERNAL_IS_LVDS
bool
default y if NORTHBRIDGE_INTEL_GM45
default y if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_NEHALEM
default n

config GFX_GMA_INTERNAL_PORT
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/intel/gma/edid.c
Expand Up @@ -39,7 +39,7 @@ static void wait_rdy(u8 *mmio)
}
}

static void intel_gmbus_stop_bus(u8 * mmio, u8 bus)
static void intel_gmbus_stop_bus(u8 *mmio, u8 bus)
{
wait_rdy(mmio);
write32(GMBUS0_ADDR, bus);
Expand Down
12 changes: 6 additions & 6 deletions src/drivers/intel/i210/i210.c
Expand Up @@ -26,7 +26,7 @@

/* This is a private function to wait for a bit mask in a given register */
/* To avoid endless loops, a time-out is implemented here. */
static int wait_done(uint32_t* reg, uint32_t mask)
static int wait_done(uint32_t *reg, uint32_t mask)
{
uint32_t timeout = I210_POLL_TIMEOUT_US;

Expand Down Expand Up @@ -58,7 +58,7 @@ static uint32_t read_flash(struct device *dev, uint32_t address,
bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
if ((!bar) || ((address + count) > 0x40))
return I210_INVALID_PARAM;
eeprd = (uint32_t*)(bar + I210_REG_EEREAD);
eeprd = (uint32_t *)(bar + I210_REG_EEREAD);
/* Prior to start ensure flash interface is ready by checking DONE-bit */
if (wait_done(eeprd, I210_DONE))
return I210_NOT_READY;
Expand Down Expand Up @@ -122,8 +122,8 @@ static uint32_t write_flash(struct device *dev, uint32_t address,
bar = pci_read_config32(dev, 0x10);
if ((!bar) || ((address + count) > 0x40))
return I210_INVALID_PARAM;
eepwr = (uint32_t*)(bar + I210_REG_EEWRITE);
eectrl = (uint32_t*)(bar + I210_REG_EECTRL);
eepwr = (uint32_t *)(bar + I210_REG_EEWRITE);
eectrl = (uint32_t *)(bar + I210_REG_EECTRL);
/* Prior to start ensure flash interface is ready by checking DONE-bit */
if (wait_done(eepwr, I210_DONE))
return I210_NOT_READY;
Expand Down Expand Up @@ -166,7 +166,7 @@ static uint32_t read_mac_adr(struct device *dev, uint8_t *mac_adr)
return I210_READ_ERROR;
/* Copy the address into destination. This is done because of possible */
/* not matching alignment for destination to uint16_t boundary. */
memcpy(mac_adr, (uint8_t*)adr, 6);
memcpy(mac_adr, (uint8_t *)adr, 6);
return I210_SUCCESS;
}

Expand All @@ -181,7 +181,7 @@ static uint32_t write_mac_adr(struct device *dev, uint8_t *mac_adr)
if (!dev || !mac_adr)
return I210_INVALID_PARAM;
/* Copy desired address into a local buffer to avoid alignment issues */
memcpy((uint8_t*)adr, mac_adr, 6);
memcpy((uint8_t *)adr, mac_adr, 6);
return write_flash(dev, 0, 3, adr);
}

Expand Down
24 changes: 23 additions & 1 deletion src/drivers/intel/wifi/Kconfig
Expand Up @@ -11,7 +11,9 @@ config USE_SAR
default n
help
Enable it when wifi driver uses SAR configuration feature.
VPD entry "wifi_sar" is required to support it.
VPD entry "wifi_sar" is read to get SAR settings, if its
not found driver may look into CBFS for default settigs.
WIFI_SAR_CBFS is option to enable CBFS lookup.

config SAR_ENABLE
bool
Expand All @@ -23,6 +25,26 @@ config DSAR_ENABLE
default n
depends on USE_SAR

config GEO_SAR_ENABLE
bool
default n
depends on USE_SAR

config WIFI_SAR_CBFS
bool
default n
depends on USE_SAR
help
wifi driver would look for "wifi_sar" vpd key and load SAR settings from
it, if the vpd key is not found then the driver tries to look for sar
settings from CBFS with file name wifi_sar_defaults.hex.
So OEM/ODM can override wifi sar with VPD.

config WIFI_SAR_CBFS_FILEPATH
string "The cbfs file which has WIFI SAR defaults"
depends on WIFI_SAR_CBFS
default "src/mainboard/$(MAINBOARDDIR)/wifi_sar_defaults.hex"

config DSAR_SET_NUM
hex "Number of SAR sets when D-SAR is enabled"
default 0x3
Expand Down
4 changes: 4 additions & 0 deletions src/drivers/intel/wifi/Makefile.inc
Expand Up @@ -12,3 +12,7 @@
#

ramstage-$(CONFIG_DRIVERS_INTEL_WIFI) += wifi.c

cbfs-files-$(CONFIG_WIFI_SAR_CBFS) += wifi_sar_defaults.hex
wifi_sar_defaults.hex-file := $(call strip_quotes,$(CONFIG_WIFI_SAR_CBFS_FILEPATH))
wifi_sar_defaults.hex-type := raw
3 changes: 3 additions & 0 deletions src/drivers/intel/wifi/chip.h
Expand Up @@ -28,6 +28,9 @@
/* EWRD Domain type */
#define EWRD_DOMAIN_TYPE_WIFI 0x7

/* WGDS Domain type */
#define WGDS_DOMAIN_TYPE_WIFI 0x7

struct drivers_intel_wifi_config {
unsigned wake; /* Wake pin for ACPI _PRW */
};
Expand Down
55 changes: 55 additions & 0 deletions src/drivers/intel/wifi/wifi.c
Expand Up @@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Vladimir Serbinenko
* Copyright (C) 2018 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
Expand Down Expand Up @@ -75,6 +76,7 @@ static void emit_sar_acpi_structures(void)
{
int i, j, package_size;
struct wifi_sar_limits sar_limits;
struct wifi_sar_delta_table *wgds;

/* Retrieve the sar limits data */
if (get_wifi_sar_limits(&sar_limits) < 0) {
Expand Down Expand Up @@ -135,6 +137,59 @@ static void emit_sar_acpi_structures(void)
acpigen_write_byte(sar_limits.sar_limit[i][j]);
acpigen_pop_len();
acpigen_pop_len();


if (!IS_ENABLED(CONFIG_GEO_SAR_ENABLE))
return;

/*
* Name ("WGDS", Package() {
* Revision,
* Package() {
* DomainType, // 0x7:WiFi
* WgdsWiFiSarDeltaGroup1PowerMax1, // Group 1 FCC 2400 Max
* WgdsWiFiSarDeltaGroup1PowerChainA1, // Group 1 FCC 2400 A Offset
* WgdsWiFiSarDeltaGroup1PowerChainB1, // Group 1 FCC 2400 B Offset
* WgdsWiFiSarDeltaGroup1PowerMax2, // Group 1 FCC 5200 Max
* WgdsWiFiSarDeltaGroup1PowerChainA2, // Group 1 FCC 5200 A Offset
* WgdsWiFiSarDeltaGroup1PowerChainB2, // Group 1 FCC 5200 B Offset
* WgdsWiFiSarDeltaGroup2PowerMax1, // Group 2 EC Jap 2400 Max
* WgdsWiFiSarDeltaGroup2PowerChainA1, // Group 2 EC Jap 2400 A Offset
* WgdsWiFiSarDeltaGroup2PowerChainB1, // Group 2 EC Jap 2400 B Offset
* WgdsWiFiSarDeltaGroup2PowerMax2, // Group 2 EC Jap 5200 Max
* WgdsWiFiSarDeltaGroup2PowerChainA2, // Group 2 EC Jap 5200 A Offset
* WgdsWiFiSarDeltaGroup2PowerChainB2, // Group 2 EC Jap 5200 B Offset
* WgdsWiFiSarDeltaGroup3PowerMax1, // Group 3 ROW 2400 Max
* WgdsWiFiSarDeltaGroup3PowerChainA1, // Group 3 ROW 2400 A Offset
* WgdsWiFiSarDeltaGroup3PowerChainB1, // Group 3 ROW 2400 B Offset
* WgdsWiFiSarDeltaGroup3PowerMax2, // Group 3 ROW 5200 Max
* WgdsWiFiSarDeltaGroup3PowerChainA2, // Group 3 ROW 5200 A Offset
* WgdsWiFiSarDeltaGroup3PowerChainB2, // Group 3 ROW 5200 B Offset
* }
* })
*/

wgds = &sar_limits.wgds;
acpigen_write_name("WGDS");
acpigen_write_package(2);
acpigen_write_dword(wgds->version);
/* Emit 'Domain Type' +
* Group specific delta of power ( 6 bytes * NUM_WGDS_SAR_GROUPS )
*/
package_size = sizeof(sar_limits.wgds.group) + 1;
acpigen_write_package(package_size);
acpigen_write_dword(WGDS_DOMAIN_TYPE_WIFI);
for (i = 0; i < SAR_NUM_WGDS_GROUPS; i++) {
acpigen_write_byte(wgds->group[i].power_max_2400mhz);
acpigen_write_byte(wgds->group[i].power_chain_a_2400mhz);
acpigen_write_byte(wgds->group[i].power_chain_b_2400mhz);
acpigen_write_byte(wgds->group[i].power_max_5200mhz);
acpigen_write_byte(wgds->group[i].power_chain_a_5200mhz);
acpigen_write_byte(wgds->group[i].power_chain_b_5200mhz);
}

acpigen_pop_len();
acpigen_pop_len();
}

static void intel_wifi_fill_ssdt(struct device *dev)
Expand Down
8 changes: 4 additions & 4 deletions src/drivers/pc80/tpm/tis.c
Expand Up @@ -109,13 +109,13 @@
*/
struct device_name {
u16 dev_id;
const char * const dev_name;
const char *const dev_name;
};

struct vendor_name {
u16 vendor_id;
const char * vendor_name;
const struct device_name* dev_names;
const char *vendor_name;
const struct device_name *dev_names;
};

static const struct device_name atmel_devices[] = {
Expand Down Expand Up @@ -443,7 +443,7 @@ static u32 tis_probe(void)
* Returns 0 on success, TPM_DRIVER_ERR on error (in case the device does
* not accept the entire command).
*/
static u32 tis_senddata(const u8 * const data, u32 len)
static u32 tis_senddata(const u8 *const data, u32 len)
{
u32 offset = 0;
u16 burst = 0;
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/usb/ehci_debug.c
Expand Up @@ -631,7 +631,7 @@ void usbdebug_re_enable(unsigned ehci_base)

diff = (unsigned)dbg_info->ehci_base - ehci_base;
dbg_info->ehci_debug -= diff;
dbg_info->ehci_base = (void*)ehci_base;
dbg_info->ehci_base = (void *)ehci_base;

for (i=0; i<DBGP_MAX_ENDPOINTS; i++)
if (dbg_info->ep_pipe[i].status & DBGP_EP_VALID)
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/usb/gadget.c
Expand Up @@ -29,7 +29,7 @@
#define USB_HUB_C_PORT_RESET 20


static int hub_port_status(const char * buf, int feature)
static int hub_port_status(const char *buf, int feature)
{
return !!(buf[feature>>3] & (1<<(feature&0x7)));
}
Expand Down
5 changes: 3 additions & 2 deletions src/drivers/xgi/common/xgi_coreboot.c
Expand Up @@ -130,8 +130,9 @@ int xgifb_probe(struct pci_dev *pdev, struct xgifb_video_info *xgifb_info)

hw_info->ulVideoMemorySize = xgifb_info->video_size;

xgifb_info->video_vbase = hw_info->pjVideoMemoryAddress = (void*)(intptr_t)xgifb_info->video_base;
xgifb_info->mmio_vbase = (void*)(intptr_t)xgifb_info->mmio_base;
xgifb_info->video_vbase = hw_info->pjVideoMemoryAddress =
(void *)(intptr_t)xgifb_info->video_base;
xgifb_info->mmio_vbase = (void *)(intptr_t)xgifb_info->mmio_base;

dev_info(&pdev->dev,
"Framebuffer at 0x%Lx, mapped to 0x%p, size %dk\n",
Expand Down
2 changes: 1 addition & 1 deletion src/ec/google/chromeec/crosec_proto.c
Expand Up @@ -24,7 +24,7 @@
#include "ec_message.h"

/* Common utilities */
void * __weak crosec_get_buffer(size_t size, int req)
void *__weak crosec_get_buffer(size_t size, int req)
{
printk(BIOS_DEBUG, "crosec_get_buffer() implementation required.\n");
return NULL;
Expand Down
1 change: 1 addition & 0 deletions src/ec/lenovo/h8/Makefile.inc
Expand Up @@ -8,6 +8,7 @@ endif
ramstage-y += h8.c
ramstage-y += bluetooth.c
ramstage-y += wwan.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ssdt.c
smm-y += smm.c

endif
140 changes: 4 additions & 136 deletions src/ec/lenovo/h8/acpi/ec.asl
Expand Up @@ -46,6 +46,9 @@ Device(EC)
Offset (0x30),
, 6,
ALMT, 1, /* Audio Mute + LED */
Offset (0x31),
, 2,
UWBE, 1, /* Ultra Wideband enable */
Offset (0x3a),
AMUT, 1, /* Audio Mute (internal use) */
, 3,
Expand Down Expand Up @@ -304,147 +307,12 @@ Device(EC)
}
}

Device (HKEY)
{
Name (_HID, EisaId ("IBM0068"))
Name (BTN, 0)
Name (BTAB, 0)

/* MASK */
Name (DHKN, 0x080C)

/* Effective Mask */
Name (EMSK, 0)

/* Effective Mask for tablet */
Name (ETAB, 0)

/* Device enabled. */
Name (EN, 0)

Method (_STA, 0, NotSerialized)
{
Return (0x0F)
}

/* Retrieve event. */
Method (MHKP, 0, NotSerialized)
{
Store (BTN, Local0)
If (LNotEqual (Local0, Zero)) {
Store (Zero, BTN)
Add (Local0, 0x1000, Local0)
Return (Local0)
}
Store (BTAB, Local0)
If (LNotEqual (Local0, Zero)) {
Store (Zero, BTAB)
Add (Local0, 0x5000, Local0)
Return (Local0)
}
Return (Zero)
}

/* Report event */
Method (RHK, 1, NotSerialized) {
ShiftLeft (One, Subtract (Arg0, 1), Local0)
If (And (EMSK, Local0)) {
Store (Arg0, BTN)
Notify (HKEY, 0x80)
}
}

/* Report tablet */
Method (RTAB, 1, NotSerialized) {
ShiftLeft (One, Subtract (Arg0, 1), Local0)
If (And (ETAB, Local0)) {
Store (Arg0, BTAB)
Notify (HKEY, 0x80)
}
}

/* Enable/disable all events. */
Method (MHKC, 1, NotSerialized) {
If (Arg0) {
Store (DHKN, EMSK)
Store (Ones, ETAB)
}
Else
{
Store (Zero, EMSK)
Store (Zero, ETAB)
}
Store (Arg0, EN)
}

/* Enable/disable event. */
Method (MHKM, 2, NotSerialized) {
If (LLessEqual (Arg0, 0x20)) {
ShiftLeft (One, Subtract (Arg0, 1), Local0)
If (Arg1)
{
Or (DHKN, Local0, DHKN)
}
Else
{
And (DHKN, Not (Local0), DHKN)
}
If (EN)
{
Store (DHKN, EMSK)
}
}
}

/* Mask hotkey all. */
Method (MHKA, 0, NotSerialized)
{
Return (0x07FFFFFF)
}

/* Report tablet mode switch state */
Method (MHKG, 0, NotSerialized)
{
Return (ShiftLeft(TBSW, 3))
}

/* Mute audio */
Method (SSMS, 1, NotSerialized)
{
Store(Arg0, ALMT)
}

/* Control mute microphone LED */
Method (MMTS, 1, NotSerialized)
{
If (Arg0)
{
TLED(0x8E)
}
Else
{
TLED(0x0E)
}
}

/* Version */
Method (MHKV, 0, NotSerialized)
{
Return (0x0100)
}

/* Master wireless switch state */
Method (WLSW, 0, NotSerialized)
{
Return (\_SB.PCI0.LPCB.EC.GSTS)
}
}

#include "ac.asl"
#include "battery.asl"
#include "sleepbutton.asl"
#include "lid.asl"
#include "beep.asl"
#include "thermal.asl"
#include "systemstatus.asl"
#include "thinkpad.asl"
}
326 changes: 326 additions & 0 deletions src/ec/lenovo/h8/acpi/thinkpad.asl
@@ -0,0 +1,326 @@
/*
* This file is part of the coreboot project.
*
* Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

Device (HKEY)
{
/* Generated by ssdt.c */
External (\HBDC, IntObj)
External (\HWAN, IntObj)
External (\HKBL, IntObj)
External (\HUWB, IntObj)

Name (_HID, EisaId ("IBM0068"))

Name (BTN, 0)

Name (BTAB, 0)

/* MASK */
Name (DHKN, 0x080C)

/* Effective Mask */
Name (EMSK, 0)

/* Effective Mask for tablet */
Name (ETAB, 0)

/* Device enabled. */
Name (EN, 0)

Method (_STA, 0, NotSerialized)
{
Return (0x0F)
}

/* Retrieve event. */
Method (MHKP, 0, NotSerialized)
{
Store (BTN, Local0)
If (LNotEqual (Local0, Zero)) {
Store (Zero, BTN)
Add (Local0, 0x1000, Local0)
Return (Local0)
}
Store (BTAB, Local0)
If (LNotEqual (Local0, Zero)) {
Store (Zero, BTAB)
Add (Local0, 0x5000, Local0)
Return (Local0)
}
Return (Zero)
}

/* Report event */
Method (RHK, 1, NotSerialized) {
ShiftLeft (One, Subtract (Arg0, 1), Local0)
If (And (EMSK, Local0)) {
Store (Arg0, BTN)
Notify (HKEY, 0x80)
}
}

/* Report tablet */
Method (RTAB, 1, NotSerialized) {
ShiftLeft (One, Subtract (Arg0, 1), Local0)
If (And (ETAB, Local0)) {
Store (Arg0, BTAB)
Notify (HKEY, 0x80)
}
}

/* Enable/disable all events. */
Method (MHKC, 1, NotSerialized) {
If (Arg0) {
Store (DHKN, EMSK)
Store (Ones, ETAB)
}
Else
{
Store (Zero, EMSK)
Store (Zero, ETAB)
}
Store (Arg0, EN)
}

/* Enable/disable event. */
Method (MHKM, 2, NotSerialized) {
If (LLessEqual (Arg0, 0x20)) {
ShiftLeft (One, Subtract (Arg0, 1), Local0)
If (Arg1)
{
Or (DHKN, Local0, DHKN)
}
Else
{
And (DHKN, Not (Local0), DHKN)
}
If (EN)
{
Store (DHKN, EMSK)
}
}
}

/* Mask hotkey all. */
Method (MHKA, 0, NotSerialized)
{
Return (0x07FFFFFF)
}

/* Report tablet mode switch state */
Method (MHKG, 0, NotSerialized)
{
Return (ShiftLeft(TBSW, 3))
}

/* Mute audio */
Method (SSMS, 1, NotSerialized)
{
Store(Arg0, ALMT)
}

/* Control mute microphone LED */
Method (MMTS, 1, NotSerialized)
{
If (Arg0)
{
TLED(0x8E)
}
Else
{
TLED(0x0E)
}
}

/* Version */
Method (MHKV, 0, NotSerialized)
{
Return (0x0100)
}

/* Master wireless switch state */
Method (WLSW, 0, NotSerialized)
{
Return (\_SB.PCI0.LPCB.EC.GSTS)
}

/* Has thinkpad_acpi module loaded */
Name (HAST, 0)

/* State after sleep */
Name (WBDC, 0)
/*
* Returns the current state:
* Bit 0: BT HW present
* Bit 1: BT radio enabled
* Bit 2: BT state at resume
*/
Method (GBDC, 0)
{
Store (One, HAST)

If (HBDC) {
Store(One, Local0)
If(\_SB.PCI0.LPCB.EC.BTEB)
{
Or(Local0, 2, Local0)
}
Or(Local0, ShiftLeft(WBDC, 2), Local0)
Return (Local0)
} Else {
Return (0)
}
}

/*
* Set the current state:
* Bit 1: BT radio enabled
* Bit 2: BT state at resume
*/
Method (SBDC, 1)
{
Store (One, HAST)

If (HBDC) {
ShiftRight (And(Arg0, 2), 1, Local0)
Store (Local0, \_SB.PCI0.LPCB.EC.BTEB)
ShiftRight (And(Arg0, 4), 2, Local0)
Store (Local0, WBDC)
}
}

/* State after sleep */
Name (WWAN, 0)
/*
* Returns the current state:
* Bit 0: WWAN HW present
* Bit 1: WWAN radio enabled
* Bit 2: WWAN state at resume
*/
Method (GWAN, 0)
{
Store (One, HAST)

If (HWAN) {
Store(One, Local0)
If(\_SB.PCI0.LPCB.EC.WWEB)
{
Or(Local0, 2, Local0)
}
Or(Local0, ShiftLeft(WWAN, 2), Local0)
Return (Local0)
} Else {
Return (0)
}
}

/*
* Set the current state:
* Bit 1: WWAN radio enabled
* Bit 2: WWAN state at resume
*/
Method (SWAN, 1)
{
Store (One, HAST)

If (HWAN) {
ShiftRight (And(Arg0, 2), 1, Local0)
Store (Local0, \_SB.PCI0.LPCB.EC.WWEB)
ShiftRight (And(Arg0, 4), 2, WWAN)
}
}

/*
* Argument is unused.
* Returns the current state:
* Bit 9: Backlight HW present
* Bit 0-1: Brightness level
*/
Method (MLCG, 1)
{
If (HKBL) {
Store (0x200, Local0)
/* FIXME: Support 2bit brightness control */
Or (Local0, \_SB.PCI0.LPCB.EC.KBLT, Local0)
Return (Local0)
} Else {
Return (0)
}
}

/*
* Set the current state:
* Bit 0-1: Brightness level
*/
Method (MLCS, 1)
{
If (HKBL) {
/* FIXME: Support 2bit brightness control */
Store (And(Arg0, 1), \_SB.PCI0.LPCB.EC.WWEB)
}
}

/*
* Returns the current state:
* Bit 0: UWB HW present
* Bit 1: UWB radio enabled
*/
Method (GUWB, 0)
{
If (HUWB) {
Store (One, Local0)
If(\_SB.PCI0.LPCB.EC.UWBE)
{
Or(Local0, 2, Local0)
}
Return (Local0)
} Else {
Return (0)
}
}

/*
* Set the current state:
* Bit 1: UWB radio enabled
*/
Method (SUWB, 1)
{
If (HUWB) {
ShiftRight (And(Arg0, 2), 1, Local0)
Store (Local0, \_SB.PCI0.LPCB.EC.UWBE)
}
}

/*
* Store initial state
*/
Method (_INI, 0, NotSerialized)
{
Store (\_SB.PCI0.LPCB.EC.BTEB, WBDC)
Store (\_SB.PCI0.LPCB.EC.WWEB, WWAN)
}

/*
* Called from _WAK
*/
Method (WAKE, 1)
{
If (HAST) {
Store (WBDC, \_SB.PCI0.LPCB.EC.BTEB)
Store (WWAN, \_SB.PCI0.LPCB.EC.WWEB)
}
}
}
11 changes: 11 additions & 0 deletions src/ec/lenovo/h8/h8.c
Expand Up @@ -181,9 +181,20 @@ static void h8_init(struct device *dev)
pc_keyboard_init(NO_AUX_DEVICE);
}

#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
static const char *h8_acpi_name(const struct device *dev)
{
return "EC";
}
#endif

struct device_operations h8_dev_ops = {
#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)
.get_smbios_strings = h8_smbios_strings,
#endif
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
.acpi_fill_ssdt_generator = h8_ssdt_generator,
.acpi_name = h8_acpi_name,
#endif
.init = h8_init,
};
Expand Down
2 changes: 2 additions & 0 deletions src/ec/lenovo/h8/h8.h
Expand Up @@ -39,6 +39,8 @@ void h8_wwan_enable(int on);
bool h8_wwan_nv_enable(void);
bool h8_has_wwan(struct device *dev);

void h8_ssdt_generator(struct device *dev);

/* EC registers */
#define H8_CONFIG0 0x00
#define H8_CONFIG0_EVENTS_ENABLE 0x02
Expand Down
58 changes: 58 additions & 0 deletions src/ec/lenovo/h8/ssdt.c
@@ -0,0 +1,58 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Patrick Rudolph <siro@das-labor.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include <console/console.h>
#include <arch/acpigen.h>
#include <string.h>

#include "h8.h"
#include "chip.h"

static char *h8_dsdt_scope(struct device *dev, const char *scope)
{
static char buf[DEVICE_PATH_MAX] = {};
const char *path = acpi_device_path(dev);

memset(buf, 0, sizeof(buf));
snprintf(buf, sizeof(buf) - 1, "%s.%s", path, scope);

return buf;
}

/*
* Generates EC SSDT.
*/
void h8_ssdt_generator(struct device *dev)
{
struct ec_lenovo_h8_config *conf = dev->chip_info;

if (!acpi_device_path(dev))
return;

printk(BIOS_INFO, "ACPI: * H8\n");

/* Scope HKEY */
acpigen_write_scope(h8_dsdt_scope(dev, "HKEY"));

/* Used by thinkpad_acpi */
acpigen_write_name_byte("HBDC", h8_has_bdc(dev) ? ONE_OP : ZERO_OP);
acpigen_write_name_byte("HWAN", h8_has_wwan(dev) ? ONE_OP : ZERO_OP);
acpigen_write_name_byte("HKBL", (conf && conf->has_keyboard_backlight) ?
ONE_OP : ZERO_OP);
acpigen_write_name_byte("HUWB", (conf && conf->has_uwb) ?
ONE_OP : ZERO_OP);

acpigen_pop_len(); /* Scope HKEY */
}
3 changes: 2 additions & 1 deletion src/include/boot/tables.h
Expand Up @@ -6,8 +6,9 @@
/*
* Write architecture specific tables as well as the common
* coreboot table.
* Returns a pointer to the table or NULL on error.
*/
void write_tables(void);
void *write_tables(void);

/*
* Allow per-architecture table writes called from write_tables(). The
Expand Down
4 changes: 2 additions & 2 deletions src/include/cpu/amd/car.h
Expand Up @@ -4,14 +4,14 @@
#include <arch/cpu.h>

void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
asmlinkage void * post_cache_as_ram(void);
asmlinkage void *post_cache_as_ram(void);
asmlinkage void cache_as_ram_new_stack(void);

void disable_cache_as_ram(void);

void asmlinkage early_all_cores(void);

void * asmlinkage romstage_main(unsigned long bist);
void *asmlinkage romstage_main(unsigned long bist);
void asmlinkage romstage_after_car(void);

#endif
18 changes: 18 additions & 0 deletions src/include/device/pci.h
Expand Up @@ -56,6 +56,20 @@ struct pci_driver {
const unsigned short *devices;
};

struct msix_entry {
union {
struct {
u32 lower_addr;
u32 upper_addr;
};
struct {
u64 addr;
};
};
u32 data;
u32 vec_control;
};

#ifdef __SIMPLE_DEVICE__
#define __pci_driver __attribute__((unused))
#else
Expand Down Expand Up @@ -104,6 +118,10 @@ void pci_assign_irqs(unsigned int bus, unsigned int slot,
const char *get_pci_class_name(struct device *dev);
const char *get_pci_subclass_name(struct device *dev);

size_t pci_msix_table_size(struct device *dev);
int pci_msix_table_bar(struct device *dev, u32 *offset, u8 *idx);
struct msix_entry *pci_msix_get_table(struct device *dev);

#define PCI_IO_BRIDGE_ALIGN 4096
#define PCI_MEM_BRIDGE_ALIGN (1024*1024)

Expand Down
12 changes: 12 additions & 0 deletions src/include/device/pci_def.h
Expand Up @@ -292,6 +292,18 @@
#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
#define PCI_MSI_MASK_BIT 16 /* Mask bits register */

/* MSI-X registers */
#define PCI_MSIX_FLAGS 2
#define PCI_MSIX_FLAGS_QSIZE 0x7FF /* table size */
#define PCI_MSIX_FLAGS_MASKALL 0x4000 /* Mask all vectors for this function */
#define PCI_MSIX_FLAGS_ENABLE 0x8000 /* MSI-X enable */
#define PCI_MSIX_TABLE 4 /* Table offset */
#define PCI_MSIX_PBA 8 /* Pending Bit Array offset */
#define PCI_MSIX_PBA_BIR 0x7 /* BAR index */
#define PCI_MSIX_PBA_OFFSET ~0x7 /* Offset into specified BAR */
#define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */


/* CompactPCI Hotswap Register */

#define PCI_CHSWP_CSR 2 /* Control and Status Register */
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1 change: 1 addition & 0 deletions src/include/device/pci_ids.h
Expand Up @@ -297,6 +297,7 @@
#define PCI_DEVICE_ID_AMD_10H_NB_HT 0x1200
#define PCI_DEVICE_ID_AMD_15H_NB_IOMMU 0x1419
#define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU 0x1423
#define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_IOMMU 0x1567

#define PCI_DEVICE_ID_ATI_SB600_LPC 0x438D
#define PCI_DEVICE_ID_ATI_SB600_SATA 0x4380
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2 changes: 1 addition & 1 deletion src/include/device/pnp.h
Expand Up @@ -31,7 +31,7 @@ extern struct device_operations pnp_ops;
/* PNP helper operations */

struct pnp_info {
struct device_operations *ops;
struct device_operations *ops; /* LDN-specific ops override */
unsigned int function; /* Must be at least 16 bits (virtual LDNs)! */
unsigned int flags;
#define PNP_IO0 0x000001
Expand Down
26 changes: 23 additions & 3 deletions src/include/sar.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Intel Corp.
* Copyright (C) 2017-2018 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
Expand All @@ -15,22 +15,42 @@
#ifndef _SAR_H_
#define _SAR_H_

#include <compiler.h>
#include <stdint.h>

#define NUM_SAR_LIMITS 4
#define BYTES_PER_SAR_LIMIT 10
enum {
SAR_FCC,
SAR_EUROPE_JAPAN,
SAR_REST_OF_WORLD,
SAR_NUM_WGDS_GROUPS
};

struct wifi_sar_delta_table {
uint8_t version;
struct {
uint8_t power_max_2400mhz;
uint8_t power_chain_a_2400mhz;
uint8_t power_chain_b_2400mhz;
uint8_t power_max_5200mhz;
uint8_t power_chain_a_5200mhz;
uint8_t power_chain_b_5200mhz;
} __packed group[SAR_NUM_WGDS_GROUPS];
} __packed;

/* Wifi SAR limit table structure */
struct wifi_sar_limits {
/* Total 4 SAR limit sets, each has 10 bytes */
uint8_t sar_limit[NUM_SAR_LIMITS][BYTES_PER_SAR_LIMIT];
};
struct wifi_sar_delta_table wgds;
} __packed;

/*
* Retrieve the SAR limits data from VPD and decode it.
* sar_limits: Pointer to wifi_sar_limits where the resulted data is stored
*
* Returns: 0 on success, -1 on errors (The VPD entry doesn't exist, or the
* Returns: 0 on success, -1 on errors (The VPD entry doesn't exist, or the
* VPD entry contains non-heximal value.)
*/
int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits);
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14 changes: 14 additions & 0 deletions src/include/smbios.h
Expand Up @@ -26,6 +26,12 @@ int smbios_add_string(u8 *start, const char *str);
int smbios_string_table_len(u8 *start);

/* Used by mainboard to add an on-board device */
enum smbios_bmc_interface_type;
int smbios_write_type38(unsigned long *current, int *handle,
const enum smbios_bmc_interface_type interface_type,
const u8 ipmi_rev, const u8 i2c_addr, const u8 nv_addr,
const u64 base_addr, const u8 base_modifier,
const u8 irq);
int smbios_write_type41(unsigned long *current, int *handle,
const char *name, u8 instance, u16 segment,
u8 bus, u8 device, u8 function);
Expand Down Expand Up @@ -216,6 +222,7 @@ typedef enum {
SMBIOS_MEMORY_DEVICE = 17,
SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS = 19,
SMBIOS_SYSTEM_BOOT_INFORMATION = 32,
SMBIOS_IPMI_DEVICE_INFORMATION = 38,
SMBIOS_ONBOARD_DEVICES_EXTENDED_INFORMATION = 41,
SMBIOS_END_OF_TABLE = 127,
} smbios_struct_type_t;
Expand Down Expand Up @@ -497,6 +504,13 @@ struct smbios_type38 {
u8 irq;
} __packed;

enum smbios_bmc_interface_type {
SMBIOS_BMC_INTERFACE_UNKNOWN = 0,
SMBIOS_BMC_INTERFACE_KCS,
SMBIOS_BMC_INTERFACE_SMIC,
SMBIOS_BMC_INTERFACE_BLOCK,
};

typedef enum {
SMBIOS_DEVICE_TYPE_OTHER = 0x01,
SMBIOS_DEVICE_TYPE_UNKNOWN,
Expand Down
5 changes: 3 additions & 2 deletions src/lib/coreboot_table.c
Expand Up @@ -585,7 +585,7 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end)
return lb_table_fini(head);
}

void write_tables(void)
void *write_tables(void)
{
uintptr_t cbtable_start;
uintptr_t cbtable_end;
Expand All @@ -596,7 +596,7 @@ void write_tables(void)

if (!cbtable_start) {
printk(BIOS_ERR, "Could not add CBMEM for coreboot table.\n");
return;
return NULL;
}

/* Add architecture specific tables. */
Expand All @@ -615,4 +615,5 @@ void write_tables(void)

/* Print CBMEM sections */
cbmem_list();
return (void *)cbtable_start;
}
3 changes: 3 additions & 0 deletions src/lib/device_tree.c
Expand Up @@ -944,6 +944,7 @@ int dt_set_bin_prop_by_path(struct device_tree *tree, const char *path,

prop_name = strrchr(path_copy, '/');
if (!prop_name) {
free(path_copy);
printk(BIOS_ERR, "Path %s does not include '/'\n", path);
return 1;
}
Expand All @@ -956,10 +957,12 @@ int dt_set_bin_prop_by_path(struct device_tree *tree, const char *path,
if (!dt_node) {
printk(BIOS_ERR, "Failed to %s %s in the device tree\n",
create ? "create" : "find", path_copy);
free(path_copy);
return 1;
}

dt_add_bin_prop(dt_node, prop_name, data, data_size);
free(path_copy);

return 0;
}
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2 changes: 1 addition & 1 deletion src/lib/rtc.c
Expand Up @@ -31,7 +31,7 @@ static const int month_offset[] = {
0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334
};

static const char * const weekdays[] = {
static const char *const weekdays[] = {
"Sun", "Mon", "Tues", "Wednes", "Thurs", "Fri", "Satur",
};

Expand Down
1 change: 0 additions & 1 deletion src/mainboard/apple/macbookair4_2/Kconfig
Expand Up @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SERIRQ_CONTINUOUS_MODE
select SOUTHBRIDGE_INTEL_BD82X6X
select SYSTEM_TYPE_LAPTOP
select VGA

config HAVE_IFD_BIN
bool
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20 changes: 17 additions & 3 deletions src/mainboard/asrock/g41c-gs/Kconfig
Expand Up @@ -14,15 +14,17 @@
# GNU General Public License for more details.
#

if BOARD_ASROCK_G41C_GS_R2_0
if BOARD_ASROCK_G41C_GS_R2_0 || BOARD_ASROCK_G41C_GS || BOARD_ASROCK_G41M_GS

config BOARD_SPECIFIC_OPTIONS
def_bool y
select ARCH_X86
select CPU_INTEL_SOCKET_LGA775
select NORTHBRIDGE_INTEL_X4X
select SOUTHBRIDGE_INTEL_I82801GX
select SUPERIO_NUVOTON_NCT6776
select SUPERIO_NUVOTON_NCT6776 if BOARD_ASROCK_G41C_GS_R2_0
select SUPERIO_WINBOND_W83627DHG if BOARD_ASROCK_G41C_GS \
|| BOARD_ASROCK_G41M_GS
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_1024
select PCIEXP_ASPM
Expand All @@ -41,10 +43,22 @@ config MAINBOARD_DIR

config MAINBOARD_PART_NUMBER
string
default "G41C-GS R2.0"
default "G41C-GS R2.0" if BOARD_ASROCK_G41C_GS_R2_0
default "G41C-GS" if BOARD_ASROCK_G41C_GS
default "G41M-GS" if BOARD_ASROCK_G41M_GS

config DEVICETREE
string
default "variants/g41c-gs-r2/devicetree.cb" if BOARD_ASROCK_G41C_GS_R2_0
default "variants/g41c-gs/devicetree.cb" if BOARD_ASROCK_G41C_GS
default "variants/g41m-gs/devicetree.cb" if BOARD_ASROCK_G41M_GS

config MAX_CPUS
int
default 4

# Override the default variant behavior, since the data.vbt is the same
config INTEL_GMA_VBT_FILE
default "src/mainboard/$(MAINBOARDDIR)/data.vbt"

endif # BOARD_ASROCK_G41C_GS_R2_0
6 changes: 6 additions & 0 deletions src/mainboard/asrock/g41c-gs/Kconfig.name
@@ -1,2 +1,8 @@
config BOARD_ASROCK_G41C_GS_R2_0
bool "G41C-GS R2.0"

config BOARD_ASROCK_G41C_GS
bool "G41C-GS / G41C-S"

config BOARD_ASROCK_G41M_GS
bool "G41M-GS"
30 changes: 30 additions & 0 deletions src/mainboard/asrock/g41c-gs/gpio.c
Expand Up @@ -45,18 +45,27 @@ static const struct pch_gpio_set1 pch_gpio_set1_direction = {
.gpio10 = GPIO_DIR_OUTPUT,
.gpio12 = GPIO_DIR_INPUT,
.gpio13 = GPIO_DIR_INPUT,
#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS)
.gpio14 = GPIO_DIR_OUTPUT,
#else
.gpio14 = GPIO_DIR_INPUT,
#endif
.gpio15 = GPIO_DIR_OUTPUT,
.gpio16 = GPIO_DIR_OUTPUT,
.gpio18 = GPIO_DIR_OUTPUT,
.gpio20 = GPIO_DIR_OUTPUT,
.gpio24 = GPIO_DIR_OUTPUT,
.gpio25 = GPIO_DIR_OUTPUT,
#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS)
.gpio26 = GPIO_DIR_OUTPUT,
#else
.gpio26 = GPIO_DIR_INPUT,
#endif
.gpio27 = GPIO_DIR_OUTPUT,
.gpio28 = GPIO_DIR_INPUT,
};

#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41C_GS_R2_0)
static const struct pch_gpio_set1 pch_gpio_set1_level = {
.gpio10 = GPIO_LEVEL_LOW,
.gpio15 = GPIO_LEVEL_LOW,
Expand All @@ -67,10 +76,31 @@ static const struct pch_gpio_set1 pch_gpio_set1_level = {
.gpio25 = GPIO_LEVEL_LOW,
.gpio27 = GPIO_LEVEL_LOW,
};
#else /* BOARD_ASROCK_G41C_GS, BOARD_ASROCK_G41M_GS*/
static const struct pch_gpio_set1 pch_gpio_set1_level = {
.gpio10 = GPIO_LEVEL_LOW,
#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS)
.gpio14 = GPIO_LEVEL_HIGH,
#endif
.gpio15 = GPIO_LEVEL_LOW,
.gpio16 = GPIO_LEVEL_HIGH,
.gpio18 = GPIO_LEVEL_LOW,
.gpio20 = GPIO_LEVEL_HIGH,
.gpio24 = GPIO_LEVEL_HIGH,
.gpio25 = GPIO_LEVEL_LOW,
#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS)
.gpio26 = GPIO_LEVEL_LOW,
#endif
.gpio27 = GPIO_LEVEL_LOW,
};
#endif

static const struct pch_gpio_set1 pch_gpio_set1_invert = {
.gpio0 = GPIO_INVERT,
.gpio6 = GPIO_INVERT,
#if IS_ENABLED(CONFIG_BOARD_ASROCK_G41M_GS)
.gpio8 = GPIO_INVERT,
#endif
.gpio12 = GPIO_INVERT,
.gpio13 = GPIO_INVERT,
};
Expand Down