diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c
diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c
diff --git a/src/cpu/amd/socket_AM2r2/Kconfig b/src/cpu/amd/socket_AM2r2/Kconfig
diff --git a/src/cpu/amd/socket_AM2r2/Makefile.inc b/src/cpu/amd/socket_AM2r2/Makefile.inc
diff --git a/src/cpu/amd/socket_AM3/Kconfig b/src/cpu/amd/socket_AM3/Kconfig
diff --git a/src/cpu/amd/socket_AM3/Makefile.inc b/src/cpu/amd/socket_AM3/Makefile.inc
diff --git a/src/cpu/amd/socket_ASB2/Kconfig b/src/cpu/amd/socket_ASB2/Kconfig
diff --git a/src/cpu/amd/socket_ASB2/Makefile.inc b/src/cpu/amd/socket_ASB2/Makefile.inc
diff --git a/src/cpu/amd/socket_C32/Kconfig b/src/cpu/amd/socket_C32/Kconfig
diff --git a/src/cpu/amd/socket_C32/Makefile.inc b/src/cpu/amd/socket_C32/Makefile.inc
diff --git a/src/cpu/amd/socket_FM2/Kconfig b/src/cpu/amd/socket_FM2/Kconfig
diff --git a/src/cpu/amd/socket_FM2/Makefile.inc b/src/cpu/amd/socket_FM2/Makefile.inc
diff --git a/src/cpu/amd/socket_F_1207/Kconfig b/src/cpu/amd/socket_F_1207/Kconfig
diff --git a/src/cpu/amd/socket_F_1207/Makefile.inc b/src/cpu/amd/socket_F_1207/Makefile.inc
diff --git a/src/cpu/amd/socket_G34/Kconfig b/src/cpu/amd/socket_G34/Kconfig
diff --git a/src/cpu/amd/socket_G34/Makefile.inc b/src/cpu/amd/socket_G34/Makefile.inc
diff --git a/src/cpu/amd/socket_G34/socket_G34.c b/src/cpu/amd/socket_G34/socket_G34.c
diff --git a/src/cpu/armltd/Kconfig b/src/cpu/armltd/Kconfig
@@ -1 +1 @@
-source src/cpu/armltd/cortex-a9/Kconfig
+source "src/cpu/armltd/cortex-a9/Kconfig"
diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig
@@ -1,32 +1,31 @@
 # CPU models
-source src/cpu/intel/model_6xx/Kconfig
-source src/cpu/intel/model_65x/Kconfig
-source src/cpu/intel/model_67x/Kconfig
-source src/cpu/intel/model_68x/Kconfig
-source src/cpu/intel/model_6bx/Kconfig
-source src/cpu/intel/model_6ex/Kconfig
-source src/cpu/intel/model_6fx/Kconfig
-source src/cpu/intel/model_1067x/Kconfig
-source src/cpu/intel/model_106cx/Kconfig
-source src/cpu/intel/model_206ax/Kconfig
-source src/cpu/intel/fsp_model_406dx/Kconfig
-source src/cpu/intel/model_2065x/Kconfig
-source src/cpu/intel/model_f2x/Kconfig
-source src/cpu/intel/model_f3x/Kconfig
-source src/cpu/intel/model_f4x/Kconfig
-source src/cpu/intel/haswell/Kconfig
+source "src/cpu/intel/model_6xx/Kconfig"
+source "src/cpu/intel/model_65x/Kconfig"
+source "src/cpu/intel/model_67x/Kconfig"
+source "src/cpu/intel/model_68x/Kconfig"
+source "src/cpu/intel/model_6bx/Kconfig"
+source "src/cpu/intel/model_6ex/Kconfig"
+source "src/cpu/intel/model_6fx/Kconfig"
+source "src/cpu/intel/model_1067x/Kconfig"
+source "src/cpu/intel/model_106cx/Kconfig"
+source "src/cpu/intel/model_206ax/Kconfig"
+source "src/cpu/intel/model_2065x/Kconfig"
+source "src/cpu/intel/model_f2x/Kconfig"
+source "src/cpu/intel/model_f3x/Kconfig"
+source "src/cpu/intel/model_f4x/Kconfig"
+source "src/cpu/intel/haswell/Kconfig"
 # Sockets/Slots
-source src/cpu/intel/slot_1/Kconfig
-source src/cpu/intel/socket_BGA956/Kconfig
-source src/cpu/intel/socket_FCBGA559/Kconfig
-source src/cpu/intel/socket_m/Kconfig
-source src/cpu/intel/socket_p/Kconfig
-source src/cpu/intel/socket_mPGA604/Kconfig
-source src/cpu/intel/socket_441/Kconfig
-source src/cpu/intel/socket_LGA775/Kconfig
+source "src/cpu/intel/slot_1/Kconfig"
+source "src/cpu/intel/socket_BGA956/Kconfig"
+source "src/cpu/intel/socket_FCBGA559/Kconfig"
+source "src/cpu/intel/socket_m/Kconfig"
+source "src/cpu/intel/socket_p/Kconfig"
+source "src/cpu/intel/socket_mPGA604/Kconfig"
+source "src/cpu/intel/socket_441/Kconfig"
+source "src/cpu/intel/socket_LGA775/Kconfig"
 # Architecture specific features
-source src/cpu/intel/fit/Kconfig
-source src/cpu/intel/turbo/Kconfig
-source src/cpu/intel/common/Kconfig
-source src/cpu/intel/microcode/Kconfig
-source src/cpu/intel/car/non-evict/Kconfig
+source "src/cpu/intel/fit/Kconfig"
+source "src/cpu/intel/turbo/Kconfig"
+source "src/cpu/intel/common/Kconfig"
+source "src/cpu/intel/microcode/Kconfig"
+source "src/cpu/intel/car/non-evict/Kconfig"
diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc
@@ -13,7 +13,6 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell
-subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY) += fsp_model_406dx
 subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775
 

diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S
@@ -18,14 +18,10 @@
 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
 
-#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
 #if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
 #error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
 #endif
 #define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
-#else
-#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE
-#endif
 
 .global bootblock_pre_c_entry
 
@@ -173,7 +169,7 @@ addrsize_set_high:
 	movl	%eax, %cr0
 
 	/* Setup the stack. */
-	mov	$_car_stack_end, %esp
+	mov	$_ecar_stack, %esp
 
 	/* Need to align stack to 16 bytes at call instruction. Account for
 	the pushes below. */

diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S
@@ -29,7 +29,7 @@ _cache_as_ram_setup:
 
 bootblock_pre_c_entry:
 
-#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
+#if !CONFIG(ROMCC_BOOTBLOCK)
 	movl	$cache_as_ram, %esp /* return address */
 	jmp	check_mtrr /* Check if CPU properly reset */
 #endif
@@ -215,7 +215,7 @@ end_microcode_update:
 	movl	%eax, %cr0
 
 	/* Setup the stack. */
-	mov	$_car_stack_end, %esp
+	mov	$_ecar_stack, %esp
 
 	/* Need to align stack to 16 bytes at call instruction. Account for
 	the pushes below. */

diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S
@@ -18,14 +18,10 @@
 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
 
-#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
 #if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
 #error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
 #endif
 #define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
-#else
-#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE
-#endif
 
 .global bootblock_pre_c_entry
 
@@ -161,7 +157,7 @@ addrsize_set_high:
 	movl	%eax, %cr0
 
 	/* Setup the stack. */
-	mov	$_car_stack_end, %esp
+	mov	$_ecar_stack, %esp
 
 	/* Need to align stack to 16 bytes at call instruction. Account for
 	the pushes below. */

diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -18,22 +18,14 @@
 
 /* Macro to access Local APIC registers at default base. */
 #define LAPIC(x)		$(LAPIC_DEFAULT_BASE | LAPIC_ ## x)
-#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK)
-/* Fixed location, ASSERTED in failover.ld if it changes. */
-.set ap_sipi_vector_in_rom, 0xff
-#endif
 
 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
 
-#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
 #if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
 #error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
 #endif
 #define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
-#else
-#define XIP_ROM_SIZE CONFIG_XIP_ROM_SIZE
-#endif
 
 .global bootblock_pre_c_entry
 
@@ -376,7 +368,7 @@ fill_cache:
 	rep	stosl
 
 	/* Setup the stack. */
-	mov	$_car_stack_end, %esp
+	mov	$_ecar_stack, %esp
 
 	/* Need to align stack to 16 bytes at call instruction. Account for
 	the pushes below. */

diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c
@@ -21,6 +21,7 @@
 #include <commonlib/helpers.h>
 #include <program_loading.h>
 #include <timestamp.h>
+#include <security/vboot/vboot_common.h>
 
 /* If we do not have a constrained _car_stack region size, use the
    following as a guideline for acceptable stack usage. */
@@ -46,11 +47,14 @@ static void romstage_main(unsigned long bist)
 		printk(BIOS_DEBUG, "Romstage stack size limited to 0x%x!\n",
 			size);
 
-	stack_base = (u32 *) (_car_stack_end - size);
+	stack_base = (u32 *) (_ecar_stack - size);
 
 	for (i = 0; i < num_guards; i++)
 		stack_base[i] = stack_guard;
 
+	if (CONFIG(VBOOT_EARLY_EC_SYNC))
+		vboot_sync_ec();
+
 	mainboard_romstage_entry();
 
 	/* Check the stack. */
@@ -67,8 +71,8 @@ static void romstage_main(unsigned long bist)
 	/* We do not return here. */
 }
 
-#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK)
-/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
+#if CONFIG(ROMCC_BOOTBLOCK)
+/* This wrapper enables easy transition away from ROMCC_BOOTBLOCK
  * keeping changes in cache_as_ram.S easy to manage.
  */
 asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)

diff --git a/src/cpu/intel/common/Kconfig b/src/cpu/intel/common/Kconfig
@@ -26,3 +26,7 @@ config CPU_INTEL_COMMON_HYPERTHREADING
 	bool
 
 endif
+
+config CPU_INTEL_COMMON_SMM
+	bool
+	default y if CPU_INTEL_COMMON
diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c
@@ -11,7 +11,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/early_variables.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/tsc.h>
 #include <cpu/intel/speedstep.h>
@@ -20,8 +19,8 @@
 #include <commonlib/helpers.h>
 #include <delay.h>
 
-static u32 g_timer_fsb CAR_GLOBAL;
-static u32 g_timer_tsc CAR_GLOBAL;
+static u32 timer_fsb;
+static u32 timer_tsc;
 
 /* This is not an architectural MSR. */
 #define MSR_PLATFORM_INFO 0xce
@@ -32,6 +31,7 @@ static int get_fsb_tsc(int *fsb, int *ratio)
 	static const short core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 };
 	static const short core2_fsb[8] = { 266, 133, 200, 166, 333, 100, 400, -1 };
 	static const short f2x_fsb[8] = { 100, 133, 200, 166, 333, -1, -1, -1 };
+	static const short rangeley_fsb[4] = { 83, 100, 133, 116 };
 	msr_t msr;
 
 	get_fms(&c, cpuid_eax(1));
@@ -56,10 +56,13 @@ static int get_fsb_tsc(int *fsb, int *ratio)
 		case 0x3a: /* IvyBridge BCLK fixed at 100MHz */
 		case 0x3c: /* Haswell BCLK fixed at 100MHz */
 		case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */
-		case 0x4d: /* Rangeley BCLK fixed at 100MHz */
 			*fsb = 100;
 			*ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff;
 			break;
+		case 0x4d: /* Rangeley */
+			*fsb = rangeley_fsb[rdmsr(MSR_FSB_FREQ).lo & 3];
+			*ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff;
+			break;
 		default:
 			return -2;
 		}
@@ -95,8 +98,8 @@ static void resolve_timebase(void)
 	ret = get_fsb_tsc(&fsb, &ratio);
 	if (ret == 0) {
 		u32 tsc = 100 * DIV_ROUND_CLOSEST(ratio * fsb, 100);
-		car_set_var(g_timer_fsb, fsb);
-		car_set_var(g_timer_tsc, tsc);
+		timer_fsb = fsb;
+		timer_tsc = tsc;
 		return;
 	}
 
@@ -106,33 +109,27 @@ static void resolve_timebase(void)
 		printk(BIOS_ERR, "CPU not supported\n");
 
 	/* Set some semi-ridiculous defaults. */
-	car_set_var(g_timer_fsb, 500);
-	car_set_var(g_timer_tsc, 5000);
+	timer_fsb = 500;
+	timer_tsc = 5000;
 	return;
 }
 
 u32 get_timer_fsb(void)
 {
-	u32 fsb;
-
-	fsb = car_get_var(g_timer_fsb);
-	if (fsb > 0)
-		return fsb;
+	if (timer_fsb > 0)
+		return timer_fsb;
 
 	resolve_timebase();
-	return car_get_var(g_timer_fsb);
+	return timer_fsb;
 }
 
 unsigned long tsc_freq_mhz(void)
 {
-	u32 tsc;
-
-	tsc = car_get_var(g_timer_tsc);
-	if (tsc > 0)
-		return tsc;
+	if (timer_tsc > 0)
+		return timer_tsc;
 
 	resolve_timebase();
-	return car_get_var(g_timer_tsc);
+	return timer_tsc;
 }
 
 /**

diff --git a/src/cpu/intel/fit/fit.ld b/src/cpu/intel/fit/fit.ld
@@ -12,7 +12,7 @@
  */
 
 SECTIONS {
-	. = 0xffffffc0;
+	. = CONFIG_X86_RESET_VECTOR - 0x30; /* 0xffffffc0 */
 	.fit_pointer (.): {
 		KEEP(*(.fit_pointer))
 	}

diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig
diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc
diff --git a/src/cpu/intel/fsp_model_406dx/acpi.c b/src/cpu/intel/fsp_model_406dx/acpi.c
diff --git a/src/cpu/intel/fsp_model_406dx/bootblock.c b/src/cpu/intel/fsp_model_406dx/bootblock.c
diff --git a/src/cpu/intel/fsp_model_406dx/chip.h b/src/cpu/intel/fsp_model_406dx/chip.h
diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h
diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c
diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c
@@ -45,49 +45,7 @@
 #define SMRR_SUPPORTED (1 << 11)
 #define PRMRR_SUPPORTED (1 << 12)
 
-struct smm_relocation_params {
-	uintptr_t ied_base;
-	size_t ied_size;
-	msr_t smrr_base;
-	msr_t smrr_mask;
-	msr_t prmrr_base;
-	msr_t prmrr_mask;
-	msr_t uncore_prmrr_base;
-	msr_t uncore_prmrr_mask;
-	/* The smm_save_state_in_msrs field indicates if SMM save state
-	 * locations live in MSRs. This indicates to the CPUs how to adjust
-	 * the SMMBASE and IEDBASE */
-	int smm_save_state_in_msrs;
-};
-
-/* This gets filled in and used during relocation. */
-static struct smm_relocation_params smm_reloc_params;
-
-static inline void write_smrr(struct smm_relocation_params *relo_params)
-{
-	printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
-	       relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
-	wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
-	wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
-}
 
-static inline void write_prmrr(struct smm_relocation_params *relo_params)
-{
-	printk(BIOS_DEBUG, "Writing PRMRR. base = 0x%08x, mask=0x%08x\n",
-	       relo_params->prmrr_base.lo, relo_params->prmrr_mask.lo);
-	wrmsr(MSR_PRMRR_PHYS_BASE, relo_params->prmrr_base);
-	wrmsr(MSR_PRMRR_PHYS_MASK, relo_params->prmrr_mask);
-}
-
-static inline void write_uncore_prmrr(struct smm_relocation_params *relo_params)
-{
-	printk(BIOS_DEBUG,
-	       "Writing UNCORE_PRMRR. base = 0x%08x, mask=0x%08x\n",
-	       relo_params->uncore_prmrr_base.lo,
-	       relo_params->uncore_prmrr_mask.lo);
-	wrmsr(MSR_UNCORE_PRMRR_PHYS_BASE, relo_params->uncore_prmrr_base);
-	wrmsr(MSR_UNCORE_PRMRR_PHYS_MASK, relo_params->uncore_prmrr_mask);
-}
 
 static void update_save_state(int cpu, uintptr_t curr_smbase,
 				uintptr_t staggered_smbase,

diff --git a/src/cpu/intel/microcode/Kconfig b/src/cpu/intel/microcode/Kconfig
@@ -1,7 +1,7 @@
 config MICROCODE_UPDATE_PRE_RAM
 	bool
 	depends on SUPPORT_CPU_UCODE_IN_CBFS
-	default y if C_ENVIRONMENT_BOOTBLOCK
+	default y if !ROMCC_BOOTBLOCK
 	help
 	  Select this option if you want to update the microcode
 	  during the cache as ram setup.
diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig
@@ -12,4 +12,4 @@ config CPU_INTEL_MODEL_1067X
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select CPU_INTEL_COMMON
 	select CPU_INTEL_COMMON_TIMEBASE
-	select SETUP_XIP_CACHE if C_ENVIRONMENT_BOOTBLOCK
+	select SETUP_XIP_CACHE
diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h
@@ -69,14 +69,12 @@
 #define PSS_LATENCY_TRANSITION		10
 #define PSS_LATENCY_BUSMASTER		10
 
-#ifdef __SMM__
 /* Lock MSRs */
 void intel_model_2065x_finalize_smm(void);
-#else
+
 /* Configure power limits for turbo mode */
 void set_power_limits(u8 power_limit_1_time);
 int cpu_config_tdp_levels(void);
-#endif
 
 /* Sanity check config options. */
 #if (CONFIG_SMM_TSEG_SIZE <= CONFIG_SMM_RESERVED_SIZE)

diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
@@ -22,10 +22,6 @@ config CPU_SPECIFIC_OPTIONS
 	select PARALLEL_MP
 	select NO_FIXED_XIP_ROM_SIZE
 
-config BOOTBLOCK_CPU_INIT
-	string
-	default "cpu/intel/model_206ax/bootblock.c"
-
 config SMM_TSEG_SIZE
 	hex
 	default 0x800000

diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
@@ -21,7 +21,11 @@ smm-y += finalize.c
 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-2a-*)
 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3a-*)
 
-cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
+bootblock-y += bootblock.c
+bootblock-y += ../car/non-evict/cache_as_ram.S
+bootblock-y += ../../x86/early_reset.S
+bootblock-y += ../car/bootblock.c
+
 postcar-y += ../car/non-evict/exit_car.S
 
 romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c
@@ -13,13 +13,11 @@
 
 #include <stdint.h>
 #include <arch/cpu.h>
-#include <cpu/x86/cache.h>
 #include <cpu/x86/msr.h>
-#include <cpu/x86/mtrr.h>
 #include <arch/io.h>
 #include <halt.h>
+#include <cpu/intel/car/bootblock.h>
 
-#include <cpu/intel/microcode/microcode.c>
 #include "model_206ax.h"
 
 #if CONFIG(SOUTHBRIDGE_INTEL_BD82X6X) || \
@@ -30,35 +28,6 @@
 #error "CPU must be paired with Intel BD82X6X or C216 southbridge"
 #endif
 
-static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size,
-	unsigned int type)
-
-{
-	/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
-	/* FIXME: It only support 4G less range */
-	msr_t basem, maskm;
-	basem.lo = base | type;
-	basem.hi = 0;
-	wrmsr(MTRR_PHYS_BASE(reg), basem);
-	maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
-	maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
-	wrmsr(MTRR_PHYS_MASK(reg), maskm);
-}
-
-static void enable_rom_caching(void)
-{
-	msr_t msr;
-
-	disable_cache();
-	set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
-	enable_cache();
-
-	/* Enable Variable MTRRs */
-	msr.hi = 0x00000000;
-	msr.lo = 0x00000800;
-	wrmsr(MTRR_DEF_TYPE_MSR, msr);
-}
-
 static void set_flex_ratio_to_tdp_nominal(void)
 {
 	msr_t flex_ratio, msr;
@@ -109,10 +78,8 @@ static void set_flex_ratio_to_tdp_nominal(void)
 	halt();
 }
 
-static void bootblock_cpu_init(void)
+void bootblock_early_cpu_init(void)
 {
 	/* Set flex ratio and reset if needed */
 	set_flex_ratio_to_tdp_nominal();
-	enable_rom_caching();
-	intel_update_microcode_from_cbfs();
 }
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h
@@ -93,14 +93,12 @@
 # error "CONFIG_IED_REGION_SIZE is not a power of 2"
 #endif
 
-#ifdef __SMM__
 /* Lock MSRs */
 void intel_model_206ax_finalize_smm(void);
-#else
+
 /* Configure power limits for turbo mode */
 void set_power_limits(u8 power_limit_1_time);
 int cpu_config_tdp_levels(void);
-#endif
 int get_platform_id(void);
 
 #endif
diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig
@@ -13,4 +13,4 @@ config CPU_INTEL_MODEL_6FX
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select CPU_INTEL_COMMON
 	select CPU_INTEL_COMMON_TIMEBASE
-	select SETUP_XIP_CACHE if C_ENVIRONMENT_BOOTBLOCK
+	select SETUP_XIP_CACHE
diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig
@@ -36,4 +36,12 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x02000
 
+config DCACHE_BSP_STACK_SIZE
+	hex
+	default 0x1000
+
+config C_ENV_BOOTBLOCK_SIZE
+	hex
+	default 0x2000
+
 endif
diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc
@@ -26,6 +26,7 @@ subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 
-cpu_incs-y += $(src)/cpu/intel/car/p3/cache_as_ram.S
+bootblock-y += ../car/p3/cache_as_ram.S
+bootblock-y += ../car/bootblock.c
 postcar-y += ../car/p4-netburst/exit_car.S
 romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/smm/Makefile.inc b/src/cpu/intel/smm/Makefile.inc
@@ -0,0 +1 @@
+ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm_reloc.c
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -11,8 +11,7 @@
  * GNU General Public License for more details.
  */
 
-/* SMM relocation with intention to work for i945-ivybridge.
-   Right now used for sandybridge and ivybridge.  */
+/* SMM relocation for i945-ivybridge. */
 
 #include <assert.h>
 #include <types.h>
@@ -39,17 +38,6 @@
 #define  C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
 
 
-
-struct smm_relocation_params {
-	uintptr_t ied_base;
-	size_t ied_size;
-	msr_t smrr_base;
-	msr_t smrr_mask;
-};
-
-/* This gets filled in and used during relocation. */
-static struct smm_relocation_params smm_reloc_params;
-
 /* On model_6fx, model_1067x and model_106cx SMRR functions slightly
    differently. The MSR are at different location from the rest
    and need to be explicitly enabled in IA32_FEATURE_CONTROL MSR. */
@@ -88,15 +76,6 @@ static void write_smrr_alt(struct smm_relocation_params *relo_params)
 	wrmsr(MSR_SMRR_PHYS_MASK, relo_params->smrr_mask);
 }
 
-static void write_smrr(struct smm_relocation_params *relo_params)
-{
-	printk(BIOS_DEBUG, "Writing SMRR. base = 0x%08x, mask=0x%08x\n",
-	       relo_params->smrr_base.lo, relo_params->smrr_mask.lo);
-
-	wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
-	wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
-}
-
 static void fill_in_relocation_params(struct smm_relocation_params *params)
 {
 	uintptr_t tseg_base;

diff --git a/src/cpu/intel/smm/smm_reloc.c b/src/cpu/intel/smm/smm_reloc.c
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/intel/smm_reloc.h>
+
+struct smm_relocation_params smm_reloc_params;
diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig
@@ -8,6 +8,11 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
 	select CPU_INTEL_MODEL_106CX
 	select MMX
 	select SSE
+	select SETUP_XIP_CACHE
+
+config C_ENV_BOOTBLOCK_SIZE
+	hex
+	default 0x4000
 
 config DCACHE_RAM_BASE
 	hex
@@ -17,4 +22,8 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x8000
 
+config DCACHE_BSP_STACK_SIZE
+	hex
+	default 0x2000
+
 endif # CPU_INTEL_SOCKET_441
diff --git a/src/cpu/intel/socket_441/Makefile.inc b/src/cpu/intel/socket_441/Makefile.inc
@@ -8,7 +8,8 @@ subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep
 
-cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S
+bootblock-y += ../car/p4-netburst/cache_as_ram.S
+bootblock-y += ../car/bootblock.c
 postcar-y += ../car/p4-netburst/exit_car.S
 
 romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig
@@ -19,6 +19,10 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x4000 # 16 kB
 
+config DCACHE_BSP_STACK_SIZE
+	hex
+	default 0x2000
+
 config DCACHE_RAM_BASE
 	hex
 	default 0xfeffc000 # 4GB - 16MB - DCACHE_RAM_SIZE

diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc
@@ -13,7 +13,10 @@ subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep
 
-cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S
+bootblock-y += ../car/p4-netburst/cache_as_ram.S
+bootblock-y += ../car/bootblock.c
+bootblock-y += ../../x86/early_reset.S
+
 postcar-y += ../car/p4-netburst/exit_car.S
 
 romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig
@@ -18,4 +18,12 @@ config DCACHE_RAM_SIZE
 	hex
 	default 0x8000
 
+config DCACHE_BSP_STACK_SIZE
+	hex
+	default 0x2000
+
+config C_ENV_BOOTBLOCK_SIZE
+	hex
+	default 0x8000
+
 endif
diff --git a/src/cpu/intel/socket_m/Makefile.inc b/src/cpu/intel/socket_m/Makefile.inc
@@ -9,7 +9,8 @@ subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep
 
-cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S
+bootblock-y += ../car/core2/cache_as_ram.S
+bootblock-y += ../car/bootblock.c
 postcar-y += ../car/p4-netburst/exit_car.S
 
 romstage-y += ../car/romstage.c
diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig
@@ -11,7 +11,6 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
 	select UDELAY_TSC
 	select TSC_MONOTONIC_TIMER
 	select SIPI_VECTOR_IN_ROM
-	select C_ENVIRONMENT_BOOTBLOCK
 	select CPU_INTEL_COMMON
 	select CPU_INTEL_COMMON_TIMEBASE
 

diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig
@@ -21,5 +21,4 @@ config CPU_QEMU_X86
 	select UDELAY_TSC
 	select TSC_MONOTONIC_TIMER
 	select UNKNOWN_TSC_RATE
-	select C_ENVIRONMENT_BOOTBLOCK
 	select SMM_ASEG
diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S
@@ -34,7 +34,7 @@ cache_as_ram:
 
 	post_code(0x21)
 
-	movl	$_car_stack_end, %esp
+	movl	$_ecar_stack, %esp
 
 	/* Align the stack and keep aligned for call to bootblock_c_entry() */
 	and	$0xfffffff0, %esp

diff --git a/src/cpu/ti/Kconfig b/src/cpu/ti/Kconfig
@@ -1 +1 @@
-source src/cpu/ti/am335x/Kconfig
+source "src/cpu/ti/am335x/Kconfig"
diff --git a/src/cpu/ti/am335x/gpio.c b/src/cpu/ti/am335x/gpio.c
@@ -45,7 +45,7 @@ int gpio_direction_input(unsigned int gpio)
 
 	if (!regs)
 		return -1;
-	setbits_le32(&regs->oe, bit);
+	setbits32(&regs->oe, bit);
 	return 0;
 }
 
@@ -60,7 +60,7 @@ int gpio_direction_output(unsigned int gpio, int value)
 		write32(&regs->setdataout, bit);
 	else
 		write32(&regs->cleardataout, bit);
-	clrbits_le32(&regs->oe, bit);
+	clrbits32(&regs->oe, bit);
 	return 0;
 }
 

diff --git a/src/cpu/via/Kconfig b/src/cpu/via/Kconfig
diff --git a/src/cpu/via/Makefile.inc b/src/cpu/via/Makefile.inc
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig
diff --git a/src/cpu/via/nano/Makefile.inc b/src/cpu/via/nano/Makefile.inc
diff --git a/src/cpu/via/nano/microcode_blob.c b/src/cpu/via/nano/microcode_blob.c
diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c
diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c
diff --git a/src/cpu/via/nano/update_ucode.h b/src/cpu/via/nano/update_ucode.h
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc
@@ -29,7 +29,7 @@
 
 #include <arch/rom_segs.h>
 
-#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) || \
+#if !CONFIG(ROMCC_BOOTBLOCK) || \
     CONFIG(SIPI_VECTOR_IN_ROM)
 /* Symbol _start16bit must be aligned to 4kB to start AP CPUs with
  * Startup IPI message without RAM.

diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld
@@ -11,16 +11,14 @@
  * GNU General Public License for more details.
  */
 
-/*
- *      _ROMTOP                 : The top of the ROM used where we
- *				  need to put the reset vector.
- */
+/* _RESET_VECTOR: typically the top of the ROM */
 
 SECTIONS {
 	/* Trigger an error if I have an unuseable start address */
-	_bogus = ASSERT(_start16bit >= 0xffff0000, "_start16bit too low. Please report.");
-	_ROMTOP = 0xfffffff0;
-	. = _ROMTOP;
+	_TOO_LOW = CONFIG_X86_RESET_VECTOR - 0xfff0;
+	_bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report.");
+
+	. = CONFIG_X86_RESET_VECTOR;
 	.reset . : {
 		*(.reset);
 		. = 15;

diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
@@ -77,7 +77,7 @@ config XIP_ROM_SIZE
 
 config SETUP_XIP_CACHE
 	bool
-	depends on C_ENVIRONMENT_BOOTBLOCK
+	depends on !ROMCC_BOOTBLOCK
 	depends on !NO_XIP_EARLY_STAGES
 	help
 	  Select this option to set up an MTRR to cache XIP stages loaded

diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc
@@ -1,11 +1,11 @@
-romstage-$(CONFIG_CAR_GLOBAL_MIGRATION) += car.c
-
 subdirs-y += pae
 subdirs-$(CONFIG_PARALLEL_MP) += name
 ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c
 ramstage-$(CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING) += mirror_payload.c
 ramstage-y += backup_default_smm.c
 
+subdirs-$(CONFIG_CPU_INTEL_COMMON_SMM) += ../intel/smm
+
 additional-dirs += $(obj)/cpu/x86
 
 SIPI_ELF=$(obj)/cpu/x86/sipi_vector.elf
Original file line number	Diff line number	Diff line change
		@@ -1 +1 @@
		source src/cpu/armltd/cortex-a9/Kconfig
		source "src/cpu/armltd/cortex-a9/Kconfig"
-Original file line number
+Diff line change
@@ Expand Up / @@ -26,3 +26,7 @@ config CPU_INTEL_COMMON_HYPERTHREADING @@
     	bool
     endif
+    config CPU_INTEL_COMMON_SMM
+    	bool
+    	default y if CPU_INTEL_COMMON
Original file line number	Diff line number	Diff line change
		@@ -0,0 +1 @@
		ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm_reloc.c
Original file line number	Diff line number	Diff line change
		@@ -1 +1 @@
		source src/cpu/ti/am335x/Kconfig
		source "src/cpu/ti/am335x/Kconfig"