| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,44 @@ | ||
| # Lenovo Thinkpad R60 | ||
|
|
||
| Untested on boards with external Radeon graphics adapter. If you have such | ||
| board, proceed at your own risk and document if it does work. | ||
|
|
||
| ## Flashing instructions | ||
|
|
||
| ### External flashing | ||
|
|
||
| The flash IC is located at the bottom center of the mainboard. Access to | ||
| the flash chip is blocked by the magnesium frame, so you need to disassemble | ||
| the entire laptop and remove the mainboard. The flash chip is referenced as U49 in | ||
| the schematics and in the boardview. | ||
|
|
||
|  | ||
|
|
||
| To disassemble the laptop, follow the [Hardware Maintenance Manual](https://thinkpads.com/support/hmm/hmm_pdf/42x3749_02.pdf). | ||
|
|
||
| ### Internal flashing on Vendor BIOS | ||
|
|
||
| This [method](https://gist.github.com/ArthurHeymans/c5ef494ada01af372735f237f6c6adbe) describes a way to install coreboot with vendor firmware still | ||
| installed on the Lenovo Thinkpad X60. It is reported to also work in Thinkpad | ||
| R60, with the only difference being the board target you build coreboot for. | ||
|
|
||
| ### Flashing on coreboot | ||
|
|
||
| Default configuration of coreboot doesn't feature any flash restrictions | ||
| like the vendor firmware, therefore flashrom is able to flash any rom without problems. | ||
|
|
||
| ## Things tested and working in Linux 5.3: | ||
|
|
||
| - Intel WiFi card | ||
| - Suspend and resume | ||
| - Native graphics initialization. Both legacy VGA and linear framebuffer work | ||
| - GRUB2 2.04 and SeaBIOS 1.12.1 payloads | ||
| - Reflashing with flashrom (use flashrom-git as of 17.09.2019) | ||
| - 2G+1G memory configuration working | ||
| - 2504 dock USB ports if not hotplugged | ||
|
|
||
| ## Things tested and not working: | ||
|
|
||
| - 2504 dock hotplugging | ||
| - Black bar at the left side of the screen. Doesn't appear in Linux. See picture at top | ||
| - Sometimes it takes several second to run coreboot. Just wait for it |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,44 @@ | ||
| # Lenovo T410 | ||
|
|
||
| ## Known issues | ||
| * Dock has wrong ACPI ID (causes "AC adapter state cannot be read" in Linux) | ||
| * TPM not working with VBOOT and C_ENV bootblock (works without C_ENV BB) | ||
|
|
||
| ## Flashing instructions | ||
| ```eval_rst | ||
| +---------------------+--------------------------------+ | ||
| | Type | Value | | ||
| +=====================+================================+ | ||
| | Socketed flash | no | | ||
| +---------------------+--------------------------------+ | ||
| | Size | 8 MiB | | ||
| +---------------------+--------------------------------+ | ||
| | In circuit flashing | Only in S3/WoL | | ||
| +---------------------+--------------------------------+ | ||
| | Package | SOIC-8 | | ||
| +---------------------+--------------------------------+ | ||
| | Write protection | No | | ||
| +---------------------+--------------------------------+ | ||
| | Dual BIOS feature | No | | ||
| +---------------------+--------------------------------+ | ||
| | Internal flashing | Yes | | ||
| +---------------------+--------------------------------+ | ||
| ``` | ||
|
|
||
| The flash IC is located at the bottom center of the mainboard. Sadly, | ||
| access to the IC is blocked by the magnesum frame, so you need to disassemble | ||
| the entire laptop and remove the mainboard. | ||
|
|
||
| Below is a picture of IC on the mainboard, with the pinouts labeled. | ||
|
|
||
|  | ||
|
|
||
| The chip will either be a Macronix MX25L6405D or a Winbond W25Q64CVSIG. | ||
| Do not rely on dots painted in the corner of the chip (such as the blue dot | ||
| pictured) to orient the pins! | ||
|
|
||
| [Flashing tutorial](../../flash_tutorial/no_ext_power.md) | ||
|
|
||
| Steps to access the flash IC are described here [T4xx series]. | ||
|
|
||
| [T4xx series]: t4xx_series.md |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,66 @@ | ||
| # Lenovo ThinkPad T440p | ||
|
|
||
| This page describes how to run coreboot on [Lenovo ThinkPad T440p]. | ||
|
|
||
| ## Required proprietary blobs | ||
|
|
||
| Please see [mrc.bin](../../northbridge/intel/haswell/mrc.bin). | ||
|
|
||
| ## Flashing instructions | ||
|
|
||
| T440p has two flash chips, an 8MB W25Q64FV and a 4MB W25Q32FV. To flash | ||
| coreboot, you just need to remove the big door according to the T440 | ||
| [Hardware Maintenance Manual] and flash the 4MB chip. | ||
|
|
||
|  | ||
|
|
||
| To access the 8MB chip, you need to remove the base cover. | ||
|
|
||
|  | ||
|
|
||
| The flash layout of the OEM firmware is as follows: | ||
|
|
||
| 00000000:00000fff fd | ||
| 00001000:00002fff gbe | ||
| 00003000:004fffff me | ||
| 00500000:00bfffff bios | ||
|
|
||
| After flashing coreboot, you may need to re-plug the AC adapter to make | ||
| the laptop able to power on. | ||
|
|
||
| ## Known Issues | ||
|
|
||
| - No audio output when using a headphone | ||
| - The touchpad is misconfigured, the 3 keys on top are all identified | ||
| as left button | ||
| - Cannot get the mainboard serial number from the mainboard: the OEM | ||
| UEFI firmware gets the serial number from an "emulated EEPROM" via | ||
| I/O port 0x1630/0x1634, but it's still unknown how to make it work | ||
|
|
||
| ## Untested | ||
|
|
||
| - the dGPU model | ||
|
|
||
| ## Working | ||
|
|
||
| - boot Arch Linux with Linux 4.19.77 from SeaBIOS payload | ||
| - integrated graphics init with libgfxinit | ||
| - EHCI debug: the port is the non-charging USB2 port on the right | ||
| - video output: internal (eDP), miniDP, dock DP, dock HDMI | ||
| - ACPI support | ||
| - keyboard and trackpoint | ||
| - SATA | ||
| - M.2 SATA SSD | ||
| - USB | ||
| - Ethernet | ||
| - WLAN | ||
| - WWAN | ||
| - bluetooth | ||
| - virtualization: VT-x and VT-d | ||
| - dock | ||
| - CMOS options: wlan, trackpoint, fn_ctrl_swap | ||
| - internal flashing when IFD is unlocked | ||
| - using `me_cleaner` | ||
|
|
||
| [Lenovo ThinkPad T440p]: https://pcsupport.lenovo.com/us/zh/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t440p | ||
| [Hardware Maintenance Manual]: https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/t440p_hmm_en_sp40a25467_04.pdf |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,44 @@ | ||
| # Lenovo X301 | ||
|
|
||
| ## Disassembly Instructions | ||
|
|
||
| You must remove the following parts to access the SPI flash: | ||
|
|
||
|  | ||
|
|
||
| * Battery pack | ||
| * Keyboard | ||
|
|
||
| Its [Hardware Maintenance Manual](https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/43y9441.pdf) can be used as a guidance of disassembly. | ||
|
|
||
| The WSON-8 flash chip (surrounded with red circle in the photo above, | ||
| already replaced with a SOIC-8 one) sits under a piece of insulating | ||
| tape. If solders between the chip and soldering pads fortunately | ||
| overflows beside the chip as tiny tin balls attached to soldering pads, | ||
| it will be possible to use a pomona 5250 clip to hold the chip, with | ||
| its metal tips just attached to tin balls, thus connecting the chip to | ||
| the programmer. Otherwise, it may be recommended to replace it with a | ||
| SOIC-8 one (you might need to add the chip to the IFD VSCC list), as | ||
| what is done in the photo. | ||
|
|
||
| The vendor IFD VSCC list contains: | ||
| -MACRONIX_MX25L6405 (0xc2, 0x2017) | ||
| -WINBOND_NEX_W25X64 (0xef, 0x3017) | ||
| -ATMEL_AT25DF641 (0x1f, 0x4800) | ||
|
|
||
| ```eval_rst | ||
| :doc:`../../flash_tutorial/ext_power` | ||
| ``` | ||
| Tested: | ||
| - CPU Core 2 Duo U9400 | ||
| - Slotted DIMM 4GiB*2 from samsung | ||
| - Camera | ||
| - pci-e slots | ||
| - sata and usb2 | ||
| - libgfxinit-based graphic init | ||
| - NVRAM options for North and South bridges | ||
| - Sound | ||
| - Thinkpad EC | ||
| - S3 | ||
| - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from | ||
| Linux payload (Heads) and Seabios. |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,93 @@ | ||
| # Supermicro X11SSM-F | ||
|
|
||
| This section details how to run coreboot on the [Supermicro X11SSM-F]. | ||
|
|
||
| ## Flashing coreboot | ||
|
|
||
| The board can be flashed externally. FTDI FT2232H and FT232H based programmers worked. | ||
|
|
||
| The flash IC [MX25L12873F] can be found near PCH PCIe Slot 4. It is socketed on retail boards. | ||
|
|
||
| For doing ISP (In-System-Programming) one needs to add a diode between VCC and the flash chip. | ||
|
|
||
| ## BMC (IPMI) | ||
|
|
||
| This board has an ASPEED [AST2400], which has BMC/[IPMI] functionality. The BMC firmware resides in a | ||
| 32 MiB SOIC-16 chip in the corner of the mainboard near the PCH PCIe Slot 4. This chip is a | ||
| [MX25L25635F]. | ||
|
|
||
| ## Tested and working | ||
|
|
||
| - GRUB2 payload with Debian testing and kernel 5.2 | ||
| - ECC ram (Linux' ie31200 driver works) | ||
| - USB ports | ||
| - Ethernet | ||
| - SATA ports | ||
| - RS232 external | ||
| - PCIe slots | ||
| - BMC (IPMI) | ||
| - VGA on Aspeed | ||
| - TPM on TPM expansion header | ||
|
|
||
| ## Known issues | ||
|
|
||
| - See general issue section | ||
| - "only partially covers this bridge" info from Linux kernel (what does that mean?) | ||
| - LNXTHERM missing | ||
| - S3 resume not working | ||
|
|
||
| ## ToDo | ||
|
|
||
| - Fix TODOs mentioned in code | ||
|
|
||
| ## Technology | ||
|
|
||
| ```eval_rst | ||
| +------------------+--------------------------------------------------+ | ||
| | CPU | Intel Kaby Lake | | ||
| +------------------+--------------------------------------------------+ | ||
| | PCH | Intel C236 | | ||
| +------------------+--------------------------------------------------+ | ||
| | Coprocessor | Intel SPS (server version of the ME) | | ||
| +------------------+--------------------------------------------------+ | ||
| | Super I/O | ASPEED AST2400 | | ||
| +------------------+--------------------------------------------------+ | ||
| | Ethernet | 2x Intel I210-AT 1 GbE | | ||
| | | 1x dedicated BMC | | ||
| +------------------+--------------------------------------------------+ | ||
| | PCIe slots | 1x 3.0 x8 | | ||
| | | 1x 3.0 x8 (in x16) | | ||
| | | 2x 3.0 x4 (in x8) | | ||
| +------------------+--------------------------------------------------+ | ||
| | USB slots | 2x USB 2.0 (ext) | | ||
| | | 2x USB 3.0 (ext) | | ||
| | | 1x USB 3.0 (int) | | ||
| | | 1x dual USB 3.0 header | | ||
| | | 2x dual USB 2.0 header | | ||
| +------------------+--------------------------------------------------+ | ||
| | SATA slots | 8x S-ATA III | | ||
| +------------------+--------------------------------------------------+ | ||
| | Other slots | 1x RS232 (ext) | | ||
| | | 1x RS232 header | | ||
| | | 1x TPM header | | ||
| | | 1x Power SMB header | | ||
| | | 5x PWM Fan connector | | ||
| | | 2x I-SGPIO | | ||
| | | 2x S-ATA DOM Power connector | | ||
| | | 1x XDP Port | | ||
| | | 1x External BMC I2C Header (for IPMI card) | | ||
| | | 1x Chassis Intrusion Header | | ||
| +------------------+--------------------------------------------------+ | ||
| ``` | ||
|
|
||
| ## Extra links | ||
|
|
||
| - [Supermicro X11SSM-F] | ||
| - [Board manual] | ||
|
|
||
| [Supermicro X11SSM-F]: https://www.supermicro.com/en/products/motherboard/X11SSM-F | ||
| [Board manual]: https://www.supermicro.com/manuals/motherboard/C236/MNL-1785.pdf | ||
| [AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376 | ||
| [IPMI]: ../../../../drivers/ipmi_kcs.md | ||
| [MX25L25635F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L25635F.pdf | ||
| [MX25L12873F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L12873F.pdf |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,68 @@ | ||
| # License Agreement for amd_blobs Repository | ||
|
|
||
| ## Abstract | ||
|
|
||
| AMD has generated a simpler and more flexible license agreement for using | ||
| proprietary precompiled binary images. The new agreement is intended to cover | ||
| all blobs in the directory structure below where the license resides and | ||
| eliminates any unique agreements previously provided for individual products. | ||
|
|
||
| A [3rdparty/amd_blobs](https://review.coreboot.org/admin/repos/amd_blobs) repo | ||
| now exists for distributing new blobs to coreboot developers and consumers. | ||
| Images for older products will be moved to amd_blobs as time permits. | ||
|
|
||
| By cloning the amd_blobs repo, you will be agreeing to the license agreement | ||
| contained there. | ||
|
|
||
| ## Text of License Agreement | ||
|
|
||
| The language of the agreement is duplicated below for your reference. The | ||
| official license agreement may be found inside the Git repository. | ||
|
|
||
| > Copyright (c) 2019 ADVANCED MICRO DEVICES, INC. | ||
| > | ||
| > READ CAREFULLY: DO NOT DOWNLOAD, COPY OR USE THE ASSOCIATED AMD SOFTWARE | ||
| > ("LICENSED SOFTWARE") UNTIL YOU HAVE CAREFULLY READ THE FOLLOWING. BY USING | ||
| > THE LICENSED SOFTWARE, YOU ARE AGREEING TO BE BOUND BY THE FOLLOWING TERMS: | ||
| > | ||
| > Redistribution and use in binary form, without modification, is permitted | ||
| > subject to the following conditions: | ||
| > | ||
| > a. Reverse engineering, disassembly, or de-compilation of the Licensed | ||
| > Software is not permitted; | ||
| > | ||
| > b. All the content of this document, including the above copyright notice and | ||
| > below disclaimer, must be included in the documentation or other materials | ||
| > provided with any distribution, and you may not alter or remove any copyright, | ||
| > trademark or patent notice(s) in the Licensed Software; and, | ||
| > | ||
| > c. The name “AMD” or “Advanced Micro Devices” may not be used to promote | ||
| > products derived from the Licensed Software. | ||
| > | ||
| > Except for the limited license expressly granted above, you have no other | ||
| > rights in the Licensed Software, whether express, implied, arising by estoppel | ||
| > or otherwise. The Licensed Software including all Intellectual Property Rights | ||
| > therein is and remains the sole and exclusive property of AMD or its | ||
| > licensors, and You shall have no right, title or interest therein except as | ||
| > expressly set forth above. | ||
| > | ||
| > Disclaimer of Warranty. THE LICENSED SOFTWARE IS PROVIDED "AS IS" WITHOUT | ||
| > WARRANTY OF ANY KIND. AMD DISCLAIMS ALL WARRANTIES, EXPRESS, IMPLIED, OR | ||
| > STATUTORY, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF | ||
| > MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NON- | ||
| > INFRINGEMENT, THAT THE LICENSED SOFTWARE WILL RUN UNINTERRUPTED OR ERROR-FREE | ||
| > OR WARRANTIES ARISING FROM CUSTOM OF TRADE OR COURSE OF USAGE. THE ENTIRE RISK | ||
| > ASSOCIATED WITH THE USE OF THE LICENSED SOFTWARE IS ASSUMED BY YOU INCLUDING, | ||
| > WITHOUT LIMITATION, PERFORMANCE AND INTEROPERABILITY ISSUES THAT MAY ADVERSELY | ||
| > AFFECT YOUR EXPERIENCE AND THE STABILITY OF YOUR COMPUTING SYSTEM; AND | ||
| > (C) OTHER EXPERIENCES RESULTING IN ADVERSE EFFECTS, INCLUDING, BUT NOT | ||
| > LIMITED, TO DATA CORRUPTION OR LOSS. AMD WILL NOT, UNDER ANY CIRCUMSTANCES BE | ||
| > LIABLE TO YOU FOR ANY PUNITIVE, DIRECT, INCIDENTAL, INDIRECT, SPECIAL OR | ||
| > CONSEQUENTIAL DAMAGES INCLUDING LOSS OF USE, PROFITS, OR DATA ARISING FROM USE | ||
| > OF THE LICENSED SOFTWARE EVEN IF AMD AND ITS LICENSORS HAVE BEEN ADVISED OF | ||
| > THE POSSIBILITY OF SUCH DAMAGES. | ||
| > | ||
| > The Licensed Software including all Intellectual Property Rights therein is | ||
| > and remains the sole and exclusive property of AMD or its licensors, and You | ||
| > shall have no right, title or interest therein except as expressly set forth | ||
| > above or as required by law. |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,7 @@ | ||
| # Qualcomm SOC-specific documentation | ||
|
|
||
| This section contains documentation about coreboot on specific Qualcomm SOCs. | ||
|
|
||
| ## Platforms | ||
|
|
||
| - [SC7180 series](sc7180/index.md) |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,19 @@ | ||
| # Qualcomm SC7180 documentation | ||
|
|
||
| ## SOC code | ||
|
|
||
| The SOC folder contains functions for: | ||
| * MMU | ||
| * CLOCK | ||
| * GPIO | ||
| * QUPv3 FW (provides a bridge to serial interfaces) | ||
| * UART | ||
| * SPI-NOR | ||
| * AOP FW | ||
| * USB | ||
|
|
||
| ## Notes about the hardware | ||
|
|
||
| The timer is used from the ARMv8 architecture specific code. | ||
|
|
||
|
|
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,268 @@ | ||
| Rebuilding coreboot image generation | ||
| ==================================== | ||
|
|
||
| Current situation | ||
| ----------------- | ||
| Chrome OS (CrOS) probably has the most complex image bundling process in the | ||
| coreboot ecosystem. To make CrOS features more accessible to the wider | ||
| coreboot community, we want to move these capabilities into upstream | ||
| coreboot’s build system. | ||
|
|
||
| Right now, the CrOS build system creates coreboot images, and various | ||
| instances of the payload (with different configuration options), plus some | ||
| more files (eg. EC firmware), then passes them to a CrOS-specific utility | ||
| (`bundle_firmware.py`) to build the final image from that. | ||
|
|
||
| `bundle_firmware` adds a flashmap (fmap) to the final image and creates | ||
| additional CBFS filesystems in fmap regions. It then extracts some files from | ||
| the original CBFS region (that was put in place carefully to later match to | ||
| the default fmap region) and copies some of them into the others, as well as | ||
| putting more data (eg. the bitmap data, keys) as raw data into other fmap | ||
| regions. | ||
|
|
||
| With the recent addition of more files to CBFS, both on the coreboot side | ||
| (dsdt, FSP, and so on) and with Chrome OS specifics (eg. more files describing | ||
| boot screens) we either need to expand the scope of bundle\_firmware or move | ||
| the capability to build complex images to upstream coreboot’s build system. | ||
| This document proposes to do the latter and outlines how this could be | ||
| achieved. | ||
|
|
||
| Problems with the current build system parts | ||
| -------------------------------------------- | ||
| One common sentiment is that it should be possible to reuse some of the | ||
| existing mechanisms that are supposed to be supplanted by this. | ||
| The main concern during this design that precluded their use was that none of | ||
| them provides a comprehensive solution to building complex coreboot based | ||
| images: | ||
| * fmap.dts and fmd provide a flash layout, but no assignment of files of regions | ||
| * cbfs-files-y ends up as an internal make variable using | ||
| `weird|formatting|to|deal|with|make’s|limitations` | ||
| * make isn’t powerful enough to deal with ordering these entries in said | ||
| variable to guarantee success if there’s enough room for the files. While that | ||
| could be added, that becomes more make macro work indistinguishable from magic | ||
| that people fail to understand, break and with good reason complain about | ||
| to work around such issues, Chrome OS firmware uses a custom tool with even | ||
| more special cases to finally build the image it needs. If coreboot upstream | ||
| is to support vboot, it should also be powerful enough not to need magic tools | ||
| that only live within downstream projects. | ||
|
|
||
| Requirements | ||
| ------------ | ||
| A complete Chrome OS coreboot image consists of (depending on the device) | ||
| * platform specific data in raw fmap regions (eg IFD, ME firmware), | ||
| * the bootblock (coming from the bootblock), | ||
| * three copies of coreboot, consisting of the stages (verstage, romstage, | ||
| ramstage) plus data, | ||
| * depthcharge plus data (with each of the coreboot copies), | ||
| * EC firmware files (with each of the coreboot copies), | ||
| * signatures over several parts of the image and | ||
| * some final checksumming over parts of the image to satisfy boot ROM | ||
| tests on ARM | ||
|
|
||
| A complete upstream coreboot image (with fallback/normal switch configuration, | ||
| using a yet to be implemented switching scheme based on fmaps) consists of | ||
| * platform specific data in raw fmap regions (eg IFD, ME firmware), | ||
| * two copies of coreboot, consisting of | ||
| * the bootblock and | ||
| * the stages (romstage, ramstage) plus data, | ||
| * payload plus data (with each of the coreboot copies), | ||
|
|
||
| Since a single platform is potentially built with different payload | ||
| configurations (eg. modding a Chromebook to not use the verified Chrome OS | ||
| boot scheme), some concerns need to be kept separate: | ||
| * Platform requirements that have nothing to do with the payload or boot schemes | ||
| * IFD, ME, … need to copied to the right place | ||
| * boot ROM requirements such as checksums must be honored | ||
| * Payload/boot scheme requirements | ||
| * Having one to three regions with certain files copied into them | ||
|
|
||
| Proposal | ||
| -------- | ||
| The proposal is based on manifest files that describe certain aspects of the | ||
| final image. | ||
| The number of manifest files may change over time, but this seems to be a | ||
| reasonable approach for now. As long as coreboot uses fmap and cbfs, there | ||
| should be few need to change the language, since composition is done through | ||
| files. | ||
|
|
||
| The final image is generated by a utility that is handed a number of manifests | ||
| and the size of the flash (derived from `CONFIG_ROM_SIZE`). These manifest files | ||
| deal with different concerns, with the following an example that should match | ||
| current use cases: | ||
|
|
||
| Chipset manifest | ||
| ---------------- | ||
| The chipset details if there are any non-coreboot regions, and assigns them | ||
| names, locations, sizes and file contents and prepares a region for what is | ||
| “platform visible” (eg. IFD’s BIOS region) that may be of flexible size | ||
| (depending on the flash chip’s size). For the purpose of this document, that | ||
| region is called “BIOS”. | ||
| It can also specify if there’s a post processing requirement on the final | ||
| image. | ||
|
|
||
| coreboot manifest | ||
| ----------------- | ||
| coreboot provides lists of the files it generates for each category it’s | ||
| building (eg. bootblock, verstage, romstage, ramstage). They not only contain | ||
| the stages themselves, but also additional files (eg. dsdt belongs to ramstage | ||
| since that’s where it is used) | ||
|
|
||
| Boot method manifest | ||
| -------------------- | ||
| The boot method manifest can subdivide the BIOS region, eg. using it directly | ||
| (for coreboot’s “simple” bootblock), splitting it in two (for coreboot’s | ||
| fallback/normal) or in many parts (for Chrome OS, which requires two CBFS | ||
| regions, one for GBB, several for VPD, …). | ||
| It also specifies which of the file lists specified earlier belong in which | ||
| region (eg. with verstage verifying romstage, verstage needs to be only in | ||
| Chrome OS’ RO region, while romstage belongs in RO and both RW regions). | ||
| It can also specify a post processing step that is executed before the | ||
| chipset’s. | ||
|
|
||
| Payload and additional manifests | ||
| -------------------------------- | ||
| External components should also provide manifests to add files to categories. | ||
| This way the payload and other components (eg. EC firmware) can be developed | ||
| without needing to touch the central boot method manifest (that likely resides | ||
| in the coreboot tree, given that coreboot needs to deal with choosing fmap | ||
| regions already). | ||
|
|
||
| coreboot build system | ||
| --------------------- | ||
| The coreboot build system will be split more distinctly in two phases: The | ||
| first is about building the files (with results like romstage.elf), while the | ||
| second phase covers the assembly of the final image. | ||
|
|
||
| By having a global picture of the final image’s requirements, we can also | ||
| avoid issues where files added earlier may prevent later additions that have | ||
| stricter constraints - without resorting to hacks like | ||
| https://chromium-review.googlesource.com/289491 that reorder the file addition | ||
| manually. | ||
|
|
||
| Example | ||
| ------- | ||
| As an example, we’ll define an Intel-based board with a postprocessing tool | ||
| (something that doesn’t exist, but isn’t hard to imagine): | ||
|
|
||
| It specifies an IFD region, an ME, and the BIOS region. After the image is | ||
| built, the entire image needs to be processed (although the tool likely works | ||
| only on a small part of it) | ||
|
|
||
| It’s built in a Chrome OS-like configuration (simplified at places to avoid | ||
| distracting from the important parts), so it has three CBFS regions, and | ||
| several data regions for its own purpose (similar to GBB, FWID, VPD, …). After | ||
| the regions are filled, one data region must be post-processed to contain | ||
| signatures to enable verifying other regions. | ||
|
|
||
| ``` | ||
| Chipset manifest | ||
| ================ | ||
| # A region called IFD, starting at 0, ending at 4K | ||
| region IFD: 0 4K | ||
| # Add the specified file “raw” into the region. | ||
| # If the file is smaller than the region, put it at the bottom and fill up | ||
| # with 0xff | ||
| raw IFD: build/ifd.bin align=bottom empty=0xff | ||
| # Call the postprocessor on the data that ends up in IFD (in this example it | ||
| # might lock the IFD) | ||
| postprocess IFD: util/ifdprocess -l | ||
| # a region called ME, starting at 4K, ending at 2M | ||
| region ME: 4K 2M | ||
| raw ME: 3rdparty/blobs/soc/intel/xanadu/me.bin align=bottom empty=0x00 | ||
| # a region called BIOS, starting at 2M, filling up the free space | ||
| # filling up fails (build error) if two regions are requested to fill up | ||
| # against each other | ||
| region BIOS: 2M * | ||
| # This would define a region that covers the last 4K of flash. | ||
| # The BIOS region specified above will end right before it instead of | ||
| # expanding to end of flash | ||
| # region AUX: -4K -0 | ||
| # specify the tool that post-processes the entire image. | ||
| postprocess image: util/intelchksum/intelchksum.sh | ||
| coreboot manifest | ||
| ================= | ||
| # declare that build/verstage.elf belongs into the group ‘verstage’ | ||
| # these groups are later referred to by the “cbfs” command. | ||
| group verstage: build/verstage.elf stage xip name=fallback/verstage | ||
| group romstage: build/romstage.elf stage xip name=fallback/romstage | ||
| group ramstage: build/ramstage.elf stage name=fallback/ramstage | ||
| compression=lzma | ||
| group ramstage: build/dsdt.aml compression=lzma | ||
| boot method manifest | ||
| ==================== | ||
| # Define RO as region inside BIOS, covering the upper half of the image. | ||
| # It’s a build error if the result crosses outside BIOS. | ||
| # math expressions are wrapped with ( ), | ||
| # and mentions of regions therein always refer to their size | ||
| subregion BIOS RO: ( image / 2 ) -0 | ||
| # Define RW to cover the rest of BIOS. | ||
| # The order of RW and RO doesn’t matter except to keep comments clearer. | ||
| # Dynamic items like RW (“*”) will be sized to fill unused space after | ||
| # everything else is placed. | ||
| subregion BIOS RW: 0 * | ||
| # It may be necessary to separate the RO/RW definition into another manifest | ||
| # file | ||
| # that defines the RO configuration of the flash | ||
| # Some more subregions, with dynamically calculated sizes | ||
| subregion RW RW_A: 0 ( RW / 2 ) | ||
| subregion RW RW_B: * -0 | ||
| subregion RW_A FW_MAIN_A: RW_A * -0 | ||
| subregion RW_A VBLOCK_A: 0 64K | ||
| # foo +bar specifies start + size, not (start, end) | ||
| # also, start is given as “the end of VBLOCK_A” | ||
| # (while using a region in the “end” field means “start of region”) | ||
| subregion RW_A FWID_A: VBLOCK_A +64 | ||
| # To make the example not too verbose, RO only has the CBFS region | ||
| subregion RO BOOTSTUB: 0 * | ||
| # Postprocess the data that ends up in VBLOCK_A, | ||
| # passing the listed regions as additional arguments. | ||
| # Circular dependencies are build errors. | ||
| postprocess VBLOCK_A(FW_MAIN_A): signtool | ||
| # binding files to regions indirectly through groups | ||
| cbfs BOOTSTUB: verstage, romstage, ramstage, payload | ||
| cbfs FW_MAIN_A: romstage, ramstage, payload | ||
| # defining defaults: unless overridden, in all regions that use CBFS (“*”), | ||
| # we want all files to come with SHA256 hashes. | ||
| # Wildcard defaults have lower priority than specific defaults. | ||
| # Other conflicts lead to a build error. | ||
| cbfsdefaults *: hash=sha3 | ||
| payload manifest | ||
| ================ | ||
| group payload: payload.elf payload | ||
| group payload: bootscreen.jpg name=splashscreen.jpg type=splashscreen | ||
| EC firmware manifest | ||
| ==================== | ||
| # overrides the cbfsdefault above | ||
| group payload: ecrw.bin name=ecrw hash=sha256 | ||
| group payload: pdrw.bin name=pdrw hash=sha256 | ||
| ``` | ||
|
|
||
| manifest parsing | ||
| ---------------- | ||
| The exact BNF is work in progress. | ||
|
|
||
| Some parser rules are | ||
| * one line per statement | ||
| * '#' introduces a command until the end of line | ||
|
|
||
| Some processing rules | ||
| * When there’s a conflict (eg. two statements on what to do to a region, | ||
| overlap, anything that can’t be determined), that is a build error. | ||
| * the order of statements doesn’t matter, enabling simple addition of more | ||
| manifests where the need arises. | ||
|
|
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,4 @@ | ||
| # Technotes | ||
|
|
||
| * [Dealing with Untrusted Input in SMM](2017-02-dealing-with-untrusted-input-in-smm.md) | ||
| * [Rebuilding coreboot image generation](2015-11-rebuilding-coreboot-image-generation.md) |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,208 @@ | ||
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,5 +1,6 @@ | ||
| config ARCH_PPC64 | ||
| bool | ||
| select RAMSTAGE_CBMEM_TOP_ARG | ||
|
|
||
| config ARCH_BOOTBLOCK_PPC64 | ||
| bool | ||
|
|
||
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,25 @@ | ||
| /* | ||
| * This file is part of the coreboot project. | ||
| * | ||
| * This program is free software; you can redistribute it and/or modify | ||
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| */ | ||
|
|
||
| #ifndef RAM_SEGS_H | ||
| #define RAM_SEGS_H | ||
|
|
||
| #define RAM_CODE_SEG 0x10 | ||
| #define RAM_DATA_SEG 0x18 | ||
| #define RAM_CODE16_SEG 0x28 | ||
| #define RAM_DATA16_SEG 0x30 | ||
| #define RAM_CODE_ACPI_SEG 0x38 | ||
| #define RAM_DATA_ACPI_SEG 0x40 | ||
| #define RAM_CODE_SEG64 0x48 | ||
|
|
||
| #endif /* RAM_SEGS_H */ |
| Original file line number | Diff line number | Diff line change |
|---|---|---|
|
|
@@ -21,8 +21,4 @@ config CPU_ADDR_BITS | |
| int | ||
| default 48 | ||
|
|
||
| endif | ||
| Original file line number | Diff line number | Diff line change |
|---|---|---|
|
|
@@ -21,8 +21,4 @@ config CPU_ADDR_BITS | |
| int | ||
| default 36 | ||
|
|
||
| endif | ||
| Original file line number | Diff line number | Diff line change |
|---|---|---|
|
|
@@ -21,8 +21,4 @@ config CPU_ADDR_BITS | |
| int | ||
| default 48 | ||
|
|
||
| endif | ||
| Original file line number | Diff line number | Diff line change |
|---|---|---|
|
|
@@ -21,10 +21,6 @@ config CPU_ADDR_BITS | |
| int | ||
| default 40 | ||
|
|
||
| config FORCE_AM1_SOCKET_SUPPORT | ||
| bool | ||
| default n | ||
|
|
||
| Original file line number | Diff line number | Diff line change |
|---|---|---|
|
|
@@ -21,8 +21,4 @@ config CPU_ADDR_BITS | |
| int | ||
| default 48 | ||
|
|
||
| endif | ||
