41 changes: 3 additions & 38 deletions Documentation/soc/amd/family17h.md
View file
Expand Up @@ -240,47 +240,12 @@ in an Integration Guide.
## APCB setup

APCBs are used to provide the PSP with SPD information and optionally a set of
GPIOs to use for selecting which SPD to load.

### Prebuilt
The picasso `Makefile` expects APCBs to be located in
`3rdparty/blobs/mainboard/$(MAINBOARDDIR)`. If you have a pre-built binary just
add the following to your mainboard's Makefile.

```
# i.e., 3rdparty/blobs/mainboard/amd/mandolin/APCB_mandolin.bin
APCB_SOURCES = mandolin
```
GPIOs to use for selecting which SPD to load. A list of APCB files should be
specified in `APCB_SOURCES`.

### Generating APCBs
If you have a template APCB file, the `apcb_edit` tool can be used to inject the
SPD and GPIOs used to select the correct slot. Entries should match this
pattern `{NAME}_x{1,2}`. There should be a matching SPD hex file in
`SPD_SOURCES_DIR` matching the pattern `{NAME}.spd.hex`.
The `_x{1,2}` suffix denotes single or dual channel. Up to 16 slots can be used.
If a slot is empty, the special empty keyword can be used. This will generate
an APCB with an empty SPD.

```
APCB_SOURCES = hynix-HMA851S6CJR6N-VK_x1 # 0b0000
APCB_SOURCES += hynix-HMAA1GS6CMR6N-VK_x2 # 0b0001
APCB_SOURCES += empty # 0b0010
APCB_SOURCES += samsung-K4A8G165WC-BCWE_x1 # 0b0011
```

#### APCB Board ID GPIO configuration.
The GPIOs determine which memory SPD will be used during boot.
```
# APCB_BOARD_ID_GPIO[0-3] = GPIO_NUMBER GPIO_IO_MUX GPIO_BANK_CTL
# GPIO_NUMBER: FCH GPIO number
# GPIO_IO_MUX: Value write to IOMUX to configure this GPIO
# GPIO_BANK_CTL: Value write to GPIOBankCtl[23:16] to configure this GPIO
APCB_BOARD_ID_GPIO0 = 121 1 0
APCB_BOARD_ID_GPIO1 = 120 1 0
APCB_BOARD_ID_GPIO2 = 131 3 0
APCB_BOARD_ID_GPIO3 = 116 1 0
```
SPD and GPIOs used to select the correct slot.

## Footnotes

Expand Down
302 changes: 302 additions & 0 deletions Documentation/technotes/asan.md
View file
@@ -0,0 +1,302 @@
# Address Sanitizer

Memory safety is hard to achieve. We, as humans, are bound to make mistakes in
our code. While it may be straightforward to detect memory corruption bugs in
few lines of code, it becomes quite challenging to find those bugs in a massive
code. In such cases, 'Address Sanitizer' may prove to be useful and could help
save time.

[Address Sanitizer](https://github.com/google/sanitizers/wiki/AddressSanitizer)
, also known as ASan, is a runtime memory debugger designed to find
out-of-bounds accesses and use-after-scope bugs. coreboot has an in-built
Address Sanitizer. Therefore, it is advised to take advantage of this debugging
tool while working on large patches. This would further help to ensure code
quality and make runtime code more robust.

## Types of errors detected
ASan in coreboot catches the following types of memory bugs:

### Stack buffer overflow
Example stack-out-of-bounds:
```c
void foo()
{
int stack_array[5] = {0};
int i, out;
for (i = 0; i < 10; i++)
out = stack_array[i];
}
```
In this example, the array is of length 5 but it is being read even beyond the
index 4.

### Global buffer overflow
Example global-out-of-bounds:
```c
char a[] = "I use coreboot";

void foo()
{
char b[] = "proprietary BIOS";
strcpy(a + 6, b);
}
```
In this example,
> well, you are replacing coreboot with proprietary BIOS. In any case, that's
an "error".

Let's come to the memory bug. The string 'a' is of length 14 but it is being
written to even beyond that.

### Use after scope
Example use-after-scope:
```c
volatile int *p = 0;

void foo() {
{
int x = 0;
p = &x;
}
*p = 5;
}
```
In this example, the value 5 is written to an undefined address instead of the
variable 'x'. This happens because 'x' can't be accessed outside its scope.

## Using ASan

In order to enable ASan on a supported platform,
select `Address sanitizer support` from `General setup` menu while configuring
coreboot.

Then build coreboot and run the image as usual. If your code contains any of the
above-mentioned memory bugs, ASan will report them in the console log as shown
below:
```text
ASan: <bug type> in <ip>
<access type> of <access size> bytes at addr <access address>
```
where,

`bug type` is either `stack-out-of-bounds`, `global-out-of-bounds` or
`use-after-scope`,

`ip` is the address of the last good instruction before the bad access,

`access type` is either `Read` or `Write`,

`access size` is the number of bytes read or written, and

`access address` is the memory location which is accessed while the error
occurs.

Next, you have to use `ip` to retrieve the instruction which causes the error.
Since stages in coreboot are relocated, you need to normalize `ip`. For this,
first subtract the start address of the stage from `ip`. Then, read the section
headers from `<stage>.debug` file to determine the offset of the text segment.
Add this offset to the difference you calculated earlier. Let's call the
resultant address `ip'`.

Next, read the contents of the symbol table and search for a function having
an address closest to `ip'`. This is the function in which our memory bug is
present. Let's denote the address of this function by `ip''`.

Finally, read the assembly contents of the object file where this function is
present. Look for the affected function. Here, the instruction which exists at
the offset `ip' - ip''` corresponds to the address `ip`. Therefore, the very
next instruction is the one which causes the error.

To see ASan in action, let's take an example. Suppose, there is a
stack-out-of-bounds error in cbfs.c that we aren’t aware of and we want ASan
to help us detect it.
```c
int cbfs_boot_region_device(struct region_device *rdev)
{
int array[5], i;
boot_device_init();

for (i = 10; i > 0; i--)
array[i] = i;

return vboot_locate_cbfs(rdev) &&
fmap_locate_area_as_rdev("COREBOOT", rdev);
}
```
First, we enable ASan from the configuration menu as shown above. Then, we
build coreboot and run the image.
ASan reports the following error in the console log:
```text
ASan: stack-out-of-bounds in 0x7f7432fd
Write of 4 bytes at addr 0x7f7c2ac8
```
Here 0x7f7432fd is `ip` i.e. the address of the last good instruction before
the bad access. First we have to normalize this address as stated above.
As per the console log, this error happened in ramstage and the stage starts
from 0x7f72c000. So, let’s look at the sections headers of ramstage from
`ramstage.debug`.
```text
$ objdump -h build/cbfs/fallback/ramstage.debug
build/cbfs/fallback/ramstage.debug: file format elf32-i386
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 00070b20 00e00000 00e00000 00001000 2**12
CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
1 .ctors 0000036c 00e70b20 00e70b20 00071b20 2**2
CONTENTS, ALLOC, LOAD, RELOC, DATA
2 .data 0001c8f4 00e70e8c 00e70e8c 00071e8c 2**2
CONTENTS, ALLOC, LOAD, RELOC, DATA
3 .bss 00012940 00e8d780 00e8d780 0008e780 2**7
ALLOC
4 .heap 00004000 00ea00c0 00ea00c0 0008e780 2**0
ALLOC
```
As you can see, the offset of the text segment is 0x00e00000. Let's subtract the
start address of the stage from `ip` and add this offset to the difference. The
resultant address i.e. `ip'` is 0x00e172fd.

Next, we read the contents of the symbol table and search for a function having
an address closest to 0x00e172fd.
```text
$ nm -n build/cbfs/fallback/ramstage.debug
........
........
00e17116 t _GLOBAL__sub_I_65535_1_gfx_get_init_done
00e17129 t tohex16
00e171db T cbfs_load_and_decompress
00e1729b T cbfs_boot_region_device
00e17387 T cbfs_boot_locate
00e1740d T cbfs_boot_map_with_leak
00e174ef T cbfs_boot_map_optionrom
........
........
```
The symbol having an address closest to 0x00e172fd is `cbfs_boot_region_device` and
its address i.e. `ip''` is 0x00e1729b.

Now, as we know the affected function, let's read the assembly contents of
`cbfs_boot_region_device()` which is present in `cbfs.o` to find the faulty
instruction.
```text
$ objdump -d build/ramstage/lib/cbfs.o
........
........
51: e8 fc ff ff ff call 52 <cbfs_boot_region_device+0x52>
56: 83 ec 0c sub $0xc,%esp
59: 57 push %edi
5a: 83 ef 04 sub $0x4,%edi
5d: e8 fc ff ff ff call 5e <cbfs_boot_region_device+0x5e>
62: 83 c4 10 add $0x10,%esp
65: 89 5f 04 mov %ebx,0x4(%edi)
68: 4b dec %ebx
69: 75 eb jne 56 <cbfs_boot_region_device+0x56>
........
........
```
Here, we look for the instruction present at the offset 62 i.e. `ip' - ip''`.
The instruction is `add $0x10,%esp` and it corresponds to
`for (i = 10; i > 0; i--)` in our code. It means the very next instruction
i.e. `mov %ebx,0x4(%edi)` is the one that causes the error. Now, as we look at
C code of `cbfs_boot_region_device()` again, we find that this instruction
corresponds to `array[i] = i`.

Voilà! We just caught the memory bug using ASan.

## Supported platforms
Presently, the following architectures support ASan in ramstage:
```eval_rst
+------------------+--------------------------------+
| Architecture | Notes |
+==================+================================+
| x86 | Support for all x86 platforms |
+------------------+--------------------------------+
```

And in romstage ASan is available on the following platforms:
```eval_rst
+---------------------+-----------------------------+
| Platform | Notes |
+=====================+=============================+
| QEMU i440-fx | |
+---------------------+-----------------------------+
| Intel Apollo Lake | |
+---------------------+-----------------------------+
| Intel Haswell | |
+---------------------+-----------------------------+
```
Alternatively, you can use `grep` to view the list of platforms that support
ASan in romstage:

$ git grep "select HAVE_ASAN_IN_ROMSTAGE"

If the x86 platform you are using is not listed here, there is
still a chance that it supports ASan in romstage.

To test it, select `HAVE_ASAN_IN_ROMSTAGE` from the Kconfig file in the
platform's dedicated directory. Then, enable ASan from the config menu as
indicated in the previous section.

If you are able to build coreboot without any errors and boot cleanly, that
means the platform supports ASan in romstage. In that case, please upload a
patch on Gerrit selecting this config option using 'ASan' topic. Also, update
the platform name in the table.

However, if you end up in compilation errors or the linker error saying that
the cache got full, additional steps need to be taken to enable ASan in
romstage on the platform. While compile errors could be resolved easily and
therefore ASan in romstage has a good chance to be supported, a full cache is
an indication that it is way more work or even likely impossible to enable
ASan in romstage.

## Future work
### Heap buffer overflow
Presently, ASan doesn't detect out-of-bounds accesses for the objects defined
in heap.

To add support for these type of memory bugs, you have to make sure that
whenever some block of memory is allocated in the heap, the surrounding areas
(redzones) are poisoned. Correspondingly, these redzones should be unpoisoned
when the memory block is de-allocated.

### ASan on other architectures
The following points should help when adding support for ASan to other
architectures like ARM or RISC-V:

* Enabling ASan in ramstage on other architectures should be easy. You just
have to make sure the shadow memory is initialized as early as possible when
ramstage is loaded. This can be done by making a function call to `asan_init()`
at the appropriate place.

* For romstage, you have to find out if there is enough room in the cache to fit
the shadow memory region. For this, find the boundary linker symbols for the
region you'd want to run ASan on, excluding the hardware mapped addresses.
Then define a new linker section named `asan_shadow` of size
`(_end - _start) >> 3`, where `_start` and `_end` are the linker symbols you
found earlier. This section should be appended to the region already occupied
by the coreboot program. Now build coreboot. If you don't see any errors while
building with the current translation function, ASan can be enabled on that
platform.

* The shadow region we currently use consumes memory equal to 1/8th of the
program memory. So, if you end up in a linker error saying that the memory got
full, you'll have to use a more compact shadow region. In that case, the
translation function could be something like
`shadow = (mem >> 7) | shadow_offset`. Since the stack buffers are protected by
the compiler, you'll also have to create a GCC patch forcing it to use the new
translation function for this particular architecture.

* Once you are sure that the architecture supports ASan in ramstage, select
`HAVE_ASAN_IN_RAMSTAGE` from the Kconfig file of that architecture. Similarly,
if the platform supports ASan in romstage, select `HAVE_ASAN_IN_ROMSTAGE` from
the platform's dedicated Kconfig file.

### Post-processing script
Unlike Linux, coreboot doesn't have `%pS` printk format to dereference pointer
to its symbolic name. Therefore, we normalise the pointer address manually to
determine the name of the affected function and further use it to find the
instruction which causes the error.

A custom script can be written to automate this process.
1 change: 1 addition & 0 deletions Documentation/technotes/index.md
View file
Expand Up @@ -3,3 +3,4 @@
* [Dealing with Untrusted Input in SMM](2017-02-dealing-with-untrusted-input-in-smm.md)
* [Rebuilding coreboot image generation](2015-11-rebuilding-coreboot-image-generation.md)
* [Unit testing coreboot](2020-03-unit-testing-coreboot.md)
* [Address Sanitizer](asan.md)
19 changes: 13 additions & 6 deletions Makefile.inc
View file
Expand Up @@ -264,12 +264,14 @@ REDUNDANT_OFFSET_REMARK = 2158
# "Multiple types (Device object requires either a _HID or _ADR, but not both)"
MULTIPLE_TYPES_WARNING = 3073

IASL_WARNINGS_LIST = $(EMPTY_RESOURCE_TEMPLATE_WARNING) $(REDUNDANT_OFFSET_REMARK)

ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT)$(CONFIG_SOC_INTEL_BROADWELL),y)
IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK) -vw $(MULTIPLE_TYPES_WARNING)
else
IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK)
IASL_WARNINGS_LIST += $(MULTIPLE_TYPES_WARNING)
endif

IGNORED_IASL_WARNINGS = $(addprefix -vw , $(IASL_WARNINGS_LIST))

define asl_template
$(CONFIG_CBFS_PREFIX)/$(1).aml-file = $(obj)/$(1).aml
$(CONFIG_CBFS_PREFIX)/$(1).aml-type = raw
Expand All @@ -280,6 +282,7 @@ $(obj)/$(1).aml: $(src)/mainboard/$(MAINBOARDDIR)/$(1).asl $(obj)/config.h
@printf " IASL $$(subst $(top)/,,$$(@))\n"
$(CC_ramstage) -x assembler-with-cpp -E -MMD -MT $$(@) $$(CPPFLAGS_ramstage) -D__ACPI__ -P -include $(src)/include/kconfig.h -I$(obj) -I$(src) -I$(src)/include -I$(src)/arch/$(ARCHDIR-$(ARCH-ramstage-y))/include -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $(obj)/$(1).asl
cd $$(dir $$@); $(IASL) $(IGNORED_IASL_WARNINGS) -we -p $$(notdir $$@) $(1).asl
echo " IASL "$(IASL_WARNINGS_LIST)" warning types were ignored!"
if ! $(IASL) -d $$@ 2>&1 | grep -Eq 'ACPI (Warning|Error)'; then \
echo " IASL $$@ disassembled correctly."; \
true; \
Expand Down Expand Up @@ -592,19 +595,23 @@ $(obj)/config.h: $(objutil)/kconfig/conf
# Creation of these is architecture and mainboard independent
DEVICETREE_FILE := $(src)/mainboard/$(MAINBOARDDIR)/$(CONFIG_DEVICETREE)

ifneq ($(CONFIG_OVERRIDE_DEVICETREE),)
SCONFIG_OPTIONS := --mainboard_devtree=$(DEVICETREE_FILE)

ifneq ($(CONFIG_OVERRIDE_DEVICETREE),)
OVERRIDE_DEVICETREE_FILE := $(src)/mainboard/$(MAINBOARDDIR)/$(CONFIG_OVERRIDE_DEVICETREE)

SCONFIG_OPTIONS += --override_devtree=$(OVERRIDE_DEVICETREE_FILE)
endif

DEVICETREE_STATIC_C := $(obj)/mainboard/$(MAINBOARDDIR)/static.c
SCONFIG_OPTIONS += --output_c=$(DEVICETREE_STATIC_C)

DEVICETREE_STATIC_H := $(obj)/static.h
SCONFIG_OPTIONS += --output_h=$(DEVICETREE_STATIC_H)

$(DEVICETREE_STATIC_C): $(DEVICETREE_FILE) $(OVERRIDE_DEVICETREE_FILE) $(objutil)/sconfig/sconfig
@printf " SCONFIG $(subst $(src)/,,$(<))\n"
mkdir -p $(dir $(DEVICETREE_STATIC_C))
$(objutil)/sconfig/sconfig $(DEVICETREE_FILE) $(DEVICETREE_STATIC_C) $(DEVICETREE_STATIC_H) $(OVERRIDE_DEVICETREE_FILE)
$(objutil)/sconfig/sconfig $(SCONFIG_OPTIONS)

ramstage-y+=$(DEVICETREE_STATIC_C)
romstage-y+=$(DEVICETREE_STATIC_C)
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu1
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.12.0.4"
CONFIG_LOCALVERSION="v4.12.0.5"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_NO_GFX_INIT=y
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu2
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.12.0.4"
CONFIG_LOCALVERSION="v4.12.0.5"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU2=y
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu3
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.12.0.4"
CONFIG_LOCALVERSION="v4.12.0.5"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU3=y
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu4
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.12.0.4"
CONFIG_LOCALVERSION="v4.12.0.5"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU4=y
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu5
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.12.0.4"
CONFIG_LOCALVERSION="v4.12.0.5"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU5=y
Expand Down
24 changes: 24 additions & 0 deletions configs/config.pcengines_apu6
View file
@@ -0,0 +1,24 @@
CONFIG_LOCALVERSION="v4.12.0.5"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU6=y
CONFIG_PXE_ROM_ID="8086,1539"
CONFIG_NO_GFX_INIT=y
CONFIG_USER_TPM2=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
CONFIG_SEABIOS_REVISION=y
CONFIG_SEABIOS_REVISION_ID="rel-1.12.1.3"
CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
CONFIG_SEABIOS_DEBUG_LEVEL=0
CONFIG_PXE=y
CONFIG_BUILD_IPXE=y
# CONFIG_PXE_SERIAL_CONSOLE is not set
CONFIG_PXE_CUSTOM_BUILD_ID="12345678"
CONFIG_PXE_ADD_SCRIPT=y
CONFIG_PXE_SCRIPT="payloads/external/iPXE/menu.ipxe"
CONFIG_MEMTEST_SECONDARY_PAYLOAD=y
CONFIG_SORTBOOTORDER_SECONDARY_PAYLOAD=y
CONFIG_MEMTEST_REVISION=y
CONFIG_MEMTEST_REVISION_ID="0b756257276729c1a12bc1d95e7a1f044894bda2"
CONFIG_SORTBOOTORDER_REVISION=y
CONFIG_SORTBOOTORDER_REVISION_ID="v4.6.20"
14 changes: 14 additions & 0 deletions payloads/coreinfo/AUTHORS
View file
@@ -0,0 +1,14 @@
# This is the list of coreinfo authors for copyright purposes.
#
# This does not necessarily list everyone who has contributed code, since in
# some cases, their employer may be the copyright holder. To see the full list
# of contributors, and their email addresses, see the revision history in source
# control.
# Run the below commands in the coreinfo repo for additional information.
# To see a list of contributors: git log --pretty=format:%an | sort | uniq
# For patches adding or removing a name: git log -i -S "NAME" --source --all

Advanced Micro Devices, Inc.
Dave Jones
Jordan Crouse
Uwe Hermann
4 changes: 0 additions & 4 deletions payloads/coreinfo/Kconfig
View file
@@ -1,7 +1,3 @@
##
##
## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
##
## SPDX-License-Identifier: GPL-2.0-only

# For a description of the syntax of this configuration file,
Expand Down
5 changes: 0 additions & 5 deletions payloads/coreinfo/Makefile
View file
@@ -1,8 +1,3 @@
##
##
## Copyright (C) 2008 Advanced Micro Devices, Inc.
## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
##
## SPDX-License-Identifier: GPL-2.0-only

src := $(CURDIR)
Expand Down
17 changes: 1 addition & 16 deletions payloads/coreinfo/bootlog_module.c
View file
@@ -1,16 +1,4 @@
/*
*
* Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */

#include "coreinfo.h"

Expand All @@ -19,14 +7,12 @@
#define LINES_SHOWN 19
#define TAB_WIDTH 2


/* Globals that are used for tracking screen state */
static char *g_buf = NULL;
static s32 g_line = 0;
static s32 g_lines_count = 0;
static s32 g_max_cursor_line = 0;


/* Copied from libpayload/drivers/cbmem_console.c */
struct cbmem_console {
u32 size;
Expand All @@ -37,7 +23,6 @@ struct cbmem_console {
#define CURSOR_MASK ((1 << 28) - 1)
#define OVERFLOW (1 << 31)


static u32 char_width(char c, u32 cursor, u32 screen_width)
{
if (c == '\n') {
Expand Down
14 changes: 1 addition & 13 deletions payloads/coreinfo/cbfs_module.c
View file
@@ -1,16 +1,4 @@
/*
*
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */

#include "coreinfo.h"
#include "endian.h"
Expand Down
14 changes: 1 addition & 13 deletions payloads/coreinfo/coreboot_module.c
View file
@@ -1,16 +1,4 @@
/*
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */

#include "coreinfo.h"
#include <coreboot_tables.h>
Expand Down
14 changes: 1 addition & 13 deletions payloads/coreinfo/coreinfo.c
View file
@@ -1,16 +1,4 @@
/*
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */

#include "coreinfo.h"

Expand Down
14 changes: 1 addition & 13 deletions payloads/coreinfo/coreinfo.h
View file
@@ -1,16 +1,4 @@
/*
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */

#ifndef COREINFO_H_
#define COREINFO_H_
Expand Down
18 changes: 3 additions & 15 deletions payloads/coreinfo/cpuid.S
View file
@@ -1,18 +1,6 @@
/*
*
* It is derived from the x86info project, which is GPLv2-licensed.
*
* Copyright (C) 2001-2007 Dave Jones <davej@codemonkey.org.uk>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */

/* It is derived from the x86info project, which is GPLv2-licensed. */

/* calling syntax: docpuid(idx,eax,ebx,ecx,edx) */

Expand Down
19 changes: 3 additions & 16 deletions payloads/coreinfo/cpuinfo_module.c
View file
@@ -1,19 +1,6 @@
/*
*
* It is derived from the x86info project, which is GPLv2-licensed.
*
* Copyright (C) 2001-2007 Dave Jones <davej@codemonkey.org.uk>
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */

/* It is derived from the x86info project, which is GPLv2-licensed. */

#include "coreinfo.h"

Expand Down
14 changes: 1 addition & 13 deletions payloads/coreinfo/multiboot_module.c
View file
@@ -1,16 +1,4 @@
/*
*
* Copyright (C) 2008 Jordan Crouse <jordan@cosmicpenguin.net>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */

#include <multiboot_tables.h>
#include "coreinfo.h"
Expand Down
14 changes: 1 addition & 13 deletions payloads/coreinfo/nvram_module.c
View file
@@ -1,16 +1,4 @@
/*
*
* Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */

#include "coreinfo.h"

Expand Down
14 changes: 1 addition & 13 deletions payloads/coreinfo/pci_module.c
View file
@@ -1,16 +1,4 @@
/*
*
* Copyright (C) 2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */

#include <arch/io.h>
#include <pci.h>
Expand Down
14 changes: 1 addition & 13 deletions payloads/coreinfo/ramdump_module.c
View file
@@ -1,16 +1,4 @@
/*
*
* Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */

#include "coreinfo.h"

Expand Down
12 changes: 1 addition & 11 deletions payloads/coreinfo/timestamps_module.c
View file
@@ -1,14 +1,4 @@
/*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: GPL-2.0-only */

#include "coreinfo.h"
#include <commonlib/timestamp_serialized.h>
Expand Down
1 change: 0 additions & 1 deletion payloads/external/LinuxBoot/Kconfig
View file
Expand Up @@ -135,7 +135,6 @@ config LINUXBOOT_KERNEL_UIMAGE

endchoice


config LINUXBOOT_DTB_FILE
string "Compiled devicetree file"
depends on LINUXBOOT_ARM64 || LINUXBOOT_RISCV
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/arch/arm64/virtual.c
View file
Expand Up @@ -30,7 +30,6 @@

unsigned long virtual_offset = 0;


int getpagesize(void)
{
return 4096;
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/arch/x86/Kconfig
View file
Expand Up @@ -52,5 +52,4 @@ config DIE_ON_UNKNOWN_INTERRUPT

endchoice


endif
1 change: 0 additions & 1 deletion payloads/libpayload/arch/x86/apic.c
View file
Expand Up @@ -127,7 +127,6 @@ void apic_start_delay(unsigned int usec)
enable_interrupts();
}


void apic_wait_delay(void)
{
/* Loop in case another interrupt has fired and resumed execution. */
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/arch/x86/delay.c
View file
Expand Up @@ -38,7 +38,6 @@
/* Let's assume APIC interrupts take at least 100us */
#define APIC_INTERRUPT_LATENCY_NS (100 * NSECS_PER_USEC)


void arch_ndelay(uint64_t ns)
{
uint64_t delta = ns * timer_hz() / NSECS_PER_SEC;
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/arch/x86/virtual.c
View file
Expand Up @@ -30,7 +30,6 @@

unsigned long virtual_offset = 0;


int getpagesize(void)
{
return 4096;
Expand Down
3 changes: 0 additions & 3 deletions payloads/libpayload/crypto/sha1.c
View file
Expand Up @@ -115,7 +115,6 @@ SHA1Transform(u_int32_t state[5], const u_int8_t buffer[SHA1_BLOCK_LENGTH])
a = b = c = d = e = 0;
}


/*
* SHA1Init - Initialize new context
*/
Expand All @@ -132,7 +131,6 @@ SHA1Init(SHA1_CTX *context)
context->state[4] = 0xC3D2E1F0;
}


/*
* Run your data through this.
*/
Expand All @@ -155,7 +153,6 @@ SHA1Update(SHA1_CTX *context, const u_int8_t *data, size_t len)
(void)memcpy(&context->buffer[j], &data[i], len - i);
}


/*
* Add padding and return the message digest.
*/
Expand Down
3 changes: 0 additions & 3 deletions payloads/libpayload/curses/PDCurses/demos/tui.c
View file
Expand Up @@ -46,14 +46,12 @@ void rmerror(void);
# define EDITBOXCOLOR (A_BOLD | A_REVERSE)
#endif


#define th 1 /* title window height */
#define mh 1 /* main menu height */
#define sh 2 /* status window height */
#define bh (LINES - th - mh - sh) /* body window height */
#define bw COLS /* body window width */


/******************************* STATIC ************************************/

static WINDOW *wtitl, *wmain, *wbody, *wstat; /* title, menu, body, status win*/
Expand Down Expand Up @@ -360,7 +358,6 @@ static void cleanup(void) /* cleanup curses settings */
}
}


/******************************* EXTERNAL **********************************/

void clsbody(void)
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/curses/PDCurses/x11/ScrollBox.c
View file
Expand Up @@ -116,7 +116,6 @@ ScrollBoxClassRec scrollBoxClassRec = {

WidgetClass scrollBoxWidgetClass = (WidgetClass)&scrollBoxClassRec;


/************************************************************************
* *
* Private Routines *
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/curses/PDCurses/x11/ScrollBox.h
View file
Expand Up @@ -42,7 +42,6 @@
*/


/* Class record constants */

extern WidgetClass scrollBoxWidgetClass;
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/curses/PDCurses/x11/ScrollBoxP.h
View file
Expand Up @@ -56,7 +56,6 @@ typedef struct {
XtGeometryMask last_query_mode;
} ScrollBoxPart;


/************************************************************************
* *
* Full instance record declaration *
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/curses/PDCurses/x11/x11.c
View file
Expand Up @@ -276,7 +276,6 @@ static char *program_name;

#define RCOLOR(name, value) RPIXEL(color##name, Color##name, value)


#define RSTRINGP(name1, name2, param) { \
#name1, #name2, XtRString, \
MAX_PATH, APPDATAOFF(name1), XtRString, (XtPointer)param \
Expand Down
3 changes: 0 additions & 3 deletions payloads/libpayload/curses/curses.priv.h
View file
Expand Up @@ -32,7 +32,6 @@
* and: Thomas E. Dickey 1996-on *
****************************************************************************/


/*
* $Id: curses.priv.h,v 1.314 2006/12/10 00:55:14 tom Exp $
*
Expand Down Expand Up @@ -497,7 +496,6 @@ struct screen {
chtype * _acs_map; /* the real alternate-charset map */
bool * _screen_acs_map;


/* used in lib_vidattr.c */
bool _use_rmso; /* true if we may use 'rmso' */
bool _use_rmul; /* true if we may use 'rmul' */
Expand Down Expand Up @@ -980,7 +978,6 @@ extern NCURSES_EXPORT(void) name (void); \
}\
TR(TRACE_ATTRS, ("new attribute is %s", _traceattr((S))));}


#define toggle_attr_off(S,at) {\
if (PAIR_NUMBER(at) > 0) {\
(S) &= ~(at|A_COLOR);\
Expand Down
2 changes: 0 additions & 2 deletions payloads/libpayload/curses/form/form.h
View file
Expand Up @@ -106,7 +106,6 @@ typedef struct fieldnode {
NCURSES_FIELD_INTERNALS
} FIELD;


/*********
* FORM *
*********/
Expand Down Expand Up @@ -138,7 +137,6 @@ typedef struct formnode {

} FORM;


/**************
* FIELDTYPE *
**************/
Expand Down
3 changes: 0 additions & 3 deletions payloads/libpayload/curses/menu/menu.h
View file
Expand Up @@ -132,7 +132,6 @@ typedef struct tagMENU

} MENU;


/* Define keys */

#define REQ_LEFT_ITEM (KEY_MAX + 1)
Expand Down Expand Up @@ -170,7 +169,6 @@ typedef struct tagMENU
# define MAX_COMMAND (KEY_MAX + 128)
#endif


/* --------- prototypes for libmenu functions ----------------------------- */

extern NCURSES_EXPORT(ITEM **) menu_items (const MENU *);
Expand Down Expand Up @@ -244,7 +242,6 @@ extern NCURSES_EXPORT(int) menu_request_by_name (const char *);
extern NCURSES_EXPORT(int) set_menu_spacing (MENU *,int,int,int);
extern NCURSES_EXPORT(int) menu_spacing (const MENU *,int *,int *,int *);


extern NCURSES_EXPORT(bool) item_value (const ITEM *);
extern NCURSES_EXPORT(bool) item_visible (const ITEM *);

Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/curses/menu/mf_common.h
View file
Expand Up @@ -66,7 +66,6 @@ extern int errno;
#define MODULE_ID(id) /*nothing*/
#endif


/* Maximum regular 8-bit character code */
#define MAX_REGULAR_CHARACTER (0xff)

Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/curses/tinycurses.c
View file
Expand Up @@ -163,7 +163,6 @@ chtype console_acs_map[128] =
// FIXME: Ugly (and insecure!) hack!
char sprintf_tmp[1024];


int curses_flags = (F_ENABLE_CONSOLE | F_ENABLE_SERIAL);

/* Return bit mask for clearing color pair number if given ch has color */
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/nvram.c
View file
Expand Up @@ -42,7 +42,6 @@
#include <libpayload-config.h>
#include <libpayload.h>


/**
* PCs can have either 64 (very old ones), 128, or 256 bytes of CMOS RAM.
*
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/serial/qcom_qupv3_serial.c
View file
Expand Up @@ -27,7 +27,6 @@
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/


/* For simplicity sake let's rely on coreboot initializing the UART. */
#include <config.h>
#include <libpayload.h>
Expand Down
2 changes: 0 additions & 2 deletions payloads/libpayload/drivers/storage/ahci.c
View file
Expand Up @@ -39,7 +39,6 @@

#include "ahci_private.h"


#ifdef DEBUG_STATUS
static inline u32 _ahci_clear_status(volatile u32 *const reg,
const char *const r,
Expand All @@ -64,7 +63,6 @@ static inline u32 _ahci_clear_status(volatile u32 *const reg)
#define ahci_clear_status(p, r) _ahci_clear_status(&(p)->r)
#endif


static inline int ahci_port_is_active(const hba_port_t *const port)
{
return (port->sata_status & (HBA_PxSSTS_IPM_MASK | HBA_PxSSTS_DET_MASK))
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/storage/ahci_ata.c
View file
Expand Up @@ -37,7 +37,6 @@

#include "ahci_private.h"


ssize_t ahci_ata_read_sectors(ata_dev_t *const ata_dev,
const lba_t start, size_t count,
u8 *const buf)
Expand Down
2 changes: 0 additions & 2 deletions payloads/libpayload/drivers/storage/ahci_atapi.c
View file
Expand Up @@ -35,10 +35,8 @@
#include <storage/ata.h>
#include <storage/ahci.h>


#include "ahci_private.h"


ssize_t ahci_packet_read_cmd(atapi_dev_t *const _dev,
const u8 *const cmd, const size_t cmdlen,
u8 *const buf, const size_t buflen)
Expand Down
2 changes: 0 additions & 2 deletions payloads/libpayload/drivers/storage/ahci_common.c
View file
Expand Up @@ -37,7 +37,6 @@

#include "ahci_private.h"


#ifdef DEBUG_STATUS
static inline u32 _ahci_clear_status(volatile u32 *const reg,
const char *const r,
Expand All @@ -62,7 +61,6 @@ static inline u32 _ahci_clear_status(volatile u32 *const reg)
#define ahci_clear_status(p, r) _ahci_clear_status(&(p)->r)
#endif


/** Give a buffer with even address. */
static u8 *ahci_prdbuf_init(ahci_dev_t *const dev,
u8 *const user_buf, const size_t len,
Expand Down
2 changes: 0 additions & 2 deletions payloads/libpayload/drivers/storage/ahci_private.h
View file
Expand Up @@ -120,7 +120,6 @@ typedef volatile struct {
#define HBA_CTRL_INTR_EN (1 << 1)
#define HBA_CTRL_RESET (1 << 0)


typedef volatile struct {
u8 dma_setup_fis[28];
u8 _reserved0[4];
Expand Down Expand Up @@ -229,5 +228,4 @@ ssize_t ahci_ata_read_sectors(ata_dev_t *const ata_dev,
const lba_t start, size_t count,
u8 *const buf);


#endif /* _AHCI_PRIVATE_H */
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/storage/ata.c
View file
Expand Up @@ -33,7 +33,6 @@

#include <storage/ata.h>


/** Reads non-sector-aligned blocks of 512 bytes. */
static ssize_t ata_read_unaligned(ata_dev_t *const dev,
const lba_t blk_start, size_t blk_count,
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/storage/atapi.c
View file
Expand Up @@ -33,7 +33,6 @@
#include <storage/ata.h>
#include <storage/atapi.h>


static int atapi_request_sense(atapi_dev_t *const dev)
{
u8 cdb[12] = { 0, };
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/storage/storage.c
View file
Expand Up @@ -32,7 +32,6 @@
#endif
#include <storage/storage.h>


static storage_dev_t **devices = NULL;
static size_t devices_length = 0;
static size_t dev_count = 0;
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/udc/chipidea.c
View file
Expand Up @@ -300,7 +300,6 @@ static void start_setup(struct usbdev_ctrl *this, int ep)
udc_handle_setup(this, ep, &dr);
}


static void chipidea_enqueue_packet(struct usbdev_ctrl *this, int endpoint,
int in_dir, void *data, int len, int zlp, int autofree)
{
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/dwc2_rh.c
View file
Expand Up @@ -12,7 +12,6 @@
* GNU General Public License for more details.
*/


#include <usb/usb.h>
#include "generic_hub.h"
#include "dwc2_private.h"
Expand Down
2 changes: 0 additions & 2 deletions payloads/libpayload/drivers/usb/ehci.c
View file
Expand Up @@ -426,7 +426,6 @@ static int ehci_bulk (endpoint_t *ep, int size, u8 *src, int finalize)
return -1;
}


/* FIXME: Handle control transfers as 3 QHs, so the 2nd stage can be >0x4000 bytes */
static int ehci_control (usbdev_t *dev, direction_t dir, int drlen, void *setup,
int dalen, u8 *src)
Expand Down Expand Up @@ -544,7 +543,6 @@ static int ehci_control (usbdev_t *dev, direction_t dir, int drlen, void *setup,
return -1;
}


typedef struct _intr_qtd_t intr_qtd_t;

struct _intr_qtd_t {
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/ehci_rh.c
View file
Expand Up @@ -171,7 +171,6 @@ ehci_rh_poll (usbdev_t *dev)
ehci_rh_scanport (dev, port);
}


void
ehci_rh_init (usbdev_t *dev)
{
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/ohci.c
View file
Expand Up @@ -627,7 +627,6 @@ ohci_bulk (endpoint_t *ep, int dalen, u8 *src, int finalize)
return result;
}


struct _intr_queue;

struct _intrq_td {
Expand Down
5 changes: 0 additions & 5 deletions payloads/libpayload/drivers/usb/usbhid.c
View file
Expand Up @@ -131,8 +131,6 @@ const char *countries[36][2] = {
/* 36 - 255: Reserved */
};



struct layout_maps {
const char *country;
const short map[4][0x80];
Expand Down Expand Up @@ -247,7 +245,6 @@ static const struct layout_maps keyboard_layouts[] = {
//#endif
};


static void usb_hid_keyboard_queue(int ch) {
/* ignore key presses if buffer full */
if (keycount < KEYBOARD_BUFFER_SIZE)
Expand Down Expand Up @@ -316,7 +313,6 @@ usb_hid_process_keyboard_event(usbhid_inst_t *const inst,
if (skip)
continue;


/* Mask off KB_MOD_CTRL */
keypress = map->map[modifiers & 0x03][current->keys[i]];

Expand Down Expand Up @@ -397,7 +393,6 @@ static struct console_input_driver cons = {
.input_type = CONSOLE_INPUT_TYPE_USB,
};


static int usb_hid_set_layout (const char *country)
{
/* FIXME should be per keyboard */
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/usbmsc.c
View file
Expand Up @@ -613,7 +613,6 @@ usb_msc_init (usbdev_t *dev)
usb_debug (" it uses %s protocol\n",
msc_protocol_strings[interface->bInterfaceProtocol]);


if (interface->bInterfaceProtocol != 0x50) {
usb_debug (" Protocol not supported.\n");
usb_detach_device (dev->controller, dev->address);
Expand Down
8 changes: 7 additions & 1 deletion payloads/libpayload/drivers/usb/xhci_commands.c
View file
Expand Up @@ -75,7 +75,13 @@ xhci_wait_for_command(xhci_t *const xhci,
/* Abort command on timeout */
xhci_debug("Aborting command (@%p), CRCR: 0x%"PRIx32"\n",
cmd_trb, xhci->opreg->crcr_lo);
xhci->opreg->crcr_lo |= CRCR_CS | CRCR_CA;
/*
* Ref. xHCI Specification Revision 1.2, May 2019.
* Section 5.4.5, Table 5-24.
*
* Abort the command and stop the ring.
*/
xhci->opreg->crcr_lo |= CRCR_CA;
xhci->opreg->crcr_hi = 0;
cc = xhci_wait_for_command_aborted(xhci, cmd_trb);

Expand Down
34 changes: 27 additions & 7 deletions payloads/libpayload/drivers/usb/xhci_events.c
View file
Expand Up @@ -226,7 +226,15 @@ xhci_wait_for_event_type(xhci_t *const xhci,
return *timeout_us;
}

/* returns cc of command in question (pointed to by `address`) */
/*
* Ref. xHCI Specification Revision 1.2, May 2019.
* Section 4.6.1.2.
*
* Process events from xHCI Abort command.
*
* Returns CC_COMMAND_RING_STOPPED on success and TIMEOUT on failure.
*/

int
xhci_wait_for_command_aborted(xhci_t *const xhci, const trb_t *const address)
{
Expand All @@ -239,33 +247,45 @@ xhci_wait_for_command_aborted(xhci_t *const xhci, const trb_t *const address)
int cc = TIMEOUT;
/*
* Expects two command completion events:
* The first with CC == COMMAND_ABORTED should point to address,
* The first with CC == COMMAND_ABORTED should point to address
* (not present if command was not running),
* the second with CC == COMMAND_RING_STOPPED should point to new dq.
*/
while (xhci_wait_for_event_type(xhci, TRB_EV_CMD_CMPL, &timeout_us)) {
if ((xhci->er.cur->ptr_low == virt_to_phys(address)) &&
(xhci->er.cur->ptr_high == 0)) {
(xhci->er.cur->ptr_high == 0)) {
cc = TRB_GET(CC, xhci->er.cur);
xhci_advance_event_ring(xhci);
break;
}

xhci_handle_command_completion_event(xhci);
}
if (!timeout_us)
xhci_debug("Warning: Timed out waiting for COMMAND_ABORTED.\n");
if (timeout_us == 0) {
xhci_debug("Warning: Timed out waiting for "
"COMMAND_ABORTED or COMMAND_RING_STOPPED.\n");
goto update_and_return;
}
if (cc == CC_COMMAND_RING_STOPPED) {
/* There may not have been a command to abort. */
goto update_and_return;
}

timeout_us = USB_MAX_PROCESSING_TIME_US; /* 5s */
while (xhci_wait_for_event_type(xhci, TRB_EV_CMD_CMPL, &timeout_us)) {
if (TRB_GET(CC, xhci->er.cur) == CC_COMMAND_RING_STOPPED) {
xhci->cr.cur = phys_to_virt(xhci->er.cur->ptr_low);
cc = CC_COMMAND_RING_STOPPED;
xhci_advance_event_ring(xhci);
break;
}

xhci_handle_command_completion_event(xhci);
}
if (!timeout_us)
if (timeout_us == 0)
xhci_debug("Warning: Timed out "
"waiting for COMMAND_RING_STOPPED.\n");

update_and_return:
xhci_update_event_dq(xhci);
return cc;
}
Expand Down
3 changes: 1 addition & 2 deletions payloads/libpayload/drivers/usb/xhci_private.h
View file
Expand Up @@ -204,7 +204,7 @@ typedef transfer_ring_t command_ring_t;
#define SC_UADDR_LEN 8
#define SC_STATE_FIELD f4 /* STATE - Slot State */
#define SC_STATE_START 27
#define SC_STATE_LEN 8
#define SC_STATE_LEN 5
#define SC_MASK(tok) MASK(SC_##tok##_START, SC_##tok##_LEN)
#define SC_GET(tok, sc) (((sc)->SC_##tok##_FIELD & SC_MASK(tok)) \
>> SC_##tok##_START)
Expand Down Expand Up @@ -515,7 +515,6 @@ static inline int xhci_ep_id(const endpoint_t *const ep) {
return ((ep->endpoint & 0x7f) * 2) + (ep->direction != OUT);
}


#ifdef XHCI_DUMPS
void xhci_dump_slotctx(const slotctx_t *);
void xhci_dump_epctx(const epctx_t *);
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/usb/xhci_rh.c
View file
Expand Up @@ -135,7 +135,6 @@ xhci_rh_enable_port(usbdev_t *const dev, int port)
return 0;
}


static const generic_hub_ops_t xhci_rh_ops = {
.hub_status_changed = xhci_rh_hub_status_changed,
.port_status_changed = xhci_rh_port_status_changed,
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/video/corebootfb.c
View file
Expand Up @@ -138,7 +138,6 @@ static void corebootfb_putchar(u8 row, u8 col, unsigned int ch)
((((vga_colors[fg] >> 16) & 0xff) >> (8 - fbinfo.red_mask_size)) << fbinfo.red_mask_pos);
}


dst = FB + ((row * font_height) * fbinfo.bytes_per_line);
dst += (col * font_width * (fbinfo.bits_per_pixel >> 3));

Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/drivers/video/geodelx.c
View file
Expand Up @@ -176,7 +176,6 @@ static void init_video_mode(void)
writel(((vga_mode.hactive - 1) << 16) | (vga_mode.vactive - 1),
DC + 0x5C);


/* Write the VG configuration */

writel(0x290000F | vga_mode.synccfg, VG + 0x08);
Expand Down
66 changes: 51 additions & 15 deletions payloads/libpayload/drivers/video/graphics.c
View file
Expand Up @@ -41,14 +41,17 @@
static struct rect canvas;
static struct rect screen;

static uint8_t *gfx_buffer;

/*
* Framebuffer is assumed to assign a higher coordinate (larger x, y) to
* a higher address
*/
static const struct cb_framebuffer *fbinfo;

/* Shorthand for up-to-date virtual framebuffer address */
#define FB ((unsigned char *)phys_to_virt(fbinfo->physical_address))
#define REAL_FB ((unsigned char *)phys_to_virt(fbinfo->physical_address))
#define FB (gfx_buffer ? gfx_buffer : REAL_FB)

#define LOG(x...) printf("CBGFX: " x)
#define PIVOT_H_MASK (PIVOT_H_LEFT|PIVOT_H_CENTER|PIVOT_H_RIGHT)
Expand Down Expand Up @@ -855,24 +858,25 @@ static int draw_bitmap_v3(const struct vector *top_left,
}

/*
* Initialize the sample array for this line. For pixels to the
* left of S0 there are no corresponding input pixels so just
* copy the S0 values over.
*
* Also initialize the equals counter, which counts how many of
* the latest pixels were exactly equal. We know the columns
* left of S0 must be equal to S0, so start with that number.
* Initialize the sample array for this line, and also
* the equals counter, which counts how many of the latest
* pixels were exactly equal.
*/
int equals = S0 * SSZ;
int equals = 0;
uint8_t last_equal = ypix[0][0];
for (sy = 0; sy < SSZ; sy++) {
for (sx = S0; sx < SSZ; sx++) {
if (sx >= dim_org->width) {
for (sx = 0; sx < SSZ; sx++) {
for (sy = 0; sy < SSZ; sy++) {
if (sx - S0 >= dim_org->width) {
sample[sx][sy] = sample[sx - 1][sy];
equals++;
continue;
}
uint8_t i = ypix[sy][sx - S0];
/*
* For pixels to the left of S0 there are no
* corresponding input pixels so just use
* ypix[sy][0].
*/
uint8_t i = ypix[sy][MAX(0, sx - S0)];
if (pal_to_rgb(i, pal, header->colors_used,
&sample[sx][sy]))
goto bitmap_error;
Expand All @@ -883,8 +887,6 @@ static int draw_bitmap_v3(const struct vector *top_left,
equals = 1;
}
}
for (sx = S0 - 1; sx >= 0; sx--)
sample[sx][sy] = sample[S0][sy];
}

ix = 0;
Expand Down Expand Up @@ -1257,3 +1259,37 @@ int get_bitmap_dimension(const void *bitmap, size_t sz, struct scale *dim_rel)

return CBGFX_SUCCESS;
}

int enable_graphics_buffer(void)
{
if (gfx_buffer)
return CBGFX_SUCCESS;

if (cbgfx_init())
return CBGFX_ERROR_INIT;

size_t buffer_size = fbinfo->y_resolution * fbinfo->bytes_per_line;
gfx_buffer = malloc(buffer_size);
if (!gfx_buffer) {
LOG("%s: Failed to create graphics buffer (%zu bytes).\n",
__func__, buffer_size);
return CBGFX_ERROR_GRAPHICS_BUFFER;
}

return CBGFX_SUCCESS;
}

int flush_graphics_buffer(void)
{
if (!gfx_buffer)
return CBGFX_ERROR_GRAPHICS_BUFFER;

memcpy(REAL_FB, gfx_buffer, fbinfo->y_resolution * fbinfo->bytes_per_line);
return CBGFX_SUCCESS;
}

void disable_graphics_buffer(void)
{
free(gfx_buffer);
gfx_buffer = NULL;
}
23 changes: 23 additions & 0 deletions payloads/libpayload/include/cbgfx.h
View file
Expand Up @@ -56,6 +56,8 @@
#define CBGFX_ERROR_FRAMEBUFFER_ADDR 0x15
/* portrait screen not supported */
#define CBGFX_ERROR_PORTRAIT_SCREEN 0x16
/* cannot use buffered I/O */
#define CBGFX_ERROR_GRAPHICS_BUFFER 0x17

struct fraction {
int32_t n;
Expand Down Expand Up @@ -272,3 +274,24 @@ void clear_blend(void);
* 0 = min alpha argument, 0% opacity
*/
#define ALPHA(percentage) MIN(255, (256 * percentage / 100))

/**
* Enable buffered I/O. All CBGFX operations will be redirected to a working
* buffer, and only updated (redrawn) when flush_graphics_buffer() is called.
*
* @return CBGFX_* error codes
*/
int enable_graphics_buffer(void);

/**
* Redraw buffered graphics data to real screen if graphics buffer is already
* enabled.
*
* @return CBGFX_* error codes
*/
int flush_graphics_buffer(void);

/**
* Stop using buffered I/O and release allocated memory.
*/
void disable_graphics_buffer(void);
1 change: 0 additions & 1 deletion payloads/libpayload/include/ctype.h
View file
Expand Up @@ -50,5 +50,4 @@ int tolower(int c);
int toupper(int c);
/** @} */


#endif
2 changes: 0 additions & 2 deletions payloads/libpayload/include/libpayload.h
View file
Expand Up @@ -456,7 +456,6 @@ static inline int log2(u32 x) { return (int)sizeof(x) * 8 - clz(x) - 1; }
static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); }
/** @} */


/**
* @defgroup mmio MMIO helper functions
* @{
Expand All @@ -475,7 +474,6 @@ static inline void buffer_to_fifo32(void *buffer, size_t size, void *fifo,
#endif
/** @} */


/**
* @defgroup hash Hashing functions
* @{
Expand Down
3 changes: 0 additions & 3 deletions payloads/libpayload/include/queue.h
View file
Expand Up @@ -344,7 +344,6 @@ struct { \
#define XSIMPLEQ_EMPTY(head) (XSIMPLEQ_FIRST(head) == XSIMPLEQ_END(head))
#define XSIMPLEQ_NEXT(head, elm, field) XSIMPLEQ_XOR(head, ((elm)->field.sqx_next))


#define XSIMPLEQ_FOREACH(var, head, field) \
for ((var) = XSIMPLEQ_FIRST(head); \
(var) != XSIMPLEQ_END(head); \
Expand Down Expand Up @@ -398,7 +397,6 @@ struct { \
XSIMPLEQ_XOR(head, &(elm)->field.sqx_next); \
} while (0)


/*
* Tail queue definitions.
*/
Expand Down Expand Up @@ -442,7 +440,6 @@ struct { \
((tvar) = TAILQ_NEXT(var, field), 1); \
(var) = (tvar))


#define TAILQ_FOREACH_REVERSE(var, head, headname, field) \
for((var) = TAILQ_LAST(head, headname); \
(var) != TAILQ_END(head); \
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/include/storage/ata.h
View file
Expand Up @@ -33,7 +33,6 @@

#include "storage.h"


/* ATA commands */
enum {
ATA_READ_DMA = 0xc8,
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/include/storage/atapi.h
View file
Expand Up @@ -34,7 +34,6 @@
#include "storage.h"
#include "ata.h"


/* ATAPI commands */
enum {
ATAPI_TEST_UNIT_READY = 0x00,
Expand Down
4 changes: 0 additions & 4 deletions payloads/libpayload/include/storage/storage.h
View file
Expand Up @@ -32,14 +32,12 @@
#include <stdint.h>
#include <unistd.h>


#if !CONFIG(LP_STORAGE_64BIT_LBA)
typedef u32 lba_t;
#else
typedef u64 lba_t;
#endif


typedef enum {
PORT_TYPE_IDE = (1 << 0),
PORT_TYPE_SATA = (1 << 1),
Expand All @@ -54,7 +52,6 @@ typedef enum {
POLL_MEDIUM_PRESENT = 1,
} storage_poll_t;


struct storage_dev;

typedef struct storage_dev {
Expand All @@ -70,7 +67,6 @@ typedef struct storage_dev {
int storage_device_count(void);
int storage_attach_device(storage_dev_t *dev);


storage_poll_t storage_probe(size_t dev_num);
ssize_t storage_read_blocks512(size_t dev_num, lba_t start, size_t count, unsigned char *buf);

Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/include/string.h
View file
Expand Up @@ -83,5 +83,4 @@ size_t strlcpy(char *d, const char *s, size_t n);
size_t strlcat(char *d, const char *s, size_t n);
/** @} */


#endif
95 changes: 61 additions & 34 deletions payloads/libpayload/libc/malloc.c
View file
Expand Up @@ -123,7 +123,8 @@ int dma_coherent(void *ptr)
return !dma_initialized() || (dma->start <= ptr && dma->end > ptr);
}

static void *alloc(int len, struct memory_type *type)
/* Find free block of size >= len */
static hdrtype_t volatile *find_free_block(int len, struct memory_type *type)
{
hdrtype_t header;
hdrtype_t volatile *ptr = (hdrtype_t volatile *)type->start;
Expand Down Expand Up @@ -156,37 +157,53 @@ static void *alloc(int len, struct memory_type *type)
halt();
}

if (header & FLAG_FREE) {
if (len <= size) {
hdrtype_t volatile *nptr = (hdrtype_t volatile *)((uintptr_t)ptr + HDRSIZE + len);
int nsize = size - (HDRSIZE + len);

/* If there is still room in this block,
* then mark it as such otherwise account
* the whole space for that block.
*/

if (nsize > 0) {
/* Mark the block as used. */
*ptr = USED_BLOCK(len);

/* Create a new free block. */
*nptr = FREE_BLOCK(nsize);
} else {
/* Mark the block as used. */
*ptr = USED_BLOCK(size);
}

return (void *)((uintptr_t)ptr + HDRSIZE);
}
}
if ((header & FLAG_FREE) && len <= size)
return ptr;

ptr = (hdrtype_t volatile *)((uintptr_t)ptr + HDRSIZE + size);

} while (ptr < (hdrtype_t *) type->end);

/* Nothing available. */
return (void *)NULL;
return NULL;
}

/* Mark the block with length 'len' as used */
static void use_block(hdrtype_t volatile *ptr, int len)
{
/* Align the size. */
len = ALIGN_UP(len, HDRSIZE);

hdrtype_t volatile *nptr = (hdrtype_t volatile *)
((uintptr_t)ptr + HDRSIZE + len);
int size = SIZE(*ptr);
int nsize = size - (HDRSIZE + len);

/*
* If there is still room in this block, then mark it as such otherwise
* account the whole space for that block.
*/
if (nsize > 0) {
/* Mark the block as used. */
*ptr = USED_BLOCK(len);

/* Create a new free block. */
*nptr = FREE_BLOCK(nsize);
} else {
/* Mark the block as used. */
*ptr = USED_BLOCK(size);
}
}

static void *alloc(int len, struct memory_type *type)
{
hdrtype_t volatile *ptr = find_free_block(len, type);

if (ptr == NULL)
return NULL;

use_block(ptr, len);
return (void *)((uintptr_t)ptr + HDRSIZE);
}

static void _consolidate(struct memory_type *type)
Expand Down Expand Up @@ -229,6 +246,10 @@ void free(void *ptr)
hdrtype_t hdr;
struct memory_type *type = heap;

/* No action occurs on NULL. */
if (ptr == NULL)
return;

/* Sanity check. */
if (ptr < type->start || ptr >= type->end) {
type = dma;
Expand Down Expand Up @@ -277,6 +298,7 @@ void *calloc(size_t nmemb, size_t size)
void *realloc(void *ptr, size_t size)
{
void *ret, *pptr;
hdrtype_t volatile *block;
unsigned int osize;
struct memory_type *type = heap;

Expand All @@ -300,18 +322,23 @@ void *realloc(void *ptr, size_t size)
* reallocated the new space.
*/
free(ptr);
ret = alloc(size, type);

block = find_free_block(size, type);
if (block == NULL)
return NULL;

ret = (void *)((uintptr_t)block + HDRSIZE);

/*
* if ret == NULL, then doh - failure.
* if ret == ptr then woo-hoo! no copy needed.
* If ret == ptr, then no copy is needed. Otherwise, move the memory to
* the new location, which might be before the old one and overlap since
* the free() above includes a _consolidate().
*/
if (ret == NULL || ret == ptr)
return ret;
if (ret != ptr)
memmove(ret, ptr, osize > size ? size : osize);

/* Move the memory to the new location. Might be before the old location
and overlap since the free() above includes a _consolidate(). */
memmove(ret, ptr, osize > size ? size : osize);
/* Mark the block as used. */
use_block(block, size);

return ret;
}
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/libc/memory.c
View file
Expand Up @@ -145,7 +145,6 @@ static int default_memcmp(const void *s1, const void *s2, size_t n)
int memcmp(const void *s1, const void *s2, size_t n)
__attribute__((weak, alias("default_memcmp")));


void *memchr(const void *s, int c, size_t n)
{
unsigned char *p = (unsigned char *)s;
Expand Down
1 change: 0 additions & 1 deletion payloads/libpayload/libc/string.c
View file
Expand Up @@ -521,7 +521,6 @@ unsigned long int strtoul(const char *ptr, char **endptr, int base)
return val;
}


/**
* Determine the number of leading characters in s that match characters in a
* @param s A pointer to the string to analyse
Expand Down
8 changes: 0 additions & 8 deletions payloads/libpayload/liblzma/lzmadecode.c
View file
Expand Up @@ -33,12 +33,10 @@
#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \
{ int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }}


#define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; }

#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2


#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; }

#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound)
Expand All @@ -56,7 +54,6 @@
do { CProb *cp = probs + res; RC_GET_BIT(cp, res) } while(--i != 0); \
res -= (1 << numLevels); }


#define kNumPosBitsMax 4
#define kNumPosStatesMax (1 << kNumPosBitsMax)

Expand All @@ -74,7 +71,6 @@
#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits))
#define kNumLenProbs (LenHigh + kLenNumHighSymbols)


#define kNumStates 12
#define kNumLitStates 7

Expand Down Expand Up @@ -143,7 +139,6 @@ int LzmaDecode(CLzmaDecoderState *vs,
UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1;
int lc = vs->Properties.lc;


int state = 0;
UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1;
int len = 0;
Expand All @@ -164,7 +159,6 @@ int LzmaDecode(CLzmaDecoderState *vs,

RC_INIT(inStream, inSize);


while(nowPos < outSize)
{
CProb *prob;
Expand Down Expand Up @@ -379,7 +373,6 @@ int LzmaDecode(CLzmaDecoderState *vs,
if (rep0 > nowPos)
return LZMA_RESULT_DATA_ERROR;


do
{
previousByte = outStream[nowPos - rep0];
Expand All @@ -391,7 +384,6 @@ int LzmaDecode(CLzmaDecoderState *vs,
}
RC_NORMALIZE;


*inSizeProcessed = (SizeT)(Buffer - inStream);
*outSizeProcessed = nowPos;
return LZMA_RESULT_OK;
Expand Down
3 changes: 0 additions & 3 deletions payloads/libpayload/liblzma/lzmadecode.h
View file
Expand Up @@ -32,7 +32,6 @@ typedef UInt32 SizeT;
#define LZMA_RESULT_OK 0
#define LZMA_RESULT_DATA_ERROR 1


#define LZMA_BASE_SIZE 1846
#define LZMA_LIT_SIZE 768

Expand All @@ -56,10 +55,8 @@ typedef struct _CLzmaDecoderState
CLzmaProperties Properties;
CProb *Probs;


} CLzmaDecoderState;


int LzmaDecode(CLzmaDecoderState *vs,
const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,
unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed);
Expand Down
1 change: 0 additions & 1 deletion src/Kconfig
View file
Expand Up @@ -1144,7 +1144,6 @@ config EM100

endmenu


###############################################################################
# Set variables with no prompt - these can be set anywhere, and putting at
# the end of this file gives the most flexibility.
Expand Down
65 changes: 61 additions & 4 deletions src/acpi/acpigen.c
View file
Expand Up @@ -832,6 +832,23 @@ void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat,
coreFreq, power, control, status);
}

void acpigen_write_pss_object(const struct acpi_sw_pstate *pstate_values, size_t nentries)
{
size_t pstate;

acpigen_write_name("_PSS");
acpigen_write_package(nentries);
for (pstate = 0; pstate < nentries; pstate++) {
acpigen_write_PSS_package(
pstate_values->core_freq, pstate_values->power,
pstate_values->transition_latency, pstate_values->bus_master_latency,
pstate_values->control_value, pstate_values->status_value);
pstate_values++;
}

acpigen_pop_len();
}

void acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype)
{
acpigen_write_name("_PSD");
Expand All @@ -850,8 +867,8 @@ void acpigen_write_CST_package_entry(acpi_cstate_t *cstate)
{
acpigen_write_package(4);
acpigen_write_register_resource(&cstate->resource);
acpigen_write_dword(cstate->ctype);
acpigen_write_dword(cstate->latency);
acpigen_write_byte(cstate->ctype);
acpigen_write_word(cstate->latency);
acpigen_write_dword(cstate->power);
acpigen_pop_len();
}
Expand All @@ -861,7 +878,7 @@ void acpigen_write_CST_package(acpi_cstate_t *cstate, int nentries)
int i;
acpigen_write_name("_CST");
acpigen_write_package(nentries+1);
acpigen_write_dword(nentries);
acpigen_write_integer(nentries);

for (i = 0; i < nentries; i++)
acpigen_write_CST_package_entry(cstate + i);
Expand All @@ -875,7 +892,7 @@ void acpigen_write_CSD_package(u32 domain, u32 numprocs, CSD_coord coordtype,
acpigen_write_name("_CSD");
acpigen_write_package(1);
acpigen_write_package(6);
acpigen_write_byte(6); // 6 values
acpigen_write_integer(6); // 6 values
acpigen_write_byte(0); // revision 0
acpigen_write_dword(domain);
acpigen_write_dword(coordtype);
Expand Down Expand Up @@ -2002,3 +2019,43 @@ void acpigen_write_create_qword_field(uint8_t op, size_t byte_offset, const char
{
_create_field(CREATE_QWORD_OP, op, byte_offset, name);
}

void acpigen_write_pct_package(const acpi_addr_t *perf_ctrl, const acpi_addr_t *perf_sts)
{
acpigen_write_name("_PCT");
acpigen_write_package(0x02);
acpigen_write_register_resource(perf_ctrl);
acpigen_write_register_resource(perf_sts);

acpigen_pop_len();
}

void acpigen_write_xpss_package(const struct acpi_xpss_sw_pstate *pstate_value)
{
acpigen_write_package(0x08);
acpigen_write_dword(pstate_value->core_freq);
acpigen_write_dword(pstate_value->power);
acpigen_write_dword(pstate_value->transition_latency);
acpigen_write_dword(pstate_value->bus_master_latency);

acpigen_write_byte_buffer((uint8_t *)&pstate_value->control_value, sizeof(uint64_t));
acpigen_write_byte_buffer((uint8_t *)&pstate_value->status_value, sizeof(uint64_t));
acpigen_write_byte_buffer((uint8_t *)&pstate_value->control_mask, sizeof(uint64_t));
acpigen_write_byte_buffer((uint8_t *)&pstate_value->status_mask, sizeof(uint64_t));

acpigen_pop_len();
}

void acpigen_write_xpss_object(const struct acpi_xpss_sw_pstate *pstate_values, size_t nentries)
{
size_t pstate;

acpigen_write_name("XPSS");
acpigen_write_package(nentries);
for (pstate = 0; pstate < nentries; pstate++) {
acpigen_write_xpss_package(pstate_values);
pstate_values++;
}

acpigen_pop_len();
}
1 change: 1 addition & 0 deletions src/arch/arm/Makefile.inc
View file
Expand Up @@ -119,6 +119,7 @@ ramstage-y += memset.S
ramstage-y += memcpy.S
ramstage-y += memmove.S
ramstage-y += clock.c
ramstage-y += boot_linux.S
ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c

rmodules_arm-y += memset.S
Expand Down
3 changes: 0 additions & 3 deletions src/arch/arm/armv7/mmu.c
View file
Expand Up @@ -87,9 +87,6 @@ typedef uint32_t pte_t;

static pte_t *const ttb_buff = (void *)_ttb;

/* Not all boards want to use subtables and declare them in memlayout.ld. */
DECLARE_OPTIONAL_REGION(ttb_subtables);

static struct {
pte_t value;
const char *name;
Expand Down
22 changes: 20 additions & 2 deletions src/arch/arm/boot.c
View file
@@ -1,14 +1,32 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <cbfs.h>
#include <arch/cache.h>
#include <program_loading.h>

void boot_linux(void *kernel_ptr, void *fdt_ptr);

void arch_prog_run(struct prog *prog)
{
void (*doit)(void *);

cache_sync_instructions();

doit = prog_entry(prog);
doit(prog_entry_arg(prog));
switch (prog_cbfs_type(prog)) {
case CBFS_TYPE_FIT:
/*
* We only load Linux payloads from the ramstage, so provide a hint to
* the linker that the below functions do not need to be included in
* earlier stages.
*/
if (!ENV_RAMSTAGE)
break;

dcache_mmu_disable();
boot_linux(prog_entry(prog), prog_entry_arg(prog));
break;
default:
doit = prog_entry(prog);
doit(prog_entry_arg(prog));
}
}
21 changes: 21 additions & 0 deletions src/arch/arm/boot_linux.S
View file
@@ -0,0 +1,21 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <arch/asm.h>

/* Required to jump to kernel in ARM state */
.arm
/* void boot_linux(void *kernel_ptr, void *fdt_ptr); */
ENTRY(boot_linux)
/* Save kernel ptr */
mov r3, r0
/* Set R2 = fdt */
mov r2, r1
/* Set R0 = 0x00000000 as expected by Linux ABI */
mov r0, #0
/* Set R1 = 0xffffffff as expected by Linux ABI */
mov r1, #-1
/* Linux ABI expects SVC mode (0x13) with IRQ(7) and FIQ(6) disabled. */
msr cpsr_cxf, #0xd3
/* Jump to kernel */
mov pc, r3
ENDPROC(boot_linux)
2 changes: 0 additions & 2 deletions src/arch/arm/tables.c
View file
Expand Up @@ -11,8 +11,6 @@ void arch_write_tables(uintptr_t coreboot_table)

void bootmem_arch_add_ranges(void)
{
DECLARE_OPTIONAL_REGION(ttb_subtables);

bootmem_add_range((uintptr_t)_ttb, REGION_SIZE(ttb), BM_MEM_RAMSTAGE);
bootmem_add_range((uintptr_t)_ttb_subtables, REGION_SIZE(ttb_subtables),
BM_MEM_RAMSTAGE);
Expand Down
2 changes: 0 additions & 2 deletions src/arch/arm64/tables.c
View file
Expand Up @@ -5,8 +5,6 @@
#include <boot/coreboot_tables.h>
#include <symbols.h>

DECLARE_OPTIONAL_REGION(bl31);

void arch_write_tables(uintptr_t coreboot_table)
{
}
Expand Down
2 changes: 0 additions & 2 deletions src/arch/riscv/tables.c
View file
Expand Up @@ -5,8 +5,6 @@
#include <boot/coreboot_tables.h>
#include <symbols.h>

DECLARE_OPTIONAL_REGION(opensbi);

void arch_write_tables(uintptr_t coreboot_table)
{
}
Expand Down
2 changes: 1 addition & 1 deletion src/arch/x86/exit_car.S
View file
Expand Up @@ -59,7 +59,7 @@ _start:
movl $1, %eax
cpuid
btl $CPUID_FEATURE_CLFLUSH_BIT, %edx
jz skip_clflush
jnc skip_clflush
clflush _cbmem_top_ptr

skip_clflush:
Expand Down
10 changes: 8 additions & 2 deletions src/arch/x86/smbios.c
View file
Expand Up @@ -281,8 +281,14 @@ static int create_smbios_type17_for_dimm(struct dimm_info *dimm,

memset(t, 0, sizeof(struct smbios_type17));
t->memory_type = dimm->ddr_type;
t->clock_speed = dimm->ddr_frequency;
t->speed = dimm->ddr_frequency;
if (dimm->configured_speed_mts != 0)
t->clock_speed = dimm->configured_speed_mts;
else
t->clock_speed = dimm->ddr_frequency;
if (dimm->max_speed_mts != 0)
t->speed = dimm->max_speed_mts;
else
t->speed = dimm->ddr_frequency;
t->type = SMBIOS_MEMORY_DEVICE;
if (dimm->dimm_size < 0x7fff) {
t->size = dimm->dimm_size;
Expand Down
1 change: 0 additions & 1 deletion src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h
View file
Expand Up @@ -144,7 +144,6 @@ struct cbfs_file_attr_align {
uint32_t alignment;
} __packed;


/*** Component sub-headers ***/

/* Following are component sub-headers for the "standard"
Expand Down
6 changes: 6 additions & 0 deletions src/commonlib/bsd/include/commonlib/bsd/sysincludes.h
View file
@@ -0,0 +1,6 @@
/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
#if defined(__FreeBSD__)
#include <sys/endian.h>
#else
#include <endian.h>
#endif
2 changes: 1 addition & 1 deletion src/commonlib/bsd/lz4_wrapper.c
View file
Expand Up @@ -2,7 +2,7 @@

#include <commonlib/bsd/compression.h>
#include <commonlib/bsd/helpers.h>
#include <endian.h>
#include <commonlib/bsd/sysincludes.h>
#include <stdint.h>
#include <string.h>

Expand Down
5 changes: 0 additions & 5 deletions src/commonlib/include/commonlib/coreboot_tables.h
View file
Expand Up @@ -140,7 +140,6 @@ struct lb_record {
uint32_t size; /* size of record (in bytes) */
};


struct lb_memory_range {
struct lb_uint64 start;
struct lb_uint64 size;
Expand Down Expand Up @@ -186,7 +185,6 @@ struct lb_timestamp {
uint32_t timestamp;
};


/* 0xe is taken by v3 */

struct lb_serial {
Expand Down Expand Up @@ -306,7 +304,6 @@ struct lb_framebuffer {
uint8_t orientation;
};


struct lb_gpio {
uint32_t port;
uint32_t polarity;
Expand Down Expand Up @@ -349,7 +346,6 @@ struct lb_x86_rom_mtrr {
uint32_t index;
};


struct lb_strapping_id {
uint32_t tag;
uint32_t size;
Expand Down Expand Up @@ -448,7 +444,6 @@ struct cmos_entries {
variable length int aligned */
};


/* CMOS enumerations record
* This record is variable length. The text field may be
* shorter than CMOS_MAX_TEXT_LENGTH.
Expand Down
2 changes: 1 addition & 1 deletion src/commonlib/include/commonlib/timestamp_serialized.h
View file
Expand Up @@ -185,7 +185,7 @@ static const struct timestamp_id_to_name {
{ TS_START_VERIFY_SLOT, "starting to verify keyblock/preamble (RSA)" },
{ TS_END_VERIFY_SLOT, "finished verifying keyblock/preamble (RSA)" },
{ TS_START_HASH_BODY, "starting to verify body (load+SHA2+RSA) " },
{ TS_DONE_LOADING, "finished loading body (ignore for x86)" },
{ TS_DONE_LOADING, "finished loading body" },
{ TS_DONE_HASHING, "finished calculating body hash (SHA2)" },
{ TS_END_HASH_BODY, "finished verifying body signature (RSA)" },
{ TS_START_TPMPCR, "starting TPM PCR extend" },
Expand Down
1 change: 0 additions & 1 deletion src/commonlib/region.c
View file
Expand Up @@ -420,7 +420,6 @@ const struct region_device_ops xlate_rdev_rw_ops = {
.eraseat = xlate_eraseat,
};


static void *incoherent_mmap(const struct region_device *rd, size_t offset,
size_t size)
{
Expand Down
1 change: 0 additions & 1 deletion src/commonlib/storage/sd.c
View file
Expand Up @@ -265,7 +265,6 @@ int sd_set_bus_width(struct storage_media *media)
return 0;
}


int sd_set_partition(struct storage_media *media,
unsigned int partition_number)
{
Expand Down
7 changes: 7 additions & 0 deletions src/console/Kconfig
View file
Expand Up @@ -302,6 +302,13 @@ config SPI_CONSOLE
This is currently working only in ramstage due to how the spi
drivers are written.

config CONSOLE_SYSTEM76_EC
bool "System76 EC console output"
default n
depends on EC_SYSTEM76_EC
help
Send coreboot debug output to a System76 embedded controller.

config CONSOLE_OVERRIDE_LOGLEVEL
bool
help
Expand Down
5 changes: 4 additions & 1 deletion src/console/console.c
View file
Expand Up @@ -9,6 +9,7 @@
#include <console/usb.h>
#include <console/spi.h>
#include <console/flash.h>
#include <console/system76_ec.h>

void console_hw_init(void)
{
Expand All @@ -21,6 +22,7 @@ void console_hw_init(void)
__usbdebug_init();
__spiconsole_init();
__flashconsole_init();
__system76_ec_init();
}

void console_tx_byte(unsigned char byte)
Expand All @@ -42,6 +44,7 @@ void console_tx_byte(unsigned char byte)
__usb_tx_byte(byte);
__spiconsole_tx_byte(byte);
__flashconsole_tx_byte(byte);
__system76_ec_tx_byte(byte);
}

void console_tx_flush(void)
Expand All @@ -50,6 +53,7 @@ void console_tx_flush(void)
__ne2k_tx_flush();
__usb_tx_flush();
__flashconsole_tx_flush();
__system76_ec_tx_flush();
}

void console_write_line(uint8_t *buffer, size_t number_of_bytes)
Expand All @@ -65,7 +69,6 @@ void console_write_line(uint8_t *buffer, size_t number_of_bytes)
console_tx_byte(*buffer++);
}


#if CONFIG(GDB_STUB) && (ENV_ROMSTAGE || ENV_RAMSTAGE)
void gdb_hw_init(void)
{
Expand Down
1 change: 0 additions & 1 deletion src/console/vtxprintf.c
View file
Expand Up @@ -99,7 +99,6 @@ static int number(void (*tx_byte)(unsigned char byte, void *data),
return count;
}


int vtxprintf(void (*tx_byte)(unsigned char byte, void *data),
const char *fmt, va_list args, void *data)
{
Expand Down
1 change: 0 additions & 1 deletion src/cpu/amd/pi/00660F01/model_15_init.c
View file
Expand Up @@ -97,7 +97,6 @@ static void model_15_init(struct device *dev)
msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);


/* Write protect SMM space with SMMLOCK. */
msr = rdmsr(HWCR_MSR);
msr.lo |= (1 << 0);
Expand Down
2 changes: 2 additions & 0 deletions src/cpu/intel/haswell/finalize.c
View file
Expand Up @@ -6,4 +6,6 @@

void intel_cpu_haswell_finalize_smm(void)
{
/* Lock memory configuration to protect SMM */
msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
}
2 changes: 0 additions & 2 deletions src/cpu/intel/haswell/smmrelocate.c
View file
Expand Up @@ -33,8 +33,6 @@
#define SMRR_SUPPORTED (1 << 11)
#define PRMRR_SUPPORTED (1 << 12)



static void update_save_state(int cpu, uintptr_t curr_smbase,
uintptr_t staggered_smbase,
struct smm_relocation_params *relo_params)
Expand Down
1 change: 0 additions & 1 deletion src/cpu/intel/hyperthreading/intel_sibling.c
View file
Expand Up @@ -52,7 +52,6 @@ void intel_sibling_init(struct device *cpu)
cpu_path.type = DEVICE_PATH_APIC;
cpu_path.apic.apic_id = cpu->path.apic.apic_id + i;


/* Allocate new CPU device structure iff sibling CPU
* was not in static device tree.
*/
Expand Down
11 changes: 9 additions & 2 deletions src/cpu/intel/model_1067x/model_1067x_init.c
View file
Expand Up @@ -166,6 +166,8 @@ static void configure_emttm_tables(void)
wrmsr(MSR_EMTTM_CR_TABLE(5), msr);
}

#define IA32_PECI_CTL 0x5a0

static void configure_misc(const int eist, const int tm2, const int emttm)
{
msr_t msr;
Expand Down Expand Up @@ -208,6 +210,13 @@ static void configure_misc(const int eist, const int tm2, const int emttm)
msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
wrmsr(IA32_MISC_ENABLE, msr);
}

/* Enable PECI
WARNING: due to Erratum AW67 described in Intel document #318733
the microcode must be updated before this MSR is written to. */
msr = rdmsr(IA32_PECI_CTL);
msr.lo |= 1;
wrmsr(IA32_PECI_CTL, msr);
}

#define PIC_SENS_CFG 0x1aa
Expand All @@ -233,7 +242,6 @@ static void model_1067x_init(struct device *cpu)
{
char processor_name[49];


/* Gather some information: */

const struct cpuid_result cpuid1 = cpuid(1);
Expand All @@ -256,7 +264,6 @@ static void model_1067x_init(struct device *cpu)
/* Test for TM2 only if EIST is available. */
const char tm2 = eist && (cpuid1.ecx & (1 << 8));


/* Turn on caching if we haven't already */
x86_enable_cache();

Expand Down
3 changes: 0 additions & 3 deletions src/cpu/intel/model_2065x/model_2065x_init.c
View file
Expand Up @@ -110,7 +110,6 @@ int cpu_config_tdp_levels(void)
return (platform_info.hi >> 1) & 3;
}


static void configure_thermal_target(void)
{
struct cpu_intel_model_2065x_config *conf;
Expand Down Expand Up @@ -158,7 +157,6 @@ static void enable_lapic_tpr(void)
wrmsr(MSR_PIC_MSG_CONTROL, msr);
}


static void set_max_ratio(void)
{
msr_t msr, perf_ctl;
Expand Down Expand Up @@ -282,7 +280,6 @@ static void post_mp_init(void)
smm_lock();
}


static const struct mp_ops mp_ops = {
.pre_mp_init = pre_mp_init,
.get_cpu_count = get_cpu_count,
Expand Down
1 change: 0 additions & 1 deletion src/cpu/intel/model_206ax/model_206ax_init.c
View file
Expand Up @@ -534,7 +534,6 @@ static void post_mp_init(void)
smm_lock();
}


static const struct mp_ops mp_ops = {
.pre_mp_init = pre_mp_init,
.get_cpu_count = get_cpu_count,
Expand Down
1 change: 0 additions & 1 deletion src/cpu/intel/slot_1/l2_cache.c
View file
Expand Up @@ -189,7 +189,6 @@ int calculate_l2_latency(void)
return 0;
}


/* Setup address, data_high:data_low into the L2
* control registers and then issue command with correct cache way
*/
Expand Down
1 change: 0 additions & 1 deletion src/cpu/intel/smm/gen1/smmrelocate.c
View file
Expand Up @@ -25,7 +25,6 @@
#define G_SMRAME (1 << 3)
#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))


/* On model_6fx, model_1067x and model_106cx SMRR functions slightly
differently. The MSR are at different location from the rest
and need to be explicitly enabled in IA32_FEATURE_CONTROL MSR. */
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/intel/speedstep/speedstep.c
View file
Expand Up @@ -104,7 +104,6 @@ void speedstep_gen_pstates(sst_table_t *const table)
/* Gather speedstep limits. */
speedstep_get_limits(&params);


/*\ First, find the number of normal states: \*/

/* Calculate with doubled values to work
Expand All @@ -130,7 +129,6 @@ void speedstep_gen_pstates(sst_table_t *const table)
if (states < 2) /* Report at least two normal states. */
states = 2;


/*\ Now, fill the table: \*/

table->num_states = 0;
Expand Down
29 changes: 13 additions & 16 deletions src/cpu/x86/lapic/lapic.c
View file
Expand Up @@ -2,16 +2,15 @@

#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <smp/node.h>

void do_lapic_init(void)
{
/* this is so interrupts work. This is very limited scope --
* linux will do better later, we hope ...
*/
/* this is the first way we learned to do it. It fails on real SMP
* stuff. So we have to do things differently ...
* see the Intel mp1.4 spec, page A-3
*/
const uint32_t lvt0_mask = LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
LAPIC_DELIVERY_MODE_MASK;
uint32_t lvt0_val = LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING;

printk(BIOS_INFO, "Setting up local APIC...\n");

Expand All @@ -28,15 +27,13 @@ void do_lapic_init(void)
lapic_write_around(LAPIC_SPIV,
(lapic_read_around(LAPIC_SPIV) & ~(LAPIC_VECTOR_MASK))
| LAPIC_SPIV_ENABLE);
lapic_write_around(LAPIC_LVT0,
(lapic_read_around(LAPIC_LVT0) &
~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
LAPIC_DELIVERY_MODE_MASK))
| (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
LAPIC_DELIVERY_MODE_EXTINT)
);

if (boot_cpu())
lvt0_val |= LAPIC_DELIVERY_MODE_EXTINT;
else
lvt0_val |= LAPIC_DELIVERY_MODE_FIXED | LAPIC_LVT_MASKED;
lapic_write_around(LAPIC_LVT0, (lapic_read_around(LAPIC_LVT0) & ~lvt0_mask) | lvt0_val);

lapic_write_around(LAPIC_LVT1,
(lapic_read_around(LAPIC_LVT1) &
~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
Expand Down
1 change: 0 additions & 1 deletion src/cpu/x86/mp_init.c
View file
Expand Up @@ -106,7 +106,6 @@ struct saved_msr {
uint32_t hi;
} __packed;


/* The sipi vector rmodule is included in the ramstage using 'objdump -B'. */
extern char _binary_sipi_vector_start[];

Expand Down
8 changes: 8 additions & 0 deletions src/cpu/x86/smm/smihandler.c
View file
Expand Up @@ -120,6 +120,14 @@ static inline void *smm_save_state(uintptr_t base, int arch_offset, int node)
return (void *)base;
}

/* This returns the SMM revision from the savestate of CPU0,
which is assumed to be the same for all CPU's. See the memory
map in smmhandler.S */
uint32_t smm_revision(void)
{
return *(uint32_t *)(SMM_BASE + SMM_ENTRY_OFFSET * 2 - SMM_REVISION_OFFSET_FROM_TOP);
}

bool smm_region_overlaps_handler(const struct region *r)
{
const struct region r_smm = {SMM_BASE, SMM_DEFAULT_SIZE};
Expand Down
9 changes: 7 additions & 2 deletions src/cpu/x86/smm/smm_module_handler.c
View file
Expand Up @@ -69,7 +69,6 @@ static void smi_set_eos(void)
southbridge_smi_set_eos();
}


static u32 pci_orig;

/**
Expand All @@ -88,7 +87,6 @@ static void smi_restore_pci_address(void)
outl(pci_orig, 0xcf8);
}


static const struct smm_runtime *smm_runtime;

struct global_nvs *gnvs;
Expand All @@ -106,6 +104,13 @@ void *smm_get_save_state(int cpu)
return base;
}

uint32_t smm_revision(void)
{
const uintptr_t save_state = (uintptr_t)(smm_get_save_state(0));

return *(uint32_t *)(save_state + smm_runtime->save_state_size - SMM_REVISION_OFFSET_FROM_TOP);
}

bool smm_region_overlaps_handler(const struct region *r)
{
const struct region r_smm = {smm_runtime->smbase, smm_runtime->smm_size};
Expand Down
1 change: 0 additions & 1 deletion src/cpu/x86/smm/smm_module_loaderv2.c
View file
Expand Up @@ -590,7 +590,6 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params)
fxsave_area = NULL;
}


handler_size = rmodule_memory_size(&smm_mod);
base -= handler_size;
total_size += handler_size;
Expand Down
4 changes: 2 additions & 2 deletions src/cpu/x86/smm/smmhandler.S
View file
Expand Up @@ -46,9 +46,9 @@
#if defined(__x86_64__)
.bss
ia32efer_backup_eax:
.long
.long 0
ia32efer_backup_edx:
.long
.long 0
#endif

/* initially SMM is some sort of real mode. Let gcc know
Expand Down
19 changes: 19 additions & 0 deletions src/device/Kconfig
View file
Expand Up @@ -519,6 +519,19 @@ config PCIEXP_PLUGIN_SUPPORT
bool
default y

config PCI_ALLOW_BUS_MASTER
bool "Allow PCI bus master bit to be enabled by coreboot"
default y
help
For security reasons, bus mastering should be enabled as late as
possible. In coreboot, it's usually not necessary and payloads
should only enable it for devices they use. Since not all payloads
enable bus mastering properly yet, this option gives some sort of
"backwards compatibility" and is enabled by default to keep the
traditional behaviour for now. This is currently necessary, for
instance, for libpayload based payloads as the drivers don't enable
bus mastering for PCI bridges.

endif # PCI

if PCIEXP_PLUGIN_SUPPORT
Expand Down Expand Up @@ -650,6 +663,9 @@ config SUBSYSTEM_VENDOR_ID
This config option will override the devicetree settings for
PCI Subsystem Vendor ID.

Note: This option is not meant for a board's Kconfig; use the
devicetree setting `subsystemid` instead.

config SUBSYSTEM_DEVICE_ID
hex "Override PCI Subsystem Device ID"
depends on PCI
Expand All @@ -658,6 +674,9 @@ config SUBSYSTEM_DEVICE_ID
This config option will override the devicetree settings for
PCI Subsystem Device ID.

Note: This option is not meant for a board's Kconfig; use the
devicetree setting `subsystemid` instead.

config VGA_BIOS
bool "Add a VGA BIOS image"
depends on ARCH_X86
Expand Down
1 change: 0 additions & 1 deletion src/device/dram/ddr3.c
View file
Expand Up @@ -493,7 +493,6 @@ int spd_xmp_decode_ddr3(dimm_attr *dimm,
return ret;
}


/**
* Fill cbmem with information for SMBIOS type 17.
*
Expand Down
78 changes: 78 additions & 0 deletions src/device/dram/ddr4.c
View file
Expand Up @@ -9,6 +9,69 @@
#include <smbios.h>
#include <types.h>

enum ddr4_speed_grade {
DDR4_1600,
DDR4_1866,
DDR4_2133,
DDR4_2400,
DDR4_2666,
DDR4_2933,
DDR4_3200
};

struct ddr4_speed_attr {
uint32_t min_clock_mhz; // inclusive
uint32_t max_clock_mhz; // inclusive
uint32_t reported_mts;
};

/**
* DDR4 speed attributes derived from JEDEC 79-4C tables 169 & 170
*
* min_clock_mhz = 1000/max_tCk_avg(ns) + 1
* Adding 1 to make minimum inclusive
* max_clock_mhz = 1000/min_tCk_avg(ns)
* reported_mts = Standard reported DDR4 speed in MT/s
* May be 1 less than the actual max MT/s
*/
static const struct ddr4_speed_attr ddr4_speeds[] = {
[DDR4_1600] = {
.min_clock_mhz = 668,
.max_clock_mhz = 800,
.reported_mts = 1600
},
[DDR4_1866] = {
.min_clock_mhz = 801,
.max_clock_mhz = 934,
.reported_mts = 1866
},
[DDR4_2133] = {
.min_clock_mhz = 935,
.max_clock_mhz = 1067,
.reported_mts = 2133
},
[DDR4_2400] = {
.min_clock_mhz = 1068,
.max_clock_mhz = 1200,
.reported_mts = 2400
},
[DDR4_2666] = {
.min_clock_mhz = 1201,
.max_clock_mhz = 1333,
.reported_mts = 2666
},
[DDR4_2933] = {
.min_clock_mhz = 1334,
.max_clock_mhz = 1466,
.reported_mts = 2933
},
[DDR4_3200] = {
.min_clock_mhz = 1467,
.max_clock_mhz = 1600,
.reported_mts = 3200
}
};

typedef enum {
BLOCK_0, /* Base Configuration and DRAM Parameters */
BLOCK_1,
Expand Down Expand Up @@ -68,6 +131,21 @@ static bool block_exists(spd_block_type type, u8 dimm_type)
}
}

/**
* Converts DDR4 clock speed in MHz to the standard reported speed in MT/s
*/
uint16_t ddr4_speed_mhz_to_reported_mts(uint16_t speed_mhz)
{
for (enum ddr4_speed_grade speed = 0; speed < ARRAY_SIZE(ddr4_speeds); speed++) {
const struct ddr4_speed_attr *speed_attr = &ddr4_speeds[speed];
if (speed_mhz >= speed_attr->min_clock_mhz &&
speed_mhz <= speed_attr->max_clock_mhz) {
return speed_attr->reported_mts;
}
}
printk(BIOS_ERR, "ERROR: DDR4 speed of %d MHz is out of range", speed_mhz);
return 0;
}

/**
* \brief Decode the raw SPD data
Expand Down
1 change: 0 additions & 1 deletion src/device/hypertransport.c
View file
Expand Up @@ -308,7 +308,6 @@ static unsigned int do_hypertransport_scan_chain(struct bus *bus, unsigned int m
}
} while ((ctrl & (1 << 5)) == 0);


/* Get and setup the device_structure. */
dev = ht_scan_get_devs(&old_devices);

Expand Down
1 change: 0 additions & 1 deletion src/device/oprom/x86emu/decode.c
View file
Expand Up @@ -1122,7 +1122,6 @@ unsigned int decode_rm10_address(
return 0; /* SHOULD NOT HAPPEN */
}


/****************************************************************************
PARAMETERS:
mod - modifier
Expand Down
1 change: 0 additions & 1 deletion src/device/oprom/x86emu/prim_ops.c
View file
Expand Up @@ -129,7 +129,6 @@ static u32 x86emu_parity_tab[8] =

/*----------------------------- Implementation ----------------------------*/


/*--------- Side effects helper functions -------*/

/****************************************************************************
Expand Down
2 changes: 0 additions & 2 deletions src/device/oprom/x86emu/sys.c
View file
Expand Up @@ -199,8 +199,6 @@ void X86API wrl(u32 addr, u32 val)

DB(if (DEBUG_MEM_TRACE())
printf("%#08x 4 <- %#x\n", addr, val);)


}

/****************************************************************************
Expand Down
3 changes: 0 additions & 3 deletions src/device/oprom/yabel/compat/of.h
View file
Expand Up @@ -31,7 +31,6 @@
* IBM Corporation - initial implementation
*****************************************************************************/


#ifndef OF_H
#define OF_H
#define p32 int
Expand All @@ -48,15 +47,13 @@ typedef struct
unsigned int args[16];
} of_arg_t;


phandle_t of_finddevice (const char *);
phandle_t of_peer(phandle_t);
phandle_t of_child(phandle_t);
phandle_t of_parent(phandle_t);
int of_getprop(phandle_t, const char *, void *, int);
void *of_call_method_3(const char *, ihandle_t, int);


ihandle_t of_open(const char *);
void of_close(ihandle_t);
int of_read(ihandle_t, void *, int);
Expand Down
1 change: 0 additions & 1 deletion src/device/oprom/yabel/compat/rtas.h
View file
Expand Up @@ -31,7 +31,6 @@
* IBM Corporation - initial implementation
*****************************************************************************/


#ifndef RTAS_H
#define RTAS_H

Expand Down
2 changes: 0 additions & 2 deletions src/device/oprom/yabel/device.c
View file
Expand Up @@ -32,7 +32,6 @@
* IBM Corporation - initial implementation
*****************************************************************************/


#include "device.h"
#include "compat/rtas.h"
#include <string.h>
Expand Down Expand Up @@ -150,7 +149,6 @@ biosemu_dev_get_addr_info(void)
void translate_address_dev(u64 *, phandle_t);
u64 get_puid(phandle_t node);


// scan all addresses assigned to the device ("assigned-addresses" and "reg")
// store in translate_address_array for faster translation using dev_translate_address
void
Expand Down
1 change: 0 additions & 1 deletion src/device/oprom/yabel/device.h
View file
Expand Up @@ -40,7 +40,6 @@
#include "compat/of.h"
#include "debug.h"


// a Expansion Header Struct as defined in Plug and Play BIOS Spec 1.0a Chapter 3.2
typedef struct {
char signature[4]; // signature
Expand Down
1 change: 0 additions & 1 deletion src/device/oprom/yabel/interrupt.c
View file
Expand Up @@ -48,7 +48,6 @@
#include <device/pci.h>
#include <device/pci_ops.h>


//setup to run the code at the address, that the Interrupt Vector points to...
static void
setupInt(int intNum)
Expand Down
1 change: 0 additions & 1 deletion src/device/pci_device.c
View file
Expand Up @@ -25,7 +25,6 @@
#include <timestamp.h>
#include <types.h>


u8 pci_moving_config8(struct device *dev, unsigned int reg)
{
u8 value, ones, zeroes;
Expand Down
6 changes: 3 additions & 3 deletions src/device/pnp_device.c
View file
Expand Up @@ -56,7 +56,7 @@ void pnp_set_enable(struct device *dev, int enable)
{
u8 tmp, bitpos;

tmp = pnp_read_config(dev, 0x30);
tmp = pnp_read_config(dev, PNP_IDX_EN);

/* Handle virtual devices, which share the same LDN register. */
bitpos = (dev->path.pnp.device >> 8) & 0x7;
Expand All @@ -66,14 +66,14 @@ void pnp_set_enable(struct device *dev, int enable)
else
tmp &= ~(1 << bitpos);

pnp_write_config(dev, 0x30, tmp);
pnp_write_config(dev, PNP_IDX_EN, tmp);
}

int pnp_read_enable(struct device *dev)
{
u8 tmp, bitpos;

tmp = pnp_read_config(dev, 0x30);
tmp = pnp_read_config(dev, PNP_IDX_EN);

/* Handle virtual devices, which share the same LDN register. */
bitpos = (dev->path.pnp.device >> 8) & 0x7;
Expand Down
1 change: 0 additions & 1 deletion src/drivers/amd/agesa/heapmanager.c
View file
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */


#include <AGESA.h>
#include <amdlib.h>

Expand Down
1 change: 0 additions & 1 deletion src/drivers/analogix/anx7625/anx7625.c
View file
Expand Up @@ -737,7 +737,6 @@ static int anx7625_power_on_init(uint8_t bus)
}
ANXINFO("Init interface.\n");


anx7625_disable_pd_protocol(bus);
anx7625_reg_read(bus, RX_P0_ADDR, OCM_FW_VERSION, &version);
anx7625_reg_read(bus, RX_P0_ADDR, OCM_FW_REVERSION, &revision);
Expand Down
1 change: 0 additions & 1 deletion src/drivers/aspeed/common/ast_dp501.c
View file
Expand Up @@ -331,7 +331,6 @@ static bool ast_init_dvo(struct drm_device *dev)
return true;
}


static void ast_init_analog(struct drm_device *dev)
{
struct ast_private *ast = dev->dev_private;
Expand Down
6 changes: 5 additions & 1 deletion src/drivers/aspeed/common/ast_drv.h
View file
Expand Up @@ -11,7 +11,6 @@
#define PCI_CHIP_AST2100 0x2010
#define PCI_CHIP_AST1180 0x1180


enum ast_chip {
AST2000,
AST2100,
Expand Down Expand Up @@ -64,6 +63,11 @@ struct ast_private {

int next_cursor;
bool support_wide_screen;
enum {
ast_use_p2a,
ast_use_dt,
ast_use_defaults
} config_mode;

enum ast_tx_chip tx_chip_type;
u8 dp501_maxclk;
Expand Down
193 changes: 130 additions & 63 deletions src/drivers/aspeed/common/ast_main.c
View file
Expand Up @@ -37,17 +37,79 @@ uint8_t ast_get_index_reg_mask(struct ast_private *ast,
return ret;
}

static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev)
{
struct ast_private *ast = dev->dev_private;
uint32_t data, jregd0, jregd1;

/* Defaults */
ast->config_mode = ast_use_defaults;
*scu_rev = 0xffffffff;

/* Not all families have a P2A bridge */
if (dev->pdev->device != PCI_CHIP_AST2000)
return;

/*
* The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge
* is disabled. We force using P2A if VGA only mode bit
* is set D[7]
*/
jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) {
/* Double check it's actually working */
data = ast_read32(ast, 0xf004);
if (data != 0xFFFFFFFF) {
/* P2A works, grab silicon revision */
ast->config_mode = ast_use_p2a;

DRM_INFO("Using P2A bridge for configuration\n");

/* Read SCU7c (silicon revision register) */
ast_write32(ast, 0xf004, 0x1e6e0000);
ast_write32(ast, 0xf000, 0x1);
*scu_rev = ast_read32(ast, 0x1207c);
return;
}
}

/* We have a P2A bridge but it's disabled */
DRM_INFO("P2A bridge disabled, using default configuration\n");
}

static int ast_detect_chip(struct drm_device *dev, bool *need_post)
{
struct ast_private *ast = dev->dev_private;
uint32_t data, jreg;
uint32_t jreg, scu_rev;

/*
* If VGA isn't enabled, we need to enable now or subsequent
* access to the scratch registers will fail. We also inform
* our caller that it needs to POST the chip
* (Assumption: VGA not enabled -> need to POST)
*/
if (!ast_is_vga_enabled(dev)) {
ast_enable_vga(dev);
DRM_INFO("VGA not enabled on entry, requesting chip POST\n");
*need_post = true;
} else
*need_post = false;


/* Enable extended register access */
ast_enable_mmio(dev);
ast_open_key(ast);

/* Find out whether P2A works or whether to use device-tree */
ast_detect_config_mode(dev, &scu_rev);

/* Identify chipset */
if (dev->pdev->device == PCI_CHIP_AST1180) {
ast->chip = AST1100;
DRM_INFO("AST 1180 detected\n");
} else {
uint32_t data;
pci_read_config_dword(ast->dev->pdev, 0x08, &data);
uint8_t revision = data & 0xff;
if (revision >= 0x40) {
Expand All @@ -60,11 +122,7 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post)
ast->chip = AST2300;
DRM_INFO("AST 2300 detected\n");
} else if (revision >= 0x10) {
ast_write32(ast, 0xf004, 0x1e6e0000);
ast_write32(ast, 0xf000, 0x1);

data = ast_read32(ast, 0x1207c);
switch (data & 0x0300) {
switch (scu_rev & 0x0300) {
case 0x0200:
ast->chip = AST1100;
DRM_INFO("AST 1100 detected\n");
Expand All @@ -89,20 +147,6 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post)
}
}

/*
* If VGA isn't enabled, we need to enable now or subsequent
* access to the scratch registers will fail. We also inform
* our caller that it needs to POST the chip
* (Assumption: VGA not enabled -> need to POST)
*/
if (!ast_is_vga_enabled(dev)) {
ast_enable_vga(dev);
ast_enable_mmio(dev);
DRM_INFO("VGA not enabled on entry, requesting chip POST\n");
*need_post = true;
} else
*need_post = false;

/* Check if we support wide screen */
switch (ast->chip) {
case AST1180:
Expand All @@ -119,16 +163,14 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post)
ast->support_wide_screen = true;
else {
ast->support_wide_screen = false;
/* Read SCU7c (silicon revision register) */
ast_write32(ast, 0xf004, 0x1e6e0000);
ast_write32(ast, 0xf000, 0x1);
data = ast_read32(ast, 0x1207c);
data &= 0x300;
if (ast->chip == AST2300 && data == 0x0) /* ast1300 */
if (ast->chip == AST2300 &&
(scu_rev & 0x300) == 0x0) /* ast1300 */
ast->support_wide_screen = true;
if (ast->chip == AST2400 && data == 0x100) /* ast1400 */
if (ast->chip == AST2400 &&
(scu_rev & 0x300) == 0x100) /* ast1400 */
ast->support_wide_screen = true;
if (ast->chip == AST2500 && data == 0x100) /* ast2510 */
if (ast->chip == AST2500 &&
scu_rev == 0x100) /* ast2510 */
ast->support_wide_screen = true;
}
break;
Expand Down Expand Up @@ -194,34 +236,44 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post)
static int ast_get_dram_info(struct drm_device *dev)
{
struct ast_private *ast = dev->dev_private;
uint8_t i;
uint32_t data, data2;
uint32_t denum, num, div, ref_pll;

ast_write32(ast, 0xf004, 0x1e6e0000);
ast_write32(ast, 0xf000, 0x1);


ast_write32(ast, 0x10000, 0xfc600309);
uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap;
uint32_t denum, num, div, ref_pll, dsel;

/* Wait up to 2.5 seconds for device initialization / register unlock */
for (i = 0; i < 250; i++) {
if (ast_read32(ast, 0x10000) == 0x01)
break;
mdelay(10);
switch (ast->config_mode) {
case ast_use_dt:
/*
* If some properties are missing, use reasonable
* defaults for AST2400
*/
mcr_cfg = 0x00000577;
mcr_scu_mpll = 0x000050C0;
mcr_scu_strap = 0;
break;
case ast_use_p2a:
ast_write32(ast, 0xf004, 0x1e6e0000);
ast_write32(ast, 0xf000, 0x1);
mcr_cfg = ast_read32(ast, 0x10004);
mcr_scu_mpll = ast_read32(ast, 0x10120);
mcr_scu_strap = ast_read32(ast, 0x10170);
break;
case ast_use_defaults:
default:
ast->dram_bus_width = 16;
ast->dram_type = AST_DRAM_1Gx16;
if (ast->chip == AST2500)
ast->mclk = 800;
else
ast->mclk = 396;
return 0;
}
if (ast_read32(ast, 0x10000) != 0x01)
dev_err(dev->pdev, "Unable to unlock SDRAM control registers\n");

data = ast_read32(ast, 0x10004);

if (data & 0x40)
if (mcr_cfg & 0x40)
ast->dram_bus_width = 16;
else
ast->dram_bus_width = 32;

if (ast->chip == AST2500) {
switch (data & 0x03) {
switch (mcr_cfg & 0x03) {
case 0:
ast->dram_type = AST_DRAM_1Gx16;
break;
Expand All @@ -237,7 +289,7 @@ static int ast_get_dram_info(struct drm_device *dev)
break;
}
} else if (ast->chip == AST2300 || ast->chip == AST2400) {
switch (data & 0x03) {
switch (mcr_cfg & 0x03) {
case 0:
ast->dram_type = AST_DRAM_512Mx16;
break;
Expand All @@ -253,13 +305,13 @@ static int ast_get_dram_info(struct drm_device *dev)
break;
}
} else {
switch (data & 0x0c) {
switch (mcr_cfg & 0x0c) {
case 0:
case 4:
ast->dram_type = AST_DRAM_512Mx16;
break;
case 8:
if (data & 0x40)
if (mcr_cfg & 0x40)
ast->dram_type = AST_DRAM_1Gx16;
else
ast->dram_type = AST_DRAM_512Mx32;
Expand All @@ -270,17 +322,15 @@ static int ast_get_dram_info(struct drm_device *dev)
}
}

data = ast_read32(ast, 0x10120);
data2 = ast_read32(ast, 0x10170);
if (data2 & 0x2000)
if (mcr_scu_strap & 0x2000)
ref_pll = 14318;
else
ref_pll = 12000;

denum = data & 0x1f;
num = (data & 0x3fe0) >> 5;
data = (data & 0xc000) >> 14;
switch (data) {
denum = mcr_scu_mpll & 0x1f;
num = (mcr_scu_mpll & 0x3fe0) >> 5;
dsel = (mcr_scu_mpll & 0xc000) >> 14;
switch (dsel) {
case 3:
div = 0x4;
break;
Expand Down Expand Up @@ -312,6 +362,19 @@ static u32 ast_get_vram_info(struct drm_device *dev)
case 3: vram_size = AST_VIDMEM_SIZE_64M; break;
}

jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xff);
switch (jreg & 0x03) {
case 1:
vram_size -= 0x100000;
break;
case 2:
vram_size -= 0x200000;
break;
case 3:
vram_size -= 0x400000;
break;
}

return vram_size;
}

Expand Down Expand Up @@ -375,15 +438,19 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags)

ast_detect_chip(dev, &need_post);

if (need_post)
ast_post_gpu(dev);

if (ast->chip != AST1180) {
ast_get_dram_info(dev);
ret = ast_get_dram_info(dev);
if (ret)
goto out_free;
ast->vram_size = ast_get_vram_info(dev);
DRM_INFO("dram %d %d %d %08x\n", ast->mclk, ast->dram_type, ast->dram_bus_width, ast->vram_size);
DRM_INFO("dram MCLK=%u Mhz type=%d bus_width=%d size=%08x\n",
ast->mclk, ast->dram_type,
ast->dram_bus_width, ast->vram_size);
}

if (need_post)
ast_post_gpu(dev);

return 0;
out_free:
kfree(ast);
Expand Down
1 change: 0 additions & 1 deletion src/drivers/aspeed/common/ast_mode.c
View file
Expand Up @@ -6,7 +6,6 @@
#include "ast_drv.h"
#include "ast_tables.h"


static inline void ast_load_palette_index(struct ast_private *ast,
u8 index, u8 red, u8 green,
u8 blue)
Expand Down