diff --git a/src/cpu/amd/pi/00730F01/update_microcode.c b/src/cpu/amd/pi/00730F01/update_microcode.c
diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc
@@ -30,9 +30,6 @@ romstage-y += heapmanager.c
 ramstage-y += heapmanager.c
 ramstage-y += amd_late_init.c
 
-romstage-y += microcode_fam16h.c
-ramstage-y += microcode_fam16h.c
-
 ifeq ($(CONFIG_HAVE_ACPI_RESUME), y)
 
 $(obj)/coreboot_s3nv.rom: $(obj)/config.h

diff --git a/src/cpu/amd/pi/microcode_fam16h.c b/src/cpu/amd/pi/microcode_fam16h.c
diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c
@@ -20,10 +20,12 @@
 
 #include <rules.h>
 #include <stdlib.h>
+#include <arch/early_variables.h>
 #include <arch/io.h>
 #include <console/uart.h>
 #include <trace.h>
 #include "uart8250reg.h"
+#include "mainboard/pcengines/apu2/bios_knobs.h"
 
 #ifndef __ROMCC__
 #include <boot/coreboot_tables.h>
@@ -46,6 +48,8 @@
 #define SINGLE_CHAR_TIMEOUT	(50 * 1000)
 #define FIFO_TIMEOUT		(16 * SINGLE_CHAR_TIMEOUT)
 
+static int port_index CAR_GLOBAL;
+
 static int uart8250_can_tx_byte(unsigned base_port)
 {
 	return inb(base_port + UART8250_LSR) & UART8250_LSR_THRE;
@@ -117,30 +121,36 @@ void uart_init(int idx)
 	unsigned int div;
 	div = uart_baudrate_divisor(default_baudrate(), BAUDRATE_REFCLK,
 		BAUDRATE_OVERSAMPLE);
-	uart8250_init(uart_platform_base(idx), div);
+
+	if ((check_com2() || idx == 1) &&
+	    !IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5))
+		car_set_var(port_index, 1);
+	else
+		car_set_var(port_index, idx);
+	uart8250_init(uart_platform_base(car_get_var(port_index)), div);
 }
 
 void uart_tx_byte(int idx, unsigned char data)
 {
-	uart8250_tx_byte(uart_platform_base(idx), data);
+	uart8250_tx_byte(uart_platform_base(car_get_var(port_index)), data);
 }
 
 unsigned char uart_rx_byte(int idx)
 {
-	return uart8250_rx_byte(uart_platform_base(idx));
+	return uart8250_rx_byte(uart_platform_base(car_get_var(port_index)));
 }
 
 void uart_tx_flush(int idx)
 {
-	uart8250_tx_flush(uart_platform_base(idx));
+	uart8250_tx_flush(uart_platform_base(car_get_var(port_index)));
 }
 
 #if ENV_RAMSTAGE
 void uart_fill_lb(void *data)
 {
 	struct lb_serial serial;
 	serial.type = LB_SERIAL_TYPE_IO_MAPPED;
-	serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
+	serial.baseaddr = uart_platform_base(car_get_var(port_index));
 	serial.baud = default_baudrate();
 	lb_add_serial(&serial, data);
 

diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc
@@ -39,7 +39,7 @@ bootorder_def-type := raw
 
 # WIV20150126 add boot order
 cbfs-files-y += bootorder
-bootorder-file := src/mainboard/$(MAINBOARDDIR)/bootorder
+bootorder-file := src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/bootorder
 bootorder-type := raw
 bootorder-align := 0x1000
 

diff --git a/src/mainboard/pcengines/apu2/bios_knobs.c b/src/mainboard/pcengines/apu2/bios_knobs.c
@@ -104,6 +104,28 @@ bool check_console(void)
 }
 #endif //CONFIG_FORCE_CONSOLE
 
+int check_com2(void)
+{
+	u8 com2en;
+ 	//
+	// Find the COM2 redirection item
+	//
+	com2en = check_knob_value("com2en");
+ 	switch (com2en) {
+	case 0:
+		return 0;
+		break;
+	case 1:
+		return 1;
+		break;
+	default:
+		printk(BIOS_INFO,
+			"Missing or invalid com2 knob, disable COM2 output.\n");
+		break;
+	}
+ 	return 0;
+}
+
 static bool check_uart(char uart_letter)
 {
 	u8 uarten;

diff --git a/src/mainboard/pcengines/apu2/bios_knobs.h b/src/mainboard/pcengines/apu2/bios_knobs.h
@@ -26,13 +26,6 @@ bool check_uartc(void);
 bool check_uartd(void);
 bool check_ehci0(void);
 bool check_mpcie2_clk(void);
+int check_com2(void);
 
 #endif
-
-
-
-
-
-
-
-
diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c
@@ -202,21 +202,31 @@ const char *smbios_mainboard_serial_number(void)
 	static char serial[10];
 	msr_t msr;
 	u32 mac_addr = 0;
-	device_t nic_dev;
+	u32 bus_no;
+	device_t dev;
 
 	// Allows the IO configuration space access method, IOCF8 and IOCFC, to be
 	// used to generate extended configuration cycles
 	msr = rdmsr(NB_CFG_MSR);
 	msr.hi |= (ENABLE_CF8_EXT_CFG);
 	wrmsr(NB_CFG_MSR, msr);
 
-	nic_dev = dev_find_slot(1, PCI_DEVFN(0, 0));
+	// In case we have PCIe module connected to mPCIe2 slot, BDF 1:0.0 may
+	// not be a NIC, because mPCIe2 slot is routed to the very first PCIe
+	// bridge and the first NIC is connected to the second PCIe bridge.
+	// Read secondary bus number from the PCIe bridge where the first NIC is
+	// connected.
+	dev = dev_find_slot(0, PCI_DEVFN(2, 2));
+	if ((serial[0] != 0) || !dev)
+		return serial;
 
-	if ((serial[0] != 0) || !nic_dev)
-	return serial;
+	bus_no = dev->link_list->secondary;
+	dev = dev_find_slot(bus_no, PCI_DEVFN(0, 0));
+	if (!dev)
+		return serial;
 
 	// Read 4 bytes starting from 0x144 offset
-	mac_addr = pci_read_config32(nic_dev, 0x144);
+	mac_addr = pci_read_config32(dev, 0x144);
 	// MSB here is always 0xff
 	// Discard it so only bottom 3b of mac address are left
 	mac_addr &= 0x00ffffff;

diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
@@ -35,7 +35,6 @@
 #include <northbridge/amd/pi/agesawrapper_call.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/lapic.h>
-#include <cpu/amd/microcode.h>
 #include <hudson.h>
 #include <cpu/amd/pi/s3_resume.h>
 #include <fchgpio.h>
@@ -129,12 +128,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);
 
 		/* COM2 on apu5 is reserved so only COM1 should be supported */
-		if ((CONFIG_UART_FOR_CONSOLE == 1) &&
-			!IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5))
-			nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE);
-		else if (CONFIG_UART_FOR_CONSOLE == 0)
-			nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);
-
+		if ((check_com2() || (CONFIG_UART_FOR_CONSOLE == 1)) &&
+		    !IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5))
+			nuvoton_enable_serial(SERIAL2_DEV, 0x2f8);
 		console_init();
 
 		printk(BIOS_INFO, "14-25-48Mhz Clock settings\n");
@@ -204,8 +200,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
 	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
 
-	update_microcode(val);
-
 	/*
 	 * This refers to LpcClkDrvSth settling time.  Without this setting, processor
 	 * initialization is slow or incorrect, so this wait has been replicated from

diff --git a/src/mainboard/pcengines/apu2/variants/apu2/bootorder b/src/mainboard/pcengines/apu2/variants/apu2/bootorder
diff --git a/src/mainboard/pcengines/apu2/variants/apu3/bootorder b/src/mainboard/pcengines/apu2/variants/apu3/bootorder
diff --git a/src/mainboard/pcengines/apu2/variants/apu4/bootorder b/src/mainboard/pcengines/apu2/variants/apu4/bootorder
diff --git a/src/mainboard/pcengines/apu2/bootorder → ...rd/pcengines/apu2/variants/apu5/bootorder b/src/mainboard/pcengines/apu2/bootorder → ...rd/pcengines/apu2/variants/apu5/bootorder