diff --git a/Documentation/mainboard/asus/f2a85-m.md b/Documentation/mainboard/asus/f2a85-m.md
@@ -0,0 +1,198 @@
+# ASUS F2A85-M
+
+This page describes how to run coreboot on the [ASUS F2A85-M].
+
+## Variants
+- ASUS F2A85-M - Working
+- ASUS F2A85-M LE - Working
+- ASUS F2A85-M PRO - Working
+- ASUS F2A85-M2 - Working
+- ASUS F2A85-M/CSM - Unsure if WIP.
+
+## Technology
+
+Both "Trinity" and "Richland" desktop processing units are working,
+the CPU architecture in these CPUs/APUs is [Piledriver],
+and their GPU is [TeraScale 3] (VLIW4-based).
+
+```eval_rst
++------------------+--------------------------------------------------+
+| F2A85-M          |                                                  |
++------------------+--------------------------------------------------+
+| DDR voltage IC   | Nuvoton NCT3933U (AUX SMBUS 0x15)                |
++------------------+--------------------------------------------------+
+| Network          | Realtek RTL8111F                                 |
++------------------+--------------------------------------------------+
+| Northbridge      | Integrated into CPU with IMC and GPU (APUs only) |
++------------------+--------------------------------------------------+
+| Southbridge      | Hudson-D4                                        |
++------------------+--------------------------------------------------+
+| Sound IC         | Realtek ALC887                                   |
++------------------+--------------------------------------------------+
+| Super I/O        | ITE 8603E                                        |
++------------------+--------------------------------------------------+
+| VRM controller   | DIGI VRM ASP1106 (Rebranded RT8894A - SMBUS 0x20)|
++------------------+--------------------------------------------------+
+```
+
+```eval_rst
++------------------+--------------------------------------------------+
+| F2A85-M LE       |                                                  |
++------------------+--------------------------------------------------+
+| DDR voltage IC   | Nuvoton NCT3933U (AUX SMBUS 0x15 - unconfirmed)  |
++------------------+--------------------------------------------------+
+| Network          | Realtek RTL8111F                                 |
++------------------+--------------------------------------------------+
+| Northbridge      | Integrated into CPU with IMC and GPU(APUs only)  |
++------------------+--------------------------------------------------+
+| Southbridge      | Hudson-D4                                        |
++------------------+--------------------------------------------------+
+| Sound IC         | Realtek ALC887                                   |
++------------------+--------------------------------------------------+
+| Super I/O        | ITE 8623E                                        |
++------------------+--------------------------------------------------+
+| VRM controller   | DIGI VRM ASP1106 (Rebranded RT8894A - SMBUS 0x20)|
++------------------+--------------------------------------------------+
+```
+
+```eval_rst
++------------------+--------------------------------------------------+
+| F2A85-M PRO      |                                                  |
++------------------+--------------------------------------------------+
+| DDR voltage IC   | Nuvoton NCT3933U (?)                             |
++------------------+--------------------------------------------------+
+| Network          | Realtek RTL8111F - Not working                   |
++------------------+--------------------------------------------------+
+| Northbridge      | Integrated into CPU with IMC and GPU(APUs only)  |
++------------------+--------------------------------------------------+
+| Southbridge      | Hudson-D4                                        |
++------------------+--------------------------------------------------+
+| Sound IC         | Realtek ALC887                                   |
++------------------+--------------------------------------------------+
+| Super I/O        | Nuvoton NCT6779D                                 |
++------------------+--------------------------------------------------+
+| VRM controller   | DIGI VRM ASP1107                                 |
++------------------+--------------------------------------------------+
+```
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | yes        |
++---------------------+------------+
+| Model               | W25Q64F    |
++---------------------+------------+
+| Size                | 8 MiB      |
++---------------------+------------+
+| Package             | DIP-8      |
++---------------------+------------+
+| Write protection    | no         |
++---------------------+------------+
+| Dual BIOS feature   | no         |
++---------------------+------------+
+| Internal flashing   | yes        |
++---------------------+------------+
+```
+
+### Internal programming
+
+The main SPI flash can be accessed using [flashrom].
+UEFI builds that allow flash chip access:
+> v5016 is untested, but expected to work as well
+> v5018
+> v5103
+> v5104
+> v5107
+> v5202
+> v6002
+> v6004
+> v6102
+> v6402
+> v6404 (requires downgrading to v6402 to flash coreboot)
+> v6501 (requires downgrading to v6402 to flash coreboot)
+> v6502 (requires downgrading to v6402 to flash coreboot)
+
+Build v6502, v6501 and v6404 do not allow access to the flash chip.
+Fortunately it is possible to downgrade build v6502, v6501, v6404 to v6402, with EZFlash.
+Downgrading is done by downloading build v6402 from ASUS' F2A85-M download page
+and copying it to (the root directory of) a FAT32 formatted USB flash drive.
+Enter the EFI setup, switch to advanced mode if necessary,
+open the 'Tool' tab and select "ASUS EZ Flash 2 Utility".
+
+## Integrated graphics
+
+### Option 1: Retrieve the VGA optionrom from the vendor EFI binary by running:
+
+    # dd if=/dev/mem of=vgabios.bin bs=1k count=64 skip=768
+
+### Option 2: Extract from the vendor binary
+
+Download the BIOS from the Support section at [ASUS F2A85-M].
+Using MMTool Aptio (versions 4.5.0 and 5.0.0):
+- Load image, click on 'Extract tab'
+- Select the 'export path' and 'link present' options
+- Choose option ROM '1002,9900' and click on 'Extract'
+
+This version is usable for all the GPUs.
+> 1002,9901 Trinity (Radeon HD 7660D)
+> 1002,9904 Trinity (Radeon HD 7560D)
+> 1002,990c Richland (Radeon HD 8670D)
+> 1002,990e Richland (Radeon HD 8570D)
+> 1002,9991 Trinity (Radeon HD 7540D)
+> 1002,9993 Trinity (Radeon HD 7480D)
+> 1002,9996 Richland (Radeon HD 8470D)
+> 1002,9998 Richland (Radeon HD 8370D)
+> 1002,999d Richland (Radeon HD 8550D)
+
+## Known issues
+
+- buggy USB 3.0 controller (works fine as 2.0 port)
+- reboot, poweroff, S3 suspend/resume (broken since 4.8.1)
+
+## Known issues (untested because of non-working ACPI sleep)
+
+- blink in suspend mode (GP43, program LDN7 F8=23 and blink with F9=2 for 1s blinks)
+- fix immediate resume after suspend (perhaps PCIe STS needs to be cleared)
+- fix resume with USB3.0 used (perhaps there is a bug in resume.c)
+
+## Untested
+
+- audio over HDMI
+- IOMMU
+- PS/2 mouse
+
+## TODOs
+
+- manage to use one ATOMBIOS for all the integrated GPUs
+
+## Working
+
+- ACPI
+- CPU frequency scaling
+- flashrom under coreboot
+- Gigabit Ethernet
+- Hardware monitor
+- Integrated graphics
+- KVM
+- Onboard audio
+- PCIe
+- PS/2 keyboard
+- SATA
+- Serial port
+- SuperIO based fan control
+- USB (XHCI is buggy)
+
+## Extra resources
+
+- [Board manual]
+- Flash chip datasheet [W25Q64FV]
+
+[ASUS F2A85-M]: https://www.asus.com/Motherboards/F2A85M/
+[Board manual]: https://dlcdnets.asus.com/pub/ASUS/mb/SocketFM2/F2A85-M/E8005_F2A85-M.pdf
+[flashrom]: https://flashrom.org/Flashrom
+[Piledriver]: https://en.wikipedia.org/wiki/Piledriver_%28microarchitecture%29#APU_lines
+[TeraScale 3]: https://en.wikipedia.org/wiki/TeraScale_%28microarchitecture%29#TeraScale_3
+[W25Q64FV]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
@@ -4,11 +4,13 @@ This section contains documentation about coreboot on specific mainboards.
 
 ## ASUS
 
+- [F2A85-M](asus/f2a85-m.md)
 - [P8H61-M LX](asus/p8h61-m_lx.md)
 
 ## ASRock
 
 - [H81M-HDS](asrock/h81m-hds.md)
+- [H110M-DVS](asrock/h110m-dvs.md)
 
 ## Cavium
 

diff --git a/Documentation/security/index.md b/Documentation/security/index.md
@@ -0,0 +1,7 @@
+# Security
+
+This section describes documentation about the security architecture of coreboot.
+
+## Vendor
+
+- [Measured Boot](vboot/measured_boot.md)
diff --git a/Documentation/security/vboot/measured_boot.md b/Documentation/security/vboot/measured_boot.md
@@ -1,6 +1,8 @@
 # Measured Boot
 coreboot measured boot is implemented as Google Verified Boot extension. This
-means in order to use it, vboot needs to be available for your platform.
+means in order to use it, vboot needs to be available for your platform. The
+goal of this implementation is to implement an easy to understand and
+transparent measured boot mechanism.
 
 ## IBB/CRTM
 The "Initial Boot Block" or "Core Root of Trust for Measurement" is the first
@@ -21,10 +23,85 @@ measured boot extension because of platform constraints.
 The "Static Root of Trust for Measurement" is the easiest way doing measurements
 by measuring code before it is loaded.
 
+### Measurements
+SRTM mode measurements are done starting with the IBB as root of trust.
+Only CBFS contents are measured at the moment.
+
+#### CBFS files (stages, blobs)
+* CBFS data is measured as raw data before decompression happens.
+* CBFS header is excluded from measurements.
+* Measurements are stored in PCR 2.
+
+#### Runtime Data
+* CBFS data which changes by external input dynamically. Never stays the same.
+* It is identified by VBOOT_MEASURED_BOOT_RUNTIME_DATA kconfig option and
+  measured into a different PCR 3 in order to avoid PCR pre-calculation issues.
+
 ![][srtm]
 
 [srtm]: srtm.png
 
+### TCPA eventlog
+coreboot makes use of its own TCPA log implementation. Normally the eventlog
+specification can be found via the TCG homepage:
+
+[UEFI Specification](https://trustedcomputinggroup.org/resource/tcg-efi-platform-specification/)
+
+[BIOS Specification](https://www.trustedcomputinggroup.org/wp-content/uploads/TCG_PCClientImplementation_1-21_1_00.pdf)
+
+Both of them are not representing firmware measurements in a generalized way.
+Therefore we have to implement our own solution.
+
+We decided to provide an easy to understand TCPA log which can be read out
+from the operating system and firmware itself.
+
+#### Table Format
+The first column describes the PCR index used for measurement.
+The second column is the hash of the raw data. The third column contains
+the hash algorithm used in the operation. The last column provides
+information about what is measured. First the namespace from where the data
+came from, CBFS or FMAP, then the name used to look up the data
+(region or file name).
+
+#### Example:
+```bash
+PCR-2 e8f2b57c9ec5ea06d1bbd3240a753974d4c3e7c8cd305c20a8ea26eed906dc89 SHA256 [FMAP: COREBOOT CBFS: bootblock]
+PCR-2 309a5fcb231d3a39127de2521792f332f9a69e05675ec52535d2dcded756dc19 SHA256 [FMAP: COREBOOT CBFS: fallback/verstage]
+PCR-2 0fbba07a833d4dcfc7024eaf313661a0ba8f80a05c6d29b8801c612e10e60dee SHA256 [FMAP: RO_VPD]
+PCR-2 431681113ed44cbf6f68a12c6e5687e901052f1d728a4777b2ad36e559962047 SHA256 [FMAP: GBB]
+PCR-2 f47a8ec3e9aff2318d896942282ad4fe37d6391c82914f54a5da8a37de1300c6 SHA256 [FMAP: SI_DESC]
+PCR-3 237f6f567f8597dbdff0a00690d34d21616af0dbe434b9a2d432b136c012765f SHA256 [FMAP: SI_ME]
+PCR-2 7d2c7ac4888bfd75cd5f56e8d61f69595121183afc81556c876732fd3782c62f SHA256 [FMAP: SI_GBE]
+PCR-0 62571891215b4efc1ceab744ce59dd0b66ea6f73 SHA1 [GBB flags]
+PCR-1 a66c8c2cda246d332d0c2025b6266e1e23c89410051002f46bfad1c9265f43d0 SHA256 [GBB HWID]
+PCR-2 ceca357524caf8fc73f5fa130f05a75293031962af884e18990d281eb259f5ff SHA256 [FMAP: FW_MAIN_B CBFS: fallback/romstage]
+PCR-2 548a097604e0a975de76f98b04c7f0b0ddec03883dd69179e47a784704a1c571 SHA256 [FMAP: FW_MAIN_B CBFS: fspm.bin]
+PCR-2 1e86b27008818244c221df2436b0113bd20a86ec6ec9d8259defe87f45d2f604 SHA256 [FMAP: FW_MAIN_B CBFS: spd2.bin]
+PCR-2 05d78005fcfc9edd4ca5625f11b1f49991d17bdb7cee33b72e722bc785db55ae SHA256 [FMAP: FW_MAIN_B CBFS: fallback/postcar]
+PCR-2 c13e95829af12a584046f1a6f3e1f6e4af691209324cfeeec573633399384141 SHA256 [FMAP: FW_MAIN_B CBFS: fallback/ramstage]
+PCR-2 a6ec2761b597abd252dba2a7237140ef4a5a8e0d47cad8afb65fa16314413401 SHA256 [FMAP: FW_MAIN_B CBFS: cpu_microcode_blob.bin]
+PCR-2 c81ffa40df0b6cd6cfde4f476d452a1f6f2217bc96a3b98a4fa4a037ee7039cf SHA256 [FMAP: FW_MAIN_B CBFS: fsps.bin]
+PCR-2 4e95f57bbf3c6627eb1c72be9c48df3aaa8e6da4f5f63d85e554cf6803505609 SHA256 [FMAP: FW_MAIN_B CBFS: vbt.bin]
+PCR-3 b7663f611ecf8637a59d72f623ae92a456c30377d4175e96021c85362f0323c8 SHA256 [FMAP: RW_NVRAM]
+PCR-2 178561f046e2adbc621b12b47d65be82756128e2a1fe5116b53ef3637da700e8 SHA256 [FMAP: FW_MAIN_B CBFS: fallback/dsdt.aml]
+PCR-2 091706f5fce3eb123dd9b96c15a9dcc459a694f5e5a86e7bf6064b819a8575c7 SHA256 [FMAP: FW_MAIN_B CBFS: fallback/payload]
+```
+
+#### Dump TCPA eventlog in the OS:
+```bash
+cbmem -L
+```
+
+#### Get CBFS file and print the hash
+```bash
+cbfstool coreboot.rom extract -r COREBOOT -n fallback/romstage -U -f /dev/stdout | sha256sum
+```
+
+#### Get FMAP partition and print the hash
+```bash
+cbfstool coreboot.rom read -n SI_ME -f /dev/stdout | sha256sum
+```
+
 ## DRTM Mode
 The "Dynamic Root of Trust for Measurement" is realised by platform features
 like Intel TXT or Boot Guard. The features provide a way of loading a signed
@@ -42,17 +119,21 @@ PCR-7 are left empty.
 
 ### PCR-0
 _Hash:_ SHA1
+
 _Description:_ Google VBoot GBB flags.
 
 ### PCR-1
 _Hash:_ SHA1/SHA256
+
 _Description:_ Google VBoot GBB HWID.
 
 ### PCR-2
 _Hash:_ SHA1/SHA256
+
 _Description:_ Core Root of Trust for Measurement which includes all stages,
 data and blobs.
 
 ### PCR-3
 _Hash:_ SHA1/SHA256
+
 _Description:_ Runtime data like hwinfo.hex or MRC cache.
diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md
@@ -0,0 +1,17 @@
+# Intel Firmware Support Package (FSP)-specific documentation
+
+This section contains documentation about Intel-FSP in public domain.
+
+## Open Source Intel FSP specification
+
+* [About Intel FSP](https://firmware.intel.com/learn/fsp/about-intel-fsp)
+
+* [FSP Specification 1.0](https://www.intel.in/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec.pdf)
+
+* [FSP Specification 1.1](https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf)
+
+* [FSP Specification 2.0](https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v2.pdf)
+
+## Additional Features in FSP 2.1 specification
+
+- [PPI](ppi/ppi.md)
diff --git a/...elake/coreboot_publish_mp_service_api.png → ...p/ppi/coreboot_publish_mp_service_api.png b/...elake/coreboot_publish_mp_service_api.png → ...p/ppi/coreboot_publish_mp_service_api.png
diff --git a/...n/soc/intel/icelake/MultiProcessorInit.md → ...ation/soc/intel/fsp/ppi/mp_service_ppi.md b/...n/soc/intel/icelake/MultiProcessorInit.md → ...ation/soc/intel/fsp/ppi/mp_service_ppi.md
diff --git a/Documentation/soc/intel/fsp/ppi/ppi.md b/Documentation/soc/intel/fsp/ppi/ppi.md
@@ -0,0 +1,14 @@
+# PEIM to PEIM Interface (PPI)
+
+This section is intended to document the purpose of creating PPI service
+inside coreboot space to perform some specific operation related to CPU,
+chipset using Intel FSP. This feature is added into FSP specification 2.1
+where FSP should be able to locate PPI, published by boot firmware and
+able to execute the same in FSP's context.
+
+* [What is PPI](https://www.intel.com/content/dam/www/public/us/en/documents/reference-guides/efi-pei-cis-v09.pdf)
+
+## List of PPI service
+
+### Publish MP Service PPI from boot firmware (coreboot) to initialize CPU
+- [MP Service PPI](mp_service_ppi.md)
diff --git a/Documentation/soc/intel/icelake/index.md b/Documentation/soc/intel/icelake/index.md
@@ -5,7 +5,3 @@ This section contains documentation about coreboot on specific Intel "Ice Lake"
 ## Ice Lake coreboot development
 
 - [Ice Lake coreboot development](iceLake_coreboot_development.md)
-
-## Multiprocessor Init
-
-- [Multiprocessor Init](MultiProcessorInit.md)
diff --git a/Documentation/soc/intel/index.md b/Documentation/soc/intel/index.md
@@ -5,4 +5,6 @@ This section contains documentation about coreboot on specific Intel SOCs.
 ## Platforms
 
 - [Common code development strategy](code_development_model/code_development_model.md)
+- [FSP](fsp/index.md)
 - [Ice Lake/9th Gen Core-i series](icelake/index.md)
+- [MP Initialization](mp_init/mp_init.md)
diff --git a/Documentation/soc/intel/mp_init/mp_init.md b/Documentation/soc/intel/mp_init/mp_init.md
@@ -0,0 +1,56 @@
+# Multiple Processor (MP) Initialization
+
+This section is intended to document the purpose of performing multiprocessor
+initialization and its possible ways in coreboot space.
+
+Entire CPU multiprocessor initialization can be divided into two parts
+1. BSP (Boot Strap Processor) Initialization
+2. AP (Application Processor) Initialization
+
+* [Multiple Processor Init](https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.pdf) - section 8.4
+
+## Problem Statement
+
+1. coreboot is capable enough to handle multiprocessor initialization on
+IA platforms.
+
+2. With restricted CPU programming logic, there might be some cases where
+certain feature programming can't be open sourced at early development of SOC.
+
+Platform code might need to compromise on those closed source nature of CPU
+programming if we don't plan to provide an alternate interface which can be
+used by coreboot to get rid of such close sourced CPU programming.
+
+## Possible Solution Space
+
+Considering these facts, there are 3 possible solutions to perform MP
+initialization from coreboot + FSP space.
+
+1. coreboot to perform complete MP initialization by its own. This includes
+BSP and AP programming of CPU features mostly non-restricted one. Preferred
+Kconfig is USE_COREBOOT_NATIVE_MP_INIT. SoCs like SKL, KBL, APL are okay to
+make use of same Kconfig option for MP initialization.
+
+2. Alternatively, SoC users also can skip coreboot doing MP initialization
+and make use of FSP binary to perform same task. This can be achieved by using
+Kconfig name USE_INTEL_FSP_MP_INIT. As of 2019 all Google Chrome products are
+using coreboot native MP initialization mechanism and some IOTG platforms
+are using FSP MP Init solution as well.
+
+3. Final option is to let coreboot publish PPI (PEIM to PEIM Interface) to
+perform some restricted (closed source) CPU programming. In that case,
+coreboot will use its native MP init and additionally publish MP service PPI
+for FSP to consume. FSP will execute some CPU programming using same PPI
+service from its own context. One can use
+USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI Kconfig to perform this
+operation.
+
+For latest SoCs like CNL, WHL, ICL, etc, its recommended to make use of this
+option in order to perform SGX and C6DRAM enabling.
+
+Typically all platforms supported by FSP 2.1 specification will have
+external PPI service feature implemented.
+
+[References]
+- [PPI](../fsp/ppi/ppi.md)
+- [MP Service PPI](../fsp/ppi/mp_service_ppi.md)
diff --git a/configs/config.pcengines_apu1 b/configs/config.pcengines_apu1
@@ -1,11 +1,11 @@
-CONFIG_LOCALVERSION="v4.9.0.3"
+CONFIG_LOCALVERSION="v4.9.0.4"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_NO_GFX_INIT=y
 CONFIG_USER_TPM2=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
 CONFIG_SEABIOS_REVISION=y
-CONFIG_SEABIOS_REVISION_ID="rel-1.12.0.1"
+CONFIG_SEABIOS_REVISION_ID="rel-1.12.1.1"
 CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder"
 CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y

diff --git a/configs/config.pcengines_apu2 b/configs/config.pcengines_apu2
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.9.0.3"
+CONFIG_LOCALVERSION="v4.9.0.4"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU2=y
@@ -7,7 +7,7 @@ CONFIG_NO_GFX_INIT=y
 CONFIG_USER_TPM2=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
 CONFIG_SEABIOS_REVISION=y
-CONFIG_SEABIOS_REVISION_ID="rel-1.12.0.1"
+CONFIG_SEABIOS_REVISION_ID="rel-1.12.1.1"
 CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y

diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu3
@@ -1,12 +1,12 @@
-CONFIG_LOCALVERSION="v4.9.0.3"
+CONFIG_LOCALVERSION="v4.9.0.4"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU3=y
 CONFIG_CPU_MICROCODE_CBFS_NONE=y
 CONFIG_NO_GFX_INIT=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
 CONFIG_SEABIOS_REVISION=y
-CONFIG_SEABIOS_REVISION_ID="rel-1.12.0.1"
+CONFIG_SEABIOS_REVISION_ID="rel-1.12.1.1"
 CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y

diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_apu4
@@ -1,12 +1,12 @@
-CONFIG_LOCALVERSION="v4.9.0.3"
+CONFIG_LOCALVERSION="v4.9.0.4"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU4=y
 CONFIG_CPU_MICROCODE_CBFS_NONE=y
 CONFIG_NO_GFX_INIT=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
 CONFIG_SEABIOS_REVISION=y
-CONFIG_SEABIOS_REVISION_ID="rel-1.12.0.1"
+CONFIG_SEABIOS_REVISION_ID="rel-1.12.1.1"
 CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y

diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu5
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.9.0.3"
+CONFIG_LOCALVERSION="v4.9.0.4"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU5=y
@@ -7,7 +7,7 @@ CONFIG_NO_GFX_INIT=y
 CONFIG_USER_TPM2=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
 CONFIG_SEABIOS_REVISION=y
-CONFIG_SEABIOS_REVISION_ID="rel-1.12.0.1"
+CONFIG_SEABIOS_REVISION_ID="rel-1.12.1.1"
 CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
 CONFIG_SEABIOS_DEBUG_LEVEL=0
 CONFIG_PXE=y

diff --git a/payloads/Kconfig b/payloads/Kconfig
@@ -100,6 +100,7 @@ config PAYLOAD_FIT_SUPPORT
 	bool "FIT support"
 	default n
 	default y if PAYLOAD_LINUX && (ARCH_ARM || ARCH_ARM64)
+	depends on ARCH_ARM64
 	select FLATTENED_DEVICE_TREE
 	help
 	  Select this option if your payload is of type FIT.

diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc
@@ -34,7 +34,6 @@ payloads/external/Memtest86Plus \
 payloads/external/iPXE \
 payloads/external/tint \
 payloads/external/sortbootorder \
-payloads/external/sgabios \
 payloads/external/tianocore \
 payloads/external/GRUB2 \
 payloads/external/LinuxBoot \

diff --git a/payloads/coreinfo/bootlog_module.c b/payloads/coreinfo/bootlog_module.c
@@ -15,7 +15,7 @@
 
 #include "coreinfo.h"
 
-#if IS_ENABLED(CONFIG_MODULE_BOOTLOG)
+#if CONFIG(MODULE_BOOTLOG)
 
 #define LINES_SHOWN 19
 #define TAB_WIDTH 2

diff --git a/payloads/coreinfo/cbfs_module.c b/payloads/coreinfo/cbfs_module.c
@@ -16,7 +16,7 @@
 #include "coreinfo.h"
 #include "endian.h"
 
-#if IS_ENABLED(CONFIG_MODULE_CBFS)
+#if CONFIG(MODULE_CBFS)
 
 #define FILES_VISIBLE		19
 

diff --git a/payloads/coreinfo/coreboot_module.c b/payloads/coreinfo/coreboot_module.c
@@ -16,7 +16,7 @@
 #include "coreinfo.h"
 #include <coreboot_tables.h>
 
-#if IS_ENABLED(CONFIG_MODULE_COREBOOT)
+#if CONFIG(MODULE_COREBOOT)
 
 #define MAX_MEMORY_COUNT 5
 

diff --git a/payloads/coreinfo/coreinfo.c b/payloads/coreinfo/coreinfo.c
@@ -28,34 +28,34 @@ extern struct coreinfo_module cbfs_module;
 extern struct coreinfo_module timestamps_module;
 
 struct coreinfo_module *system_modules[] = {
-#if IS_ENABLED(CONFIG_MODULE_CPUINFO)
+#if CONFIG(MODULE_CPUINFO)
 	&cpuinfo_module,
 #endif
-#if IS_ENABLED(CONFIG_MODULE_PCI)
+#if CONFIG(MODULE_PCI)
 	&pci_module,
 #endif
-#if IS_ENABLED(CONFIG_MODULE_NVRAM)
+#if CONFIG(MODULE_NVRAM)
 	&nvram_module,
 #endif
-#if IS_ENABLED(CONFIG_MODULE_RAMDUMP)
+#if CONFIG(MODULE_RAMDUMP)
 	&ramdump_module,
 #endif
 };
 
 struct coreinfo_module *firmware_modules[] = {
-#if IS_ENABLED(CONFIG_MODULE_COREBOOT)
+#if CONFIG(MODULE_COREBOOT)
 	&coreboot_module,
 #endif
-#if IS_ENABLED(CONFIG_MODULE_MULTIBOOT)
+#if CONFIG(MODULE_MULTIBOOT)
 	&multiboot_module,
 #endif
-#if IS_ENABLED(CONFIG_MODULE_BOOTLOG)
+#if CONFIG(MODULE_BOOTLOG)
 	&bootlog_module,
 #endif
-#if IS_ENABLED(CONFIG_MODULE_CBFS)
+#if CONFIG(MODULE_CBFS)
 	&cbfs_module,
 #endif
-#if IS_ENABLED(CONFIG_MODULE_TIMESTAMPS)
+#if CONFIG(MODULE_TIMESTAMPS)
 	&timestamps_module,
 #endif
 };
@@ -114,7 +114,7 @@ static void print_submenu(struct coreinfo_cat *cat)
 	mvwprintw(menuwin, 0, 0, menu);
 }
 
-#if IS_ENABLED(CONFIG_SHOW_DATE_TIME)
+#if CONFIG(SHOW_DATE_TIME)
 static void print_time_and_date(void)
 {
 	struct tm tm;
@@ -149,7 +149,7 @@ static void print_menu(void)
 
 	mvwprintw(menuwin, 1, 0, menu);
 
-#if IS_ENABLED(CONFIG_SHOW_DATE_TIME)
+#if CONFIG(SHOW_DATE_TIME)
 	print_time_and_date();
 #endif
 }
@@ -253,7 +253,7 @@ static void loop(void)
 	while (1) {
 		int ch = -1;
 
-#if IS_ENABLED(CONFIG_SHOW_DATE_TIME)
+#if CONFIG(SHOW_DATE_TIME)
 		print_time_and_date();
 		wrefresh(menuwin);
 #endif
@@ -291,7 +291,7 @@ int main(void)
 {
 	int i, j;
 
-	if (IS_ENABLED(CONFIG_LP_USB))
+	if (CONFIG(LP_USB))
 		usb_initialize();
 
 	initscr();

diff --git a/payloads/coreinfo/cpuinfo_module.c b/payloads/coreinfo/cpuinfo_module.c
@@ -18,7 +18,7 @@
 
 #include "coreinfo.h"
 
-#if IS_ENABLED(CONFIG_MODULE_CPUINFO)
+#if CONFIG(MODULE_CPUINFO)
 #include <arch/rdtsc.h>
 
 #define VENDOR_INTEL 0x756e6547

diff --git a/payloads/coreinfo/multiboot_module.c b/payloads/coreinfo/multiboot_module.c
@@ -16,7 +16,7 @@
 #include <multiboot_tables.h>
 #include "coreinfo.h"
 
-#if IS_ENABLED(CONFIG_MODULE_MULTIBOOT)
+#if CONFIG(MODULE_MULTIBOOT)
 
 #define MAX_MEMORY_COUNT  10
 

diff --git a/payloads/coreinfo/nvram_module.c b/payloads/coreinfo/nvram_module.c
@@ -15,7 +15,7 @@
 
 #include "coreinfo.h"
 
-#if IS_ENABLED(CONFIG_MODULE_NVRAM)
+#if CONFIG(MODULE_NVRAM)
 
 /**
  * Dump 256 bytes of NVRAM.

diff --git a/payloads/coreinfo/pci_module.c b/payloads/coreinfo/pci_module.c
@@ -18,7 +18,7 @@
 #include <libpayload.h>
 #include "coreinfo.h"
 
-#if IS_ENABLED(CONFIG_MODULE_PCI)
+#if CONFIG(MODULE_PCI)
 
 struct pci_devices {
 	pcidev_t device;

diff --git a/payloads/coreinfo/ramdump_module.c b/payloads/coreinfo/ramdump_module.c
@@ -15,7 +15,7 @@
 
 #include "coreinfo.h"
 
-#if IS_ENABLED(CONFIG_MODULE_RAMDUMP)
+#if CONFIG(MODULE_RAMDUMP)
 
 static s64 cursor = 0;
 static s64 cursor_max = (1 * 1024 * 1024 * 1024); /* Max. 1 GB RAM for now. */

diff --git a/payloads/coreinfo/timestamps_module.c b/payloads/coreinfo/timestamps_module.c
@@ -14,7 +14,7 @@
 #include "coreinfo.h"
 #include <commonlib/timestamp_serialized.h>
 
-#if IS_ENABLED(CONFIG_MODULE_TIMESTAMPS)
+#if CONFIG(MODULE_TIMESTAMPS)
 
 #define LINES_SHOWN 19
 #define TAB_WIDTH 2
@@ -203,8 +203,10 @@ static int timestamps_module_init(void)
 			SCREEN_X, LINES_SHOWN);
 
 	/* Sanity check, chars_count must be padded to full line */
-	if (chars_count % SCREEN_X != 0)
+	if (chars_count % SCREEN_X != 0) {
+		free(buffer);
 		return -2;
+	}
 
 	g_lines_count = chars_count / SCREEN_X;
 	g_max_cursor_line = MAX(g_lines_count - 1 - LINES_SHOWN, 0);

diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig
@@ -5,7 +5,7 @@ choice
 	default SEABIOS_STABLE
 
 config SEABIOS_STABLE
-	bool "1.12.0"
+	bool "1.12.1"
 	help
 	  Stable SeaBIOS version
 config SEABIOS_MASTER

diff --git a/payloads/external/sgabios/Makefile b/payloads/external/sgabios/Makefile
diff --git a/payloads/external/tint/libpayload_tint.patch b/payloads/external/tint/libpayload_tint.patch
@@ -371,7 +371,7 @@ diff -rupN tint-0.04+nmu1/tint.c tint/tint.c
     int ch;
     engine_t engine;
     /* Initialize */
-+   if (IS_ENABLED(CONFIG_LP_USB))
++   if (CONFIG(LP_USB))
 +      usb_initialize();
     rand_init ();							/* must be called before engine_init () */
     engine_init (&engine,score_function);	/* must be called before using engine.curshape */

diff --git a/payloads/libpayload/arch/arm/main.c b/payloads/libpayload/arch/arm/main.c
@@ -48,7 +48,7 @@ void start_main(void)
 	lib_get_sysinfo();
 
 	/* Optionally set up the consoles. */
-#if !IS_ENABLED(CONFIG_LP_SKIP_CONSOLE_INIT)
+#if !CONFIG(LP_SKIP_CONSOLE_INIT)
 	console_init();
 #endif
 

diff --git a/payloads/libpayload/arch/arm64/main.c b/payloads/libpayload/arch/arm64/main.c
@@ -123,7 +123,7 @@ void start_main(void)
 
 	post_sysinfo_scan_mmu_setup();
 
-#if !IS_ENABLED(CONFIG_LP_SKIP_CONSOLE_INIT)
+#if !CONFIG(LP_SKIP_CONSOLE_INIT)
 	console_init();
 #endif
 

diff --git a/payloads/libpayload/arch/mips/main.c b/payloads/libpayload/arch/mips/main.c
@@ -34,7 +34,7 @@ void start_main(void)
 	lib_get_sysinfo();
 
 	/* Optionally set up the consoles. */
-#if !IS_ENABLED(CONFIG_LP_SKIP_CONSOLE_INIT)
+#if !CONFIG(LP_SKIP_CONSOLE_INIT)
 	console_init();
 #endif
 

diff --git a/payloads/libpayload/arch/x86/delay.c b/payloads/libpayload/arch/x86/delay.c
@@ -50,7 +50,7 @@ void arch_ndelay(uint64_t ns)
 	if (ns > APIC_INTERRUPT_LATENCY_NS)
 		apic_us = (ns - APIC_INTERRUPT_LATENCY_NS) / NSECS_PER_USEC;
 
-	if (IS_ENABLED(CONFIG_LP_ENABLE_APIC) && apic_initialized() && apic_us)
+	if (CONFIG(LP_ENABLE_APIC) && apic_initialized() && apic_us)
 		apic_delay(apic_us);
 
 	if (delta > PAUSE_THRESHOLD_TICKS)

diff --git a/payloads/libpayload/arch/x86/exception.c b/payloads/libpayload/arch/x86/exception.c
@@ -173,10 +173,10 @@ void exception_dispatch(void)
 		handlers[vec](vec);
 		goto success;
 	} else if (vec >= EXC_COUNT
-		   && IS_ENABLED(CONFIG_LP_IGNORE_UNKNOWN_INTERRUPTS)) {
+		   && CONFIG(LP_IGNORE_UNKNOWN_INTERRUPTS)) {
 		goto success;
 	} else if (vec >= EXC_COUNT
-		   && IS_ENABLED(CONFIG_LP_LOG_UNKNOWN_INTERRUPTS)) {
+		   && CONFIG(LP_LOG_UNKNOWN_INTERRUPTS)) {
 		printf("Ignoring interrupt vector %u\n", vec);
 		goto success;
 	}
@@ -192,7 +192,7 @@ void exception_dispatch(void)
 	return;
 
 success:
-	if (IS_ENABLED(CONFIG_LP_ENABLE_APIC))
+	if (CONFIG(LP_ENABLE_APIC))
 		apic_eoi(vec);
 }
 

diff --git a/payloads/libpayload/arch/x86/main.c b/payloads/libpayload/arch/x86/main.c
@@ -52,13 +52,13 @@ int start_main(void)
 	lib_get_sysinfo();
 
 	/* Optionally set up the consoles. */
-#if !IS_ENABLED(CONFIG_LP_SKIP_CONSOLE_INIT)
+#if !CONFIG(LP_SKIP_CONSOLE_INIT)
 	console_init();
 #endif
 
 	exception_init();
 
-	if (IS_ENABLED(CONFIG_LP_ENABLE_APIC)) {
+	if (CONFIG(LP_ENABLE_APIC)) {
 		apic_init();
 
 		enable_interrupts();

diff --git a/payloads/libpayload/arch/x86/multiboot.c b/payloads/libpayload/arch/x86/multiboot.c
@@ -40,7 +40,7 @@ static int mb_add_memrange(struct sysinfo_t *info, unsigned long long base,
 	if (info->n_memranges >= SYSINFO_MAX_MEM_RANGES)
 		return -1;
 
-#if IS_ENABLED(CONFIG_LP_MEMMAP_RAM_ONLY)
+#if CONFIG(LP_MEMMAP_RAM_ONLY)
 	/* 1 == normal RAM.  Ignore everything else for now */
 	if (type != 1)
 		return 0;

diff --git a/payloads/libpayload/arch/x86/rom_media.c b/payloads/libpayload/arch/x86/rom_media.c
@@ -83,7 +83,7 @@ int init_x86rom_cbfs_media(struct cbfs_media *media) {
 	struct cbfs_header *header = (struct cbfs_header*)
 			*(uint32_t*)(0xfffffffc);
 	if (CBFS_HEADER_MAGIC != ntohl(header->magic)) {
-#if IS_ENABLED(CONFIG_LP_ROM_SIZE)
+#if CONFIG(LP_ROM_SIZE)
 		printk(BIOS_ERR, "Invalid CBFS master header at %p\n", header);
 		media->context = (void*)CONFIG_LP_ROM_SIZE;
 #else
@@ -92,7 +92,7 @@ int init_x86rom_cbfs_media(struct cbfs_media *media) {
 	} else {
 		uint32_t romsize = ntohl(header->romsize);
 		media->context = (void*)romsize;
-#if IS_ENABLED(CONFIG_LP_ROM_SIZE)
+#if CONFIG(LP_ROM_SIZE)
 		if (CONFIG_LP_ROM_SIZE != romsize)
 			printk(BIOS_INFO, "Warning: rom size unmatch (%d/%d)\n",
 			       CONFIG_LP_ROM_SIZE, romsize);

diff --git a/payloads/libpayload/arch/x86/sysinfo.c b/payloads/libpayload/arch/x86/sysinfo.c
@@ -40,7 +40,7 @@
  */
 struct sysinfo_t lib_sysinfo = {
 	.cpu_khz = CPU_KHZ_DEFAULT,
-#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE)
+#if CONFIG(LP_SERIAL_CONSOLE)
 	.ser_ioport = CONFIG_LP_SERIAL_IOBASE,
 #else
 	.ser_ioport = 0x3f8,
@@ -51,7 +51,7 @@ int lib_get_sysinfo(void)
 {
 	int ret;
 
-#if IS_ENABLED(CONFIG_LP_MULTIBOOT)
+#if CONFIG(LP_MULTIBOOT)
 	/* Get the information from the multiboot tables,
 	 * if they exist */
 	get_multiboot_info(&lib_sysinfo);

diff --git a/payloads/libpayload/configs/config.mistral b/payloads/libpayload/configs/config.mistral
@@ -0,0 +1,3 @@
+CONFIG_LP_CHROMEOS=y
+CONFIG_LP_ARCH_ARM64=y
+CONFIG_LP_TIMER_ARM64_ARCH=y
diff --git a/payloads/libpayload/crypto/sha1.c b/payloads/libpayload/crypto/sha1.c
@@ -30,7 +30,7 @@ typedef unsigned int u_int;
 
 /* Moved from libpayload.h */
 
-#if IS_ENABLED(CONFIG_LP_LITTLE_ENDIAN)
+#if CONFIG(LP_LITTLE_ENDIAN)
 #define BYTE_ORDER      LITTLE_ENDIAN
 #else
 #define BYTE_ORDER      BIG_ENDIAN

diff --git a/payloads/libpayload/curses/keyboard.c b/payloads/libpayload/curses/keyboard.c
@@ -45,7 +45,7 @@ static int _halfdelay = 0;
 
 /* ============== Serial ==================== */
 
-#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE)
+#if CONFIG(LP_SERIAL_CONSOLE)
 /* We treat serial like a vt100 terminal.  For now we
    do the cooking in here, but we should probably eventually
    pass it to dedicated vt100 code */
@@ -146,29 +146,29 @@ static int cook_serial(unsigned char ch)
 
 static int curses_getchar(int _delay)
 {
-#if IS_ENABLED(CONFIG_LP_USB_HID) || IS_ENABLED(CONFIG_LP_PC_KEYBOARD) || \
-	IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE)
+#if CONFIG(LP_USB_HID) || CONFIG(LP_PC_KEYBOARD) || \
+	CONFIG(LP_SERIAL_CONSOLE)
 	unsigned short c;
 #endif
 
 	do {
-#if IS_ENABLED(CONFIG_LP_USB_HID)
+#if CONFIG(LP_USB_HID)
 		usb_poll();
 		if ((curses_flags & F_ENABLE_CONSOLE) &&
 		    usbhid_havechar()) {
 			c = usbhid_getchar();
 			if (c != 0) return c;
 		}
 #endif
-#if IS_ENABLED(CONFIG_LP_PC_KEYBOARD)
+#if CONFIG(LP_PC_KEYBOARD)
 		if ((curses_flags & F_ENABLE_CONSOLE) &&
 		    keyboard_havechar()) {
 			c = keyboard_getchar();
 			if (c != 0) return c;
 		}
 #endif
 
-#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE)
+#if CONFIG(LP_SERIAL_CONSOLE)
 		if ((curses_flags & F_ENABLE_SERIAL) &&
 		    serial_havechar()) {
 			c = serial_getchar();
@@ -226,7 +226,7 @@ int nocbreak(void)
 	return 0;
 }
 
-#if IS_ENABLED(CONFIG_LP_VGA_VIDEO_CONSOLE)
+#if CONFIG(LP_VGA_VIDEO_CONSOLE)
 void curses_enable_vga(int state)
 {
 	if (state)
@@ -244,7 +244,7 @@ void curses_enable_vga(int state) { }
 int curses_vga_enabled(void) { return 0; }
 #endif
 
-#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE)
+#if CONFIG(LP_SERIAL_CONSOLE)
 void curses_enable_serial(int state)
 {
 	if (state)

diff --git a/payloads/libpayload/curses/local.h b/payloads/libpayload/curses/local.h
@@ -70,13 +70,13 @@
 
 /* Flags used to determine what output methods are available */
 
-#if IS_ENABLED(CONFIG_LP_VIDEO_CONSOLE)
+#if CONFIG(LP_VIDEO_CONSOLE)
 #define F_ENABLE_CONSOLE 0x01
 #else
 #define F_ENABLE_CONSOLE 0x00
 #endif
 
-#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE)
+#if CONFIG(LP_SERIAL_CONSOLE)
 #define F_ENABLE_SERIAL  0x02
 #else
 #define F_ENABLE_SERIAL  0x00

diff --git a/payloads/libpayload/curses/pdcurses-backend/pdcdisp.c b/payloads/libpayload/curses/pdcurses-backend/pdcdisp.c
@@ -66,8 +66,8 @@ chtype fallback_acs_map[128] =
 	'|',	'<',	'>',	'*',	'!',	'f',	'o',	' ',
 	};
 
-#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE)
-#if IS_ENABLED(CONFIG_LP_SERIAL_ACS_FALLBACK)
+#if CONFIG(LP_SERIAL_CONSOLE)
+#if CONFIG(LP_SERIAL_ACS_FALLBACK)
 chtype serial_acs_map[128];
 #else
 /* See acsc of vt100. */
@@ -93,7 +93,7 @@ chtype serial_acs_map[128] =
 #endif
 #endif
 
-#if IS_ENABLED(CONFIG_LP_VIDEO_CONSOLE)
+#if CONFIG(LP_VIDEO_CONSOLE)
 /* See acsc of linux. */
 chtype console_acs_map[128] =
 	{
@@ -122,10 +122,10 @@ void PDC_gotoyx(int row, int col)
 {
     PDC_LOG(("PDC_gotoyx() - called: row %d col %d\n", row, col));
 
-#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE)
+#if CONFIG(LP_SERIAL_CONSOLE)
     serial_set_cursor(col, row);
 #endif
-#if IS_ENABLED(CONFIG_LP_VIDEO_CONSOLE)
+#if CONFIG(LP_VIDEO_CONSOLE)
     video_console_set_cursor(col, row);
 #endif
 }
@@ -139,7 +139,7 @@ void PDC_transform_line(int lineno, int x, int len, const chtype *srcp)
 
     PDC_LOG(("PDC_transform_line() - called: line %d, len %d, curses_flags %d\n", lineno, len, curses_flags));
 
-#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE)
+#if CONFIG(LP_SERIAL_CONSOLE)
     int serial_is_bold = 0;
     int serial_is_reverse = 0;
     int serial_is_altcharset = 0;
@@ -157,7 +157,7 @@ void PDC_transform_line(int lineno, int x, int len, const chtype *srcp)
     {
 	ch = srcp[j];
 	attr = ch;
-#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE)
+#if CONFIG(LP_SERIAL_CONSOLE)
 	if (curses_flags & F_ENABLE_SERIAL) {
 		if (attr & A_BOLD) {
 			if (!serial_is_bold) {
@@ -222,7 +222,7 @@ void PDC_transform_line(int lineno, int x, int len, const chtype *srcp)
 
 	}
 #endif
-#if IS_ENABLED(CONFIG_LP_VIDEO_CONSOLE)
+#if CONFIG(LP_VIDEO_CONSOLE)
 	unsigned char c = pdc_atrtab[srcp[j] >> PDC_ATTR_SHIFT];
 
 	if (curses_flags & F_ENABLE_CONSOLE) {

diff --git a/payloads/libpayload/curses/pdcurses-backend/pdckbd.c b/payloads/libpayload/curses/pdcurses-backend/pdckbd.c
@@ -5,7 +5,7 @@
 
 unsigned long pdc_key_modifiers = 0L;
 
-#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE)
+#if CONFIG(LP_SERIAL_CONSOLE)
 /* We treat serial like a vt100 terminal.  For now we
    do the cooking in here, but we should probably eventually
    pass it to dedicated vt100 code */
@@ -108,22 +108,22 @@ void PDC_set_keyboard_binary(bool on)
 
 bool PDC_check_key(void)
 {
-#if IS_ENABLED(CONFIG_LP_USB_HID)
+#if CONFIG(LP_USB_HID)
     usb_poll();
     if ((curses_flags & F_ENABLE_CONSOLE) &&
         usbhid_havechar()) {
         return TRUE;
     }
 #endif
 
-#if IS_ENABLED(CONFIG_LP_PC_KEYBOARD)
+#if CONFIG(LP_PC_KEYBOARD)
     if ((curses_flags & F_ENABLE_CONSOLE) &&
         keyboard_havechar()) {
         return TRUE;
     }
 #endif
 
-#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE)
+#if CONFIG(LP_SERIAL_CONSOLE)
     if ((curses_flags & F_ENABLE_SERIAL) &&
         serial_havechar()) {
         return TRUE;
@@ -139,22 +139,22 @@ int PDC_get_key(void)
 {
     int c = 0;
 
-#if IS_ENABLED(CONFIG_LP_USB_HID)
+#if CONFIG(LP_USB_HID)
     usb_poll();
     if ((curses_flags & F_ENABLE_CONSOLE) &&
         usbhid_havechar()) {
         c = usbhid_getchar();
     }
 #endif
 
-#if IS_ENABLED(CONFIG_LP_PC_KEYBOARD)
+#if CONFIG(LP_PC_KEYBOARD)
     if ((curses_flags & F_ENABLE_CONSOLE) &&
         keyboard_havechar() && (c == 0)) {
         c = keyboard_getchar();
     }
 #endif
 
-#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE)
+#if CONFIG(LP_SERIAL_CONSOLE)
     if ((curses_flags & F_ENABLE_SERIAL) &&
         serial_havechar() && (c == 0)) {
         c = cook_serial(serial_getchar());

diff --git a/payloads/libpayload/curses/pdcurses-backend/pdcscrn.c b/payloads/libpayload/curses/pdcurses-backend/pdcscrn.c
@@ -72,7 +72,7 @@ int PDC_scr_open(int argc, char **argv)
     SP->lines = PDC_get_rows();
     SP->cols = PDC_get_columns();
 
-#if IS_ENABLED(CONFIG_LP_SPEAKER)
+#if CONFIG(LP_SPEAKER)
     SP->audible = TRUE;
 #endif
 

diff --git a/payloads/libpayload/curses/pdcurses-backend/pdcsetsc.c b/payloads/libpayload/curses/pdcurses-backend/pdcsetsc.c
@@ -13,12 +13,12 @@ int PDC_curs_set(int visibility)
     ret_vis = SP->visibility;
     SP->visibility = visibility;
 
-#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE)
+#if CONFIG(LP_SERIAL_CONSOLE)
     if (curses_flags & F_ENABLE_SERIAL) {
         serial_cursor_enable(visibility);
     }
 #endif
-#if IS_ENABLED(CONFIG_LP_VIDEO_CONSOLE)
+#if CONFIG(LP_VIDEO_CONSOLE)
     if (curses_flags & F_ENABLE_CONSOLE) {
         video_console_cursor_enable(visibility);
     }

diff --git a/payloads/libpayload/curses/pdcurses-backend/pdcutil.c b/payloads/libpayload/curses/pdcurses-backend/pdcutil.c
@@ -11,7 +11,7 @@ void PDC_beep(void)
 {
     PDC_LOG(("PDC_beep() - called\n"));
 
-#if IS_ENABLED(CONFIG_LP_SPEAKER)
+#if CONFIG(LP_SPEAKER)
     speaker_tone(1760, 500); /* 1760 == note A6 */
 #endif
 }

diff --git a/payloads/libpayload/curses/tinycurses.c b/payloads/libpayload/curses/tinycurses.c
@@ -111,8 +111,8 @@ chtype fallback_acs_map[128] =
 	'|',	'<',	'>',	'*',	'!',	'f',	'o',	' ',
 	};
 
-#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE)
-#if IS_ENABLED(CONFIG_LP_SERIAL_ACS_FALLBACK)
+#if CONFIG(LP_SERIAL_CONSOLE)
+#if CONFIG(LP_SERIAL_ACS_FALLBACK)
 chtype serial_acs_map[128];
 #else
 /* See acsc of vt100. */
@@ -138,7 +138,7 @@ chtype serial_acs_map[128] =
 #endif
 #endif
 
-#if IS_ENABLED(CONFIG_LP_VIDEO_CONSOLE)
+#if CONFIG(LP_VIDEO_CONSOLE)
 /* See acsc of linux. */
 chtype console_acs_map[128] =
 	{
@@ -191,7 +191,7 @@ NCURSES_CH_T _nc_render(WINDOW *win, NCURSES_CH_T ch)
 int beep(void)
 {
 	/* TODO: Flash the screen if beeping fails? */
-#if IS_ENABLED(CONFIG_LP_SPEAKER)
+#if CONFIG(LP_SPEAKER)
 	speaker_tone(1760, 500);	/* 1760 == note A6 */
 #endif
 	return OK;
@@ -202,12 +202,12 @@ int cbreak(void) { /* TODO */ return 0; }
 // int color_content(short color, short *r, short *g, short *b) {}
 int curs_set(int on)
 {
-#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE)
+#if CONFIG(LP_SERIAL_CONSOLE)
 	if (curses_flags & F_ENABLE_SERIAL) {
 		serial_cursor_enable(on);
 	}
 #endif
-#if IS_ENABLED(CONFIG_LP_VIDEO_CONSOLE)
+#if CONFIG(LP_VIDEO_CONSOLE)
 	if (curses_flags & F_ENABLE_CONSOLE) {
 		video_console_cursor_enable(on);
 	}
@@ -315,12 +315,12 @@ WINDOW *initscr(void)
 
 	for (i = 0; i < 128; i++)
 	  acs_map[i] = (chtype) i | A_ALTCHARSET;
-#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE)
+#if CONFIG(LP_SERIAL_CONSOLE)
 	if (curses_flags & F_ENABLE_SERIAL) {
 		serial_clear();
 	}
 #endif
-#if IS_ENABLED(CONFIG_LP_VIDEO_CONSOLE)
+#if CONFIG(LP_VIDEO_CONSOLE)
 	if (curses_flags & F_ENABLE_CONSOLE) {
 		/* Clear the screen and kill the cursor */
 
@@ -724,7 +724,7 @@ int whline(WINDOW *win, chtype ch, int n)
 	(((c) & 0x4400) >> 2) | ((c) & 0xAA00) | (((c) & 0x1100) << 2)
 int wnoutrefresh(WINDOW *win)
 {
-#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE)
+#if CONFIG(LP_SERIAL_CONSOLE)
 	// FIXME.
 	int serial_is_bold = 0;
 	int serial_is_reverse = 0;
@@ -737,7 +737,7 @@ int wnoutrefresh(WINDOW *win)
 	int x, y;
 	chtype ch;
 
-#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE)
+#if CONFIG(LP_SERIAL_CONSOLE)
 	serial_end_bold();
 	serial_end_altcharset();
 #endif
@@ -749,7 +749,7 @@ int wnoutrefresh(WINDOW *win)
 
 		/* Position the serial cursor */
 
-#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE)
+#if CONFIG(LP_SERIAL_CONSOLE)
 		if (curses_flags & F_ENABLE_SERIAL)
 			serial_set_cursor(win->_begy + y, win->_begx +
 					win->_line[y].firstchar);
@@ -758,7 +758,7 @@ int wnoutrefresh(WINDOW *win)
 		for (x = win->_line[y].firstchar; x <= win->_line[y].lastchar; x++) {
 			attr_t attr = win->_line[y].text[x].attr;
 
-#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE)
+#if CONFIG(LP_SERIAL_CONSOLE)
 			if (curses_flags & F_ENABLE_SERIAL) {
 				ch = win->_line[y].text[x].chars[0];
 
@@ -824,7 +824,7 @@ int wnoutrefresh(WINDOW *win)
 
 			}
 #endif
-#if IS_ENABLED(CONFIG_LP_VIDEO_CONSOLE)
+#if CONFIG(LP_VIDEO_CONSOLE)
 			unsigned int c =
 				((int)color_pairs[PAIR_NUMBER(attr)]) << 8;
 
@@ -865,12 +865,12 @@ int wnoutrefresh(WINDOW *win)
 		win->_line[y].lastchar = _NOCHANGE;
 	}
 
-#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE)
+#if CONFIG(LP_SERIAL_CONSOLE)
 	if (curses_flags & F_ENABLE_SERIAL)
 		serial_set_cursor(win->_begy + win->_cury, win->_begx + win->_curx);
 #endif
 
-#if IS_ENABLED(CONFIG_LP_VIDEO_CONSOLE)
+#if CONFIG(LP_VIDEO_CONSOLE)
 	if (curses_flags & F_ENABLE_CONSOLE)
 		video_console_set_cursor(win->_begx + win->_curx, win->_begy + win->_cury);
 #endif

diff --git a/payloads/libpayload/drivers/i8042/i8042.c b/payloads/libpayload/drivers/i8042/i8042.c
@@ -229,7 +229,7 @@ u8 i8042_probe(void)
 	}
 
 	/* Test secondary port */
-	if (IS_ENABLED(CONFIG_LP_PC_MOUSE)) {
+	if (CONFIG(LP_PC_MOUSE)) {
 		if (i8042_cmd_with_response(I8042_CMD_AUX_TEST) == 0)
 			aux_fifo = fifo_init(4 * 32);
 	}

diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c
@@ -45,7 +45,7 @@ static struct layout_maps *map;
 static int modifier = 0;
 
 static struct layout_maps keyboard_layouts[] = {
-#if IS_ENABLED(CONFIG_LP_PC_KEYBOARD_LAYOUT_US)
+#if CONFIG(LP_PC_KEYBOARD_LAYOUT_US)
 { .country = "us", .map = {
 	{ /* No modifier */
 	 0x00, 0x1B, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36,
@@ -101,7 +101,7 @@ static struct layout_maps keyboard_layouts[] = {
 	 }
 }},
 #endif
-#if IS_ENABLED(CONFIG_LP_PC_KEYBOARD_LAYOUT_DE)
+#if CONFIG(LP_PC_KEYBOARD_LAYOUT_DE)
 { .country = "de", .map = {
 	{ /* No modifier */
 	 0x00, 0x1B, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36,
@@ -309,16 +309,16 @@ void keyboard_init(void)
 
 	/* Set scancode set 1 */
 	ret = keyboard_cmd(I8042_KBCMD_SET_SCANCODE);
-	if (!ret && !IS_ENABLED(CONFIG_LP_PC_KEYBOARD_IGNORE_INIT_FAILURE))
+	if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE))
 		return;
 
 	ret = keyboard_cmd(I8042_SCANCODE_SET_1);
-	if (!ret && !IS_ENABLED(CONFIG_LP_PC_KEYBOARD_IGNORE_INIT_FAILURE))
+	if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE))
 		return;
 
 	/* Enable scanning */
 	ret = keyboard_cmd(I8042_KBCMD_EN);
-	if (!ret && !IS_ENABLED(CONFIG_LP_PC_KEYBOARD_IGNORE_INIT_FAILURE))
+	if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE))
 		return;
 
 	console_add_input_driver(&cons);

diff --git a/payloads/libpayload/drivers/mouse_cursor.c b/payloads/libpayload/drivers/mouse_cursor.c
@@ -60,7 +60,7 @@ void mouse_cursor_add_input_driver(struct mouse_cursor_input_driver *const in)
 /** Init enabled mouse cursor drivers */
 void mouse_cursor_init(void)
 {
-#if IS_ENABLED(CONFIG_LP_PC_MOUSE)
+#if CONFIG(LP_PC_MOUSE)
 	i8042_mouse_init();
 #endif
 }

diff --git a/payloads/libpayload/drivers/nvram.c b/payloads/libpayload/drivers/nvram.c
@@ -60,7 +60,7 @@
  * doesn't try to do this on its own.
  */
 #define RTC_PORT_STANDARD      0x70
-#if IS_ENABLED(CONFIG_LP_RTC_PORT_EXTENDED_VIA)
+#if CONFIG(LP_RTC_PORT_EXTENDED_VIA)
 #define RTC_PORT_EXTENDED      0x74
 #else
 #define RTC_PORT_EXTENDED      0x72

diff --git a/payloads/libpayload/drivers/serial/8250.c b/payloads/libpayload/drivers/serial/8250.c
@@ -41,7 +41,7 @@ static uint8_t serial_read_reg(int offset)
 {
 	offset *= lib_sysinfo.serial->regwidth;
 
-#if IS_ENABLED(CONFIG_LP_IO_ADDRESS_SPACE)
+#if CONFIG(LP_IO_ADDRESS_SPACE)
 	if (!serial_is_mem_mapped)
 		return inb(IOBASE + offset);
 	else
@@ -56,7 +56,7 @@ static void serial_write_reg(uint8_t val, int offset)
 {
 	offset *= lib_sysinfo.serial->regwidth;
 
-#if IS_ENABLED(CONFIG_LP_IO_ADDRESS_SPACE)
+#if CONFIG(LP_IO_ADDRESS_SPACE)
 	if (!serial_is_mem_mapped)
 		outb(val, IOBASE + offset);
 	else
@@ -67,13 +67,13 @@ static void serial_write_reg(uint8_t val, int offset)
 			writeb(val, MEMBASE + offset);
 }
 
-#if IS_ENABLED(CONFIG_LP_SERIAL_SET_SPEED)
+#if CONFIG(LP_SERIAL_SET_SPEED)
 static void serial_hardware_init(int speed, int word_bits,
 				 int parity, int stop_bits)
 {
 	unsigned char reg;
 
-#if !IS_ENABLED(CONFIG_LP_PL011_SERIAL_CONSOLE)
+#if !CONFIG(LP_PL011_SERIAL_CONSOLE)
 	/* Disable interrupts. */
 	serial_write_reg(0, 0x01);
 
@@ -114,7 +114,7 @@ void serial_init(void)
 		(lib_sysinfo.serial->type == CB_SERIAL_TYPE_MEMORY_MAPPED);
 
 	if (!serial_is_mem_mapped) {
-#if IS_ENABLED(CONFIG_LP_IO_ADDRESS_SPACE)
+#if CONFIG(LP_IO_ADDRESS_SPACE)
 		if ((inb(IOBASE + 0x05) == 0xFF) &&
 				(inb(IOBASE + 0x06) == 0xFF)) {
 			printf("IO space mapped serial not present.");
@@ -126,7 +126,7 @@ void serial_init(void)
 #endif
 	}
 
-#if IS_ENABLED(CONFIG_LP_SERIAL_SET_SPEED)
+#if CONFIG(LP_SERIAL_SET_SPEED)
 	serial_hardware_init(CONFIG_LP_SERIAL_BAUD_RATE, 8, 0, 1);
 #endif
 }
@@ -147,7 +147,7 @@ void serial_putchar(unsigned int c)
 {
 	if (!serial_hardware_is_present)
 		return;
-#if !IS_ENABLED(CONFIG_LP_PL011_SERIAL_CONSOLE)
+#if !CONFIG(LP_PL011_SERIAL_CONSOLE)
 	while ((serial_read_reg(0x05) & 0x20) == 0) ;
 #endif
 	serial_write_reg(c, 0x00);

diff --git a/payloads/libpayload/drivers/storage/ahci.c b/payloads/libpayload/drivers/storage/ahci.c
@@ -153,15 +153,15 @@ static int ahci_dev_init(hba_ctrl_t *const ctrl,
 	switch (port->signature) {
 	case HBA_PxSIG_ATA:
 		printf("ahci: ATA drive on port #%d.\n", portnum);
-#if IS_ENABLED(CONFIG_LP_STORAGE_ATA)
+#if CONFIG(LP_STORAGE_ATA)
 		dev->ata_dev.identify = ahci_identify_device;
 		dev->ata_dev.read_sectors = ahci_ata_read_sectors;
 		return ata_attach_device(&dev->ata_dev, PORT_TYPE_SATA);
 #endif
 		break;
 	case HBA_PxSIG_ATAPI:
 		printf("ahci: ATAPI drive on port #%d.\n", portnum);
-#if IS_ENABLED(CONFIG_LP_STORAGE_ATAPI)
+#if CONFIG(LP_STORAGE_ATAPI)
 		dev->atapi_dev.identify = ahci_identify_device;
 		dev->atapi_dev.packet_read_cmd = ahci_packet_read_cmd;
 		return atapi_attach_device(&dev->atapi_dev, PORT_TYPE_SATA);
@@ -218,7 +218,7 @@ static void ahci_port_probe(hba_ctrl_t *const ctrl,
 	ahci_dev_init(ctrl, port, portnum);
 }
 
-#if IS_ENABLED(CONFIG_LP_STORAGE_AHCI_ONLY_TESTED)
+#if CONFIG(LP_STORAGE_AHCI_ONLY_TESTED)
 static u32 working_controllers[] = {
 	0x8086 | 0x2929 << 16, /* Mobile ICH9 */
 	0x8086 | 0x1c03 << 16, /* Mobile Cougar Point PCH */
@@ -236,7 +236,7 @@ static void ahci_init_pci(pcidev_t dev)
 	const u16 vendor = pci_read_config16(dev, 0x00);
 	const u16 device = pci_read_config16(dev, 0x02);
 
-#if IS_ENABLED(CONFIG_LP_STORAGE_AHCI_ONLY_TESTED)
+#if CONFIG(LP_STORAGE_AHCI_ONLY_TESTED)
 	const u32 vendor_device = pci_read_config32(dev, 0x0);
 	for (i = 0; i < ARRAY_SIZE(working_controllers); ++i)
 		if (vendor_device == working_controllers[i])

diff --git a/payloads/libpayload/drivers/storage/ahci_ata.c b/payloads/libpayload/drivers/storage/ahci_ata.c
@@ -56,7 +56,7 @@ ssize_t ahci_ata_read_sectors(ata_dev_t *const ata_dev,
 		       printf("ahci: Sector count too high (max. 256).\n");
 		       count = 256;
 		}
-#if IS_ENABLED(CONFIG_LP_STORAGE_64BIT_LBA)
+#if CONFIG(LP_STORAGE_64BIT_LBA)
 	} else if (ata_dev->read_cmd == ATA_READ_DMA_EXT) {
 		if (start >= (1ULL << 48)) {
 			printf("ahci: Sector is not 48-bit addressable.\n");
@@ -84,7 +84,7 @@ ssize_t ahci_ata_read_sectors(ata_dev_t *const ata_dev,
 	dev->cmdtable->fis[ 6] = (start >> 16) & 0xff;
 	dev->cmdtable->fis[ 7] = FIS_H2D_DEV_LBA;
 	dev->cmdtable->fis[ 8] = (start >> 24) & 0xff;
-#if IS_ENABLED(CONFIG_LP_STORAGE_64BIT_LBA)
+#if CONFIG(LP_STORAGE_64BIT_LBA)
 	if (ata_dev->read_cmd == ATA_READ_DMA_EXT) {
 		dev->cmdtable->fis[ 9] = (start >> 32) & 0xff;
 		dev->cmdtable->fis[10] = (start >> 40) & 0xff;

diff --git a/payloads/libpayload/drivers/storage/ata.c b/payloads/libpayload/drivers/storage/ata.c
@@ -212,7 +212,7 @@ int ata_attach_device(ata_dev_t *const dev, const storage_port_t port_type)
 	ata_strncpy(model, id + 27, sizeof(model));
 	printf("ata: Identified %s [%s]\n", model, fw);
 
-#if IS_ENABLED(CONFIG_LP_STORAGE_64BIT_LBA)
+#if CONFIG(LP_STORAGE_64BIT_LBA)
 	if (id[ATA_CMDS_AND_FEATURE_SETS + 1] & (1 << 10)) {
 		printf("ata: Support for LBA-48 enabled.\n");
 		dev->read_cmd = ATA_READ_DMA_EXT;

diff --git a/payloads/libpayload/drivers/storage/storage.c b/payloads/libpayload/drivers/storage/storage.c
@@ -28,7 +28,7 @@
  */
 
 #include <libpayload.h>
-#if IS_ENABLED(CONFIG_LP_STORAGE_AHCI)
+#if CONFIG(LP_STORAGE_AHCI)
 # include <storage/ahci.h>
 #endif
 #include <storage/storage.h>
@@ -110,7 +110,7 @@ ssize_t storage_read_blocks512(const size_t dev_num,
  */
 void storage_initialize(void)
 {
-#if IS_ENABLED(CONFIG_LP_STORAGE_AHCI)
+#if CONFIG(LP_STORAGE_AHCI)
 	ahci_initialize();
 #endif
 }
diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c
@@ -850,7 +850,7 @@ ehci_init (unsigned long physical_bar)
 	return controller;
 }
 
-#if IS_ENABLED(CONFIG_LP_USB_PCI)
+#if CONFIG(LP_USB_PCI)
 hci_t *
 ehci_pci_init (pcidev_t addr)
 {

diff --git a/payloads/libpayload/drivers/usb/ehci_rh.c b/payloads/libpayload/drivers/usb/ehci_rh.c
@@ -102,7 +102,7 @@ ehci_rh_scanport (usbdev_t *dev, int port)
 	/* device connected, handle */
 	if (RH_INST(dev)->ports[port] & P_CURR_CONN_STATUS) {
 		mdelay(100); // usb20 spec 9.1.2
-		if (!IS_ENABLED(CONFIG_LP_USB_EHCI_HOSTPC_ROOT_HUB_TT) &&
+		if (!CONFIG(LP_USB_EHCI_HOSTPC_ROOT_HUB_TT) &&
 				(RH_INST(dev)->ports[port] & P_LINE_STATUS) ==
 				P_LINE_STATUS_LOWSPEED) {
 			ehci_rh_hand_over_port(dev, port);
@@ -138,7 +138,7 @@ ehci_rh_scanport (usbdev_t *dev, int port)
 			ehci_rh_hand_over_port(dev, port);
 			return;
 		}
-		if (IS_ENABLED(CONFIG_LP_USB_EHCI_HOSTPC_ROOT_HUB_TT)) {
+		if (CONFIG(LP_USB_EHCI_HOSTPC_ROOT_HUB_TT)) {
 			port_speed = (usb_speed)
 				((EHCI_INST(dev->controller)->operation->hostpc
 				>> 25) & 0x03);

diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c
@@ -247,7 +247,7 @@ ohci_init (unsigned long physical_bar)
 	return controller;
 }
 
-#if IS_ENABLED(CONFIG_LP_USB_PCI)
+#if CONFIG(LP_USB_PCI)
 hci_t *
 ohci_pci_init (pcidev_t addr)
 {

diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c
@@ -563,7 +563,7 @@ set_address (hci_t *controller, usb_speed speed, int hubport, int hubaddr)
 		break;
 	case hid_device:
 		usb_debug ("HID\n");
-#if IS_ENABLED(CONFIG_LP_USB_HID)
+#if CONFIG(LP_USB_HID)
 		dev->init = usb_hid_init;
 		return dev->address;
 #else
@@ -581,7 +581,7 @@ set_address (hci_t *controller, usb_speed speed, int hubport, int hubaddr)
 		break;
 	case msc_device:
 		usb_debug ("MSC\n");
-#if IS_ENABLED(CONFIG_LP_USB_MSC)
+#if CONFIG(LP_USB_MSC)
 		dev->init = usb_msc_init;
 		return dev->address;
 #else
@@ -590,7 +590,7 @@ set_address (hci_t *controller, usb_speed speed, int hubport, int hubaddr)
 		break;
 	case hub_device:
 		usb_debug ("hub\n");
-#if IS_ENABLED(CONFIG_LP_USB_HUB)
+#if CONFIG(LP_USB_HUB)
 		dev->init = usb_hub_init;
 		return dev->address;
 #else

diff --git a/payloads/libpayload/drivers/usb/usbhid.c b/payloads/libpayload/drivers/usb/usbhid.c
@@ -142,7 +142,7 @@ struct layout_maps {
 static const struct layout_maps *map;
 
 static const struct layout_maps keyboard_layouts[] = {
-// #if IS_ENABLED(CONFIG_LP_PC_KEYBOARD_LAYOUT_US)
+// #if CONFIG(LP_PC_KEYBOARD_LAYOUT_US)
 { .country = "us", .map = {
 	{ /* No modifier */
 	-1, -1, -1, -1, 'a', 'b', 'c', 'd',

diff --git a/payloads/libpayload/drivers/usb/usbinit.c b/payloads/libpayload/drivers/usb/usbinit.c
@@ -37,7 +37,7 @@
 #include "dwc2.h"
 #include <usb/usbdisk.h>
 
-#if IS_ENABLED(CONFIG_LP_USB_PCI)
+#if CONFIG(LP_USB_PCI)
 /**
  * Initializes USB controller attached to PCI
  *
@@ -72,7 +72,7 @@ static int usb_controller_initialize(int bus, int dev, int func)
 			pciid >> 16, pciid & 0xFFFF, func);
 		switch (prog_if) {
 		case 0x00:
-#if IS_ENABLED(CONFIG_LP_USB_UHCI)
+#if CONFIG(LP_USB_UHCI)
 			usb_debug("UHCI controller\n");
 			uhci_pci_init (pci_device);
 #else
@@ -81,7 +81,7 @@ static int usb_controller_initialize(int bus, int dev, int func)
 			break;
 
 		case 0x10:
-#if IS_ENABLED(CONFIG_LP_USB_OHCI)
+#if CONFIG(LP_USB_OHCI)
 			usb_debug("OHCI controller\n");
 			ohci_pci_init(pci_device);
 #else
@@ -90,7 +90,7 @@ static int usb_controller_initialize(int bus, int dev, int func)
 			break;
 
 		case 0x20:
-#if IS_ENABLED(CONFIG_LP_USB_EHCI)
+#if CONFIG(LP_USB_EHCI)
 			usb_debug("EHCI controller\n");
 			ehci_pci_init(pci_device);
 #else
@@ -99,7 +99,7 @@ static int usb_controller_initialize(int bus, int dev, int func)
 			break;
 
 		case 0x30:
-#if IS_ENABLED(CONFIG_LP_USB_XHCI)
+#if CONFIG(LP_USB_XHCI)
 			usb_debug("xHCI controller\n");
 			xhci_pci_init(pci_device);
 #else
@@ -166,7 +166,7 @@ static void usb_scan_pci_bus(int bus)
  */
 int usb_initialize(void)
 {
-#if IS_ENABLED(CONFIG_LP_USB_PCI)
+#if CONFIG(LP_USB_PCI)
 	usb_scan_pci_bus(0);
 #endif
 	return 0;
@@ -175,19 +175,19 @@ int usb_initialize(void)
 hci_t *usb_add_mmio_hc(hc_type type, void *bar)
 {
 	switch (type) {
-#if IS_ENABLED(CONFIG_LP_USB_OHCI)
+#if CONFIG(LP_USB_OHCI)
 	case OHCI:
 		return ohci_init((unsigned long)bar);
 #endif
-#if IS_ENABLED(CONFIG_LP_USB_EHCI)
+#if CONFIG(LP_USB_EHCI)
 	case EHCI:
 		return ehci_init((unsigned long)bar);
 #endif
-#if IS_ENABLED(CONFIG_LP_USB_DWC2)
+#if CONFIG(LP_USB_DWC2)
 	case DWC2:
 		return dwc2_init(bar);
 #endif
-#if IS_ENABLED(CONFIG_LP_USB_XHCI)
+#if CONFIG(LP_USB_XHCI)
 	case XHCI:
 		return xhci_init((unsigned long)bar);
 #endif

diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c
@@ -88,7 +88,7 @@ xhci_init_cycle_ring(transfer_ring_t *const tr, const size_t ring_size)
 }
 
 /* On Panther Point: switch ports shared with EHCI to xHCI */
-#if IS_ENABLED(CONFIG_LP_USB_PCI)
+#if CONFIG(LP_USB_PCI)
 static void
 xhci_switch_ppt_ports(pcidev_t addr)
 {
@@ -112,7 +112,7 @@ xhci_switch_ppt_ports(pcidev_t addr)
 }
 #endif
 
-#if IS_ENABLED(CONFIG_LP_USB_PCI)
+#if CONFIG(LP_USB_PCI)
 /* On Panther Point: switch all ports back to EHCI */
 static void
 xhci_switchback_ppt_ports(pcidev_t addr)
@@ -297,7 +297,7 @@ xhci_init (unsigned long physical_bar)
 	return NULL;
 }
 
-#if IS_ENABLED(CONFIG_LP_USB_PCI)
+#if CONFIG(LP_USB_PCI)
 hci_t *
 xhci_pci_init (pcidev_t addr)
 {
@@ -336,7 +336,7 @@ xhci_reset(hci_t *const controller)
 	 * Without this delay, the subsequent HC register access,
 	 * may result in a system hang very rarely.
 	 */
-	if (IS_ENABLED(CONFIG_LP_ARCH_X86))
+	if (CONFIG(LP_ARCH_X86))
 		mdelay(1);
 
 	xhci_debug("Resetting controller... ");
@@ -426,7 +426,7 @@ xhci_shutdown(hci_t *const controller)
 	xhci_t *const xhci = XHCI_INST(controller);
 	xhci_stop(controller);
 
-#if IS_ENABLED(CONFIG_LP_USB_PCI)
+#if CONFIG(LP_USB_PCI)
         if (controller->pcidev)
 		xhci_switchback_ppt_ports(controller->pcidev);
 #endif
@@ -563,7 +563,7 @@ xhci_enqueue_td(transfer_ring_t *const tr, const int ep, const size_t mps,
 			cur_length = length;
 			packets = 0;
 			length = 0;
-		} else if (!IS_ENABLED(CONFIG_LP_USB_XHCI_MTK_QUIRK)) {
+		} else if (!CONFIG(LP_USB_XHCI_MTK_QUIRK)) {
 			packets -= (residue + cur_length) / mps;
 			residue = (residue + cur_length) % mps;
 			length -= cur_length;
@@ -576,7 +576,7 @@ xhci_enqueue_td(transfer_ring_t *const tr, const int ep, const size_t mps,
 		TRB_SET(TDS, trb, MIN(TRB_MAX_TD_SIZE, packets));
 		TRB_SET(CH, trb, 1);
 
-		if (length && IS_ENABLED(CONFIG_LP_USB_XHCI_MTK_QUIRK)) {
+		if (length && CONFIG(LP_USB_XHCI_MTK_QUIRK)) {
 			/*
 			 * For MTK's xHCI controller, TDS defines a number of
 			 * packets that remain to be transferred for a TD after

diff --git a/payloads/libpayload/drivers/usb/xhci_devconf.c b/payloads/libpayload/drivers/usb/xhci_devconf.c
@@ -353,7 +353,7 @@ xhci_finish_ep_config(const endpoint_t *const ep, inputctx_t *const ic)
 	EC_SET(AVRTRB,	epctx, avrtrb);
 	EC_SET(MXESIT,  epctx, EC_GET(MPS, epctx) * EC_GET(MBS, epctx));
 
-	if (IS_ENABLED(CONFIG_LP_USB_XHCI_MTK_QUIRK)) {
+	if (CONFIG(LP_USB_XHCI_MTK_QUIRK)) {
 		/* The MTK xHCI defines some extra SW parameters which are
 		 * put into reserved DWs in Slot and Endpoint Contexts for
 		 * synchronous endpoints. But for non-isochronous transfers,

diff --git a/payloads/libpayload/drivers/usb/xhci_rh.c b/payloads/libpayload/drivers/usb/xhci_rh.c
@@ -122,7 +122,7 @@ xhci_rh_reset_port(usbdev_t *const dev, const int port)
 static int
 xhci_rh_enable_port(usbdev_t *const dev, int port)
 {
-	if (IS_ENABLED(CONFIG_LP_USB_XHCI_MTK_QUIRK)) {
+	if (CONFIG(LP_USB_XHCI_MTK_QUIRK)) {
 		xhci_t *const xhci = XHCI_INST(dev->controller);
 		volatile u32 *const portsc =
 			&xhci->opreg->prs[port - 1].portsc;

diff --git a/payloads/libpayload/drivers/video/video.c b/payloads/libpayload/drivers/video/video.c
@@ -31,27 +31,27 @@
 #include <libpayload.h>
 #include <video_console.h>
 
-#if IS_ENABLED(CONFIG_LP_GEODELX_VIDEO_CONSOLE)
+#if CONFIG(LP_GEODELX_VIDEO_CONSOLE)
 extern struct video_console geodelx_video_console;
 #endif
 
-#if IS_ENABLED(CONFIG_LP_COREBOOT_VIDEO_CONSOLE)
+#if CONFIG(LP_COREBOOT_VIDEO_CONSOLE)
 extern struct video_console coreboot_video_console;
 #endif
 
-#if IS_ENABLED(CONFIG_LP_VGA_VIDEO_CONSOLE)
+#if CONFIG(LP_VGA_VIDEO_CONSOLE)
 extern struct video_console vga_video_console;
 #endif
 
 static struct video_console *console_list[] =
 {
-#if IS_ENABLED(CONFIG_LP_GEODELX_VIDEO_CONSOLE)
+#if CONFIG(LP_GEODELX_VIDEO_CONSOLE)
 	&geodelx_video_console,
 #endif
-#if IS_ENABLED(CONFIG_LP_COREBOOT_VIDEO_CONSOLE)
+#if CONFIG(LP_COREBOOT_VIDEO_CONSOLE)
 	&coreboot_video_console,
 #endif
-#if IS_ENABLED(CONFIG_LP_VGA_VIDEO_CONSOLE)
+#if CONFIG(LP_VGA_VIDEO_CONSOLE)
 	&vga_video_console,
 #endif
 };

diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
@@ -202,6 +202,7 @@ struct cb_gpios {
 
 #define CB_TAG_VBNV		0x0019
 #define CB_TAG_VBOOT_HANDOFF	0x0020
+#define CB_TAG_VBOOT_WORKBUF	0x0034
 #define CB_TAG_DMA		0x0022
 #define CB_TAG_RAM_OOPS		0x0023
 #define CB_TAG_MTC		0x002b

diff --git a/payloads/libpayload/include/endian.h b/payloads/libpayload/include/endian.h
@@ -53,7 +53,7 @@ static inline uint64_t swap_bytes64(uint64_t in)
 
 /* Endian functions from glibc 2.9 / BSD "endian.h" */
 
-#if IS_ENABLED(CONFIG_LP_BIG_ENDIAN)
+#if CONFIG(LP_BIG_ENDIAN)
 
 #define htobe16(in) (in)
 #define htobe32(in) (in)
@@ -63,7 +63,7 @@ static inline uint64_t swap_bytes64(uint64_t in)
 #define htole32(in) swap_bytes32(in)
 #define htole64(in) swap_bytes64(in)
 
-#elif IS_ENABLED(CONFIG_LP_LITTLE_ENDIAN)
+#elif CONFIG(LP_LITTLE_ENDIAN)
 
 #define htobe16(in) swap_bytes16(in)
 #define htobe32(in) swap_bytes32(in)

diff --git a/payloads/libpayload/include/kconfig.h b/payloads/libpayload/include/kconfig.h
@@ -17,5 +17,7 @@
 #define __config_enabled(arg1_or_junk) ___config_enabled(arg1_or_junk 1, 0, 0)
 #define ___config_enabled(__ignored, val, ...) val
 
-#define IS_ENABLED(option) config_enabled(option)
+#define IS_ENABLED(option) config_enabled(option)	/* deprecated */
+#define CONFIG(option) config_enabled(CONFIG_##option)
+
 #endif
diff --git a/payloads/libpayload/include/stdlib.h b/payloads/libpayload/include/stdlib.h
@@ -45,7 +45,7 @@
  * @defgroup malloc Memory allocation functions
  * @{
  */
-#if IS_ENABLED(CONFIG_LP_DEBUG_MALLOC) && !defined(IN_MALLOC_C)
+#if CONFIG(LP_DEBUG_MALLOC) && !defined(IN_MALLOC_C)
 #define free(p)	\
 	({ \
 	 extern void print_malloc_map(void); \
@@ -222,7 +222,7 @@ void gdb_exit(s8 exit_status);
 void halt(void) __attribute__((noreturn));
 void exit(int status) __attribute__((noreturn));
 #define abort() halt()    /**< Alias for the halt() function */
-#if IS_ENABLED(CONFIG_LP_REMOTEGDB)
+#if CONFIG(LP_REMOTEGDB)
 /* Override abort()/halt() to trap into GDB if it is enabled. */
 #define halt() do { gdb_enter(); halt(); } while (0)
 #endif

diff --git a/payloads/libpayload/include/storage/storage.h b/payloads/libpayload/include/storage/storage.h
@@ -34,7 +34,7 @@
 #include <unistd.h>
 
 
-#if !IS_ENABLED(CONFIG_LP_STORAGE_64BIT_LBA)
+#if !CONFIG(LP_STORAGE_64BIT_LBA)
 typedef u32 lba_t;
 #else
 typedef u64 lba_t;

diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
@@ -97,8 +97,10 @@ struct sysinfo_t {
 
 	void	*vboot_handoff;
 	u32	vboot_handoff_size;
+	void *vboot_workbuf;
+	uint32_t vboot_workbuf_size;
 
-#if IS_ENABLED(CONFIG_LP_ARCH_X86)
+#if CONFIG(LP_ARCH_X86)
 	int x86_rom_var_mtrr_index;
 #endif
 

diff --git a/payloads/libpayload/libc/64bit_div.c b/payloads/libpayload/libc/64bit_div.c
@@ -30,7 +30,7 @@
 #include <libpayload-config.h>
 #include <stdlib.h>
 
-#if !IS_ENABLED(CONFIG_LP_LITTLE_ENDIAN)
+#if !CONFIG(LP_LITTLE_ENDIAN)
 #error this code is for little endian only
 #endif
 

diff --git a/payloads/libpayload/libc/console.c b/payloads/libpayload/libc/console.c
@@ -102,16 +102,16 @@ int console_remove_output_driver(void *function)
 
 void console_init(void)
 {
-#if IS_ENABLED(CONFIG_LP_VIDEO_CONSOLE)
+#if CONFIG(LP_VIDEO_CONSOLE)
 	video_console_init();
 #endif
-#if IS_ENABLED(CONFIG_LP_SERIAL_CONSOLE)
+#if CONFIG(LP_SERIAL_CONSOLE)
 	serial_console_init();
 #endif
-#if IS_ENABLED(CONFIG_LP_PC_KEYBOARD)
+#if CONFIG(LP_PC_KEYBOARD)
 	keyboard_init();
 #endif
-#if IS_ENABLED(CONFIG_LP_CBMEM_CONSOLE)
+#if CONFIG(LP_CBMEM_CONSOLE)
 	cbmem_console_init();
 #endif
 }
@@ -147,7 +147,7 @@ int puts(const char *s)
 
 int havekey(void)
 {
-#if IS_ENABLED(CONFIG_LP_USB)
+#if CONFIG(LP_USB)
 	usb_poll();
 #endif
 	struct console_input_driver *in;
@@ -164,7 +164,7 @@ int havekey(void)
 int getchar(void)
 {
 	while (1) {
-#if IS_ENABLED(CONFIG_LP_USB)
+#if CONFIG(LP_USB)
 		usb_poll();
 #endif
 		struct console_input_driver *in;

diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c
@@ -56,7 +56,7 @@ static void cb_parse_memory(void *ptr, struct sysinfo_t *info)
 	for (i = 0; i < count; i++) {
 		struct cb_memory_range *range = MEM_RANGE_PTR(mem, i);
 
-#if IS_ENABLED(CONFIG_LP_MEMMAP_RAM_ONLY)
+#if CONFIG(LP_MEMMAP_RAM_ONLY)
 		if (range->type != CB_MEM_RAM)
 			continue;
 #endif
@@ -86,6 +86,14 @@ static void cb_parse_vboot_handoff(unsigned char *ptr, struct sysinfo_t *info)
 	info->vboot_handoff_size = vbho->range_size;
 }
 
+static void cb_parse_vboot_workbuf(unsigned char *ptr, struct sysinfo_t *info)
+{
+	struct lb_range *vbwb = (struct lb_range *)ptr;
+
+	info->vboot_workbuf = (void *)(uintptr_t)vbwb->range_start;
+	info->vboot_workbuf_size = vbwb->range_size;
+}
+
 static void cb_parse_vbnv(unsigned char *ptr, struct sysinfo_t *info)
 {
 	struct lb_range *vbnv = (struct lb_range *)ptr;
@@ -155,7 +163,7 @@ static void cb_parse_sku_id(unsigned char *ptr, struct sysinfo_t *info)
 	info->sku_id = sku_id->id_code;
 }
 
-#if IS_ENABLED(CONFIG_LP_NVRAM)
+#if CONFIG(LP_NVRAM)
 static void cb_parse_optiontable(void *ptr, struct sysinfo_t *info)
 {
 	/* ptr points to a coreboot table entry and is already virtual */
@@ -171,7 +179,7 @@ static void cb_parse_checksum(void *ptr, struct sysinfo_t *info)
 }
 #endif
 
-#if IS_ENABLED(CONFIG_LP_COREBOOT_VIDEO_CONSOLE)
+#if CONFIG(LP_COREBOOT_VIDEO_CONSOLE)
 static void cb_parse_framebuffer(void *ptr, struct sysinfo_t *info)
 {
 	/* ptr points to a coreboot table entry and is already virtual */
@@ -232,7 +240,7 @@ static void cb_parse_vpd(void *ptr, struct sysinfo_t *info)
 	info->chromeos_vpd = phys_to_virt(cbmem->cbmem_tab);
 }
 
-#if IS_ENABLED(CONFIG_LP_TIMER_RDTSC)
+#if CONFIG(LP_TIMER_RDTSC)
 static void cb_parse_tsc_info(void *ptr, struct sysinfo_t *info)
 {
 	const struct cb_tsc_info *tsc_info = ptr;
@@ -328,15 +336,15 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 		case CB_TAG_ASSEMBLER:
 			cb_parse_string(ptr, &info->assembler);
 			break;
-#if IS_ENABLED(CONFIG_LP_NVRAM)
+#if CONFIG(LP_NVRAM)
 		case CB_TAG_CMOS_OPTION_TABLE:
 			cb_parse_optiontable(ptr, info);
 			break;
 		case CB_TAG_OPTION_CHECKSUM:
 			cb_parse_checksum(ptr, info);
 			break;
 #endif
-#if IS_ENABLED(CONFIG_LP_COREBOOT_VIDEO_CONSOLE)
+#if CONFIG(LP_COREBOOT_VIDEO_CONSOLE)
 		// FIXME we should warn on serial if coreboot set up a
 		// framebuffer buf the payload does not know about it.
 		case CB_TAG_FRAMEBUFFER:
@@ -355,6 +363,9 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 		case CB_TAG_VBOOT_HANDOFF:
 			cb_parse_vboot_handoff(ptr, info);
 			break;
+		case CB_TAG_VBOOT_WORKBUF:
+			cb_parse_vboot_workbuf(ptr, info);
+			break;
 		case CB_TAG_MAC_ADDRS:
 			cb_parse_mac_addresses(ptr, info);
 			break;
@@ -394,7 +405,7 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
 		case CB_TAG_BOOT_MEDIA_PARAMS:
 			cb_parse_boot_media_params(ptr, info);
 			break;
-#if IS_ENABLED(CONFIG_LP_TIMER_RDTSC)
+#if CONFIG(LP_TIMER_RDTSC)
 		case CB_TAG_TSC_INFO:
 			cb_parse_tsc_info(ptr, info);
 			break;

diff --git a/payloads/libpayload/libc/exec.c b/payloads/libpayload/libc/exec.c
@@ -30,7 +30,7 @@
 #include <libpayload-config.h>
 #include <libpayload.h>
 
-#if IS_ENABLED(CONFIG_LP_ARCH_X86)
+#if CONFIG(LP_ARCH_X86)
 extern void i386_do_exec(long addr, int argc, char **argv, int *ret);
 #endif
 
@@ -46,7 +46,7 @@ int exec(long addr, int argc, char **argv)
 {
 	int val = -1;
 
-#if IS_ENABLED(CONFIG_LP_ARCH_X86)
+#if CONFIG(LP_ARCH_X86)
 	i386_do_exec(addr, argc, argv, &val);
 #endif
 	return val;

diff --git a/payloads/libpayload/libc/malloc.c b/payloads/libpayload/libc/malloc.c
@@ -47,7 +47,7 @@ struct memory_type {
 	void *start;
 	void *end;
 	struct align_region_t* align_regions;
-#if IS_ENABLED(CONFIG_LP_DEBUG_MALLOC)
+#if CONFIG(LP_DEBUG_MALLOC)
 	int magic_initialized;
 	size_t minimal_free;
 	const char *name;
@@ -58,7 +58,7 @@ extern char _heap, _eheap;	/* Defined in the ldscript. */
 
 static struct memory_type default_type =
 	{ (void *)&_heap, (void *)&_eheap, NULL
-#if IS_ENABLED(CONFIG_LP_DEBUG_MALLOC)
+#if CONFIG(LP_DEBUG_MALLOC)
 	, 0, 0, "HEAP"
 #endif
 	};
@@ -104,7 +104,7 @@ void init_dma_memory(void *start, u32 size)
 	dma->end = start + size;
 	dma->align_regions = NULL;
 
-#if IS_ENABLED(CONFIG_LP_DEBUG_MALLOC)
+#if CONFIG(LP_DEBUG_MALLOC)
 	dma->minimal_free = 0;
 	dma->magic_initialized = 0;
 	dma->name = "DMA";
@@ -139,7 +139,7 @@ static void *alloc(int len, struct memory_type *type)
 	if (!HAS_MAGIC(*ptr)) {
 		size_t size = (type->end - type->start) - HDRSIZE;
 		*ptr = FREE_BLOCK(size);
-#if IS_ENABLED(CONFIG_LP_DEBUG_MALLOC)
+#if CONFIG(LP_DEBUG_MALLOC)
 		type->magic_initialized = 1;
 		type->minimal_free = size;
 #endif
@@ -356,7 +356,7 @@ static struct align_region_t *allocate_region(int alignment, int num_elements,
 	struct align_region_t *r;
 	size_t extra_space;
 
-#if IS_ENABLED(CONFIG_LP_DEBUG_MALLOC)
+#if CONFIG(LP_DEBUG_MALLOC)
 	printf("%s(old align_regions=%p, alignment=%u, num_elements=%u, size=%zu)\n",
 		__func__, type->align_regions, alignment, num_elements, size);
 #endif
@@ -479,7 +479,7 @@ static void *alloc_aligned(size_t align, size_t size, struct memory_type *type)
 	{
 		if ((reg->alignment == align) && (reg->free >= (size + align - 1)/align))
 		{
-#if IS_ENABLED(CONFIG_LP_DEBUG_MALLOC)
+#if CONFIG(LP_DEBUG_MALLOC)
 			printf("  found memalign region. %x free, %x required\n", reg->free, (size + align - 1)/align);
 #endif
 			break;
@@ -488,12 +488,12 @@ static void *alloc_aligned(size_t align, size_t size, struct memory_type *type)
 	}
 	if (reg == 0)
 	{
-#if IS_ENABLED(CONFIG_LP_DEBUG_MALLOC)
+#if CONFIG(LP_DEBUG_MALLOC)
 		printf("  need to allocate a new memalign region\n");
 #endif
 		/* get align regions */
 		reg = allocate_region(align, large_request/align, size, type);
-#if IS_ENABLED(CONFIG_LP_DEBUG_MALLOC)
+#if CONFIG(LP_DEBUG_MALLOC)
 		printf("  ... returned %p\n", reg);
 #endif
 	}
@@ -539,7 +539,7 @@ void *dma_memalign(size_t align, size_t size)
 }
 
 /* This is for debugging purposes. */
-#if IS_ENABLED(CONFIG_LP_DEBUG_MALLOC)
+#if CONFIG(LP_DEBUG_MALLOC)
 void print_malloc_map(void)
 {
 	struct memory_type *type = heap;

diff --git a/payloads/libpayload/libc/string.c b/payloads/libpayload/libc/string.c
@@ -517,16 +517,11 @@ unsigned long long int strtoull(const char *ptr, char **endptr, int base)
 	/* Base 16 allows the 0x on front - so skip over it */
 
 	if (base == 16) {
-		if (ptr[0] == '0' && (ptr[1] == 'x' || ptr[1] == 'X'))
+		if (ptr[0] == '0' && (ptr[1] == 'x' || ptr[1] == 'X') &&
+		    _valid(ptr[2], base))
 			ptr += 2;
 	}
 
-	/* If the first character isn't valid, then don't
-	 * bother */
-
-	if (!*ptr || !_valid(*ptr, base))
-		return 0;
-
 	for( ; *ptr && _valid(*ptr, base); ptr++)
 		ret = (ret * base) + _offset(*ptr, base);
 

diff --git a/payloads/libpayload/libc/time.c b/payloads/libpayload/libc/time.c
@@ -34,7 +34,7 @@
 
 #include <libpayload-config.h>
 #include <libpayload.h>
-#if IS_ENABLED(CONFIG_LP_ARCH_X86) && IS_ENABLED(CONFIG_LP_NVRAM)
+#if CONFIG(LP_ARCH_X86) && CONFIG(LP_NVRAM)
 #include <arch/rdtsc.h>
 #endif
 
@@ -70,7 +70,7 @@ static void update_clock(void)
 	}
 }
 
-#if IS_ENABLED(CONFIG_LP_NVRAM)
+#if CONFIG(LP_NVRAM)
 
 static unsigned int day_of_year(int mon, int day, int year)
 {

diff --git a/payloads/libpayload/libcbfs/cbfs.c b/payloads/libpayload/libcbfs/cbfs.c
@@ -31,11 +31,11 @@
 
 #ifdef LIBPAYLOAD
 # include <libpayload-config.h>
-# if IS_ENABLED(CONFIG_LP_LZMA)
+# if CONFIG(LP_LZMA)
 #  include <lzma.h>
 #  define CBFS_CORE_WITH_LZMA
 # endif
-# if IS_ENABLED(CONFIG_LP_LZ4)
+# if CONFIG(LP_LZ4)
 #  include <lz4.h>
 #  define CBFS_CORE_WITH_LZ4
 # endif

diff --git a/payloads/libpayload/libcbfs/cbfs_core.c b/payloads/libpayload/libcbfs/cbfs_core.c
@@ -119,7 +119,7 @@ static int get_cbfs_range(uint32_t *offset, uint32_t *cbfs_end,
 	// Logical offset (for source media) of first file.
 	*offset = ntohl(header->offset);
 	*cbfs_end = ntohl(header->romsize);
-#if IS_ENABLED(CONFIG_LP_ARCH_X86)
+#if CONFIG(LP_ARCH_X86)
 	// resolve actual length of ROM used for CBFS components
 	// the bootblock size was not taken into account
 	*cbfs_end -= ntohl(header->bootblocksize);

diff --git a/payloads/nvramcui/nvramcui.c b/payloads/nvramcui/nvramcui.c
@@ -176,7 +176,7 @@ int main(void)
 	int ch, done;
 	int i;
 
-	if (IS_ENABLED(CONFIG_LP_USB))
+	if (CONFIG(LP_USB))
 		usb_initialize();
 
 	/* coreboot data structures */

diff --git a/src/Kconfig b/src/Kconfig
@@ -631,33 +631,33 @@ config SMBIOS_PROVIDED_BY_MOBO
 	default n
 
 config MAINBOARD_SERIAL_NUMBER
-	string "SMBIOS Serial Number"
+	prompt "SMBIOS Serial Number" if !SMBIOS_PROVIDED_BY_MOBO
+	string
 	depends on GENERATE_SMBIOS_TABLES
-	depends on !SMBIOS_PROVIDED_BY_MOBO
 	default "123456789"
 	help
 	  The Serial Number to store in SMBIOS structures.
 
 config MAINBOARD_VERSION
-	string "SMBIOS Version Number"
+	prompt "SMBIOS Version Number" if !SMBIOS_PROVIDED_BY_MOBO
+	string
 	depends on GENERATE_SMBIOS_TABLES
-	depends on !SMBIOS_PROVIDED_BY_MOBO
 	default "1.0"
 	help
 	  The Version Number to store in SMBIOS structures.
 
 config MAINBOARD_SMBIOS_MANUFACTURER
-	string "SMBIOS Manufacturer"
+	prompt "SMBIOS Manufacturer" if !SMBIOS_PROVIDED_BY_MOBO
+	string
 	depends on GENERATE_SMBIOS_TABLES
-	depends on !SMBIOS_PROVIDED_BY_MOBO
 	default MAINBOARD_VENDOR
 	help
 	  Override the default Manufacturer stored in SMBIOS structures.
 
 config MAINBOARD_SMBIOS_PRODUCT_NAME
-	string "SMBIOS Product name"
+	prompt "SMBIOS Product name" if !SMBIOS_PROVIDED_BY_MOBO
+	string
 	depends on GENERATE_SMBIOS_TABLES
-	depends on !SMBIOS_PROVIDED_BY_MOBO
 	default MAINBOARD_PART_NUMBER
 	help
 	  Override the default Product name stored in SMBIOS structures.

diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c
@@ -37,7 +37,7 @@
 
 #include <arch/cache.h>
 
-#if IS_ENABLED(CONFIG_ARM_LPAE)
+#if CONFIG(ARM_LPAE)
 /* See B3.6.2 of ARMv7 Architecture Reference Manual */
 /* TODO: Utilize the contiguous hint flag */
 #define ATTR_BLOCK (\
@@ -170,7 +170,7 @@ static pte_t *mmu_create_subtable(pte_t *pgd_entry)
 	/* Initialize the new subtable with entries of the same attributes
 	 * (XN bit moves from 4 to 0, set PAGE unless block was unmapped). */
 	pte_t attr = *pgd_entry & ~(BLOCK_MASK);
-	if (!IS_ENABLED(CONFIG_ARM_LPAE) && (attr & (1 << 4)))
+	if (!CONFIG(ARM_LPAE) && (attr & (1 << 4)))
 		attr = ((attr & ~(1 << 4)) | (1 << 0));
 	if (attr & ATTR_BLOCK)
 		attr = (attr & ~ATTR_BLOCK) | ATTR_PAGE;
@@ -208,7 +208,7 @@ void mmu_config_range_kb(u32 start_kb, u32 size_kb, enum dcache_policy policy)
 
 	/* Always _one_ _damn_ bit that won't fit... (XN moves from 4 to 0) */
 	pte_t attr = attrs[policy].value;
-	if (!IS_ENABLED(CONFIG_ARM_LPAE) && (attr & (1 << 4)))
+	if (!CONFIG(ARM_LPAE) && (attr & (1 << 4)))
 		attr = ((attr & ~(1 << 4)) | (1 << 0));
 
 	/* Mask away high address bits that are handled by upper level table. */
@@ -277,7 +277,7 @@ void mmu_init(void)
 	for (; (pte_t *)_ettb_subtables - table > 0; table += SUBTABLE_PTES)
 		table[0] = ATTR_UNUSED;
 
-	if (CONFIG_ARM_LPAE) {
+	if (CONFIG(ARM_LPAE)) {
 		pte_t *const pgd_buff = (pte_t *)(_ttb + 16*KiB);
 		pte_t *pmd = ttb_buff;
 		int i;
@@ -331,7 +331,7 @@ void mmu_init(void)
 	 * See B3.5.4 and B3.6.4 for how TTBR0 or TTBR1 is selected.
 	 */
 	write_ttbcr(
-		CONFIG_ARM_LPAE << 31 |	/* EAE. 1:Enable LPAE */
+		CONFIG(ARM_LPAE) << 31 |/* EAE. 1:Enable LPAE */
 		0 << 16 | 0 << 0	/* Use TTBR0 for all addresses */
 		);
 

diff --git a/src/arch/arm/include/arch/memlayout.h b/src/arch/arm/include/arch/memlayout.h
@@ -18,16 +18,16 @@
 #ifndef __ARCH_MEMLAYOUT_H
 #define __ARCH_MEMLAYOUT_H
 
-#define SUPERPAGE_SIZE ((1 + IS_ENABLED(CONFIG_ARM_LPAE)) * 1M)
+#define SUPERPAGE_SIZE ((1 + CONFIG(ARM_LPAE)) * 1M)
 
 #define TTB(addr, size) \
 	REGION(ttb, addr, size, 16K) \
-	_ = ASSERT(size >= 16K + IS_ENABLED(CONFIG_ARM_LPAE) * 32, \
+	_ = ASSERT(size >= 16K + CONFIG(ARM_LPAE) * 32, \
 		"TTB must be 16K (+ 32 for LPAE)!");
 
 #define TTB_SUBTABLES(addr, size) \
-	REGION(ttb_subtables, addr, size, IS_ENABLED(CONFIG_ARM_LPAE)*3K + 1K) \
-	_ = ASSERT(size % (1K + 3K * IS_ENABLED(CONFIG_ARM_LPAE)) == 0, \
+	REGION(ttb_subtables, addr, size, CONFIG(ARM_LPAE)*3K + 1K) \
+	_ = ASSERT(size % (1K + 3K * CONFIG(ARM_LPAE)) == 0, \
 		"TTB subtable region must be evenly divisible by table size!");
 
 /* ARM stacks need 8-byte alignment and stay in one place through ramstage. */

diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h
@@ -134,7 +134,7 @@ static inline void write_mair0(uint32_t val)
 /* write translation table base register 0 (TTBR0) */
 static inline void write_ttbr0(uint32_t val)
 {
-	if (IS_ENABLED(CONFIG_ARM_LPAE))
+	if (CONFIG(ARM_LPAE))
 		asm volatile ("mcrr p15, 0, %[val], %[zero], c2" : :
 			[val] "r" (val), [zero] "r" (0));
 	else

diff --git a/src/arch/arm/tables.c b/src/arch/arm/tables.c
@@ -32,7 +32,7 @@ void bootmem_arch_add_ranges(void)
 	bootmem_add_range((uintptr_t)_ttb_subtables, REGION_SIZE(ttb_subtables),
 			  BM_MEM_RAMSTAGE);
 
-	if (!IS_ENABLED(CONFIG_COMMON_CBFS_SPI_WRAPPER))
+	if (!CONFIG(COMMON_CBFS_SPI_WRAPPER))
 		return;
 	bootmem_add_range((uintptr_t)_postram_cbfs_cache,
 			  REGION_SIZE(postram_cbfs_cache), BM_MEM_RAMSTAGE);

diff --git a/src/arch/arm64/arm_tf.c b/src/arch/arm64/arm_tf.c
@@ -56,7 +56,7 @@ void arm_tf_run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr)
 
 	SET_PARAM_HEAD(&bl31_params, PARAM_BL31, VERSION_1, 0);
 
-	if (IS_ENABLED(CONFIG_ARM64_USE_SECURE_OS)) {
+	if (CONFIG(ARM64_USE_SECURE_OS)) {
 		struct prog bl32 = PROG_INIT(PROG_BL32,
 					     CONFIG_CBFS_PREFIX"/secure_os");
 

diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c
@@ -220,7 +220,7 @@ void exception_init(void)
 	printk(BIOS_DEBUG, "ARM64: Exception handlers installed.\n");
 
 	/* Only spend time testing on debug builds that are trying to detect more errors. */
-	if (IS_ENABLED(CONFIG_FATAL_ASSERTS)) {
+	if (CONFIG(FATAL_ASSERTS)) {
 		printk(BIOS_DEBUG, "ARM64: Testing exception\n");
 		test_exception();
 		printk(BIOS_DEBUG, "ARM64: Done test exception\n");

diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c
@@ -19,7 +19,6 @@
 #include <arch/transition.h>
 #include <arm_tf.h>
 #include <program_loading.h>
-#include <string.h>
 
 static void run_payload(struct prog *prog)
 {
@@ -30,7 +29,7 @@ static void run_payload(struct prog *prog)
 	arg = prog_entry_arg(prog);
 	u64 payload_spsr = get_eret_el(EL2, SPSR_USE_L);
 
-	if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE))
+	if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE))
 		arm_tf_run_bl31((u64)doit, (u64)arg, payload_spsr);
 	else
 		transition_to_el2(doit, arg, payload_spsr);

diff --git a/src/arch/arm64/include/armv8/arch/barrier.h b/src/arch/arm64/include/armv8/arch/barrier.h
@@ -30,7 +30,7 @@
 #define rmb()		asm volatile("dsb ld" : : : "memory")
 #define wmb()		asm volatile("dsb st" : : : "memory")
 
-#if IS_ENABLED(CONFIG_SMP)
+#if CONFIG(SMP)
 #define barrier() __asm__ __volatile__("": : :"memory")
 #endif
 

diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c
@@ -30,12 +30,12 @@ void bootmem_arch_add_ranges(void)
 {
 	bootmem_add_range((uintptr_t)_ttb, REGION_SIZE(ttb), BM_MEM_RAMSTAGE);
 
-	if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) &&
+	if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE) &&
 	    REGION_SIZE(bl31) > 0)
 		bootmem_add_range((uintptr_t)_bl31, REGION_SIZE(bl31),
 				  BM_MEM_BL31);
 
-	if (!IS_ENABLED(CONFIG_COMMON_CBFS_SPI_WRAPPER))
+	if (!CONFIG(COMMON_CBFS_SPI_WRAPPER))
 		return;
 	bootmem_add_range((uintptr_t)_postram_cbfs_cache,
 			  REGION_SIZE(postram_cbfs_cache), BM_MEM_RAMSTAGE);

diff --git a/src/arch/mips/ashldi3.c b/src/arch/mips/ashldi3.c
@@ -19,7 +19,7 @@
 #errror "What endian are you!?"
 #endif
 
-typedef unsigned word_type;
+typedef unsigned int word_type;
 long long __ashldi3(long long u, word_type b);
 
 struct DWstruct {

diff --git a/src/arch/mips/bootblock_simple.c b/src/arch/mips/bootblock_simple.c
@@ -26,16 +26,16 @@ void main(void)
 	/* Mainboard basic init */
 	bootblock_mainboard_init();
 
-#if IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)
+#if CONFIG(BOOTBLOCK_CONSOLE)
 	console_init();
 #endif
 
 	bootblock_mmu_init();
 
-	if (init_extra_hardware()) {
+	if (init_extra_hardware())
 		printk(BIOS_ERR, "bootblock_simple: failed to init HW.\n");
-	} else {
+	else
 		run_romstage();
-	}
+
 	halt();
 }
diff --git a/src/arch/mips/include/arch/mmio.h b/src/arch/mips/include/arch/mmio.h
@@ -24,43 +24,47 @@
 #include <arch/cache.h>
 #include <endian.h>
 
-static inline uint8_t read8(unsigned long addr)
+static inline uint8_t read8(const volatile void *addr)
 {
 	asm("sync");
 	return *(volatile uint8_t *)addr;
 }
 
-static inline uint16_t read16(unsigned long addr)
+static inline uint16_t read16(const volatile void *addr)
 {
 	asm("sync");
 	return *(volatile uint16_t *)addr;
 }
 
-static inline uint32_t read32(unsigned long addr)
+static inline uint32_t read32(const volatile void *addr)
 {
 	asm("sync");
 	return *(volatile uint32_t *)addr;
 }
 
-static inline void write8(unsigned long addr, uint8_t val)
+static inline void write8(volatile void *addr, uint8_t val)
 {
 	asm("sync");
 	*(volatile uint8_t *)addr = val;
 	asm("sync");
 }
 
-static inline void write16(unsigned long addr, uint16_t val)
+static inline void write16(volatile void *addr, uint16_t val)
 {
 	asm("sync");
 	*(volatile uint16_t *)addr = val;
 	asm("sync");
 }
 
-static inline void write32(unsigned long addr, uint32_t val)
+static inline void write32(volatile void *addr, uint32_t val)
 {
 	asm("sync");
 	*(volatile uint32_t *)addr = val;
 	asm("sync");
 }
 
+/* Fixing soc/imgtech/pistachio seemed painful at the time. */
+#define read32_x(addr)		read32((void *)(addr))
+#define write32_x(addr, val)	write32((void *)(addr), (val))
+
 #endif	/* __MIPS_ARCH_IO_H */
diff --git a/src/arch/ppc64/include/arch/cpu.h b/src/arch/ppc64/include/arch/cpu.h
@@ -31,7 +31,7 @@ struct thread;
 struct cpu_info {
 	struct device *cpu;
 	unsigned long index;
-#if IS_ENABLED(CONFIG_COOP_MULTITASKING)
+#if CONFIG(COOP_MULTITASKING)
 	struct thread *thread;
 #endif
 };

diff --git a/src/arch/ppc64/include/arch/mmio.h b/src/arch/ppc64/include/arch/mmio.h
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_MMIO_H__
+#define __ARCH_MMIO_H__
+
+#include <stdint.h>
+
+/* NOTE: These are just stubs; if the architecture requires special
+ * care to avoid posted writes or cachelines, it is not yet done here.
+ */
+
+static inline uint8_t read8(const volatile void *addr)
+{
+	return *(volatile uint8_t *)addr;
+}
+
+static inline uint16_t read16(const volatile void *addr)
+{
+	return *(volatile uint16_t *)addr;
+}
+
+static inline uint32_t read32(const volatile void *addr)
+{
+	return *(volatile uint32_t *)addr;
+}
+
+static inline void write8(volatile void *addr, uint8_t val)
+{
+	*(volatile uint8_t *)addr = val;
+}
+
+static inline void write16(volatile void *addr, uint16_t val)
+{
+	*(volatile uint16_t *)addr = val;
+}
+
+static inline void write32(volatile void *addr, uint32_t val)
+{
+	*(volatile uint32_t *)addr = val;
+}
+
+#endif /* __ARCH_MMIO_H__ */
diff --git a/src/arch/riscv/include/arch/cpu.h b/src/arch/riscv/include/arch/cpu.h
@@ -33,7 +33,7 @@ struct thread;
 struct cpu_info {
 	struct device *cpu;
 	unsigned long index;
-#if IS_ENABLED(CONFIG_COOP_MULTITASKING)
+#if CONFIG(COOP_MULTITASKING)
 	struct thread *thread;
 #endif
 };

diff --git a/src/arch/riscv/sbi.c b/src/arch/riscv/sbi.c
@@ -45,7 +45,7 @@ static uintptr_t sbi_set_timer(uint64_t when)
 	return 0;
 }
 
-#if IS_ENABLED(CONFIG_CONSOLE_SERIAL)
+#if CONFIG(CONSOLE_SERIAL)
 static uintptr_t sbi_console_putchar(uint8_t ch)
 {
 	uart_tx_byte(CONFIG_UART_FOR_CONSOLE, ch);
@@ -86,7 +86,7 @@ void handle_sbi(trapframe *tf)
 		ret = sbi_set_timer(arg0);
 #endif
 		break;
-#if IS_ENABLED(CONFIG_CONSOLE_SERIAL)
+#if CONFIG(CONSOLE_SERIAL)
 	case SBI_CONSOLE_PUTCHAR:
 		ret = sbi_console_putchar(arg0);
 		break;

diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
@@ -17,7 +17,6 @@
 #include <arch/encoding.h>
 #include <arch/exception.h>
 #include <console/console.h>
-#include <string.h>
 #include <vm.h>
 #include <mcall.h>
 #include <sbi.h>

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
@@ -47,6 +47,11 @@ cbfs-files-$(CONFIG_VGA_BIOS) += pci$(stripped_vgabios_id).rom
 pci$(stripped_vgabios_id).rom-file := $(call strip_quotes,$(CONFIG_VGA_BIOS_FILE))
 pci$(stripped_vgabios_id).rom-type := optionrom
 
+stripped_vgabios_dgpu_id = $(call strip_quotes,$(CONFIG_VGA_BIOS_DGPU_ID))
+cbfs-files-$(CONFIG_VGA_BIOS_DGPU) += pci$(stripped_vgabios_dgpu_id).rom
+pci$(stripped_vgabios_dgpu_id).rom-file := $(call strip_quotes,$(CONFIG_VGA_BIOS_DGPU_FILE))
+pci$(stripped_vgabios_dgpu_id).rom-type := optionrom
+
 verstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
 bootblock-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
 romstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c
@@ -322,8 +327,6 @@ ramstage-y += memmove.c
 ramstage-y += memset.c
 ramstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
 ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c
-ramstage-y += pci_ops_conf1.c
-ramstage-$(CONFIG_NO_MMCONF_SUPPORT) += pci_ops.c
 ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c
 ramstage-y += rdrand.c
 ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c

diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c
@@ -150,7 +150,7 @@ int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic)
 unsigned long acpi_create_madt_lapics(unsigned long current)
 {
 	struct device *cpu;
-	int index, apic_ids[CONFIG_MAX_CPUS], num_cpus = 0;
+	int index, apic_ids[CONFIG_MAX_CPUS] = {0}, num_cpus = 0;
 
 	for (cpu = all_devices; cpu; cpu = cpu->next) {
 		if ((cpu->path.type != DEVICE_PATH_APIC) ||
@@ -163,7 +163,8 @@ unsigned long acpi_create_madt_lapics(unsigned long current)
 			break;
 		apic_ids[num_cpus++] = cpu->path.apic.apic_id;
 	}
-	bubblesort(apic_ids, num_cpus, NUM_ASCENDING);
+	if (num_cpus > 1)
+		bubblesort(apic_ids, num_cpus, NUM_ASCENDING);
 	for (index = 0; index < num_cpus; index++) {
 		current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current,
 				index, apic_ids[index]);
@@ -1066,7 +1067,7 @@ void acpi_write_bert(acpi_bert_t *bert, uintptr_t region, size_t length)
 	header->checksum = acpi_checksum((void *)bert, header->length);
 }
 
-#if IS_ENABLED(CONFIG_COMMON_FADT)
+#if CONFIG(COMMON_FADT)
 void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
 {
 	acpi_header_t *header = &(fadt->header);
@@ -1088,11 +1089,11 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
 	fadt->x_dsdt_l = (unsigned long)dsdt;
 	fadt->x_dsdt_h = 0;
 
-	if (IS_ENABLED(CONFIG_SYSTEM_TYPE_CONVERTIBLE) ||
-	    IS_ENABLED(CONFIG_SYSTEM_TYPE_LAPTOP))
+	if (CONFIG(SYSTEM_TYPE_CONVERTIBLE) ||
+	    CONFIG(SYSTEM_TYPE_LAPTOP))
 		fadt->preferred_pm_profile = PM_MOBILE;
-	else if (IS_ENABLED(CONFIG_SYSTEM_TYPE_DETACHABLE) ||
-		 IS_ENABLED(CONFIG_SYSTEM_TYPE_TABLET))
+	else if (CONFIG(SYSTEM_TYPE_DETACHABLE) ||
+		 CONFIG(SYSTEM_TYPE_TABLET))
 		fadt->preferred_pm_profile = PM_TABLET;
 	else
 		fadt->preferred_pm_profile = PM_DESKTOP;
@@ -1256,7 +1257,7 @@ unsigned long write_acpi_tables(unsigned long start)
 		acpi_add_table(rsdp, mcfg);
 	}
 
-	if (IS_ENABLED(CONFIG_TPM1)) {
+	if (CONFIG(TPM1)) {
 		printk(BIOS_DEBUG, "ACPI:    * TCPA\n");
 		tcpa = (acpi_tcpa_t *) current;
 		acpi_create_tcpa(tcpa);
@@ -1267,7 +1268,7 @@ unsigned long write_acpi_tables(unsigned long start)
 		}
 	}
 
-	if (IS_ENABLED(CONFIG_TPM2)) {
+	if (CONFIG(TPM2)) {
 		printk(BIOS_DEBUG, "ACPI:    * TPM2\n");
 		tpm2 = (acpi_tpm2_t *) current;
 		acpi_create_tpm2(tpm2);

diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c
@@ -19,7 +19,7 @@
 #include <arch/acpigen.h>
 #include <device/device.h>
 #include <device/path.h>
-#if IS_ENABLED(CONFIG_GENERIC_GPIO_LIB)
+#if CONFIG(GENERIC_GPIO_LIB)
 #include <gpio.h>
 #endif
 
@@ -342,7 +342,7 @@ void acpi_device_write_gpio(const struct acpi_gpio *gpio)
 	/* Pin Table, one word for each pin */
 	for (pin = 0; pin < gpio->pin_count; pin++) {
 		uint16_t acpi_pin = gpio->pins[pin];
-#if IS_ENABLED(CONFIG_GENERIC_GPIO_LIB)
+#if CONFIG(GENERIC_GPIO_LIB)
 		acpi_pin = gpio_acpi_pin(acpi_pin);
 #endif
 		acpigen_emit_word(acpi_pin);
@@ -352,7 +352,7 @@ void acpi_device_write_gpio(const struct acpi_gpio *gpio)
 	acpi_device_fill_from_len(resource_offset, start);
 
 	/* Resource Source Name String */
-#if IS_ENABLED(CONFIG_GENERIC_GPIO_LIB)
+#if CONFIG(GENERIC_GPIO_LIB)
 	acpigen_emit_string(gpio->resource ? : gpio_acpi_path(gpio->pins[0]));
 #else
 	acpigen_emit_string(gpio->resource);

diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c
@@ -82,7 +82,7 @@ static int backup_create_or_update(struct resume_backup *backup_mem,
 {
 	uintptr_t top;
 
-	if (IS_ENABLED(CONFIG_ACPI_HUGE_LOWMEM_BACKUP)) {
+	if (CONFIG(ACPI_HUGE_LOWMEM_BACKUP)) {
 		base = CONFIG_RAMBASE;
 		size = HIGH_MEMORY_SAVE;
 	}
@@ -169,7 +169,7 @@ void acpi_prepare_resume_backup(void)
 	if (!acpi_s3_resume_allowed())
 		return;
 
-	if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE))
+	if (CONFIG(RELOCATABLE_RAMSTAGE))
 		return;
 
 	backup_create_or_update(NULL, (uintptr_t)_program,
@@ -194,7 +194,7 @@ static void acpi_jump_to_wakeup(void *vector)
 		return;
 	}
 
-	if (!IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) {
+	if (!CONFIG(RELOCATABLE_RAMSTAGE)) {
 		struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME);
 		if (backup_mem && backup_mem->valid) {
 			backup_mem->valid = 0;
@@ -224,7 +224,7 @@ void __weak mainboard_suspend_resume(void)
 
 void acpi_resume(void *wake_vec)
 {
-	if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+	if (CONFIG(HAVE_SMI_HANDLER)) {
 		void *gnvs_address = cbmem_find(CBMEM_ID_ACPI_GNVS);
 
 		/* Restore GNVS pointer in SMM if found */

diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S
@@ -16,7 +16,7 @@
 
 #include <rules.h>
 
-#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
+#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
 
 /*
  * This path is for stages that are post bootblock when employing
@@ -43,8 +43,8 @@ _start:
 	sub	%edi, %ecx
 	rep	stosl
 
-#if ((ENV_VERSTAGE && IS_ENABLED(CONFIG_VERSTAGE_DEBUG_SPINLOOP)) \
-	|| (ENV_ROMSTAGE && IS_ENABLED(CONFIG_ROMSTAGE_DEBUG_SPINLOOP)))
+#if ((ENV_VERSTAGE && CONFIG(VERSTAGE_DEBUG_SPINLOOP)) \
+	|| (ENV_ROMSTAGE && CONFIG(ROMSTAGE_DEBUG_SPINLOOP)))
 
 	/* Wait for a JTAG debugger to break in and set EBX non-zero */
 	xor	%ebx, %ebx
@@ -55,7 +55,7 @@ debug_spinloop:
 #endif
 
 	andl	$0xfffffff0, %esp
-#if IS_ENABLED(CONFIG_IDT_IN_EVERY_STAGE)
+#if CONFIG(IDT_IN_EVERY_STAGE)
 	call	exception_init
 #endif
 	call	car_stage_entry
@@ -75,7 +75,7 @@ car_stage_entry:
 #include <arch/x86/prologue.inc>
 #include <cpu/x86/32bit/entry32.inc>
 #include <cpu/x86/fpu_enable.inc>
-#if IS_ENABLED(CONFIG_SSE)
+#if CONFIG(SSE)
 #include <cpu/x86/sse_enable.inc>
 #endif
 

diff --git a/src/arch/x86/boot.c b/src/arch/x86/boot.c
@@ -15,7 +15,6 @@
 #include <console/console.h>
 #include <program_loading.h>
 #include <ip_checksum.h>
-#include <string.h>
 #include <symbols.h>
 
 int payload_arch_usable_ram_quirk(uint64_t start, uint64_t size)

diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld
@@ -17,7 +17,7 @@
 #include <cpu/x86/16bit/entry16.ld>
 #include <cpu/x86/16bit/reset16.ld>
 #include <arch/x86/id.ld>
-#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
+#if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
 #include <cpu/intel/fit/fit.ld>
 #endif
 

diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S
@@ -32,7 +32,7 @@
 #include <cpu/x86/16bit/reset16.inc>
 #include <cpu/x86/32bit/entry32.inc>
 
-#if IS_ENABLED(CONFIG_BOOTBLOCK_DEBUG_SPINLOOP)
+#if CONFIG(BOOTBLOCK_DEBUG_SPINLOOP)
 
 	/* Wait for a JTAG debugger to break in and set EBX non-zero */
 	xor	%ebx, %ebx
@@ -44,7 +44,7 @@ debug_spinloop:
 
 bootblock_protected_mode_entry:
 
-#if !IS_ENABLED(CONFIG_USE_MARCH_586)
+#if !CONFIG(USE_MARCH_586)
 	/* MMX registers required here */
 
 	/* BIST result in eax */
@@ -57,12 +57,12 @@ bootblock_protected_mode_entry:
 	movd	%edx, %mm2
 #endif
 
-#if IS_ENABLED(CONFIG_SSE)
+#if CONFIG(SSE)
 enable_sse:
 	mov	%cr4, %eax
 	or	$CR4_OSFXSR, %ax
 	mov	%eax, %cr4
-#endif /* IS_ENABLED(CONFIG_SSE) */
+#endif /* CONFIG(SSE) */
 
 	/* We're done. Now it's up to platform-specific code */
 	jmp	bootblock_pre_c_entry
diff --git a/src/arch/x86/bootblock_romcc.S b/src/arch/x86/bootblock_romcc.S
@@ -37,7 +37,7 @@
 
 #include <arch/x86/timestamp.inc>
 
-#if IS_ENABLED(CONFIG_SSE)
+#if CONFIG(SSE)
 #include <cpu/x86/sse_enable.inc>
 #endif
 

diff --git a/src/arch/x86/bootblock_simple.c b/src/arch/x86/bootblock_simple.c
@@ -22,12 +22,12 @@ static void main(unsigned long bist)
 		bootblock_mainboard_init();
 
 		sanitize_cmos();
-#if IS_ENABLED(CONFIG_CMOS_POST)
+#if CONFIG(CMOS_POST)
 		cmos_post_init();
 #endif
 	}
 
-#if IS_ENABLED(CONFIG_VBOOT_SEPARATE_VERSTAGE)
+#if CONFIG(VBOOT_SEPARATE_VERSTAGE)
 	const char *target1 = "fallback/verstage";
 #else
 	const char *target1 = "fallback/romstage";

diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S
@@ -25,7 +25,7 @@
 _stack:
 .space (CONFIG_MAX_CPUS+1)*CONFIG_STACK_SIZE
 _estack:
-#if IS_ENABLED(CONFIG_COOP_MULTITASKING)
+#if CONFIG(COOP_MULTITASKING)
 .global thread_stacks
 thread_stacks:
 .space CONFIG_STACK_SIZE*CONFIG_NUM_THREADS
@@ -76,7 +76,7 @@ _start:
 	movl	$_estack, %esp
 	andl	$(~(CONFIG_STACK_SIZE-1)), %esp
 
-#if IS_ENABLED(CONFIG_COOP_MULTITASKING)
+#if CONFIG(COOP_MULTITASKING)
 	/* Push the thread pointer. */
 	push	$0
 #endif
@@ -93,7 +93,7 @@ _start:
 
 	andl	$0xFFFFFFF0, %esp
 
-#if IS_ENABLED(CONFIG_GDB_WAIT)
+#if CONFIG(GDB_WAIT)
 	call gdb_hw_init
 	call gdb_stub_breakpoint
 #endif
@@ -104,7 +104,7 @@ _start:
 	hlt
 	jmp	.Lhlt
 
-#if IS_ENABLED(CONFIG_GDB_WAIT)
+#if CONFIG(GDB_WAIT)
 
 	.globl gdb_stub_breakpoint
 gdb_stub_breakpoint:

diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
@@ -19,7 +19,7 @@
 . = CONFIG_DCACHE_RAM_BASE;
 .car.data . (NOLOAD) : {
 	_car_region_start = . ;
-#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM)
+#if CONFIG(PAGING_IN_CACHE_AS_RAM)
 	/* Page table pre-allocation. CONFIG_DCACHE_RAM_BASE should be 4KiB
 	 * aligned when using this option. */
 	_pagetables = . ;
@@ -28,13 +28,17 @@
 #endif
 	/* Vboot work buffer only needs to be available when verified boot
 	 * starts in bootblock. */
-#if IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK)
-	VBOOT2_WORK(., 16K)
+#if CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)
+	VBOOT2_WORK(., 12K)
 #endif
+	/* Vboot measured boot TCPA log measurements.
+	 * Needs to be transferred until CBMEM is available
+	 */
+	VBOOT2_TPM_LOG(., 2K)
 	/* Stack for CAR stages. Since it persists across all stages that
 	 * use CAR it can be reused. The chipset/SoC is expected to provide
 	 * the stack size. */
-#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
+#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
 	_car_stack_start = .;
 	. += CONFIG_DCACHE_BSP_STACK_SIZE;
 	_car_stack_end = .;
@@ -44,7 +48,7 @@
          * multiple stages (romstage and verstage) have a consistent
          * link address of these shared objects. */
 	PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE)
-#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM)
+#if CONFIG(PAGING_IN_CACHE_AS_RAM)
 	. = ALIGN(32);
 	/* Page directory pointer table resides here. There are 4 8-byte entries
 	 * totalling 32 bytes that need to be 32-byte aligned. The reason the
@@ -70,7 +74,7 @@
 	 * cbmem console. This is useful for clearing this area on a per-stage
 	 * basis when more than one stage uses cache-as-ram for CAR_GLOBALs. */
 	_car_global_start = .;
-#if IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION)
+#if CONFIG(NO_CAR_GLOBAL_MIGRATION)
 	/* Allow global unitialized variables when CAR_GLOBALs are not used. */
 	*(.bss)
 	*(.bss.*)
@@ -85,15 +89,15 @@
 	_car_global_end = .;
 	_car_relocatable_data_end = .;
 
-#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) && \
-    !IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT)
+#if CONFIG(NORTHBRIDGE_INTEL_SANDYBRIDGE) && \
+    !CONFIG(USE_NATIVE_RAMINIT)
 	. = ABSOLUTE(0xff7e1000);
 	_mrc_pool = .;
 	. += 0x5000;
 	_emrc_pool = .;
 #endif
 
-#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
+#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK)
 	_car_stack_start = .;
 	_car_stack_end = _car_region_end;
 #endif
@@ -109,7 +113,7 @@
 .illegal_globals . : {
 	*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data)
 		*(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*)
-#if !IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION)
+#if !CONFIG(NO_CAR_GLOBAL_MIGRATION)
 	*(.bss)
 	*(.bss.*)
 	*(.sbss)
@@ -121,9 +125,9 @@
 }
 
 _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
-#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM)
+#if CONFIG(PAGING_IN_CACHE_AS_RAM)
 _bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned");
 #endif
-#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
+#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
 _bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured");
 #endif
diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c
@@ -15,7 +15,7 @@
 #include <cbmem.h>
 #include <arch/acpi.h>
 
-#if IS_ENABLED(CONFIG_CBMEM_TOP_BACKUP)
+#if CONFIG(CBMEM_TOP_BACKUP)
 
 void *cbmem_top(void)
 {
@@ -39,7 +39,7 @@ void *cbmem_top(void)
 /* Something went wrong, our high memory area got wiped */
 void cbmem_fail_resume(void)
 {
-#if !defined(__PRE_RAM__) && IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#if !defined(__PRE_RAM__) && CONFIG(HAVE_ACPI_RESUME)
 	/* ACPI resume needs to be cleared in the fail-to-recover case, but that
 	 * condition is only handled during ramstage. */
 	acpi_fail_wakeup();

diff --git a/src/arch/x86/cf9_reset.c b/src/arch/x86/cf9_reset.c
@@ -18,7 +18,6 @@
 #include <cf9_reset.h>
 #include <console/console.h>
 #include <halt.h>
-#include <reset.h>
 
 /*
  * A system reset in terms of the CF9 register asserts the INIT#

diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c
@@ -284,7 +284,7 @@ void lb_arch_add_records(struct lb_header *header)
 	struct lb_tsc_info *tsc_info;
 
 	/* Don't advertise a TSC rate unless it's constant. */
-	if (!IS_ENABLED(CONFIG_TSC_CONSTANT_RATE))
+	if (!CONFIG(TSC_CONSTANT_RATE))
 		return;
 
 	freq_khz = tsc_freq_mhz() * 1000;
@@ -302,7 +302,7 @@ void lb_arch_add_records(struct lb_header *header)
 void arch_bootstate_coreboot_exit(void)
 {
 	/* APs are already parked by existing infrastructure. */
-	if (!IS_ENABLED(CONFIG_PARALLEL_MP_AP_WORK))
+	if (!CONFIG(PARALLEL_MP_AP_WORK))
 		return;
 
 	/* APs are waiting for work. Last thing to do is park them. */

diff --git a/src/arch/x86/exception.c b/src/arch/x86/exception.c
@@ -22,7 +22,7 @@
 #include <stdint.h>
 #include <string.h>
 
-#if IS_ENABLED(CONFIG_GDB_STUB)
+#if CONFIG(GDB_STUB)
 
 /* BUFMAX defines the maximum number of characters in inbound/outbound buffers.
  * At least NUM_REGBYTES*2 are needed for register packets
@@ -394,7 +394,7 @@ void x86_exception(struct eregs *info);
 
 void x86_exception(struct eregs *info)
 {
-#if IS_ENABLED(CONFIG_GDB_STUB)
+#if CONFIG(GDB_STUB)
 	int signo;
 	memcpy(gdb_stub_registers, info, 8*sizeof(uint32_t));
 	gdb_stub_registers[PC] = info->eip;

diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S
@@ -61,7 +61,7 @@ _start:
 	 *   0x00: Number of variable MTRRs to clear
 	 */
 
-#if IS_ENABLED(CONFIG_SOC_SETS_MSRS)
+#if CONFIG(SOC_SETS_MSRS)
 
 	mov	%esp, %ebp
 	/* Need to align stack to 16 bytes at the call instruction. Therefore

diff --git a/src/arch/x86/failover.ld b/src/arch/x86/failover.ld
@@ -28,7 +28,7 @@ SECTIONS
 	 * boundary anyway, so no pad byte appears between _rom and _start.
 	 */
 	.bogus ROMLOC_MIN : {
-		. = CONFIG_SIPI_VECTOR_IN_ROM ?	ALIGN(4096) : ALIGN(4);
+		. = CONFIG(SIPI_VECTOR_IN_ROM) ? ALIGN(4096) : ALIGN(4);
 		ROMLOC = .;
 	} >rom = 0xff
 
@@ -50,10 +50,10 @@ SECTIONS
 	 * address gets applied.
 	 */
 	ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) -
-		(CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0);
+		(CONFIG(SIPI_VECTOR_IN_ROM) ? 4096 : 0);
 
 	/* Post-check proper SIPI vector. */
-	_bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || (ap_sipi_vector_in_rom == 0xff),
+	_bogus = ASSERT(!CONFIG(SIPI_VECTOR_IN_ROM) || (ap_sipi_vector_in_rom == 0xff),
 		"Address mismatch on AP_SIPI_VECTOR");
 
 	/DISCARD/ : {

diff --git a/src/arch/x86/gdt.c b/src/arch/x86/gdt.c
@@ -40,7 +40,7 @@ static void move_gdt(int is_recovery)
 	struct gdtarg gdtarg;
 
 	/* ramstage is already in high memory. No need to use a new gdt. */
-	if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE))
+	if (CONFIG(RELOCATABLE_RAMSTAGE))
 		return;
 
 	newgdt = cbmem_find(CBMEM_ID_GDT);

diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
@@ -32,7 +32,7 @@
  * The type and enable fields are common in ACPI, but the
  * values themselves are hardware implementation defined.
  */
-#if IS_ENABLED(CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES)
+#if CONFIG(ACPI_INTEL_HARDWARE_SLEEP_VALUES)
  #define SLP_EN		(1 << 13)
  #define SLP_TYP_SHIFT	10
  #define SLP_TYP	(7 << SLP_TYP_SHIFT)
@@ -41,7 +41,7 @@
  #define  SLP_TYP_S3	5
  #define  SLP_TYP_S4	6
  #define  SLP_TYP_S5	7
-#elif IS_ENABLED(CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES)
+#elif CONFIG(ACPI_AMD_HARDWARE_SLEEP_VALUES)
  #define SLP_EN		(1 << 13)
  #define SLP_TYP_SHIFT	10
  #define SLP_TYP	(7 << SLP_TYP_SHIFT)
@@ -776,7 +776,7 @@ unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current);
 void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id);
 void acpi_write_bert(acpi_bert_t *bert, uintptr_t region, size_t length);
 void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt);
-#if IS_ENABLED(CONFIG_COMMON_FADT)
+#if CONFIG(COMMON_FADT)
 void acpi_fill_fadt(acpi_fadt_t *fadt);
 #endif
 
@@ -885,8 +885,8 @@ enum {
 	ACPI_S5,
 };
 
-#if IS_ENABLED(CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES) \
-		|| IS_ENABLED(CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES)
+#if CONFIG(ACPI_INTEL_HARDWARE_SLEEP_VALUES) \
+		|| CONFIG(ACPI_AMD_HARDWARE_SLEEP_VALUES)
 /* Given the provided PM1 control register return the ACPI sleep type. */
 static inline int acpi_sleep_from_pm1(uint32_t pm1_cnt)
 {
@@ -909,7 +909,7 @@ int acpi_get_gpe(int gpe);
 
 static inline int acpi_s3_resume_allowed(void)
 {
-	return IS_ENABLED(CONFIG_HAVE_ACPI_RESUME);
+	return CONFIG(HAVE_ACPI_RESUME);
 }
 
 /* Return address in reserved memory where to backup low memory
@@ -919,7 +919,7 @@ static inline int acpi_s3_resume_allowed(void)
  */
 void *acpi_backup_container(uintptr_t base, size_t size);
 
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
+#if CONFIG(HAVE_ACPI_RESUME)
 
 #ifdef __PRE_RAM__
 static inline int acpi_is_wakeup_s3(void)

diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
@@ -188,7 +188,7 @@ struct thread;
 struct cpu_info {
 	struct device *cpu;
 	unsigned int index;
-#if IS_ENABLED(CONFIG_COOP_MULTITASKING)
+#if CONFIG(COOP_MULTITASKING)
 	struct thread *thread;
 #endif
 };