diff --git a/Documentation/mainboard/system76/oryp8.md b/Documentation/mainboard/system76/oryp8.md
@@ -0,0 +1,70 @@
+# System76 Oryx Pro 8 (oryp8)
+
+## Specs
+
+- CPU
+  - Intel Core i7-11800H
+- Chipset
+  - Intel HM570
+- EC
+  - ITE IT570E running [System76 EC](https://github.com/system76/ec)
+- Graphics
+  - dGPU options
+    - NVIDIA GeForce RTX 3070 (Max-Q)
+    - NVIDIA GeForce RTX 3080 (Max-Q)
+  - eDP options
+    - 15.6" 1920x1080@144Hz LCD (LG LP156WFG-SPB3)
+    - 17.3" 1920x1080@144Hz LCD (LG LP173WFG-SPB3)
+  - 1x HDMI 2.1
+  - 1x Mini DisplayPort 1.4
+  - 1x DisplayPort 1.4 over USB-C
+- Memory
+  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
+- Networking
+  - Gigabit Ethernet
+  - M.2 PCIe/CNVi WiFi/Bluetooth
+    - Intel Wi-Fi 6 AX200/AX201
+- Power
+  - 180W (19.5V, 9.23A) AC barrel adapter
+    - Lite-On PA-1181-16, using a C5 power cord
+  - 73Wh 3-cell battery
+- Sound
+  - Realtek ALC1220 codec
+  - TI TAS5825M smart amp
+  - Internal speakers and microphone
+  - Combined 3.5mm headphone & microphone jack
+  - Combined 3.5mm microphone & S/PDIF jack
+  - HDMI, mDP, USB-C DP audio
+- Storage
+  - 1x M.2 PCIe NVMe Gen 4 SSD
+  - 1x M.2 PCIe NVMe Gen 3 or SATA SSD
+- USB
+  - 1x USB Type-C with Thunderbolt 4
+  - 3x USB 3.0 Type-A
+- Dimensions
+  - 15": 35.75cm x 23.8cm x 1.98cm, 1.99kg
+  - 17": 39.59cm x 26.495cm x 1.99cm, 2.3kg
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+-----------------+
+| Type                | Value           |
++=====================+=================+
+| Socketed flash      | no              |
++---------------------+-----------------+
+| Vendor              | GigaDevice      |
++---------------------+-----------------+
+| Model               | GD25B127D       |
++---------------------+-----------------+
+| Size                | 16 MiB          |
++---------------------+-----------------+
+| Package             | SOIC-8          |
++---------------------+-----------------+
+| Internal flashing   | yes             |
++---------------------+-----------------+
+| External flashing   | yes             |
++---------------------+-----------------+
+```
+
+The flash chip (U74) is right of the bottom DIMM slot.
diff --git a/Documentation/releases/coreboot-4.14-relnotes.md b/Documentation/releases/coreboot-4.14-relnotes.md
@@ -142,7 +142,7 @@ primarily to serve the needs of the server market.
 
 coreboot support for Xeon-SP is in src/soc/intel/xeon_sp directory.
 This release has support for SkyLake-SP (SKX-SP) which is the 2nd
-generation, and for CooperLake-SP (CPX-SP) which is the 3rd generation
+generation, and for Cooper Lake-SP (CPX-SP) which is the 3rd generation
 or the latest generation [2] on market.
 
 With this release, the codebase for multiple generations of Xeon-SP

diff --git a/Documentation/releases/coreboot-4.15-relnotes.md b/Documentation/releases/coreboot-4.15-relnotes.md
@@ -1,14 +1,69 @@
-Upcoming release - coreboot 4.15
+coreboot 4.15
 ================================
 
-The 4.15 release is planned for October 2021.
+coreboot 4.15 was released on November 5th, 2021.
 
-Update this document with changes that should be in the release notes.
+Since 4.14 there have been more than 2597 new commits by more than 219 developers.
+Of these, over 73 contributed to coreboot for the first time.
 
-* Please use Markdown.
-* See the past few release notes for the general format.
-* The chip and board additions and removals will be updated right
-  before the release, so those do not need to be added.
+Welcome to the project!
+
+Thank you to all the developers who continue to make coreboot the
+great open source firmware project that it is.
+
+Important Announcement
+----------------------
+We are going to be changing the cadence from every 6 months, to every 3 months.
+That means the 4.16 release will be coming in February, 2022.
+
+
+New mainboards
+--------------
+* Asus p8h61-m_pro_cm6630
+* Asus p8h77-v
+* Asus p8z77-v
+* Google nipperkin
+* Lenovo w541
+* Siemens mc_ehl
+* SuperMicro x9sae
+* System76 addw1
+* System76 addw2
+* System76 bonw14
+* System76 darp6
+* System76 darp7
+* System76 galp2
+* System76 galp3
+* System76 galp3-b
+* System76 galp4
+* System76 galp5
+* System76 gaze14
+* System76 lemp10
+* System76 oryp7
+* System76 oryp8
+
+Removed mainboards
+------------------
+* Google Mancomb
+
+Deprecations and incompatible changes
+-------------------------------------
+
+### COREBOOTPAYLOAD option
+
+Drop the deprecated COREBOOTPAYLOAD option, and replace it with MrChromebox's
+updated UefiPayloadPkg option. Simplify the Kconfig options to make it easier
+to build from upstream edk2 master. Drop the TIANOCORE_USE_8254_TIMER Kconfig
+option since it applies only to CorebootPayloadPkg. Clean up the Makefile now
+that we're only building from a single Tianocore package/target.
+
+### Remove old lp4x and ddr4 versions of spd_tools
+
+The migration to the new unified version of spd_tools is complete, so
+the old lp4x and ddr4 versions can be removed.
+
+### Remove AMD PI 00630F01
+
+No board currently uses AMD PI 00630F01 so remove it.
 
 Significant changes
 -------------------
@@ -37,4 +92,35 @@ payload)
 Unit testing of libpayload is now possible in the same fashion as in the main
 coreboot tree.
 
-### Add significant changes here
+### Introduce new method for accessing cpu_info
+
+There is currently a fundamental flaw in the current cpu_info()
+implementation. It assumes that current stack is CONFIG_STACK_SIZE
+aligned. This assumption breaks down when performing SMM relocation.
+
+The first step in performing SMM relocation is changing the SMBASE. This
+is accomplished by installing the smmstub at 0x00038000, which is the
+default SMM entry point. The stub is configured to set up a new stack
+with the size of 1 KiB (CONFIG_SMM_STUB_STACK_SIZE), and an entry point
+of smm_do_relocation located in RAMSTAGE RAM.
+
+This means that when smm_do_relocation is executed, it is running in SMM
+with a different sized stack. When cpu_info() gets called it will be
+using CONFIG_STACK_SIZE to calculate the location of the cpu_info
+struct. This results in reading random memory. Since cpu_info() has to
+run in multiple environments, we can't use a compile time constant to
+locate the cpu_info struct.
+
+This CL introduces a new way of locating cpu_info. It uses a per-cpu
+segment descriptor that points to a per-cpu segment that is allocated on
+the stack. By using a segment descriptor to point to the per-cpu data,
+we no longer need to calculate the location of the cpu_info struct. This
+has the following advantages:
+* Stacks no longer need to be CONFIG_STACK_SIZE aligned.
+* Accessing an unconfigured segment will result in an exception. This
+  ensures no one can call cpu_info() from an unsupported environment.
+* Segment selectors are cleared when entering SMM and restored when
+  leaving SMM.
+* There is a 1:1 mapping between cpu and cpu_info. When using
+  COOP_MULTITASKING, a new cpu_info is currently allocated at the top of
+  each thread's stack. This no longer needs to happen.
diff --git a/Documentation/releases/coreboot-4.16-relnotes.md b/Documentation/releases/coreboot-4.16-relnotes.md
@@ -0,0 +1,19 @@
+Upcoming release - coreboot 4.16
+================================
+
+The 4.16 release is planned for February, 2022.
+
+We are increasing the frequency of releases in order to enable others to release quarterly on
+a fresher version of coreboot.
+
+Update this document with changes that should be in the release notes.
+
+* Please use Markdown.
+* See the past few release notes for the general format.
+* The chip and board additions and removals will be updated right
+  before the release, so those do not need to be added.
+
+Significant changes
+-------------------
+
+### Add significant changes here
diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md
@@ -15,6 +15,7 @@ Release notes for previous releases
 * [4.12 - May 2020](coreboot-4.12-relnotes.md)
 * [4.13 - November 2020](coreboot-4.13-relnotes.md)
 * [4.14 - May 2021](coreboot-4.14-relnotes.md)
+* [4.15 - November 2021](coreboot-4.15-relnotes.md)
 
 The checklist contains instructions to ensure that a release covers all
 important things and provides a reliable format for tarballs, branch
@@ -26,4 +27,4 @@ Upcoming release
 ----------------
 
 Please add to the release notes as changes are added:
-* [4.15 - October 2021](coreboot-4.15-relnotes.md)
+* [4.16 - Feb 2022](coreboot-4.16-relnotes.md)
diff --git a/Documentation/security/vboot/list_vboot.md b/Documentation/security/vboot/list_vboot.md
@@ -31,6 +31,7 @@
 - Zako (HP Chromebox G1)
 - Butterfly (HP Pavilion Chromebook 14)
 - Cherry
+- Tomato
 - Banon (Acer Chromebook 15 (CB3-532))
 - Celes (Samsung Chromebook 3)
 - Cyan (Acer Chromebook R11 (C738T))
@@ -66,60 +67,68 @@
 - Nefario
 - Rainier
 - Guybrush
-- Akemi
-- Dratini
+- Nipperkin
+- Dewatt
+- Akemi (IdeaPad Flex 5/5i Chromebook)
+- Dratini (HP Pro c640 Chromebook)
 - Duffy Legacy (32MB)
-- Duffy
-- Faffy
+- Duffy (ASUS Chromebox 4)
+- Faffy (ASUS Fanless Chromebox)
 - Hatch
-- Jinlon
+- Jinlon (HP Elite c1030 Chromebook)
 - Kaisa Legacy (32MB)
-- Kaisa
-- Kohaku
-- Kindred
-- Helios
+- Kaisa (Acer Chromebox CXI4)
+- Kohaku (Samsung Galaxy Chromebook)
+- Kindred (Acer Chromebook 712)
+- Helios (ASUS Chromebook Flip C436FA)
 - Mushu
 - Palkia
-- Nightfury
-- Noibat
+- Nightfury (Samsung Galaxy Chromebook 2)
+- Noibat (HP Chromebox G3)
 - Puff
 - Helios_Diskswap
 - Stryke
-- Wyvern
+- Wyvern (CTL Chromebox CBx2)
 - Dooly
 - Ambassador
 - Genesis
+- Scout
+- Moonbuggy
 - Herobrine
+- Senor
+- Piglin
+- Hoglin
 - Guado (ASUS Chromebox CN62)
 - Jecht
 - Rikku (Acer Chromebox CXI2)
 - Tidus (Lenovo ThinkCentre Chromebox)
-- Aleena
-- Careena
+- Aleena/Kasumi (Acer Chromebook  315 (CB315-2H), 311 (C721) / Spin 311 (R721T))
+- Barla/Careena (HP Chromebook 11A G6/G8 EE, 14A G5/G6)
 - Grunt
-- Liara
+- Liara (Lenovo 14e Chromebook, Chromebook S345-14)
 - Nuwani
-- Treeya
+- Treeya (Lenovo 100e/300e Gen2 AMD)
 - Kukui
-- Krane
-- Kodama
+- Krane (Lenovo Chromebook Duet/Lenovo IdeaPad Duet Chromebook)
+- Kodama (Lenovo 10e Chromebook Tablet)
 - Kakadu
 - Flapjack
 - Katsu
 - Jacuzzi
-- Juniper
+- Juniper (Acer Chromebook Spin 311 (CP311-3H))
 - Kappa
-- Damu
+- Damu (ASUS Chromebook Flip CM3 (CM3200))
 - Cerise
 - Stern
 - Willow
-- Esche
-- Burnet
+- Esche (HP Chromebook 11MK G9 EE)
+- Burnet (HP Chromebook x360 11MK G3 EE)
 - Fennel
 - Cozmo
 - Makomo
+- Munna
+- Pico
 - Link (Google Chromebook Pixel (2013))
-- Mancomb
 - Mistral
 - Nyan
 - Nyan Big (Acer Chromebook 13 (CB5-311))
@@ -132,7 +141,7 @@
 - Atlas (Google Pixelbook Go)
 - Poppy
 - Nami
-- Nautilus (Samsung Chromebook Plus (V2 / LTE))
+- Nautilus (Samsung Chromebook Plus V2, V2 LTE)
 - Nocturne (Google Pixel Slate)
 - Rammus (Asus Chromebook C425, Flip C433, Flip C434)
 - Soraka (HP Chromebook x2)
@@ -158,8 +167,8 @@
 - Snappy (HP Chromebook x360 11 G1 EE)
 - Nasher
 - Coral
-- Arcada
-- Sarien
+- Arcada (Latitude 5300 2-in-1 Chromebook Enterprise)
+- Sarien (Dell Latitude 5400 Chromebook Enterprise)
 - Falco (HP Chromebook 14)
 - Leon (Toshiba Chromebook)
 - Peppy (Acer C720/C720P Chromebook)
@@ -177,8 +186,8 @@
 - Pazquel
 - Pompom
 - Quackingstick
-- Trogdor
 - Wormdingler
+- Trogdor
 - Veyron_Jaq (Haier Chromebook 11)
 - Veyron_Jerry (Hisense Chromebook 11)
 - Veyron_Mighty (Haier Chromebook 11(edu))
@@ -187,22 +196,23 @@
 - Veyron_Mickey (Asus Chromebit CS10)
 - Veyron_Rialto
 - Dalboz
-- Vilboz
-- Ezkinil
-- Morphius
+- Vilboz (Lenovo 100e/300e Gen3 AMD)
+- Ezkinil (Acer Chromebook Spin 514)
+- Morphius (Lenovo ThinkPad C13 Yoga Chromebook)
 - Trembyle
-- Berknip
-- Woomax
-- Dirinboz
+- Berknip (HP Pro c645 Chromebook Enterprise)
+- Woomax (ASUS Chromebook Flip CM5)
+- Dirinboz (HP Chromebook 14a-nd0097nr)
 - Shuboz
-- Gumboz
+- Gumboz (HP Chromebook x360 14a)
 
 ## HP
 - Z220 SFF Workstation
 
 ## Intel
 - Alderlake-P RVP
 - Alderlake-P RVP with Chrome EC
+- Alderlake-P RVP with Microchip EC
 - Alderlake-M RVP
 - Alderlake-M RVP with Chrome EC
 - Basking Ridge CRB

diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md
@@ -2,6 +2,18 @@
 
 This section contains documentation about Intel-FSP in public domain.
 
+## Integration Guidelines
+
+Some guiding principles when working on the glue to integrate FSP into
+coreboot, e.g. on how to configure a board in devicetree when that affects
+the way FSP works:
+
+* It should be possible to replace FSP based boot with a native coreboot
+  implementation for a given chipset without touching the mainboard code.
+* The devicetree configures coreboot and part of what coreboot does with the
+  information is setting some FSP UPDs. The devicetree isn't supposed to
+  directly configure FSP.
+
 ## Bugs
 As Intel doesn't even list known bugs, they are collected here until
 those are fixed. If possible a workaround is described here as well.

diff --git a/Documentation/superio/nuvoton/nct5539d.md b/Documentation/superio/nuvoton/nct5539d.md
@@ -1,9 +1,9 @@
-# NCT5539D SuperIO
+# NCT5539D Super I/O
 
-The SuperIO has the ID `0xd121` and the source can be found in
+The Super I/O has the ID `0xd121` and the source can be found in
 `src/superio/nuvoton/nct5539d/`.
 
 ## For developers
 
-The SuperIO generates ACPI using the
+The Super I/O generates ACPI using the
 [SSDT generator for generic SuperIOs](../common/ssdt.md).
diff --git a/Documentation/technotes/2021-05-code-coverage.md b/Documentation/technotes/2021-05-code-coverage.md
@@ -4,6 +4,9 @@ Code coverage for the coreboot unit tests allows us to see what lines of
 code in the coreboot library are covered by unit tests, and allows a test
 author to see where they need to add test cases for additional coverage.
 
+Code coverage requires `lcov`; install the tool if necessary by
+`sudo apt install lcov` or the equivalent for your system.
+
 Enable code coverage in your unit test build by setting the environment
 variable `COV` to 1; either `export COV=1` in your shell, or add it to your
 `make` command, e.g. `COV=1 make unit-tests`.

diff --git a/MAINTAINERS b/MAINTAINERS
@@ -169,6 +169,11 @@ F:	src/mainboard/asrock/h81m-hds/
 
 
 
+ASUS A88XM-E MAINBOARD
+M:	Mike Banon <mikebdp2@gmail.com>
+S:	Maintained
+F:	src/mainboard/asus/a88xm-e/
+
 ASUS AM1I-A MAINBOARD
 M:	Mike Banon <mikebdp2@gmail.com>
 S:	Maintained

diff --git a/Makefile.inc b/Makefile.inc
@@ -1217,6 +1217,10 @@ cbfs-files-$(CONFIG_HAVE_RAMSTAGE) += $(CONFIG_CBFS_PREFIX)/ramstage
 $(CONFIG_CBFS_PREFIX)/ramstage-file := $(RAMSTAGE)
 $(CONFIG_CBFS_PREFIX)/ramstage-type := stage
 $(CONFIG_CBFS_PREFIX)/ramstage-compression := $(CBFS_COMPRESS_FLAG)
+# The AMD LPC SPI DMA controller requires source files to be 64 byte aligned.
+ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y)
+$(CONFIG_CBFS_PREFIX)/ramstage-align := 64
+endif
 
 cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode
 $(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB)

diff --git a/configs/config.pcengines_apu1 b/configs/config.pcengines_apu1
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.14.0.6"
+CONFIG_LOCALVERSION="v4.15.0.1"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_CBFS_SIZE=0x00200000
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"

diff --git a/configs/config.pcengines_apu2 b/configs/config.pcengines_apu2
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.14.0.6"
+CONFIG_LOCALVERSION="v4.15.0.1"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_PXE_ROM_ID="8086,157b"

diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu3
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.14.0.6"
+CONFIG_LOCALVERSION="v4.15.0.1"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_PXE_ROM_ID="8086,1539"

diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_apu4
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.14.0.6"
+CONFIG_LOCALVERSION="v4.15.0.1"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_PXE_ROM_ID="8086,1539"

diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu5
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.14.0.6"
+CONFIG_LOCALVERSION="v4.15.0.1"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_PXE_ROM_ID="8086,1539"

diff --git a/configs/config.pcengines_apu6 b/configs/config.pcengines_apu6
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.14.0.6"
+CONFIG_LOCALVERSION="v4.15.0.1"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_PXE_ROM_ID="8086,1539"

diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc
@@ -201,10 +201,12 @@ payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd tianocore: $(DOTCONFI
 		CONFIG_TIANOCORE_BOOTSPLASH_FILE=$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
 		CONFIG_TIANOCORE_UEFIPAYLOAD=$(CONFIG_TIANOCORE_UEFIPAYLOAD) \
 		CONFIG_TIANOCORE_UPSTREAM=$(CONFIG_TIANOCORE_UPSTREAM) \
-		CONFIG_MMCONF_BASE_ADDRESS=$(CONFIG_MMCONF_BASE_ADDRESS) \
+		CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \
 		CONFIG_TIANOCORE_ABOVE_4G_MEMORY=$(CONFIG_TIANOCORE_ABOVE_4G_MEMORY) \
 		CONFIG_TIANOCORE_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) \
 		CONFIG_TIANOCORE_CBMEM_LOGGING=$(CONFIG_TIANOCORE_CBMEM_LOGGING) \
+		CONFIG_TIANOCORE_COREBOOTPAYLOAD=$(CONFIG_TIANOCORE_COREBOOTPAYLOAD) \
+		CONFIG_TIANOCORE_USE_8254_TIMER=$(CONFIG_TIANOCORE_USE_8254_TIMER) \
 		GCC_CC_x86_32=$(GCC_CC_x86_32) \
 		GCC_CC_x86_64=$(GCC_CC_x86_64) \
 		GCC_CC_arm=$(GCC_CC_arm) \

diff --git a/payloads/external/tianocore/Kconfig b/payloads/external/tianocore/Kconfig
@@ -14,6 +14,9 @@ choice
 	  UefiPayload: MrChromebox's customized fork of Tianocore which works on most
 	  x86_64 devices
 	  Upstream: Use upstream Tianocore payload from https://github.com/tianocore/edk2
+	  CorebootPayload: MrChromebox's customized fork of the deprecated CorebootPayloadPkg
+	  Tianocore build target. It may work better on some older hardware (eg, x230)
+	  which does not work properly with the UefiPayloadPkg options.
 
 config TIANOCORE_UEFIPAYLOAD
 	bool "UEFIPayload"
@@ -26,6 +29,12 @@ config TIANOCORE_UPSTREAM
 	help
 	  Select this option if you want to use upstream EDK2 to build Tianocore.
 
+config TIANOCORE_COREBOOTPAYLOAD
+	bool "CorebootPayload"
+	help
+	  Select this option to build using MrChromebox's older (now deprecated)
+	  CorebootPayloadPkg-based Tianocore branch
+
 endchoice
 
 config TIANOCORE_REVISION_ID
@@ -105,6 +114,15 @@ config TIANOCORE_ABOVE_4G_MEMORY
 
 endif
 
+if TIANOCORE_COREBOOTPAYLOAD
+
+config TIANOCORE_USE_8254_TIMER
+	bool "TianoCore 8254 Timer"
+	help
+	  Use 8254 Timer for legacy support.
+
+endif
+
 config TIANOCORE_BOOT_TIMEOUT
 	int
 	default 2

diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile
@@ -9,7 +9,14 @@ project_git_repo=https://github.com/3mdeb/edk2
 project_git_branch=coreboot-4.7.x-uefi
 upstream_git_repo=https://github.com/tianocore/edk2
 
-build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_MMCONF_BASE_ADDRESS) -DPS2_KEYBOARD_ENABLE
+build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) -DPS2_KEYBOARD_ENABLE
+
+ifeq ($(CONFIG_TIANOCORE_COREBOOTPAYLOAD),y)
+project_git_branch=coreboot_fb
+bootloader=CorebootPayloadPkg
+else
+bootloader=UefiPayloadPkg
+endif
 
 ifeq ($(CONFIG_TIANOCORE_UPSTREAM),y)
 TAG=upstream/master
@@ -41,7 +48,15 @@ endif
 
 TIMEOUT=-D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT)
 
+ifneq ($(CONFIG_TIANOCORE_USE_8254_TIMER), y)
+TIMER=-DUSE_HPET_TIMER
+endif
+
+ifeq ($(CONFIG_TIANOCORE_COREBOOTPAYLOAD),y)
+BUILD_STR=-q -a IA32 -a X64 -p CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -t COREBOOT -b $(BUILD_TYPE) $(TIMER) -DPS2_KEYBOARD_ENABLE
+else
 BUILD_STR=-q -a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc -t COREBOOT -b $(BUILD_TYPE) $(TIMEOUT) $(build_flavor) $(CBMEM) $(4G)
+endif
 
 all: clean build
 
@@ -99,7 +114,7 @@ build: update checktools
 			cat ../tools_def.txt >> $(project_dir)/Conf/tools_def.txt; \
 		fi; \
 		build $(BUILD_STR); \
-		mv $(project_dir)/Build/UefiPayloadPkg*/*/FV/UEFIPAYLOAD.fd $(project_dir)/Build/UEFIPAYLOAD.fd; \
+		mv $(project_dir)/Build/$(bootloader)*/*/FV/UEFIPAYLOAD.fd $(project_dir)/Build/UEFIPAYLOAD.fd; \
 		git checkout MdeModulePkg/Logo/Logo.bmp > /dev/null 2>&1 || true
 
 clean:

diff --git a/payloads/libpayload/include/mock/arch/io.h b/payloads/libpayload/include/mock/arch/io.h
@@ -26,4 +26,21 @@ void write16(volatile void *addr, uint16_t val);
 void write32(volatile void *addr, uint32_t val);
 void write64(volatile void *addr, uint64_t val);
 
+/* x86 I/O functions */
+unsigned int inl(int port);
+unsigned short inw(int port);
+unsigned char inb(int port);
+
+void outl(unsigned int val, int port);
+void outw(unsigned short val, int port);
+void outb(unsigned char val, int port);
+
+void outsl(int port, const void *addr, unsigned long count);
+void outsw(int port, const void *addr, unsigned long count);
+void outsb(int port, const void *addr, unsigned long count);
+
+void insl(int port, void *addr, unsigned long count);
+void insw(int port, void *addr, unsigned long count);
+void insb(int port, void *addr, unsigned long count);
+
 #endif /* _ARCH_IO_H */
diff --git a/payloads/libpayload/tests/drivers/Makefile.inc b/payloads/libpayload/tests/drivers/Makefile.inc
@@ -6,4 +6,3 @@ speaker-test-srcs += tests/drivers/speaker-test.c
 speaker-test-mocks += inb
 speaker-test-mocks += outb
 speaker-test-mocks += arch_ndelay
-speaker-test-cflags += -include $(testsrc)/include/mocks/x86_io.h
diff --git a/payloads/libpayload/tests/drivers/speaker-test.c b/payloads/libpayload/tests/drivers/speaker-test.c
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <libpayload.h>
-#include <mocks/x86_io.h>
 
 /* Include source to gain access to private defines */
 #include "../drivers/speaker.c"

diff --git a/payloads/libpayload/tests/include/mocks/x86_io.h b/payloads/libpayload/tests/include/mocks/x86_io.h
diff --git a/spd/lp5/memory_parts.json b/spd/lp5/memory_parts.json
@@ -0,0 +1,34 @@
+{
+    "parts": [
+        {
+            "name": "MT62F512M32D2DR-031 WT:B",
+            "attribs": {
+                "densityPerDieGb": 8,
+                "diesPerPackage": 2,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 1,
+                "speedMbps": 6400
+            }
+        },
+        {
+            "name": "MT62F1G32D4DR-031 WT:B",
+            "attribs": {
+                "densityPerDieGb": 8,
+                "diesPerPackage": 4,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 2,
+                "speedMbps": 6400
+            }
+        },
+        {
+            "name": "H9JCNNNCP3MLYR-N6E",
+            "attribs": {
+                "densityPerDieGb": 8,
+                "diesPerPackage": 4,
+                "bitWidthPerChannel": 16,
+                "ranksPerChannel": 2,
+                "speedMbps": 6400
+            }
+        }
+    ]
+}
diff --git a/spd/lp5/platforms_manifest.generated.txt b/spd/lp5/platforms_manifest.generated.txt
@@ -0,0 +1,4 @@
+# Generated by:
+# util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
+
+ADL,set-0
diff --git a/spd/lp5/set-0/parts_spd_manifest.generated.txt b/spd/lp5/set-0/parts_spd_manifest.generated.txt
@@ -0,0 +1,6 @@
+# Generated by:
+# util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
+
+MT62F512M32D2DR-031 WT:B,spd-1.hex
+MT62F1G32D4DR-031 WT:B,spd-2.hex
+H9JCNNNCP3MLYR-N6E,spd-2.hex
diff --git a/spd/lp5/set-0/spd-1.hex b/spd/lp5/set-0/spd-1.hex
@@ -0,0 +1,32 @@
+23 10 13 0E 15 1A 95 08 00 00 00 00 02 01 00 00
+00 00 0A 00 00 00 00 00 AA 00 90 A8 90 90 06 C0
+03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/spd/lp5/set-0/spd-2.hex b/spd/lp5/set-0/spd-2.hex
@@ -0,0 +1,32 @@
+23 10 13 0E 15 1A B5 08 00 00 00 00 0A 01 00 00
+00 00 0A 00 00 00 00 00 AA 00 90 A8 90 90 06 C0
+03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/spd/lp5/set-0/spd-empty.hex b/spd/lp5/set-0/spd-empty.hex
@@ -0,0 +1,32 @@
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/Kconfig b/src/Kconfig
@@ -395,6 +395,16 @@ config FW_CONFIG
 	  Enable support for probing devices with fw_config.  This is a simple
 	  bitmask broken into fields and options for probing.
 
+config FW_CONFIG_SOURCE_CHROMEEC_CBI
+	bool "Obtain Firmware Configuration value from Google Chrome EC CBI"
+	depends on FW_CONFIG && EC_GOOGLE_CHROMEEC
+	default n
+	help
+	  This option tells coreboot to read the firmware configuration value
+	  from the Google Chrome Embedded Controller CBI interface.  This source
+	  is not tried if FW_CONFIG_SOURCE_CBFS is enabled and the value was
+	  found in CBFS.
+
 config FW_CONFIG_SOURCE_CBFS
 	bool "Obtain Firmware Configuration value from CBFS"
 	depends on FW_CONFIG
@@ -403,17 +413,18 @@ config FW_CONFIG_SOURCE_CBFS
 	  With this option enabled coreboot will look for the 32bit firmware
 	  configuration value in CBFS at the selected prefix with the file name
 	  "fw_config".  This option will override other sources and allow the
-	  local image to preempt the mainboard selected source.
+	  local image to preempt the mainboard selected source and can be used as
+	  FW_CONFIG_SOURCE_CHROMEEC_CBI fallback option.
 
-config FW_CONFIG_SOURCE_CHROMEEC_CBI
-	bool "Obtain Firmware Configuration value from Google Chrome EC CBI"
-	depends on FW_CONFIG && EC_GOOGLE_CHROMEEC
+config FW_CONFIG_SOURCE_VPD
+	bool "Obtain Firmware Configuration value from VPD"
+	depends on FW_CONFIG && VPD
 	default n
 	help
-	  This option tells coreboot to read the firmware configuration value
-	  from the Google Chrome Embedded Controller CBI interface.  This source
-	  is not tried if FW_CONFIG_SOURCE_CBFS is enabled and the value was
-	  found in CBFS.
+	  With this option enabled coreboot will look for the 32bit firmware
+	  configuration value in VPD key name "fw_config".  This option will
+	  override other sources and allow the local image to preempt the mainboard
+	  selected source and can be used for other FW_CONFIG_SOURCEs fallback option.
 
 config HAVE_RAMPAYLOAD
 	bool
@@ -677,12 +688,12 @@ config TIMER_QUEUE
 
 config COOP_MULTITASKING
 	def_bool n
-	depends on TIMER_QUEUE && ARCH_X86 && CPU_INFO_V2
+	select TIMER_QUEUE
+	depends on ARCH_X86 && CPU_INFO_V2
 	help
 	  Cooperative multitasking allows callbacks to be multiplexed on the
-	  main thread of ramstage. With this enabled it allows for multiple
-	  execution paths to take place when they have udelay() calls within
-	  their code.
+	  main thread. With this enabled it allows for multiple execution paths
+	  to take place when they have udelay() calls within their code.
 
 config NUM_THREADS
 	int
@@ -785,6 +796,21 @@ config GENERATE_SMBIOS_TABLES
 
 	  If unsure, say Y.
 
+config SMBIOS_TYPE41_PROVIDED_BY_DEVTREE
+	bool
+	depends on ARCH_X86
+	help
+	  If enabled, only generate SMBIOS Type 41 entries for PCI devices in
+	  the devicetree for which Type 41 information is provided, e.g. with
+	  the `smbios_dev_info` devicetree syntax. This is useful to manually
+	  assign specific instance IDs to onboard devices irrespective of the
+	  device traversal order. It is assumed that instance IDs for devices
+	  of the same class are unique.
+	  When disabled, coreboot autogenerates SMBIOS Type 41 entries for all
+	  appropriate PCI devices in the devicetree. Instance IDs are assigned
+	  successive numbers from a monotonically increasing counter, with one
+	  counter for each device class.
+
 config SMBIOS_PROVIDED_BY_MOBO
 	bool
 	default n
@@ -1153,7 +1179,7 @@ config DEBUG_INTEL_ME
 endif
 
 config DEBUG_FUNC
-	bool "Enable function entry and exit reporting macros" if DEFAULT_CONSOLE_LOGLEVEL_8
+	bool "Enable function entry and exit reporting macros" if DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL
 	default n
 	help
 	  This option enables additional function entry and exit debug messages

diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c
@@ -266,7 +266,8 @@ void acpi_create_madt(acpi_madt_t *madt)
 static unsigned long acpi_fill_mcfg(unsigned long current)
 {
 	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
-			CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1);
+			CONFIG_ECAM_MMCONF_BASE_ADDRESS, 0, 0,
+			CONFIG_ECAM_MMCONF_BUS_NUMBER - 1);
 	return current;
 }
 
@@ -291,7 +292,7 @@ void acpi_create_mcfg(acpi_mcfg_t *mcfg)
 	header->length = sizeof(acpi_mcfg_t);
 	header->revision = get_acpi_table_revision(MCFG);
 
-	if (CONFIG(MMCONF_SUPPORT))
+	if (CONFIG(ECAM_MMCONF_SUPPORT))
 		current = acpi_fill_mcfg(current);
 
 	/* (Re)calculate length and checksum. */
@@ -1248,7 +1249,7 @@ unsigned long acpi_write_dbg2_pci_uart(acpi_rsdp_t *rsdp, unsigned long current,
 		printk(BIOS_INFO, "%s: Device not enabled\n", __func__);
 		return current;
 	}
-	res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	res = probe_resource(dev, PCI_BASE_ADDRESS_0);
 	if (!res) {
 		printk(BIOS_ERR, "%s: Unable to find resource for %s\n",
 		       __func__, dev_path(dev));

diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c
@@ -2020,35 +2020,6 @@ void acpigen_write_rom(void *bios, const size_t length)
 	acpigen_pop_len();
 }
 
-/* Soc-implemented functions -- weak definitions. */
-int __weak acpigen_soc_read_rx_gpio(unsigned int gpio_num)
-{
-	printk(BIOS_ERR, "ERROR: %s not implemented\n", __func__);
-	acpigen_write_debug_string("read_rx_gpio not available");
-	return -1;
-}
-
-int __weak acpigen_soc_get_tx_gpio(unsigned int gpio_num)
-{
-	printk(BIOS_ERR, "ERROR: %s not implemented\n", __func__);
-	acpigen_write_debug_string("get_tx_gpio not available");
-	return -1;
-}
-
-int __weak acpigen_soc_set_tx_gpio(unsigned int gpio_num)
-{
-	printk(BIOS_ERR, "ERROR: %s not implemented\n", __func__);
-	acpigen_write_debug_string("set_tx_gpio not available");
-	return -1;
-}
-
-int __weak acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
-{
-	printk(BIOS_ERR, "ERROR: %s not implemented\n", __func__);
-	acpigen_write_debug_string("clear_tx_gpio not available");
-	return -1;
-}
-
 /*
  * Helper functions for enabling/disabling Tx GPIOs based on the GPIO
  * polarity. These functions end up calling acpigen_soc_{set,clear}_tx_gpio to

diff --git a/src/acpi/dsdt_top.asl b/src/acpi/dsdt_top.asl
@@ -31,13 +31,13 @@ Method (_PIC, 1)
 	PICM = Arg0
 }
 
-#if CONFIG(MMCONF_SUPPORT)
+#if CONFIG(ECAM_MMCONF_SUPPORT)
 Scope(\_SB) {
 	/* Base address of PCIe config space */
-	Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)
+	Name(PCBA, CONFIG_ECAM_MMCONF_BASE_ADDRESS)
 
 	/* Length of PCIe config space, 1MB each bus */
-	Name(PCLN, CONFIG_MMCONF_LENGTH)
+	Name(PCLN, CONFIG_ECAM_MMCONF_LENGTH)
 
 	/* PCIe Configuration Space */
 	OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */

diff --git a/src/arch/arm/include/armv4/arch/smp/spinlock.h b/src/arch/arm/include/armv4/arch/smp/spinlock.h
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
@@ -43,6 +43,13 @@ cbfs-files-$(CONFIG_VGA_BIOS_DGPU) += pci$(stripped_vgabios_dgpu_id).rom
 pci$(stripped_vgabios_dgpu_id).rom-file := $(call strip_quotes,$(CONFIG_VGA_BIOS_DGPU_FILE))
 pci$(stripped_vgabios_dgpu_id).rom-type := optionrom
 
+# The AMD LPC SPI DMA controller requires source files to be 64 byte aligned.
+ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA),y)
+pci$(stripped_vgabios_id).rom-align := 64
+pci$(stripped_second_vbios_id).rom-align := 64
+pci$(stripped_vgabios_dgpu_id).rom-align := 64
+endif # CONFIG_SOC_AMD_COMMON_BLOCK_LPC_SPI_DMA
+
 ###############################################################################
 # common support for early assembly includes
 ###############################################################################

diff --git a/src/arch/x86/include/arch/pci_io_cfg.h b/src/arch/x86/include/arch/pci_io_cfg.h
@@ -69,7 +69,7 @@ void pci_io_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value)
 	outl(value, 0xCFC);
 }
 
-#if !CONFIG(MMCONF_SUPPORT)
+#if !CONFIG(ECAM_MMCONF_SUPPORT)
 
 /* Avoid name collisions as different stages have different signature
  * for these functions. The _s_ stands for simple, fundamental IO or

diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h
@@ -4,6 +4,8 @@
 #define ARCH_I386_PCI_OPS_H
 
 #include <arch/pci_io_cfg.h>
+#if CONFIG(ECAM_MMCONF_SUPPORT)
 #include <device/pci_mmio_cfg.h>
+#endif
 
 #endif /* ARCH_I386_PCI_OPS_H */
diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h
@@ -15,10 +15,6 @@ typedef struct {
 
 #define SPIN_LOCK_UNLOCKED { 1 }
 
-#define STAGE_HAS_SPINLOCKS !ENV_ROMSTAGE_OR_BEFORE
-
-#if STAGE_HAS_SPINLOCKS
-
 #define DECLARE_SPIN_LOCK(x)	\
 	static spinlock_t x = SPIN_LOCK_UNLOCKED;
 
@@ -71,14 +67,4 @@ static __always_inline void spin_unlock(spinlock_t *lock)
 		: "=m" (lock->lock) : : "memory");
 }
 
-#else
-
-#define DECLARE_SPIN_LOCK(x)
-#define spin_is_locked(lock)	0
-#define spin_unlock_wait(lock)	do {} while (0)
-#define spin_lock(lock)		do {} while (0)
-#define spin_unlock(lock)	do {} while (0)
-
-#endif
-
 #endif /* ARCH_SMP_SPINLOCK_H */
diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c
@@ -224,6 +224,9 @@ static int create_smbios_type17_for_dimm(struct dimm_info *dimm,
 					 unsigned long *current, int *handle,
 					 int type16_handle)
 {
+	struct spd_info info;
+	get_spd_info(dimm->ddr_type, dimm->mod_type, &info);
+
 	struct smbios_type17 *t = smbios_carve_table(*current, SMBIOS_MEMORY_DEVICE,
 						     sizeof(*t), *handle);
 
@@ -244,24 +247,7 @@ static int create_smbios_type17_for_dimm(struct dimm_info *dimm,
 	}
 	t->data_width = 8 * (1 << (dimm->bus_width & 0x7));
 	t->total_width = t->data_width + 8 * ((dimm->bus_width & 0x18) >> 3);
-
-	switch (dimm->mod_type) {
-	case SPD_RDIMM:
-	case SPD_MINI_RDIMM:
-		t->form_factor = MEMORY_FORMFACTOR_RIMM;
-		break;
-	case SPD_UDIMM:
-	case SPD_MICRO_DIMM:
-	case SPD_MINI_UDIMM:
-		t->form_factor = MEMORY_FORMFACTOR_DIMM;
-		break;
-	case SPD_SODIMM:
-		t->form_factor = MEMORY_FORMFACTOR_SODIMM;
-		break;
-	default:
-		t->form_factor = MEMORY_FORMFACTOR_UNKNOWN;
-		break;
-	}
+	t->form_factor = info.form_factor;
 
 	smbios_fill_dimm_manufacturer_from_id(dimm->mod_id, t);
 	smbios_fill_dimm_serial_number(dimm, t);
@@ -278,19 +264,8 @@ static int create_smbios_type17_for_dimm(struct dimm_info *dimm,
 	t->maximum_voltage = dimm->vdd_voltage;
 
 	/* Fill in type detail */
-	switch (dimm->mod_type) {
-	case SPD_RDIMM:
-	case SPD_MINI_RDIMM:
-		t->type_detail = MEMORY_TYPE_DETAIL_REGISTERED;
-		break;
-	case SPD_UDIMM:
-	case SPD_MINI_UDIMM:
-		t->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED;
-		break;
-	default:
-		t->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
-		break;
-	}
+	t->type_detail = info.type_detail;
+
 	/* Synchronous = 1 */
 	t->type_detail |= MEMORY_TYPE_DETAIL_SYNCHRONOUS;
 	/* no handle for error information */
@@ -1177,30 +1152,55 @@ static u8 smbios_get_device_type_from_dev(struct device *dev)
 	}
 }
 
-static int smbios_generate_type41_from_devtree(struct device *dev, int *handle,
-					       unsigned long *current)
+static bool smbios_get_type41_instance_id(struct device *dev, u8 device_type, u8 *instance_id)
 {
+#if CONFIG(SMBIOS_TYPE41_PROVIDED_BY_DEVTREE)
+	*instance_id = dev->smbios_instance_id;
+	return dev->smbios_instance_id_valid;
+#else
 	static u8 type41_inst_cnt[SMBIOS_DEVICE_TYPE_COUNT + 1] = {};
 
+	if (device_type == SMBIOS_DEVICE_TYPE_OTHER ||
+	    device_type == SMBIOS_DEVICE_TYPE_UNKNOWN)
+		return false;
+
+	if (device_type > SMBIOS_DEVICE_TYPE_COUNT)
+		return false;
+
+	*instance_id = type41_inst_cnt[device_type]++;
+	return true;
+#endif
+}
+
+static const char *smbios_get_type41_refdes(struct device *dev)
+{
+#if CONFIG(SMBIOS_TYPE41_PROVIDED_BY_DEVTREE)
+	if (dev->smbios_refdes)
+		return dev->smbios_refdes;
+#endif
+	return get_pci_subclass_name(dev);
+}
+
+static int smbios_generate_type41_from_devtree(struct device *dev, int *handle,
+					       unsigned long *current)
+{
 	if (dev->path.type != DEVICE_PATH_PCI)
 		return 0;
 	if (!dev->on_mainboard)
 		return 0;
 
-	u8 device_type = smbios_get_device_type_from_dev(dev);
+	const u8 device_type = smbios_get_device_type_from_dev(dev);
 
-	if (device_type == SMBIOS_DEVICE_TYPE_OTHER ||
-	    device_type == SMBIOS_DEVICE_TYPE_UNKNOWN)
-		return 0;
+	u8 instance_id;
 
-	if (device_type > SMBIOS_DEVICE_TYPE_COUNT)
+	if (!smbios_get_type41_instance_id(dev, device_type, &instance_id))
 		return 0;
 
-	const char *name = get_pci_subclass_name(dev);
+	const char *name = smbios_get_type41_refdes(dev);
 
 	return smbios_write_type41(current, handle,
 					name, // name
-					type41_inst_cnt[device_type]++, // inst
+					instance_id, // inst
 					0, // segment
 					dev->bus->secondary, //bus
 					PCI_SLOT(dev->path.pci.devfn), // device

diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc
@@ -22,6 +22,9 @@ smm-y += region.c
 postcar-y += region.c
 
 ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp_relocate.c
+ifeq ($(CONFIG_FSP_M_XIP),)
+romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c
+endif
 ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp_relocate.c
 
 bootblock-y += cbfs.c

diff --git a/src/commonlib/include/commonlib/mem_pool.h b/src/commonlib/include/commonlib/mem_pool.h
@@ -3,6 +3,7 @@
 #ifndef _MEM_POOL_H_
 #define _MEM_POOL_H_
 
+#include <assert.h>
 #include <stddef.h>
 #include <stdint.h>
 
@@ -16,23 +17,23 @@
  * were chosen to optimize for the CBFS cache case which may need two buffers
  * to map a single compressed file, and will free them in reverse order.)
  *
- * The memory returned by allocations are at least 8 byte aligned. Note
- * that this requires the backing buffer to start on at least an 8 byte
- * alignment.
+ * You must ensure the backing buffer is 'alignment' aligned.
  */
 
 struct mem_pool {
 	uint8_t *buf;
 	size_t size;
+	size_t alignment;
 	uint8_t *last_alloc;
 	uint8_t *second_to_last_alloc;
 	size_t free_offset;
 };
 
-#define MEM_POOL_INIT(buf_, size_)		\
+#define MEM_POOL_INIT(buf_, size_, alignment_)	\
 	{					\
 		.buf = (buf_),			\
 		.size = (size_),		\
+		.alignment = (alignment_),	\
 		.last_alloc = NULL,		\
 		.second_to_last_alloc = NULL,	\
 		.free_offset = 0,		\
@@ -46,10 +47,15 @@ static inline void mem_pool_reset(struct mem_pool *mp)
 }
 
 /* Initialize a memory pool. */
-static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz)
+static inline void mem_pool_init(struct mem_pool *mp, void *buf, size_t sz,
+					 size_t alignment)
 {
+	assert(alignment);
+	assert((uintptr_t)buf % alignment == 0);
+
 	mp->buf = buf;
 	mp->size = sz;
+	mp->alignment = alignment;
 	mem_pool_reset(mp);
 }
 

diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h
@@ -157,6 +157,17 @@ static inline int rdev_chain_full(struct region_device *child,
 	return rdev_chain(child, parent, 0, region_device_sz(parent));
 }
 
+/*
+ * Returns < 0 on error otherwise returns size of data read at provided
+ * offset filling in the buffer passed.
+ *
+ * You must ensure the buffer is large enough to hold the full region_device.
+ */
+static inline ssize_t rdev_readat_full(const struct region_device *rd, void *b)
+{
+	return rdev_readat(rd, b, 0, region_device_sz(rd));
+}
+
 /*
  * Compute relative offset of the child (c) w.r.t. the parent (p). Returns < 0
  * when child is not within the parent's region.

diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h
@@ -56,6 +56,8 @@ enum timestamp_id {
 	TS_DELAY_END = 111,
 	TS_READ_UCODE_START = 112,
 	TS_READ_UCODE_END = 113,
+	TS_ELOG_INIT_START = 114,
+	TS_ELOG_INIT_END = 115,
 
 	/* 500+ reserved for vendorcode extensions (500-600: google/chromeos) */
 	TS_START_COPYVER = 501,
@@ -113,6 +115,11 @@ enum timestamp_id {
 	TS_ME_INFORM_DRAM_DONE = 941,
 	TS_ME_BEFORE_END_OF_POST = 942,
 	TS_ME_AFTER_END_OF_POST = 943,
+	TS_ME_BOOT_STALL_DONE = 944,
+	TS_ME_ICC_CONFIG_START = 945,
+	TS_ME_HOST_BOOT_PREP_DONE = 946,
+	TS_ME_RECEIVED_CRDA_FROM_PMC = 947,
+	TS_FIT_UCODE_LOADED = 948,
 
 	/* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */
 	TS_FSP_MEMORY_INIT_START = 950,
@@ -195,6 +202,8 @@ static const struct timestamp_id_to_name {
 	{ TS_DELAY_END,		"Forced delay end" },
 	{ TS_READ_UCODE_START,	"started reading uCode" },
 	{ TS_READ_UCODE_END,	"finished reading uCode" },
+	{ TS_ELOG_INIT_START,	"started elog init" },
+	{ TS_ELOG_INIT_END,	"finished elog init" },
 
 	{ TS_START_COPYVER,	"starting to load verstage" },
 	{ TS_END_COPYVER,	"finished loading verstage" },
@@ -267,6 +276,11 @@ static const struct timestamp_id_to_name {
 	{ TS_ME_INFORM_DRAM_DONE,	"finished waiting for ME response"},
 	{ TS_ME_BEFORE_END_OF_POST,	"before sending EOP to ME"},
 	{ TS_ME_AFTER_END_OF_POST,	"after sending EOP to ME"},
+	{ TS_ME_BOOT_STALL_DONE,	"CSE sent 'Boot Stall Done' to PMC"},
+	{ TS_ME_ICC_CONFIG_START,	"CSE started to handle ICC configuration"},
+	{ TS_ME_HOST_BOOT_PREP_DONE,	"CSE sent 'Host BIOS Prep Done' to PMC"},
+	{ TS_ME_RECEIVED_CRDA_FROM_PMC,	"CSE received 'CPU Reset Done Ack sent' from PMC"},
+	{ TS_FIT_UCODE_LOADED,		"CPU has loaded UCODE/PCODE from FIT"},
 
 	/* FSP related timestamps */
 	{ TS_FSP_MEMORY_INIT_START, "calling FspMemoryInit" },

diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c
@@ -7,8 +7,11 @@ void *mem_pool_alloc(struct mem_pool *mp, size_t sz)
 {
 	void *p;
 
-	/* Make all allocations be at least 8 byte aligned. */
-	sz = ALIGN_UP(sz, 8);
+	if (mp->alignment == 0)
+		return NULL;
+
+	/* We assume that mp->buf started mp->alignment aligned */
+	sz = ALIGN_UP(sz, mp->alignment);
 
 	/* Determine if any space available. */
 	if ((mp->size - mp->free_offset) < sz)

diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig
@@ -3,11 +3,3 @@
 config CPU_AMD_AGESA_FAMILY14
 	bool
 	select X86_AMD_FIXED_MTRRS
-
-if CPU_AMD_AGESA_FAMILY14
-
-config CPU_ADDR_BITS
-	int
-	default 36
-
-endif
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c
@@ -25,9 +25,7 @@ static void model_14_init(struct device *dev)
 	disable_cache();
 	/*
 	 * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set
-	 * by coreboot. The amd_setup_mtrrs should work, but needs debug on fam14.
-	 * TODO:
-	 * amd_setup_mtrrs();
+	 * by coreboot.
 	 */
 
 	/* Enable access to AMD RdDram and WrDram extension bits */

diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig
@@ -4,11 +4,3 @@ config CPU_AMD_AGESA_FAMILY15_TN
 	bool
 	select IDS_OPTIONS_HOOKED_UP
 	select X86_AMD_FIXED_MTRRS
-
-if CPU_AMD_AGESA_FAMILY15_TN
-
-config CPU_ADDR_BITS
-	int
-	default 48
-
-endif
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -25,9 +25,10 @@ static void model_15_init(struct device *dev)
 	u32 siblings;
 #endif
 
-	//enable_cache();
-	//amd_setup_mtrrs();
-	//x86_mtrr_check();
+	/*
+	 * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set
+	 * by coreboot.
+	 */
 	disable_cache();
 	/* Enable access to AMD RdDram and WrDram extension bits */
 	msr = rdmsr(SYSCFG_MSR);

diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig
@@ -6,10 +6,6 @@ config CPU_AMD_AGESA_FAMILY16_KB
 
 if CPU_AMD_AGESA_FAMILY16_KB
 
-config CPU_ADDR_BITS
-	int
-	default 40
-
 config FORCE_AM1_SOCKET_SUPPORT
 	bool
 	default n

diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c
@@ -23,9 +23,10 @@ static void model_16_init(struct device *dev)
 	u32 siblings;
 #endif
 
-	//enable_cache();
-	//amd_setup_mtrrs();
-	//x86_mtrr_check();
+	/*
+	 * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set
+	 * by coreboot.
+	 */
 	disable_cache();
 	/* Enable access to AMD RdDram and WrDram extension bits */
 	msr = rdmsr(SYSCFG_MSR);

diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -3,72 +3,11 @@
 #include <amdblocks/biosram.h>
 #include <console/console.h>
 #include <device/device.h>
-#include <arch/cpu.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
-#include <cpu/x86/cache.h>
-
-/* These will likely move to some device node or cbmem. */
-static uint64_t amd_topmem = 0;
-static uint64_t amd_topmem2 = 0;
-
-uint64_t bsp_topmem(void)
-{
-	return amd_topmem;
-}
-
-uint64_t bsp_topmem2(void)
-{
-	return amd_topmem2;
-}
-
-/* Take a copy of BSP CPUs TOP_MEM and TOP_MEM2 registers,
- * so they can be distributed to AP CPUs. Not strictly MTRRs,
- * but this is not that bad a place to have this code.
- */
-void setup_bsp_ramtop(void)
-{
-	msr_t msr, msr2;
-
-	/* TOP_MEM: the top of DRAM below 4G */
-	msr = rdmsr(TOP_MEM);
-	printk(BIOS_INFO,
-	    "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
-	     __func__, msr.lo, msr.hi);
-
-	/* TOP_MEM2: the top of DRAM above 4G */
-	msr2 = rdmsr(TOP_MEM2);
-	printk(BIOS_INFO,
-	    "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
-	     __func__, msr2.lo, msr2.hi);
-
-	amd_topmem = (uint64_t) msr.hi << 32 | msr.lo;
-	amd_topmem2 = (uint64_t) msr2.hi << 32 | msr2.lo;
-}
-
-static void setup_ap_ramtop(void)
-{
-	msr_t msr;
-	uint64_t v;
-
-	v = bsp_topmem();
-	if (!v)
-		return;
-
-	msr.hi = v >> 32;
-	msr.lo = (uint32_t) v;
-	wrmsr(TOP_MEM, msr);
-
-	v = bsp_topmem2();
-	msr.hi = v >> 32;
-	msr.lo = (uint32_t) v;
-	wrmsr(TOP_MEM2, msr);
-}
 
 void add_uma_resource_below_tolm(struct device *nb, int idx)
 {
-	uint32_t topmem = bsp_topmem();
+	uint32_t topmem = amd_topmem();
 	uint32_t top_of_cacheable = restore_top_of_low_cacheable();
 
 	if (top_of_cacheable == topmem)
@@ -82,79 +21,3 @@ void add_uma_resource_below_tolm(struct device *nb, int idx)
 
 	uma_resource(nb, idx, uma_base / KiB, uma_size / KiB);
 }
-
-void amd_setup_mtrrs(void)
-{
-	unsigned long address_bits;
-	unsigned long i;
-	msr_t msr, sys_cfg;
-	// Test if this CPU is a Fam 0Fh rev. F or later
-	const int cpu_id = cpuid_eax(0x80000001);
-	printk(BIOS_SPEW, "CPU ID 0x80000001: %x\n", cpu_id);
-	const int has_tom2wb =
-		// ExtendedFamily > 0
-		 (((cpu_id>>20)&0xf) > 0) ||
-		// Family == 0F
-		((((cpu_id>>8)&0xf) == 0xf) &&
-		// Rev>=F deduced from rev tables
-		 (((cpu_id>>16)&0xf) >= 0x4));
-	if (has_tom2wb)
-		printk(BIOS_DEBUG, "CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB\n");
-
-	/* Enable the access to AMD RdDram and WrDram extension bits */
-	disable_cache();
-	sys_cfg = rdmsr(SYSCFG_MSR);
-	sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramModEn;
-	wrmsr(SYSCFG_MSR, sys_cfg);
-	enable_cache();
-
-	/* Setup fixed MTRRs, but do not enable them just yet. */
-	x86_setup_fixed_mtrrs_no_enable();
-
-	disable_cache();
-
-	setup_ap_ramtop();
-
-	/* if DRAM above 4GB: set SYSCFG_MSR_TOM2En and SYSCFG_MSR_TOM2WB */
-	sys_cfg.lo &= ~(SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB);
-	if (bsp_topmem2() > (uint64_t)1 << 32) {
-		sys_cfg.lo |= SYSCFG_MSR_TOM2En;
-		if (has_tom2wb)
-			sys_cfg.lo |= SYSCFG_MSR_TOM2WB;
-	}
-
-	/* zero the IORR's before we enable to prevent
-	 * undefined side effects.
-	 */
-	msr.lo = msr.hi = 0;
-	for (i = MTRR_IORR0_BASE; i <= MTRR_IORR1_MASK; i++)
-		wrmsr(i, msr);
-
-	/* Enable Variable Mtrrs
-	 * Enable the RdMem and WrMem bits in the fixed mtrrs.
-	 * Disable access to the RdMem and WrMem in the fixed mtrr.
-	 */
-	sys_cfg.lo |= SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn;
-	sys_cfg.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
-	wrmsr(SYSCFG_MSR, sys_cfg);
-
-	enable_fixed_mtrr();
-
-	enable_cache();
-
-	//K8 could be 40, and GH could be 48
-	address_bits = CONFIG_CPU_ADDR_BITS;
-
-	/* AMD specific cpuid function to query number of address bits */
-	if (cpuid_eax(0x80000000) >= 0x80000008)
-		address_bits = cpuid_eax(0x80000008) & 0xff;
-
-	/* Now that I have mapped what is memory and what is not
-	 * Set up the mtrrs so we can cache the memory.
-	 */
-
-	// Rev. F K8 supports has SYSCFG_MSR_TOM2WB and doesn't need
-	// variable MTRR to span memory above 4GB
-	// Lower revisions K8 need variable MTRR over 4GB
-	x86_setup_var_mtrrs(address_bits, has_tom2wb ? 0 : 1);
-}
diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig
@@ -5,11 +5,3 @@ config CPU_AMD_PI_00730F01
 	select X86_AMD_FIXED_MTRRS
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select MICROCODE_BLOB_UNDISCLOSED
-
-if CPU_AMD_PI_00730F01
-
-config CPU_ADDR_BITS
-	int
-	default 40
-
-endif
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
@@ -588,8 +588,8 @@ static void pre_mp_init(void)
 static int get_cpu_count(void)
 {
 	msr_t msr;
-	int num_threads;
-	int num_cores;
+	unsigned int num_threads;
+	unsigned int num_cores;
 
 	msr = rdmsr(MSR_CORE_THREAD_COUNT);
 	num_threads = (msr.lo >> 0) & 0xffff;

diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
@@ -23,7 +23,7 @@ static void pre_mp_init(void)
 static int get_cpu_count(void)
 {
 	const struct cpuid_result cpuid1 = cpuid(1);
-	const char cores = (cpuid1.ebx >> 16) & 0xf;
+	const unsigned int cores = (cpuid1.ebx >> 16) & 0xf;
 
 	printk(BIOS_DEBUG, "CPU has %u cores.\n", cores);
 

diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig
@@ -11,11 +11,3 @@ config CPU_INTEL_MODEL_106CX
 	select SERIALIZED_SMM_INITIALIZATION
 	select CPU_INTEL_COMMON
 	select CPU_INTEL_COMMON_TIMEBASE
-
-if CPU_INTEL_MODEL_106CX
-
-config CPU_ADDR_BITS
-	int
-	default 32
-
-endif
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c
@@ -124,8 +124,8 @@ static void pre_mp_init(void)
 static int get_cpu_count(void)
 {
 	msr_t msr;
-	int num_threads;
-	int num_cores;
+	unsigned int num_threads;
+	unsigned int num_cores;
 
 	msr = rdmsr(MSR_CORE_THREAD_COUNT);
 	num_threads = (msr.lo >> 0) & 0xffff;

diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -380,8 +380,8 @@ static void pre_mp_init(void)
 static int get_cpu_count(void)
 {
 	msr_t msr;
-	int num_threads;
-	int num_cores;
+	unsigned int num_threads;
+	unsigned int num_cores;
 
 	msr = rdmsr(MSR_CORE_THREAD_COUNT);
 	num_threads = (msr.lo >> 0) & 0xffff;

diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
@@ -90,10 +90,6 @@ config SETUP_XIP_CACHE
 	  non-eviction mode and therefore need to be careful to avoid
 	  eviction.
 
-config CPU_ADDR_BITS
-	int
-	default 36
-
 config LOGICAL_CPUS
 	bool
 	default y

diff --git a/src/device/Kconfig b/src/device/Kconfig
@@ -499,13 +499,21 @@ config PCI
 
 if PCI
 
-config NO_MMCONF_SUPPORT
+config NO_ECAM_MMCONF_SUPPORT
 	bool
 	default n
+	help
+	  Disable the use of the Enhanced Configuration
+	  Access mechanism (ECAM) method for accessing PCI config
+	  address space.
 
-config MMCONF_SUPPORT
+config ECAM_MMCONF_SUPPORT
 	bool
-	default !NO_MMCONF_SUPPORT
+	default !NO_ECAM_MMCONF_SUPPORT
+	help
+	  Enable the use of the Enhanced Configuration
+	  Access mechanism (ECAM) method for accessing PCI config
+	  address space.
 
 config PCIX_PLUGIN_SUPPORT
 	bool
@@ -540,20 +548,20 @@ config PCIEXP_PLUGIN_SUPPORT
 	bool
 	default y
 
-config MMCONF_BASE_ADDRESS
+config ECAM_MMCONF_BASE_ADDRESS
 	hex
-	depends on MMCONF_SUPPORT
+	depends on ECAM_MMCONF_SUPPORT
 
-config MMCONF_BUS_NUMBER
+config ECAM_MMCONF_BUS_NUMBER
 	int
-	depends on MMCONF_SUPPORT
+	depends on ECAM_MMCONF_SUPPORT
 
-config MMCONF_LENGTH
+config ECAM_MMCONF_LENGTH
 	hex
-	depends on MMCONF_SUPPORT
-	default 0x04000000 if MMCONF_BUS_NUMBER = 64
-	default 0x08000000 if MMCONF_BUS_NUMBER = 128
-	default 0x10000000 if MMCONF_BUS_NUMBER = 256
+	depends on ECAM_MMCONF_SUPPORT
+	default 0x04000000 if ECAM_MMCONF_BUS_NUMBER = 64
+	default 0x08000000 if ECAM_MMCONF_BUS_NUMBER = 128
+	default 0x10000000 if ECAM_MMCONF_BUS_NUMBER = 256
 	default 0x0
 
 config PCI_ALLOW_BUS_MASTER
@@ -619,7 +627,7 @@ config PCIEXP_CLK_PM
 config PCIEXP_L1_SUB_STATE
 	prompt "Enable PCIe ASPM L1 SubState"
 	bool
-	depends on (MMCONF_SUPPORT || PCI_IO_CFG_EXT)
+	depends on (ECAM_MMCONF_SUPPORT || PCI_IO_CFG_EXT)
 	default n
 	help
 	  Detect and enable ASPM on PCIe links.
@@ -635,8 +643,8 @@ if PCIEXP_HOTPLUG
 
 config PCIEXP_HOTPLUG_BUSES
 	int "PCI Express Hotplug Buses"
-	default  8 if MMCONF_SUPPORT && MMCONF_BUS_NUMBER <=  64
-	default 16 if MMCONF_SUPPORT && MMCONF_BUS_NUMBER <= 128
+	default  8 if ECAM_MMCONF_SUPPORT && ECAM_MMCONF_BUS_NUMBER <=  64
+	default 16 if ECAM_MMCONF_SUPPORT && ECAM_MMCONF_BUS_NUMBER <= 128
 	default 32
 	help
 	  This is the number of buses allocated for hotplug PCI express

diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c
@@ -227,7 +227,7 @@ __weak void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid)
 {
 }
 
-static void codec_init(struct device *dev, u8 *base, int addr)
+void azalia_codec_init(u8 *base, int addr, const u32 *verb_table, u32 verb_table_bytes)
 {
 	u32 reg32;
 	const u32 *verb;
@@ -252,7 +252,7 @@ static void codec_init(struct device *dev, u8 *base, int addr)
 	/* 2 */
 	reg32 = read32(base + HDA_IR_REG);
 	printk(BIOS_DEBUG, "azalia_audio: codec viddid: %08x\n", reg32);
-	verb_size = azalia_find_verb(cim_verb_data, cim_verb_data_size, reg32, &verb);
+	verb_size = azalia_find_verb(verb_table, verb_table_bytes, reg32, &verb);
 
 	if (!verb_size) {
 		printk(BIOS_DEBUG, "azalia_audio: No verb!\n");
@@ -261,19 +261,22 @@ static void codec_init(struct device *dev, u8 *base, int addr)
 	printk(BIOS_DEBUG, "azalia_audio: verb_size: %u\n", verb_size);
 
 	/* 3 */
-	azalia_program_verb_table(base, verb, verb_size);
-	printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n");
+	const int rc = azalia_program_verb_table(base, verb, verb_size);
+	if (rc < 0)
+		printk(BIOS_DEBUG, "azalia_audio: verb not loaded.\n");
+	else
+		printk(BIOS_DEBUG, "azalia_audio: verb loaded.\n");
 
 	mainboard_azalia_program_runtime_verbs(base, reg32);
 }
 
-static void codecs_init(struct device *dev, u8 *base, u16 codec_mask)
+void azalia_codecs_init(u8 *base, u16 codec_mask)
 {
 	int i;
 
 	for (i = CONFIG_AZALIA_MAX_CODECS - 1; i >= 0; i--) {
 		if (codec_mask & (1 << i))
-			codec_init(dev, base, i);
+			azalia_codec_init(base, i, cim_verb_data, cim_verb_data_size);
 	}
 
 	azalia_program_verb_table(base, pc_beep_verbs, pc_beep_verbs_size);
@@ -285,7 +288,7 @@ void azalia_audio_init(struct device *dev)
 	struct resource *res;
 	u16 codec_mask;
 
-	res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	res = probe_resource(dev, PCI_BASE_ADDRESS_0);
 	if (!res)
 		return;
 
@@ -297,7 +300,7 @@ void azalia_audio_init(struct device *dev)
 
 	if (codec_mask) {
 		printk(BIOS_DEBUG, "azalia_audio: codec_mask = %02x\n", codec_mask);
-		codecs_init(dev, base, codec_mask);
+		azalia_codecs_init(base, codec_mask);
 	}
 }
 

diff --git a/src/device/device_util.c b/src/device/device_util.c
@@ -857,8 +857,8 @@ void fixed_io_resource(struct device *dev, unsigned long index,
 void mmconf_resource(struct device *dev, unsigned long index)
 {
 	struct resource *resource = new_resource(dev, index);
-	resource->base = CONFIG_MMCONF_BASE_ADDRESS;
-	resource->size = CONFIG_MMCONF_LENGTH;
+	resource->base = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
+	resource->size = CONFIG_ECAM_MMCONF_LENGTH;
 	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
 		IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 

diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c
@@ -545,19 +545,19 @@ enum cb_err spd_add_smbios17(const u8 channel, const u8 slot,
 
 		switch (info->dimm_type) {
 		case SPD_DDR3_DIMM_TYPE_SO_DIMM:
-			dimm->mod_type = SPD_SODIMM;
+			dimm->mod_type = DDR3_SPD_SODIMM;
 			break;
 		case SPD_DDR3_DIMM_TYPE_72B_SO_CDIMM:
-			dimm->mod_type = SPD_72B_SO_CDIMM;
+			dimm->mod_type = DDR3_SPD_72B_SO_CDIMM;
 			break;
 		case SPD_DDR3_DIMM_TYPE_72B_SO_RDIMM:
-			dimm->mod_type = SPD_72B_SO_RDIMM;
+			dimm->mod_type = DDR3_SPD_72B_SO_RDIMM;
 			break;
 		case SPD_DDR3_DIMM_TYPE_UDIMM:
-			dimm->mod_type = SPD_UDIMM;
+			dimm->mod_type = DDR3_SPD_UDIMM;
 			break;
 		case SPD_DDR3_DIMM_TYPE_RDIMM:
-			dimm->mod_type = SPD_RDIMM;
+			dimm->mod_type = DDR3_SPD_RDIMM;
 			break;
 		case SPD_DDR3_DIMM_TYPE_UNDEFINED:
 		default:

diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c
@@ -299,16 +299,16 @@ enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot, const u16 sel
 
 		switch (info->dimm_type) {
 		case SPD_DDR4_DIMM_TYPE_SO_DIMM:
-			dimm->mod_type = SPD_SODIMM;
+			dimm->mod_type = DDR4_SPD_SODIMM;
 			break;
 		case SPD_DDR4_DIMM_TYPE_72B_SO_RDIMM:
-			dimm->mod_type = SPD_72B_SO_RDIMM;
+			dimm->mod_type = DDR4_SPD_72B_SO_RDIMM;
 			break;
 		case SPD_DDR4_DIMM_TYPE_UDIMM:
-			dimm->mod_type = SPD_UDIMM;
+			dimm->mod_type = DDR4_SPD_UDIMM;
 			break;
 		case SPD_DDR4_DIMM_TYPE_RDIMM:
-			dimm->mod_type = SPD_RDIMM;
+			dimm->mod_type = DDR4_SPD_RDIMM;
 			break;
 		default:
 			dimm->mod_type = SPD_UNDEFINED;

diff --git a/src/device/dram/spd.c b/src/device/dram/spd.c
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
 #include <device/dram/spd.h>
+#include <spd.h>
 
 const char *spd_manufacturer_name(const uint16_t mod_id)
 {
@@ -38,3 +39,219 @@ const char *spd_manufacturer_name(const uint16_t mod_id)
 		return NULL;
 	}
 }
+
+static void convert_default_module_type_to_spd_info(struct spd_info *info)
+{
+	info->form_factor = MEMORY_FORMFACTOR_UNKNOWN;
+	info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
+}
+
+static void convert_ddr2_module_type_to_spd_info(enum ddr2_module_type module_type,
+		struct spd_info *info)
+{
+	switch (module_type) {
+	case DDR2_SPD_RDIMM:
+	case DDR2_SPD_MINI_RDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_RIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED;
+		break;
+	case DDR2_SPD_UDIMM:
+	case DDR2_SPD_MINI_UDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_DIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED;
+		break;
+	case DDR2_SPD_MICRO_DIMM:
+		info->form_factor = MEMORY_FORMFACTOR_DIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
+		break;
+	case DDR2_SPD_SODIMM:
+		info->form_factor = MEMORY_FORMFACTOR_SODIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
+		break;
+	default:
+		convert_default_module_type_to_spd_info(info);
+		break;
+	}
+}
+
+static void convert_ddr3_module_type_to_spd_info(enum ddr3_module_type module_type,
+		struct spd_info *info)
+{
+	switch (module_type) {
+	case DDR3_SPD_RDIMM:
+	case DDR3_SPD_MINI_RDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_RIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED;
+		break;
+	case DDR3_SPD_UDIMM:
+	case DDR3_SPD_MINI_UDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_DIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED;
+		break;
+	case DDR3_SPD_MICRO_DIMM:
+		info->form_factor = MEMORY_FORMFACTOR_DIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
+		break;
+	case DDR3_SPD_SODIMM:
+	case DDR3_SPD_72B_SO_UDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_SODIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
+		break;
+	default:
+		convert_default_module_type_to_spd_info(info);
+		break;
+	}
+}
+
+static void convert_ddr4_module_type_to_spd_info(enum ddr4_module_type module_type,
+		struct spd_info *info)
+{
+	switch (module_type) {
+	case DDR4_SPD_RDIMM:
+	case DDR4_SPD_MINI_RDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_RIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED;
+		break;
+	case DDR4_SPD_UDIMM:
+	case DDR4_SPD_MINI_UDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_DIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED;
+		break;
+	case DDR4_SPD_SODIMM:
+	case DDR4_SPD_72B_SO_UDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_SODIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
+		break;
+	default:
+		convert_default_module_type_to_spd_info(info);
+		break;
+	}
+}
+
+static void convert_ddr5_module_type_to_spd_info(enum ddr5_module_type module_type,
+		struct spd_info *info)
+{
+	switch (module_type) {
+	case DDR5_SPD_RDIMM:
+	case DDR5_SPD_MINI_RDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_RIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_REGISTERED;
+		break;
+	case DDR5_SPD_UDIMM:
+	case DDR5_SPD_MINI_UDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_DIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNBUFFERED;
+		break;
+	case DDR5_SPD_SODIMM:
+	case DDR5_SPD_72B_SO_UDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_SODIMM;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
+		break;
+	case DDR5_SPD_2DPC:
+		info->form_factor = MEMORY_FORMFACTOR_PROPRIETARY_CARD;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
+		break;
+	default:
+		convert_default_module_type_to_spd_info(info);
+		break;
+	}
+}
+
+static void convert_lpx_module_type_to_spd_info(enum lpx_module_type module_type,
+		struct spd_info *info)
+{
+	switch (module_type) {
+	case LPX_SPD_NONDIMM:
+		info->form_factor = MEMORY_FORMFACTOR_ROC;
+		info->type_detail = MEMORY_TYPE_DETAIL_UNKNOWN;
+		break;
+	default:
+		convert_default_module_type_to_spd_info(info);
+		break;
+	}
+}
+
+void get_spd_info(smbios_memory_type memory_type, uint8_t module_type, struct spd_info *info)
+{
+	switch (memory_type) {
+	case MEMORY_TYPE_DDR2:
+		convert_ddr2_module_type_to_spd_info(module_type, info);
+		break;
+	case MEMORY_TYPE_DDR3:
+		convert_ddr3_module_type_to_spd_info(module_type, info);
+		break;
+	case MEMORY_TYPE_DDR4:
+		convert_ddr4_module_type_to_spd_info(module_type, info);
+		break;
+	case MEMORY_TYPE_DDR5:
+		convert_ddr5_module_type_to_spd_info(module_type, info);
+		break;
+	case MEMORY_TYPE_LPDDR3:
+	case MEMORY_TYPE_LPDDR4:
+	case MEMORY_TYPE_LPDDR5:
+		convert_lpx_module_type_to_spd_info(module_type, info);
+		break;
+	default:
+		convert_default_module_type_to_spd_info(info);
+		break;
+	}
+}
+
+static uint8_t convert_default_form_factor_to_module_type(void)
+{
+	return SPD_UNDEFINED;
+}
+
+static uint8_t convert_ddrx_form_factor_to_module_type(smbios_memory_type memory_type,
+		smbios_memory_form_factor form_factor)
+{
+	uint8_t module_type;
+
+	switch (form_factor) {
+	case MEMORY_FORMFACTOR_DIMM:
+		return DDR2_SPD_UDIMM;
+	case MEMORY_FORMFACTOR_RIMM:
+		return DDR2_SPD_RDIMM;
+	case MEMORY_FORMFACTOR_SODIMM:
+		module_type = (memory_type == MEMORY_TYPE_DDR2) ? DDR2_SPD_SODIMM
+				: DDR3_SPD_SODIMM;
+		return module_type;
+	default:
+		return convert_default_form_factor_to_module_type();
+	}
+}
+
+static uint8_t convert_lpx_form_factor_to_module_type(smbios_memory_form_factor form_factor)
+{
+	switch (form_factor) {
+	case MEMORY_FORMFACTOR_ROC:
+		return LPX_SPD_NONDIMM;
+	default:
+		return convert_default_form_factor_to_module_type();
+	}
+}
+
+uint8_t convert_form_factor_to_module_type(smbios_memory_type memory_type,
+		smbios_memory_form_factor form_factor)
+{
+	uint8_t module_type;
+
+	switch (memory_type) {
+	case MEMORY_TYPE_DDR2:
+	case MEMORY_TYPE_DDR3:
+	case MEMORY_TYPE_DDR4:
+	case MEMORY_TYPE_DDR5:
+		module_type = convert_ddrx_form_factor_to_module_type(memory_type, form_factor);
+		break;
+	case MEMORY_TYPE_LPDDR3:
+	case MEMORY_TYPE_LPDDR4:
+	case MEMORY_TYPE_LPDDR5:
+		module_type = convert_lpx_form_factor_to_module_type(form_factor);
+		break;
+	default:
+		module_type = convert_default_form_factor_to_module_type();
+		break;
+	}
+
+	return module_type;
+}
diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c
@@ -7,7 +7,7 @@
 #include <device/pci_ops.h>
 #include <device/pci_type.h>
 
-u8 *const pci_mmconf = (void *)(uintptr_t)CONFIG_MMCONF_BASE_ADDRESS;
+u8 *const pci_mmconf = (void *)(uintptr_t)CONFIG_ECAM_MMCONF_BASE_ADDRESS;
 
 /**
  * Given a device, a capability type, and a last position, return the next

diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c
@@ -16,6 +16,21 @@
 void __weak map_oprom_vendev_rev(u32 *vendev, u8 *rev) { return; }
 u32 __weak map_oprom_vendev(u32 vendev) { return vendev; }
 
+void vga_oprom_preload(void)
+{
+/* The CONFIG_VGA_BIOS_ID symbol is only defined when VGA_BIOS is selected */
+#if CONFIG(VGA_BIOS)
+	const char name[] = "pci" CONFIG_VGA_BIOS_ID ".rom";
+
+	if (!CONFIG(CBFS_PRELOAD))
+		return;
+
+	printk(BIOS_DEBUG, "Preloading VGA ROM %s\n", name);
+
+	cbfs_preload(name);
+#endif
+}
+
 static void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device)
 {
 	char name[17] = "pciXXXX,XXXX.rom";

diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c
@@ -36,22 +36,18 @@ static void romstage_main(void)
 	struct postcar_frame pcf;
 	struct sysinfo romstage_state;
 	struct sysinfo *cb = &romstage_state;
-	unsigned int initial_apic_id = initial_lapicid();
 	int cbmem_initted = 0;
 
 	fill_sysinfo(cb);
 
-	if (initial_apic_id == 0) {
+	timestamp_add_now(TS_START_ROMSTAGE);
 
-		timestamp_add_now(TS_START_ROMSTAGE);
+	board_BeforeAgesa(cb);
 
-		board_BeforeAgesa(cb);
-
-		console_init();
-	}
+	console_init();
 
 	printk(BIOS_DEBUG, "APIC %02u: CPU Family_Model = %08x\n",
-		initial_apic_id, cpuid_eax(1));
+	       initial_lapicid(), cpuid_eax(1));
 
 	set_ap_entry_ptr(ap_romstage_main);
 

diff --git a/src/drivers/aspeed/common/ast_mode_corebootfb.c b/src/drivers/aspeed/common/ast_mode_corebootfb.c
@@ -22,7 +22,7 @@ int ast_crtc_do_set_base(struct drm_crtc *crtc)
 	struct drm_framebuffer *fb = crtc->primary->fb;
 
 	/* PCI BAR 0 */
-	struct resource *res = find_resource(crtc->dev->pdev, PCI_BASE_ADDRESS_0);
+	struct resource *res = probe_resource(crtc->dev->pdev, PCI_BASE_ADDRESS_0);
 	if (!res) {
 		printk(BIOS_ERR, "BAR0 resource not found.\n");
 		return -EIO;

diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c
@@ -16,6 +16,7 @@
 #include <smbios.h>
 #include <stdint.h>
 #include <string.h>
+#include <timestamp.h>
 
 #define ELOG_MIN_AVAILABLE_ENTRIES	2  /* Shrink when this many can't fit */
 #define ELOG_SHRINK_PERCENTAGE		25 /* Percent of total area to remove */
@@ -749,6 +750,9 @@ int elog_init(void)
 	}
 	elog_state.elog_initialized = ELOG_BROKEN;
 
+	if (!ENV_SMM)
+		timestamp_add_now(TS_ELOG_INIT_START);
+
 	elog_debug("%s()\n", __func__);
 
 	/* Set up the backing store */
@@ -781,6 +785,10 @@ int elog_init(void)
 
 	if (ENV_PAYLOAD_LOADER)
 		elog_add_boot_count();
+
+	if (!ENV_SMM)
+		timestamp_add_now(TS_ELOG_INIT_END);
+
 	return 0;
 }
 

diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S
@@ -181,7 +181,7 @@ CAR_init_done:
 	pushl	%eax	/* tsc[31:0] */
 
 before_romstage:
-	post_code(0x2A)
+	post_code(0x2a)
 
 	/* Call bootblock_c_entry(uint64_t base_timestamp) */
 	call	bootblock_c_entry

diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
@@ -18,7 +18,6 @@
 #include <stage_cache.h>
 #include <string.h>
 #include <timestamp.h>
-#include <vendorcode/google/chromeos/chromeos.h>
 
 static void raminit_common(struct romstage_params *params)
 {
@@ -104,9 +103,9 @@ void cache_as_ram_stage_main(FSP_INFO_HEADER *fih)
 	timestamp_add_now(TS_START_ROMSTAGE);
 
 	/* Display parameters */
-	if (!CONFIG(NO_MMCONF_SUPPORT))
-		printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n",
-			CONFIG_MMCONF_BASE_ADDRESS);
+	if (!CONFIG(NO_ECAM_MMCONF_SUPPORT))
+		printk(BIOS_SPEW, "CONFIG_ECAM_MMCONF_BASE_ADDRESS: 0x%08x\n",
+			CONFIG_ECAM_MMCONF_BASE_ADDRESS);
 	printk(BIOS_INFO, "Using FSP 1.1\n");
 
 	/* Display FSP banner */

diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
@@ -218,6 +218,16 @@ config FSP_COMPRESS_FSP_M_LZ4
 	bool
 	depends on !FSP_M_XIP
 
+config FSP_ALIGNMENT_FSP_S
+	int
+	help
+	  Sets the CBFS alignment for FSP-S
+
+config FSP_ALIGNMENT_FSP_M
+	int
+	help
+	  Sets the CBFS alignment for FSP-M
+
 config FSP_M_ADDR
 	hex
 	help

diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc
@@ -65,6 +65,9 @@ endif
 ifeq ($(CONFIG_FSP_COMPRESS_FSP_M_LZ4),y)
 $(FSP_M_CBFS)-compression := LZ4
 endif
+ifneq ($(CONFIG_FSP_ALIGNMENT_FSP_M),)
+$(FSP_M_CBFS)-align := $(CONFIG_FSP_ALIGNMENT_FSP_M)
+endif
 
 cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(FSP_S_CBFS)
 $(FSP_S_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_S_FILE))
@@ -75,6 +78,9 @@ endif
 ifeq ($(CONFIG_FSP_COMPRESS_FSP_S_LZ4),y)
 $(FSP_S_CBFS)-compression := LZ4
 endif
+ifneq ($(CONFIG_FSP_ALIGNMENT_FSP_S),)
+$(FSP_S_CBFS)-align := $(CONFIG_FSP_ALIGNMENT_FSP_S)
+endif
 
 ifeq ($(CONFIG_FSP_FULL_FD),y)
 $(obj)/Fsp_M.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) $(DOTCONFIG)

diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -32,7 +32,9 @@ enum fsp_notify_phase {
 };
 
 /* Main FSP stages */
+void preload_fspm(void);
 void fsp_memory_init(bool s3wake);
+void preload_fsps(void);
 void fsp_silicon_init(void);
 
 /*

diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
@@ -340,6 +340,15 @@ static void *fspm_allocator(void *arg, size_t size, const union cbfs_mdata *unus
 	return (void *)fspm_begin;
 }
 
+void preload_fspm(void)
+{
+	if (!CONFIG(CBFS_PRELOAD))
+		return;
+
+	printk(BIOS_DEBUG, "Preloading %s\n", CONFIG_FSP_M_CBFS);
+	cbfs_preload(CONFIG_FSP_M_CBFS);
+}
+
 void fsp_memory_init(bool s3wake)
 {
 	struct range_entry prog_ranges[2];

diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c
@@ -94,9 +94,22 @@ efi_return_status_t mp_startup_all_cpus(efi_ap_procedure procedure,
 	/* Run on BSP */
 	procedure(argument);
 
-	/* Run on APs */
-	if (mp_run_on_aps((void *)procedure, argument,
-			MP_RUN_ON_ALL_CPUS, timeout_usec) != CB_SUCCESS) {
+	/*
+	 * Run on APs Serially
+	 *
+	 * FIXME: As per MP service specification, EDK2 is allowed to specify the mode
+	 * in which a 'func' routine should be executed on APs (i.e. execute serially
+	 * or concurrently).
+	 *
+	 * MP service API `StartupAllCPUs` doesn't specify such requirement.
+	 * Hence, running the `CpuCacheInfoCollectCoreAndCacheData`
+	 * (UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c#194)
+	 * simultaneously on APs results in a coherency issue (hang while executing `func`)
+	 * due to lack of acquiring a spin lock while accessing common data structure in
+	 * multiprocessor environment.
+	 */
+	if (mp_run_on_all_aps((void *)procedure, argument, timeout_usec, false) !=
+				CB_SUCCESS) {
 		printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__);
 		return FSP_NOT_STARTED;
 	}

diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -230,6 +230,15 @@ void fsps_load(void)
 	load_done = 1;
 }
 
+void preload_fsps(void)
+{
+	if (!CONFIG(CBFS_PRELOAD))
+		return;
+
+	printk(BIOS_DEBUG, "Preloading %s\n", CONFIG_FSP_S_CBFS);
+	cbfs_preload(CONFIG_FSP_S_CBFS);
+}
+
 void fsp_silicon_init(void)
 {
 	timestamp_add_now(TS_FSP_SILICON_INIT_LOAD);

diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c
@@ -163,8 +163,8 @@ enum cb_err fsp_load_component(struct fsp_load_descriptor *fspld, struct fsp_hea
 	if (!dest)
 		return CB_ERR;
 
-	/* Don't allow FSP-M relocation. */
-	if (!fspm_env() && fsp_component_relocate((uintptr_t)dest, dest, output_size) < 0) {
+	/* Don't allow FSP-M relocation when XIP. */
+	if (!fspm_xip() && fsp_component_relocate((uintptr_t)dest, dest, output_size) < 0) {
 		printk(BIOS_ERR, "Unable to relocate FSP component!\n");
 		return CB_ERR;
 	}

diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c
@@ -847,6 +847,9 @@ static void write_i2c_camera_device(const struct device *dev, const char *scope)
 	acpigen_write_name_integer("_UID", config->acpi_uid);
 	acpigen_write_name_string("_DDN", config->chip_name);
 	acpigen_write_STA(acpi_device_status(dev));
+	acpigen_write_method("_DSC", 0);
+	acpigen_write_return_integer(config->max_dstate_for_probe);
+	acpigen_pop_len(); /* Method _DSC */
 
 	/* Resources */
 	acpigen_write_name("_CRS");

diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h
@@ -257,6 +257,17 @@ struct drivers_intel_mipi_camera_config {
 	bool has_power_resource;
 	/* Perform low power probe */
 	bool low_power_probe;
+	/*
+	 * This will create a _DSC method in ACPI which returns an integer, to tell the kernel
+	 * the highest allowed D state for a device during probe
+	 * Number   State   Description
+	 * 0	    D0	    Device fully powered on
+	 * 1	    D1
+	 * 2	    D2
+	 * 3	    D3hot
+	 * 4	    D3cold  Off
+	 */
+	uint8_t max_dstate_for_probe;
 };
 
 #endif
diff --git a/src/drivers/net/Kconfig b/src/drivers/net/Kconfig
@@ -38,6 +38,13 @@ config RT8168_SET_LED_MODE
 	  Configuration for details. With this flag enabled, the
 	  customized_leds variable will be read from devicetree setting.
 
+config RT8168_GEN_ACPI_POWER_RESOURCE
+	bool
+	default n
+	depends on REALTEK_8168_RESET
+	help
+	  Select this if an ACPI power resource needs to be generated.
+
 config ATHEROS_ATL1E_SETMAC
 	bool
 	help

diff --git a/src/drivers/net/atl1e.c b/src/drivers/net/atl1e.c
@@ -106,7 +106,7 @@ static int atl1e_eeprom_exist(u32 mem_base)
 static void atl1e_init(struct device *dev)
 {
 	/* Get the resource of the NIC mmio */
-	struct resource *nic_res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	struct resource *nic_res = probe_resource(dev, PCI_BASE_ADDRESS_0);
 
 	if (nic_res == NULL) {
 		printk(BIOS_ERR, "atl1e: resource not found\n");

diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c
@@ -317,7 +317,7 @@ static void r8168_net_fill_ssdt(const struct device *dev)
 		acpigen_write_name_string("_DDN", dev->chip_ops->name);
 
 	/* Power Resource */
-	if (config->has_power_resource) {
+	if (CONFIG(RT8168_GEN_ACPI_POWER_RESOURCE) && config->has_power_resource) {
 		const struct acpi_power_res_params power_res_params = {
 			.stop_gpio = &config->stop_gpio,
 			.stop_delay_ms = config->stop_delay_ms,

diff --git a/src/drivers/parade/ps8640/ps8640.c b/src/drivers/parade/ps8640/ps8640.c
@@ -5,7 +5,7 @@
 #include <edid.h>
 #include <console/console.h>
 #include <timer.h>
-
+#include <dp_aux.h>
 #include "ps8640.h"
 
 int ps8640_get_edid(uint8_t bus, uint8_t chip, struct edid *out)
@@ -80,3 +80,101 @@ int ps8640_init(uint8_t bus, uint8_t chip)
 
 	return 0;
 }
+
+static cb_err_t ps8640_bridge_aux_request(uint8_t bus,
+					  uint8_t chip,
+					  unsigned int target_reg,
+					  unsigned int total_size,
+					  enum aux_request request,
+					  uint8_t *data)
+{
+	int i;
+	uint32_t length;
+	uint8_t buf;
+	uint8_t reg;
+	int ret;
+
+	if (target_reg & ~SWAUX_ADDR_MASK)
+		return CB_ERR;
+
+	while (total_size) {
+		length = MIN(total_size, DP_AUX_MAX_PAYLOAD_BYTES);
+		total_size -= length;
+
+		ret = i2c_writeb(bus, chip, PAGE0_AUXCH_CFG3, AUXCH_CFG3_RESET);
+		if (ret)
+			return CB_ERR;
+
+		enum i2c_over_aux cmd = dp_get_aux_cmd(request, total_size);
+		if (i2c_writeb(bus, chip, PAGE0_SWAUX_ADDR_23_16,
+			(target_reg >> 16) | (cmd << 4)) ||
+		    i2c_writeb(bus, chip, PAGE0_SWAUX_ADDR_15_8, target_reg >> 8) ||
+		    i2c_writeb(bus, chip, PAGE0_SWAUX_ADDR_7_0, target_reg)) {
+			return CB_ERR;
+		}
+
+		if (dp_aux_request_is_write(request)) {
+			reg = PAGE0_SWAUX_WDATA;
+			for (i = 0; i < length; i++) {
+				ret = i2c_writeb(bus, chip, reg++, *data++);
+				if (ret)
+					return CB_ERR;
+			}
+		} else {
+			if (length == 0)
+				i2c_writeb(bus, chip, PAGE0_SWAUX_LENGTH, SWAUX_NO_PAYLOAD);
+			else
+				i2c_writeb(bus, chip, PAGE0_SWAUX_LENGTH, length - 1);
+		}
+
+		ret = i2c_writeb(bus, chip, PAGE0_SWAUX_CTRL, SWAUX_SEND);
+		if (ret)
+			return CB_ERR;
+
+		if (!wait_ms(100, !i2c_readb(bus, chip, PAGE0_SWAUX_CTRL, &buf) &&
+				  !(buf & SWAUX_SEND)))
+			return CB_ERR;
+
+		if (i2c_readb(bus, chip, PAGE0_SWAUX_STATUS, &buf))
+			return CB_ERR;
+
+		switch (buf & SWAUX_STATUS_MASK) {
+		case SWAUX_STATUS_NACK:
+		case SWAUX_STATUS_I2C_NACK:
+		case SWAUX_STATUS_INVALID:
+		case SWAUX_STATUS_TIMEOUT:
+			return CB_ERR;
+		case SWAUX_STATUS_ACKM:
+			length = buf & SWAUX_M_MASK;
+			break;
+		}
+
+		if (length && !dp_aux_request_is_write(request)) {
+			reg = PAGE0_SWAUX_RDATA;
+			for (i = 0; i < length; i++) {
+				if (i2c_readb(bus, chip, reg++, &buf))
+					return CB_ERR;
+				*data++ = buf;
+			}
+		}
+	}
+
+	return CB_SUCCESS;
+}
+
+void ps8640_backlight_enable(uint8_t bus, uint8_t chip)
+{
+	uint8_t val;
+
+	val = DP_BACKLIGHT_CONTROL_MODE_DPCD;
+	ps8640_bridge_aux_request(bus, chip, DP_BACKLIGHT_MODE_SET, 1,
+				  DPCD_WRITE, &val);
+
+	val = 0xff;
+	ps8640_bridge_aux_request(bus, chip, DP_BACKLIGHT_BRIGHTNESS_MSB, 1,
+				  DPCD_WRITE, &val);
+
+	val = DP_BACKLIGHT_ENABLE;
+	ps8640_bridge_aux_request(bus, chip, DP_DISPLAY_CONTROL_REGISTER, 1,
+				  DPCD_WRITE, &val);
+}
diff --git a/src/drivers/parade/ps8640/ps8640.h b/src/drivers/parade/ps8640/ps8640.h
@@ -24,11 +24,33 @@ enum {
 };
 
 enum {
-	EDID_LENGTH         = 128,
-	EDID_I2C_ADDR       = 0x50,
-	EDID_EXTENSION_FLAG = 0x7e,
+	PAGE0_AUXCH_CFG3 = 0x76,
+	AUXCH_CFG3_RESET = 0xff,
+	PAGE0_SWAUX_ADDR_7_0 = 0x7d,
+	PAGE0_SWAUX_ADDR_15_8 = 0x7e,
+	PAGE0_SWAUX_ADDR_23_16 = 0x7f,
+	SWAUX_ADDR_MASK = 0xfffff,
+	PAGE0_SWAUX_LENGTH = 0x80,
+	SWAUX_LENGTH_MASK = 0xf,
+	SWAUX_NO_PAYLOAD = BIT(7),
+	PAGE0_SWAUX_WDATA = 0x81,
+	PAGE0_SWAUX_RDATA = 0x82,
+	PAGE0_SWAUX_CTRL = 0x83,
+	SWAUX_SEND = BIT(0),
+	PAGE0_SWAUX_STATUS = 0x84,
+	SWAUX_M_MASK = 0x1f,
+	SWAUX_STATUS_MASK = (0x7 << 5),
+	SWAUX_STATUS_NACK = (0x1 << 5),
+	SWAUX_STATUS_DEFER = (0x2 << 5),
+	SWAUX_STATUS_ACKM = (0x3 << 5),
+	SWAUX_STATUS_INVALID = (0x4 << 5),
+	SWAUX_STATUS_I2C_NACK = (0x5 << 5),
+	SWAUX_STATUS_I2C_DEFER = (0x6 << 5),
+	SWAUX_STATUS_TIMEOUT = (0x7 << 5),
 };
 
 int ps8640_init(uint8_t bus, uint8_t chip);
 int ps8640_get_edid(uint8_t bus, uint8_t chip, struct edid *out);
+void ps8640_backlight_enable(uint8_t bus, uint8_t chip);
+
 #endif
diff --git a/src/drivers/siemens/nc_fpga/Kconfig b/src/drivers/siemens/nc_fpga/Kconfig
@@ -5,3 +5,8 @@ config DRIVER_SIEMENS_NC_FPGA
 config NC_FPGA_NOTIFY_CB_READY
 	bool
 	default n
+
+config NC_FPGA_POST_CODE
+	bool
+	default n
+	select EARLY_PCI_BRIDGE
diff --git a/src/drivers/siemens/nc_fpga/Makefile.inc b/src/drivers/siemens/nc_fpga/Makefile.inc
@@ -1,3 +1,9 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
 ramstage-$(CONFIG_DRIVER_SIEMENS_NC_FPGA) += nc_fpga.c
+
+all-$(CONFIG_NC_FPGA_POST_CODE) += nc_fpga_early.c
+
+ifeq ($(CONFIG_NC_FPGA_POST_CODE),y)
+CPPFLAGS_common += -I$(src)/drivers/siemens/nc_fpga
+endif
diff --git a/src/drivers/siemens/nc_fpga/nc_fpga.c b/src/drivers/siemens/nc_fpga/nc_fpga.c
@@ -142,9 +142,21 @@ static void set_fw_done(void *unused)
 BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, set_fw_done, NULL);
 #endif
 
+static void nc_fpga_set_resources(struct device *dev)
+{
+	pci_dev_set_resources(dev);
+
+	if (CONFIG(NC_FPGA_POST_CODE)) {
+		/* Re-initialize base address after set_resources for POST display
+		   to work properly.*/
+		nc_fpga_remap(pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xf);
+	}
+}
+
+
 static struct device_operations nc_fpga_ops  = {
 	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
+	.set_resources    = nc_fpga_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init             = nc_fpga_init,
 };

diff --git a/src/drivers/siemens/nc_fpga/nc_fpga.h b/src/drivers/siemens/nc_fpga/nc_fpga.h
@@ -17,6 +17,7 @@
 #define  NC_DIAG_FW_DONE		0x10000
 #define NC_BL_BRIGHTNESS_OFFSET		0x88
 #define NC_BL_PWM_OFFSET		0x8C
+#define NC_FPGA_POST_OFFSET		0xE0
 #define NC_FANMON_CTRL_OFFSET		0x400
 
 #define MAX_NUM_SENSORS			8
@@ -58,4 +59,7 @@ typedef struct {
 	uint32_t	fanmon;
 } __packed fan_ctrl_t;
 
+void nc_fpga_post(uint8_t value);
+void nc_fpga_remap(uint32_t new_mmio);
+
 #endif /* _SIEMENS_NC_FPGA_H_ */
diff --git a/src/drivers/siemens/nc_fpga/nc_fpga_early.c b/src/drivers/siemens/nc_fpga/nc_fpga_early.c
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/mmio.h>
+#include <device/pci.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <types.h>
+
+#include "nc_fpga.h"
+
+static DEVTREE_CONST uint32_t fpga_bar = CONFIG_EARLY_PCI_MMIO_BASE;
+static bool nc_fpga_present = false;
+
+int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base)
+{
+	pci_devfn_t pci_dev = PCI_DEV(bus, dev, 0);
+	uint32_t id = pci_s_read_config32(pci_dev, PCI_VENDOR_ID);
+
+	if (id != (0x4091 << 16 | PCI_VENDOR_ID_SIEMENS))
+		return -1;
+
+	/* Setup base address for BAR0. */
+	pci_s_write_config32(pci_dev, PCI_BASE_ADDRESS_0, mmio_base);
+	/* Enable memory access for pci_dev. */
+	u16 reg16 = pci_s_read_config16(pci_dev, PCI_COMMAND);
+	reg16 |= PCI_COMMAND_MEMORY;
+	pci_s_write_config16(pci_dev, PCI_COMMAND, reg16);
+	nc_fpga_present = true;
+
+	return 0;
+}
+
+void nc_fpga_remap(uint32_t new_mmio)
+{
+#if ENV_RAMSTAGE
+	fpga_bar = new_mmio;
+#endif
+}
+
+void nc_fpga_post(uint8_t value)
+{
+	/* The function pci_earyl_device_probe is called in bootblock and romstage. Make sure
+	   that in these stages the initialization code was successful before the POST code
+	   value is written to the register. */
+	if ((ENV_BOOTBLOCK || ENV_ROMSTAGE) && nc_fpga_present == false)
+		return;
+	write32((void *)(fpga_bar + NC_FPGA_POST_OFFSET), value);
+}
diff --git a/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c b/src/drivers/ti/sn65dsi86bridge/sn65dsi86bridge.c
@@ -4,6 +4,7 @@
 #include <delay.h>
 #include <endian.h>
 #include <device/i2c_simple.h>
+#include <dp_aux.h>
 #include <edid.h>
 #include <timer.h>
 #include <types.h>
@@ -31,14 +32,6 @@
 #define DP_MAX_SUPPORTED_RATES		8 /* 16-bit little-endian */
 #define DP_LANE_COUNT_MASK		0xf
 
-/* Backlight configuration */
-#define DP_BACKLIGHT_MODE_SET			0x721
-#define DP_BACKLIGHT_CONTROL_MODE_MASK		0x3
-#define DP_BACKLIGHT_CONTROL_MODE_DPCD		0x2
-#define DP_DISPLAY_CONTROL_REGISTER		0x720
-#define DP_BACKLIGHT_ENABLE			0x1
-#define DP_BACKLIGHT_BRIGHTNESS_MSB		0x722
-
 /* link configuration */
 #define DP_LINK_BW_SET		0x100
 #define DP_LINK_BW_1_62		0x06
@@ -132,17 +125,6 @@ enum vstream_config {
 	VSTREAM_ENABLE = 1,
 };
 
-enum i2c_over_aux {
-	I2C_OVER_AUX_WRITE_MOT_0 = 0x0,
-	I2C_OVER_AUX_READ_MOT_0 = 0x1,
-	I2C_OVER_AUX_WRITE_STATUS_UPDATE_0 = 0x2,
-	I2C_OVER_AUX_WRITE_MOT_1 = 0x4,
-	I2C_OVER_AUX_READ_MOT_1 = 0x5,
-	I2C_OVER_AUX_WRITE_STATUS_UPDATE_1 = 0x6,
-	NATIVE_AUX_WRITE = 0x8,
-	NATIVE_AUX_READ = 0x9,
-};
-
 enum aux_cmd_status {
 	NAT_I2C_FAIL = 1 << 6,
 	AUX_SHORT = 1 << 5,
@@ -166,21 +148,6 @@ enum ml_tx_mode {
 	REDRIVER_SEMI_AUTO_LINK_TRAINING = 0xb,
 };
 
-enum aux_request {
-	DPCD_READ,
-	DPCD_WRITE,
-	I2C_RAW_READ,
-	I2C_RAW_WRITE,
-	I2C_RAW_READ_AND_STOP,
-	I2C_RAW_WRITE_AND_STOP,
-};
-
-enum {
-	EDID_LENGTH = 128,
-	EDID_I2C_ADDR = 0x50,
-	EDID_EXTENSION_FLAG = 0x7e,
-};
-
 /*
  * LUT index corresponds to register value and LUT values corresponds
  * to dp data rate supported by the bridge in Mbps unit.
@@ -189,41 +156,6 @@ static const unsigned int sn65dsi86_bridge_dp_rate_lut[] = {
 	0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
 };
 
-static bool request_is_write(enum aux_request request)
-{
-	switch (request) {
-	case I2C_RAW_WRITE_AND_STOP:
-	case I2C_RAW_WRITE:
-	case DPCD_WRITE:
-		return true;
-	default:
-		return false;
-	}
-}
-
-static enum i2c_over_aux get_aux_cmd(enum aux_request request, uint32_t remaining_after_this)
-{
-	switch (request) {
-	case I2C_RAW_WRITE_AND_STOP:
-		if (!remaining_after_this)
-			return I2C_OVER_AUX_WRITE_MOT_0;
-		/* fallthrough */
-	case I2C_RAW_WRITE:
-		return I2C_OVER_AUX_WRITE_MOT_1;
-	case I2C_RAW_READ_AND_STOP:
-		if (!remaining_after_this)
-			return I2C_OVER_AUX_READ_MOT_0;
-		/* fallthrough */
-	case I2C_RAW_READ:
-		return I2C_OVER_AUX_READ_MOT_1;
-	case DPCD_WRITE:
-		return NATIVE_AUX_WRITE;
-	case DPCD_READ:
-	default:
-		return NATIVE_AUX_READ;
-	}
-}
-
 static cb_err_t sn65dsi86_bridge_aux_request(uint8_t bus,
 					     uint8_t chip,
 					     unsigned int target_reg,
@@ -241,18 +173,18 @@ static cb_err_t sn65dsi86_bridge_aux_request(uint8_t bus,
 		   NAT_I2C_FAIL | AUX_SHORT | AUX_DFER | AUX_RPLY_TOUT | SEND_INT);
 
 	while (total_size) {
-		length = MIN(total_size, 16);
+		length = MIN(total_size, DP_AUX_MAX_PAYLOAD_BYTES);
 		total_size -= length;
 
-		enum i2c_over_aux cmd = get_aux_cmd(request, total_size);
+		enum i2c_over_aux cmd = dp_get_aux_cmd(request, total_size);
 		if (i2c_writeb(bus, chip, SN_AUX_CMD_REG, (cmd << 4)) ||
 		    i2c_writeb(bus, chip, SN_AUX_ADDR_19_16_REG, (target_reg >> 16) & 0xF) ||
 		    i2c_writeb(bus, chip, SN_AUX_ADDR_15_8_REG, (target_reg >> 8) & 0xFF) ||
 		    i2c_writeb(bus, chip, SN_AUX_ADDR_7_0_REG, (target_reg) & 0xFF) ||
 		    i2c_writeb(bus, chip, SN_AUX_LENGTH_REG, length))
 			return CB_ERR;
 
-		if (request_is_write(request)) {
+		if (dp_aux_request_is_write(request)) {
 			reg = SN_AUX_WDATA_REG_0;
 			for (i = 0; i < length; i++)
 				if (i2c_writeb(bus, chip, reg++, *data++))
@@ -273,7 +205,7 @@ static cb_err_t sn65dsi86_bridge_aux_request(uint8_t bus,
 			return CB_ERR;
 		}
 
-		if (!request_is_write(request)) {
+		if (!dp_aux_request_is_write(request)) {
 			reg = SN_AUX_RDATA_REG_0;
 			for (i = 0; i < length; i++) {
 				if (i2c_readb(bus, chip, reg++, &buf))

diff --git a/src/drivers/uart/oxpcie.c b/src/drivers/uart/oxpcie.c
@@ -12,7 +12,7 @@ static void oxford_oxpcie_enable(struct device *dev)
 {
 	printk(BIOS_DEBUG, "Initializing Oxford OXPCIe952\n");
 
-	struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	struct resource *res = probe_resource(dev, PCI_BASE_ADDRESS_0);
 	if (!res) {
 		printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n");
 		return;

diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c
@@ -75,7 +75,7 @@ static void pci_ehci_set_resources(struct device *dev)
 
 	if (ehci_drv_ops->set_resources)
 		ehci_drv_ops->set_resources(dev);
-	res = find_resource(dev, EHCI_BAR_INDEX);
+	res = probe_resource(dev, EHCI_BAR_INDEX);
 	if (!res)
 		return;
 

diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c
@@ -273,7 +273,7 @@ static void sar_emit_ewrd(const struct sar_profile *sar)
 	 * Emit 'Domain Type' + 'Dynamic SAR Enable' + 'Extended SAR sets count'
 	 * + number of bytes for Set#2 & 3 & 4
 	 */
-	package_size = 1 + 1 + 1 + table_size * sar->dsar_set_count;
+	package_size = 1 + 1 + 1 + table_size * MAX_DSAR_SET_COUNT;
 	acpigen_write_package(package_size);
 	acpigen_write_dword(DOMAIN_TYPE_WIFI);
 	acpigen_write_dword(1);

diff --git a/src/ec/google/chromeec/vboot_storage.c b/src/ec/google/chromeec/vboot_storage.c
@@ -3,7 +3,7 @@
 #include <assert.h>
 #include <console/console.h>
 #include <ec/google/chromeec/ec.h>
-#include <vendorcode/google/chromeos/chromeos.h>
+#include <security/vboot/vboot_common.h>
 
 #define VBOOT_HASH_VSLOT 0
 #define VBOOT_HASH_VSLOT_MASK (1 << (VBOOT_HASH_VSLOT))

diff --git a/src/ec/starlabs/it8987/Kconfig b/src/ec/starlabs/it8987/Kconfig
diff --git a/src/ec/starlabs/it8987/Makefile.inc b/src/ec/starlabs/it8987/Makefile.inc
diff --git a/src/ec/starlabs/it8987/acpi/ac.asl b/src/ec/starlabs/it8987/acpi/ac.asl
diff --git a/src/ec/starlabs/it8987/acpi/battery.asl b/src/ec/starlabs/it8987/acpi/battery.asl
diff --git a/src/ec/starlabs/it8987/acpi/cmos.asl b/src/ec/starlabs/it8987/acpi/cmos.asl