32 changes: 17 additions & 15 deletions MAINTAINERS
View file
@@ -1,6 +1,14 @@


List of maintainers and how to submit coreboot changes
List of upstream coreboot maintainers
and how to submit coreboot changes

This represents the list of maintainers that work on the upstream coreboot
code base (on coreboot.org). Maintainers are assigned to topics and when
applicable to subtrees of the source tree. You'll find some subtrees that
don't have a maintainer. If you are looking for reviewers for such a sub-
tree, it's often a good choice to look at the git history to see who worked
on it last.

Please try to follow the guidelines below. This will make things
easier on the maintainers. Not all of these guidelines matter for every
Expand Down Expand Up @@ -65,6 +73,8 @@ trivial patch so apply some common sense.
Descriptions of section entries:

M: Maintainer: FullName <address@domain>
Must be registered to Gerrit (https://review.coreboot.org/).
Should have experience with upstream coreboot development.
R: Designated reviewer: FullName <address@domain>
These reviewers should be CCed on patches.
L: Mailing list that is relevant to this area
Expand All @@ -73,8 +83,12 @@ Descriptions of section entries:
T: SCM tree type and location.
Type is one of: git, hg, quilt, stgit, topgit
S: Status, one of the following:
Supported: Someone is actually paid to look after this.
Maintained: Someone actually looks after it.
Supported: Someone is continuously paid to look after this and
a reaction to review requests can be expected
within a few days, a month at most.
Maintained: Someone actually looks after it and a reaction to
review requests can usually be expected within a
few weeks.
Odd Fixes: It has a maintainer but they don't have time to do
much other than throw the odd patch in. See below..
Orphan: No current maintainer [but maybe you could take the
Expand Down Expand Up @@ -196,18 +210,6 @@ F: src/soc/intel/fsp_broadwell_de/
F: src/vendorcode/intel/fsp1_0/broadwell_de/
F: src/mainboard/intel/camelbackmountain_fsp/

INTEL FSP IVYBRIDGE/PANTHERPOINT/CAVECREEK & CRBs
M: York Yang <york.yang@intel.com>
S: Supported
F: src/cpu/intel/fsp_model_206ax/
F: src/northbridge/intel/fsp_sandybridge/
F: src/southbridge/intel/fsp_bd82x6x/
F: src/southbridge/intel/fsp_i89xx/
F: src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x
F: src/vendorcode/intel/fsp1_0/ivybridge_i89xx
F: src/mainboard/intel/cougar_canyon2/
F: src/mainboard/intel/stargo2/

INTEL FSP DENVERTON-NS SOC & HARCUVAR CRB
M: SweeHeng Wong <swee.heng.wong@intel.com>
M: Jeff Daly <jeffrey.daly@intel.com>
Expand Down
4 changes: 4 additions & 0 deletions Makefile.inc
View file
Expand Up @@ -1053,6 +1053,10 @@ ifeq ($(CONFIG_CPU_MICROCODE_CBFS_GENERATE),y)
$(CBFSTOOL) $@.tmp update-fit -n cpu_microcode_blob.bin -x $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \
$(FIT_OPTIONS)
endif
endif

ifeq ($(CONFIG_AGESA_UCODE_EXPERIMENTAL),y)
dd if=$(CONFIG_CPU_UCODE_BINARIES) of=$@.tmp bs=1 seek=6665692 count=3424 conv=notrunc 2> /dev/null
endif
mv $@.tmp $@
@printf " CBFSLAYOUT $(subst $(obj)/,,$(@))\n\n"
Expand Down
4 changes: 2 additions & 2 deletions configs/config.pcengines_apu1
View file
@@ -1,11 +1,11 @@
CONFIG_LOCALVERSION="v4.8.0.6"
CONFIG_LOCALVERSION="v4.8.0.7"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU1=y
CONFIG_NO_GFX_INIT=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
CONFIG_SEABIOS_REVISION=y
CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.6"
CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.7"
CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder"
CONFIG_SEABIOS_DEBUG_LEVEL=0
CONFIG_PXE=y
Expand Down
5 changes: 2 additions & 3 deletions configs/config.pcengines_apu2
View file
@@ -1,12 +1,11 @@
CONFIG_LOCALVERSION="v4.8.0.6"
CONFIG_LOCALVERSION="v4.8.0.7"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU2=y
CONFIG_CPU_MICROCODE_CBFS_NONE=y
CONFIG_NO_GFX_INIT=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
CONFIG_SEABIOS_REVISION=y
CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.6"
CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.7"
CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
CONFIG_SEABIOS_DEBUG_LEVEL=0
CONFIG_PXE=y
Expand Down
5 changes: 2 additions & 3 deletions configs/config.pcengines_apu3
View file
@@ -1,12 +1,11 @@
CONFIG_LOCALVERSION="v4.8.0.6"
CONFIG_LOCALVERSION="v4.8.0.7"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU3=y
CONFIG_CPU_MICROCODE_CBFS_NONE=y
CONFIG_NO_GFX_INIT=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
CONFIG_SEABIOS_REVISION=y
CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.6"
CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.7"
CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
CONFIG_SEABIOS_DEBUG_LEVEL=0
CONFIG_PXE=y
Expand Down
5 changes: 2 additions & 3 deletions configs/config.pcengines_apu4
View file
@@ -1,12 +1,11 @@
CONFIG_LOCALVERSION="v4.8.0.6"
CONFIG_LOCALVERSION="v4.8.0.7"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU4=y
CONFIG_CPU_MICROCODE_CBFS_NONE=y
CONFIG_NO_GFX_INIT=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
CONFIG_SEABIOS_REVISION=y
CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.6"
CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.7"
CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
CONFIG_SEABIOS_DEBUG_LEVEL=0
CONFIG_PXE=y
Expand Down
5 changes: 2 additions & 3 deletions configs/config.pcengines_apu5
View file
@@ -1,12 +1,11 @@
CONFIG_LOCALVERSION="v4.8.0.6"
CONFIG_LOCALVERSION="v4.8.0.7"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU5=y
CONFIG_CPU_MICROCODE_CBFS_NONE=y
CONFIG_NO_GFX_INIT=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y
CONFIG_SEABIOS_REVISION=y
CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.6"
CONFIG_SEABIOS_REVISION_ID="rel-1.11.0.7"
CONFIG_SEABIOS_BOOTORDER_FILE="$(top)/src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/bootorder"
CONFIG_SEABIOS_DEBUG_LEVEL=0
CONFIG_PXE=y
Expand Down
4 changes: 2 additions & 2 deletions payloads/external/LinuxBoot/Kconfig
View file
Expand Up @@ -73,7 +73,7 @@ config LINUXBOOT_KERNEL_CONFIGFILE
Add your own kernel configuration file. Otherwise a default
minimal defconfig is used.

config LINUXBOOT_KERNEL_COMMANDLINE
config LINUX_COMMAND_LINE
string "Kernel command-line"
default ""
help
Expand Down Expand Up @@ -128,7 +128,7 @@ config LINUXBOOT_UROOT_FILES
Path to directory containing root structure for embedding into the
initramfs.

config PAYLOAD_USERSPACE
config LINUX_INITRD
string
default "payloads/external/LinuxBoot/linuxboot/initramfs.cpio.xz"

Expand Down
8 changes: 4 additions & 4 deletions payloads/external/LinuxBoot/Makefile
View file
Expand Up @@ -82,20 +82,20 @@ $(project_dir)/target.dtb: $(PWD)/$(CONFIG_LINUXBOOT_DTB_FILE)
$(project_dir)/vmlinux.bin.lzma: $(project_dir)/vmlinux.bin
xz -c -k -f --format=lzma --lzma1=dict=1MiB,lc=3,lp=0,pb=3 $< > $@

$(project_dir)/kernel-image: $(project_dir)/vmlinux.bin.lzma $(project_dir)/../arm64/kernel_fdt_lzma.its $(project_dir)/target.dtb $(PWD)/$(CONFIG_PAYLOAD_USERSPACE)
$(project_dir)/kernel-image: $(project_dir)/vmlinux.bin.lzma $(project_dir)/../arm64/kernel_fdt_lzma.its $(project_dir)/target.dtb $(PWD)/$(CONFIG_LINUX_INITRD)
cp $(project_dir)/../arm64/kernel_fdt_lzma.its $(project_dir)
mkimage -f $(project_dir)/kernel_fdt_lzma.its $@
endif

ifeq ($(CONFIG_LINUXBOOT_UROOT),y)
$(PWD)/$(CONFIG_PAYLOAD_USERSPACE):
$(PWD)/$(CONFIG_LINUX_INITRD):
$(MAKE) -f targets/u-root.mk
else
$(PWD)/$(CONFIG_PAYLOAD_USERSPACE):
$(PWD)/$(CONFIG_LINUX_INITRD):
echo "Building without u-root support"
endif

linuxboot: $(project_dir)/kernel-image $(PWD)/$(CONFIG_PAYLOAD_USERSPACE)
linuxboot: $(project_dir)/kernel-image $(PWD)/$(CONFIG_LINUX_INITRD)

clean:
if [ -d "$(kernel_dir)" ]; then rm -rf $(kernel_dir); fi
Expand Down
16 changes: 2 additions & 14 deletions payloads/external/Makefile.inc
View file
Expand Up @@ -32,18 +32,7 @@ $(PAYLOAD_CONFIG): payloads/external/depthcharge/depthcharge/build/depthcharge.e
#TODO: Figure out version
endif

ifeq ($(CONFIG_PAYLOAD_LINUXBOOT),y)
ifeq ($(CONFIG_ARCH_X86),y)
ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUXBOOT_KERNEL_COMMANDLINE))),)
ADDITIONAL_PAYLOAD_CONFIG+=-C $(CONFIG_LINUXBOOT_KERNEL_COMMANDLINE)
endif
ifneq ($(strip $(call strip_quotes,$(CONFIG_PAYLOAD_USERSPACE))),)
ADDITIONAL_PAYLOAD_CONFIG+=-I $(strip $(call strip_quotes,$(CONFIG_PAYLOAD_USERSPACE)))
endif
endif
endif

ifeq ($(CONFIG_PAYLOAD_LINUX),y)
ifeq ($(CONFIG_PAYLOAD_LINUX)$(CONFIG_PAYLOAD_LINUXBOOT),y)
ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUX_COMMAND_LINE))),)
ADDITIONAL_PAYLOAD_CONFIG+=-C $(CONFIG_LINUX_COMMAND_LINE)
endif
Expand Down Expand Up @@ -330,14 +319,13 @@ linuxboot:
CPUS=$(CPUS) \
CONFIG_LINUXBOOT_KERNEL_VERSION=$(CONFIG_LINUXBOOT_KERNEL_VERSION) \
CONFIG_LINUXBOOT_KERNEL_CONFIGFILE=$(CONFIG_LINUXBOOT_KERNEL_CONFIGFILE) \
CONFIG_LINUXBOOT_KERNEL_COMMANDLINE=$(CONFIG_LINUXBOOT_KERNEL_COMMANDLINE) \
CONFIG_LINUXBOOT_UROOT_VERSION=$(CONFIG_LINUXBOOT_UROOT_VERSION) \
CONFIG_LINUXBOOT_UROOT_COMMANDS=$(CONFIG_LINUXBOOT_UROOT_COMMANDS) \
CONFIG_LINUXBOOT_ARCH=$(CONFIG_LINUXBOOT_ARCH) \
CONFIG_LINUXBOOT_UROOT=$(CONFIG_LINUXBOOT_UROOT) \
CONFIG_LINUXBOOT_UROOT_FILES=$(CONFIG_LINUXBOOT_UROOT_FILES) \
CONFIG_LINUXBOOT_DTB_FILE=$(CONFIG_LINUXBOOT_DTB_FILE) \
CONFIG_PAYLOAD_USERSPACE=$(CONFIG_PAYLOAD_USERSPACE)
CONFIG_LINUX_INITRD=$(CONFIG_LINUX_INITRD)


payloads/external/LinuxBoot/linuxboot/kernel-image: linuxboot
Expand Down
2 changes: 1 addition & 1 deletion payloads/external/sortbootorder/Makefile
View file
@@ -1,4 +1,4 @@
version=4.6.11
version=4.6.12
branch_name=v$(version)
project_url=https://github.com/pcengines/sortbootorder/archive/$(branch_name).tar.gz
archive_name=$(branch_name).tar.gz
Expand Down
3 changes: 2 additions & 1 deletion payloads/external/tianocore/Makefile
View file
Expand Up @@ -16,7 +16,8 @@
# force the shell to bash - the edksetup.sh script doesn't work with dash
export SHELL := env bash

STABLE_COMMIT_ID=315d9d08fd77db1024ccc5307823da8aaed85e2f
# STABLE_COMMIT_ID represent official edk2 release, currently UDK2018
STABLE_COMMIT_ID=3e72ffe8afdd03f1f89eba65c921cbdcb004cfee
TAG-$(CONFIG_TIANOCORE_MASTER)=origin/master
TAG-$(CONFIG_TIANOCORE_STABLE)=$(STABLE_COMMIT_ID)
TAG-$(CONFIG_TIANOCORE_REVISION)=$(CONFIG_TIANOCORE_REVISION_ID)
Expand Down
10 changes: 5 additions & 5 deletions payloads/external/tianocore/patches/01_CorebootPayloadPkg_pcinoenum.patch
View file
@@ -1,4 +1,4 @@
From 4f9d41e69356ce7486b0c74a754ff494256723de Mon Sep 17 00:00:00 2001
From c3da734cd08117ce2d5cd48367f5a94848aa9321 Mon Sep 17 00:00:00 2001
From: CoolStar <coolstarorganization@gmail.com>
Date: Sun, 4 Dec 2016 11:23:38 -0800
Subject: [PATCH] PCI: use Duet's PciNoEnumeration
Expand All @@ -10,7 +10,7 @@ Subject: [PATCH] PCI: use Duet's PciNoEnumeration
3 files changed, 6 insertions(+), 12 deletions(-)

diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
index 303e626842..a39e3999ba 100644
index 7994f0c94928..d71b3ec55690 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf
+++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
@@ -124,8 +124,8 @@ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
Expand All @@ -25,7 +25,7 @@ index 303e626842..a39e3999ba 100644
#
# ISA Support
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
index cdfcb75b59..e838aca61d 100644
index ace1bc0a3726..0f4e475187ee 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
@@ -450,11 +450,8 @@
Expand All @@ -43,7 +43,7 @@ index cdfcb75b59..e838aca61d 100644
#
# SCSI/ATA/IDE/DISK Support
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
index 6b16af63ba..c25d821fd4 100644
index 2492142b972d..97bb0a8ae0a1 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
@@ -451,11 +451,8 @@
Expand All @@ -61,5 +61,5 @@ index 6b16af63ba..c25d821fd4 100644
#
# SCSI/ATA/IDE/DISK Support
--
2.13.2.725.g09c95d1e9-goog
2.17.0

48 changes: 24 additions & 24 deletions payloads/external/tianocore/patches/02_CorebootPayloadPkg_bds.patch
View file
@@ -1,20 +1,20 @@
From 5121087836c1ad2a08857d494c0d9ecb183f4f98 Mon Sep 17 00:00:00 2001
From e72cac80c845429b042c7f9c36ede642cbe9e150 Mon Sep 17 00:00:00 2001
From: CoolStar <coolstarorganization@gmail.com>
Date: Tue, 18 Jul 2017 15:50:38 -0600
Subject: [PATCH] Rebasing

---
CorebootModulePkg/CorebootModulePkg.dec | 8 +
.../Include/Guid/LdrMemoryDescriptor.h | 33 +
.../Include/Guid/PciExpressBaseAddress.h | 46 +
CorebootModulePkg/Include/Guid/PciOptionRomTable.h | 41 +
.../Library/CorebootBdsLib/BdsPlatform.c | 1731 ++++++++++++++++++++
.../Library/CorebootBdsLib/BdsPlatform.h | 288 ++++
.../Library/CorebootBdsLib/PlatformBds.inf | 65 +
.../Library/CorebootBdsLib/PlatformData.c | 161 ++
CorebootPayloadPkg/CorebootPayloadPkg.fdf | 5 +-
CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc | 12 +-
CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc | 12 +-
CorebootModulePkg/CorebootModulePkg.dec | 8 +
.../Include/Guid/LdrMemoryDescriptor.h | 33 +
.../Include/Guid/PciExpressBaseAddress.h | 46 +
.../Include/Guid/PciOptionRomTable.h | 41 +
.../Library/CorebootBdsLib/BdsPlatform.c | 1731 +++++++++++++++++
.../Library/CorebootBdsLib/BdsPlatform.h | 288 +++
.../Library/CorebootBdsLib/PlatformBds.inf | 65 +
.../Library/CorebootBdsLib/PlatformData.c | 161 ++
CorebootPayloadPkg/CorebootPayloadPkg.fdf | 5 +-
CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc | 12 +-
.../CorebootPayloadPkgIa32X64.dsc | 12 +-
11 files changed, 2388 insertions(+), 14 deletions(-)
create mode 100644 CorebootModulePkg/Include/Guid/LdrMemoryDescriptor.h
create mode 100644 CorebootModulePkg/Include/Guid/PciExpressBaseAddress.h
Expand All @@ -25,7 +25,7 @@ Subject: [PATCH] Rebasing
create mode 100644 CorebootModulePkg/Library/CorebootBdsLib/PlatformData.c

diff --git a/CorebootModulePkg/CorebootModulePkg.dec b/CorebootModulePkg/CorebootModulePkg.dec
index 7f1309bdae..20932a1d04 100644
index 7f1309bdae61..20932a1d0467 100644
--- a/CorebootModulePkg/CorebootModulePkg.dec
+++ b/CorebootModulePkg/CorebootModulePkg.dec
@@ -33,8 +33,16 @@
Expand All @@ -47,7 +47,7 @@ index 7f1309bdae..20932a1d04 100644

diff --git a/CorebootModulePkg/Include/Guid/LdrMemoryDescriptor.h b/CorebootModulePkg/Include/Guid/LdrMemoryDescriptor.h
new file mode 100644
index 0000000000..38a997deea
index 000000000000..38a997deea0c
--- /dev/null
+++ b/CorebootModulePkg/Include/Guid/LdrMemoryDescriptor.h
@@ -0,0 +1,33 @@
Expand Down Expand Up @@ -86,7 +86,7 @@ index 0000000000..38a997deea
+#endif
diff --git a/CorebootModulePkg/Include/Guid/PciExpressBaseAddress.h b/CorebootModulePkg/Include/Guid/PciExpressBaseAddress.h
new file mode 100644
index 0000000000..ff554383c1
index 000000000000..ff554383c11b
--- /dev/null
+++ b/CorebootModulePkg/Include/Guid/PciExpressBaseAddress.h
@@ -0,0 +1,46 @@
Expand Down Expand Up @@ -138,7 +138,7 @@ index 0000000000..ff554383c1
+#endif
diff --git a/CorebootModulePkg/Include/Guid/PciOptionRomTable.h b/CorebootModulePkg/Include/Guid/PciOptionRomTable.h
new file mode 100644
index 0000000000..a2fb99710a
index 000000000000..a2fb99710a69
--- /dev/null
+++ b/CorebootModulePkg/Include/Guid/PciOptionRomTable.h
@@ -0,0 +1,41 @@
Expand Down Expand Up @@ -185,7 +185,7 @@ index 0000000000..a2fb99710a
+
diff --git a/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.c b/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.c
new file mode 100644
index 0000000000..b6253a17f8
index 000000000000..b6253a17f8ea
--- /dev/null
+++ b/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.c
@@ -0,0 +1,1731 @@
Expand Down Expand Up @@ -1922,7 +1922,7 @@ index 0000000000..b6253a17f8
+}
diff --git a/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.h b/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.h
new file mode 100644
index 0000000000..d447f77747
index 000000000000..d447f77747e3
--- /dev/null
+++ b/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.h
@@ -0,0 +1,288 @@
Expand Down Expand Up @@ -2216,7 +2216,7 @@ index 0000000000..d447f77747
+#endif // _PLATFORM_SPECIFIC_BDS_PLATFORM_H_
diff --git a/CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf b/CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf
new file mode 100644
index 0000000000..578c74afae
index 000000000000..578c74afae22
--- /dev/null
+++ b/CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf
@@ -0,0 +1,65 @@
Expand Down Expand Up @@ -2287,7 +2287,7 @@ index 0000000000..578c74afae
+
diff --git a/CorebootModulePkg/Library/CorebootBdsLib/PlatformData.c b/CorebootModulePkg/Library/CorebootBdsLib/PlatformData.c
new file mode 100644
index 0000000000..fbdcc7de81
index 000000000000..fbdcc7de8166
--- /dev/null
+++ b/CorebootModulePkg/Library/CorebootBdsLib/PlatformData.c
@@ -0,0 +1,161 @@
Expand Down Expand Up @@ -2453,7 +2453,7 @@ index 0000000000..fbdcc7de81
+EFI_DEVICE_PATH_PROTOCOL *gPlatformConnectSequence[] = { NULL };
+
diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
index a39e3999ba..623ff9c344 100644
index d71b3ec55690..22987093da58 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf
+++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
@@ -95,8 +95,9 @@ INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntime
Expand All @@ -2469,7 +2469,7 @@ index a39e3999ba..623ff9c344 100644
INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
!else
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
index e838aca61d..a329b78f08 100644
index 0f4e475187ee..053f380a8608 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
@@ -165,6 +165,7 @@
Expand Down Expand Up @@ -2508,7 +2508,7 @@ index e838aca61d..a329b78f08 100644
PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
!else
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
index c25d821fd4..790efd7810 100644
index 97bb0a8ae0a1..bb328349b44a 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
@@ -165,6 +165,7 @@
Expand Down Expand Up @@ -2547,5 +2547,5 @@ index c25d821fd4..790efd7810 100644
PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
!else
--
2.13.2.932.g7449e964c-goog
2.17.0

12 changes: 6 additions & 6 deletions payloads/external/tianocore/patches/03_Library_EndofDXE.patch
View file
@@ -1,16 +1,16 @@
From 760f1cafdd689beedc8418ab89e856b54296389c Mon Sep 17 00:00:00 2001
From 1e9c5c97a55f3ad3c0d6d5dde380b4d73bd15860 Mon Sep 17 00:00:00 2001
From: CoolStar <coolstarorganization@gmail.com>
Date: Sun, 4 Dec 2016 12:07:30 -0800
Subject: [PATCH] CorebootBdsLib: Call End of DXE event to allow booting 3rd
party efi binaries.

---
.../Library/CorebootBdsLib/BdsPlatform.c | 42 ++++++++++++++++++++++
.../Library/CorebootBdsLib/PlatformBds.inf | 1 +
.../Library/CorebootBdsLib/BdsPlatform.c | 42 +++++++++++++++++++
.../Library/CorebootBdsLib/PlatformBds.inf | 1 +
2 files changed, 43 insertions(+)

diff --git a/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.c b/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.c
index b6253a17f8..cf3e5320cb 100644
index b6253a17f8ea..cf3e5320cbe8 100644
--- a/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.c
+++ b/CorebootModulePkg/Library/CorebootBdsLib/BdsPlatform.c
@@ -1129,6 +1129,46 @@ Returns:
Expand Down Expand Up @@ -70,7 +70,7 @@ index b6253a17f8..cf3e5320cb 100644
// Init the time out value
//
diff --git a/CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf b/CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf
index 578c74afae..992bd846bd 100644
index 578c74afae22..992bd846bdc4 100644
--- a/CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf
+++ b/CorebootModulePkg/Library/CorebootBdsLib/PlatformBds.inf
@@ -58,6 +58,7 @@
Expand All @@ -82,5 +82,5 @@ index 578c74afae..992bd846bd 100644
[Pcd]
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
--
2.13.2.725.g09c95d1e9-goog
2.17.0

10 changes: 5 additions & 5 deletions payloads/external/tianocore/patches/04_CorebootPayloadPkg_addps2.patch
View file
@@ -1,4 +1,4 @@
From 77c5dfcce842819215490fe63c481860fa7d752d Mon Sep 17 00:00:00 2001
From e8d6ed35c15b92497cd3ede6cd35523b0e7366ac Mon Sep 17 00:00:00 2001
From: CoolStar <coolstarorganization@gmail.com>
Date: Sun, 4 Dec 2016 11:50:00 -0800
Subject: [PATCH] CorebootPayloadPkg: Add PS/2 keyboard drivers.
Expand All @@ -10,7 +10,7 @@ Subject: [PATCH] CorebootPayloadPkg: Add PS/2 keyboard drivers.
3 files changed, 9 insertions(+)

diff --git a/CorebootPayloadPkg/CorebootPayloadPkg.fdf b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
index 347e9c75ce..a347af0c9a 100644
index 22987093da58..0961e96c250d 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkg.fdf
+++ b/CorebootPayloadPkg/CorebootPayloadPkg.fdf
@@ -132,6 +132,9 @@ INF DuetPkg/PciBusNoEnumerationDxe/PciBusNoEnumeration.inf
Expand All @@ -24,7 +24,7 @@ index 347e9c75ce..a347af0c9a 100644
#
# Console Support
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
index 5ce823bb95..60ee064c59 100644
index 053f380a8608..6ddd64faf7a5 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
@@ -492,6 +492,9 @@
Expand All @@ -38,7 +38,7 @@ index 5ce823bb95..60ee064c59 100644
#
# Console Support
diff --git a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
index fea297a77a..167329c897 100644
index bb328349b44a..19c203e6cbb6 100644
--- a/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
+++ b/CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
@@ -493,6 +493,9 @@
Expand All @@ -52,5 +52,5 @@ index fea297a77a..167329c897 100644
#
# Console Support
--
2.13.2.725.g09c95d1e9-goog
2.17.0

2 changes: 1 addition & 1 deletion payloads/external/tianocore/patches/06_CorebootPayloadPkg_keep_cb_table.patch
View file
@@ -1,4 +1,4 @@
From 336ce69129206ea6cb5bea2a99c5f00e77850518 Mon Sep 17 00:00:00 2001
From 9c28ac87eb2df7319d4f5a48124c837b8bf123b3 Mon Sep 17 00:00:00 2001
From: ReddestDream <reddestdream@gmail.com>
Date: Wed, 3 May 2017 00:13:28 -0400
Subject: [PATCH] CbSupportPei: prevent lower coreboot table from being
Expand Down
9 changes: 6 additions & 3 deletions payloads/external/tianocore/patches/07_CorebootPayloadPkg-Use-correct-BytesPerScanLine.patch
View file
@@ -1,4 +1,4 @@
From 07dec11fe965e73cfef7df38af70c945b6ff21a2 Mon Sep 17 00:00:00 2001
From 2e75f9ad6ef625575185dfc262c6803a89850dd5 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Wed, 24 Jan 2018 10:07:08 +0100
Subject: [PATCH] CorebootPayloadPkg: Use correct BytesPerScanLine
Expand All @@ -12,9 +12,12 @@ This fixes a garbled display when HorizontalResolution * (BitsPerPixel

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
CorebootPayloadPkg/FbGop/FbGop.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/CorebootPayloadPkg/FbGop/FbGop.c b/CorebootPayloadPkg/FbGop/FbGop.c
index 37d6def7f7..6790617033 100644
index 37d6def7f780..679061703358 100644
--- a/CorebootPayloadPkg/FbGop/FbGop.c
+++ b/CorebootPayloadPkg/FbGop/FbGop.c
@@ -822,7 +822,7 @@ FbGopCheckForVbe (
Expand All @@ -27,5 +30,5 @@ index 37d6def7f7..6790617033 100644
ModeBuffer = (FB_VIDEO_MODE_DATA *) AllocatePool (
ModeNumber * sizeof (FB_VIDEO_MODE_DATA)
--
2.16.1
2.17.0

6 changes: 3 additions & 3 deletions .../external/tianocore/patches/08_BaseTools-Fix-building-with-Werror-stringop-truncati.patch
View file
@@ -1,4 +1,4 @@
From b652262ed0dd554c44e7b1bf7134d3458f5edef1 Mon Sep 17 00:00:00 2001
From 8cb365e9ec90420e3d04b77f6e7999a65d5983a6 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <siro@das-labor.org>
Date: Sun, 17 Jun 2018 08:44:51 +0200
Subject: [PATCH] BaseTools: Fix building with -Werror=stringop-truncation
Expand All @@ -9,7 +9,7 @@ Signed-off-by: Patrick Rudolph <siro@das-labor.org>
1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/BaseTools/Source/C/GenVtf/GenVtf.c b/BaseTools/Source/C/GenVtf/GenVtf.c
index acc142a6d1..5d77016eba 100644
index 65ae08eeceb8..d4200621457c 100644
--- a/BaseTools/Source/C/GenVtf/GenVtf.c
+++ b/BaseTools/Source/C/GenVtf/GenVtf.c
@@ -129,9 +129,9 @@ Returns:
Expand All @@ -24,7 +24,7 @@ index acc142a6d1..5d77016eba 100644
}

sscanf (
@@ -1529,7 +1529,7 @@ Returns:
@@ -1521,7 +1521,7 @@ Returns:
//
FitStartPtr = (FIT_TABLE *) RelativeAddress;

Expand Down
40 changes: 0 additions & 40 deletions payloads/external/tianocore/patches/09_gcc7-Fix-building-with-fpermissive.patch
View file

This file was deleted.

4 changes: 2 additions & 2 deletions payloads/libpayload/drivers/storage/ahci_common.c
View file
Expand Up @@ -72,7 +72,7 @@ static u8 *ahci_prdbuf_init(ahci_dev_t *const dev,
if ((u32)user_buf & 1) {
printf("ahci: Odd buffer pointer (%p).\n", user_buf);
if (dev->buf) /* orphaned buffer */
free((void *)dev->buf - *(dev->buf - 1));
free(dev->buf - *(dev->buf - 1));
dev->buf = malloc(len + 2);
if (!dev->buf)
return NULL;
Expand Down Expand Up @@ -100,7 +100,7 @@ static void ahci_prdbuf_finalize(ahci_dev_t *const dev)
if (dev->buf) {
if (dev->write_back)
memcpy(dev->user_buf, dev->buf, dev->buflen);
free((void *)dev->buf - *(dev->buf - 1));
free(dev->buf - *(dev->buf - 1));
}
dev->buf = NULL;
dev->user_buf = NULL;
Expand Down
7 changes: 7 additions & 0 deletions src/Kconfig
View file
Expand Up @@ -693,6 +693,13 @@ config FATAL_ASSERTS
help
If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().

config HAVE_DEBUG_GPIO
bool

config DEBUG_GPIO
bool "Output verbose GPIO debug messages"
depends on HAVE_DEBUG_GPIO

config DEBUG_CBFS
bool "Output verbose CBFS debug messages"
default n
Expand Down
1 change: 0 additions & 1 deletion src/arch/arm/armv7/mmu.c
View file
Expand Up @@ -33,7 +33,6 @@
#include <stdint.h>
#include <symbols.h>

#include <cbmem.h>
#include <console/console.h>

#include <arch/cache.h>
Expand Down
2 changes: 1 addition & 1 deletion src/arch/arm/armv7/thread.c
View file
Expand Up @@ -12,7 +12,7 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>

#include <thread.h>

/* The stack frame looks like the following. */
Expand Down
1 change: 0 additions & 1 deletion src/arch/arm64/arm_tf.c
View file
Expand Up @@ -20,7 +20,6 @@
#include <arm_tf.h>
#include <assert.h>
#include <cbfs.h>
#include <cbmem.h>
#include <program_loading.h>

/*
Expand Down
2 changes: 0 additions & 2 deletions src/arch/arm64/boot.c
View file
Expand Up @@ -18,8 +18,6 @@
#include <arch/stages.h>
#include <arch/transition.h>
#include <arm_tf.h>
#include <cbmem.h>
#include <console/console.h>
#include <program_loading.h>
#include <rules.h>
#include <string.h>
Expand Down
2 changes: 0 additions & 2 deletions src/arch/arm64/eabi_compat.c
View file
Expand Up @@ -14,8 +14,6 @@
* GNU General Public License for more details.
*/

#include <console/console.h>

int raise (int signum) __attribute__((used));
int raise (int signum)
{
Expand Down
1 change: 0 additions & 1 deletion src/arch/arm64/transition.c
View file
Expand Up @@ -18,7 +18,6 @@
#include <arch/mmu.h>
#include <arch/transition.h>
#include <assert.h>
#include <console/console.h>

/* Litte-endian, No XN-forced, Instr cache disabled,
* Stack alignment disabled, Data and unified cache
Expand Down
2 changes: 1 addition & 1 deletion src/arch/riscv/trap_handler.c
View file
Expand Up @@ -125,7 +125,7 @@ void trap_handler(trapframe *tf)
return;
}

switch(tf->cause) {
switch (tf->cause) {
case CAUSE_MISALIGNED_FETCH:
case CAUSE_FETCH_ACCESS:
case CAUSE_ILLEGAL_INSTRUCTION:
Expand Down
2 changes: 1 addition & 1 deletion src/arch/x86/acpi_s3.c
View file
Expand Up @@ -16,8 +16,8 @@
#include <console/console.h>
#include <string.h>
#include <arch/acpi.h>
#include <arch/cpu.h>
#include <cbmem.h>
#include <cpu/cpu.h>
#include <fallback.h>
#include <timestamp.h>
#include <program_loading.h>
Expand Down
3 changes: 3 additions & 0 deletions src/arch/x86/car.ld
View file
Expand Up @@ -113,3 +113,6 @@ _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DC
#if IS_ENABLED(CONFIG_PAGING_IN_CACHE_AS_RAM)
_bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned");
#endif
#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
_bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured");
#endif
20 changes: 18 additions & 2 deletions src/arch/x86/include/arch/early_variables.h
View file
Expand Up @@ -79,12 +79,28 @@ static inline size_t car_object_offset(void *ptr)
}

#else

/*
* We might end up here if:
* 1. ENV_CACHE_AS_RAM is not set for the stage or
* 2. ENV_CACHE_AS_RAM is set for the stage but CONFIG_NO_CAR_GLOBAL_MIGRATION
* is also set. In this case, there is no need to migrate CAR global
* variables. But, since we might still be running out of CAR, car_active needs
* to return 1 if ENV_CACHE_AS_RAM is set.
*/

#define CAR_GLOBAL
static inline void *car_get_var_ptr(void *var) { return var; }

#if ENV_CACHE_AS_RAM
static inline int car_active(void) { return 1; }
#else
static inline int car_active(void) { return 0; }
#endif /* ENV_CACHE_AS_RAM */

#define car_get_var(var) (var)
#define car_sync_var(var) (var)
#define car_set_var(var, val) (var) = (val)
#endif
#endif /* ENV_CACHE_AS_RAM && !IS_ENABLED(CONFIG_NO_CAR_GLOBAL_MIGRATION) */

#endif
#endif /* ARCH_EARLY_VARIABLES_H */
1 change: 0 additions & 1 deletion src/arch/x86/mpspec.c
View file
Expand Up @@ -16,7 +16,6 @@
#include <console/console.h>
#include <device/path.h>
#include <device/pci_ids.h>
#include <cpu/cpu.h>
#include <arch/smp/mpspec.h>
#include <string.h>
#include <arch/cpu.h>
Expand Down
1 change: 0 additions & 1 deletion src/arch/x86/pirq_routing.c
View file
Expand Up @@ -18,7 +18,6 @@
#include <arch/pirq_routing.h>
#include <string.h>
#include <device/pci.h>
#include <arch/pirq_routing.h>

void __weak pirq_assign_irqs(const unsigned char pirq[CONFIG_MAX_PIRQ_LINKS])
{
Expand Down
2 changes: 1 addition & 1 deletion src/arch/x86/postcar_loader.c
View file
Expand Up @@ -167,7 +167,7 @@ static void load_postcar_cbfs(struct prog *prog, struct postcar_frame *pcf)
void run_postcar_phase(struct postcar_frame *pcf)
{
struct prog prog =
PROG_INIT(PROG_UNKNOWN, CONFIG_CBFS_PREFIX "/postcar");
PROG_INIT(PROG_POSTCAR, CONFIG_CBFS_PREFIX "/postcar");

postcar_commit_mtrrs(pcf);

Expand Down
1 change: 0 additions & 1 deletion src/arch/x86/tables.c
View file
Expand Up @@ -16,7 +16,6 @@
*/

#include <console/console.h>
#include <cpu/cpu.h>
#include <bootmem.h>
#include <bootstate.h>
#include <boot/tables.h>
Expand Down
1 change: 0 additions & 1 deletion src/commonlib/storage/mmc.c
View file
Expand Up @@ -21,7 +21,6 @@

#include <commonlib/storage.h>
#include <delay.h>
#include "sd_mmc.h"
#include "mmc.h"
#include "sd_mmc.h"
#include "storage.h"
Expand Down
2 changes: 1 addition & 1 deletion src/console/Kconfig
View file
Expand Up @@ -29,7 +29,7 @@ config SQUELCH_EARLY_SMP
config CONSOLE_SERIAL
bool "Serial port console output"
default y
depends on DRIVERS_UART_8250IO || DRIVERS_UART_8250MEM || HAVE_UART_SPECIAL
depends on DRIVERS_UART
help
Send coreboot debug output to a serial port.

Expand Down
6 changes: 3 additions & 3 deletions src/cpu/Kconfig
View file
Expand Up @@ -160,8 +160,8 @@ config CPU_MICROCODE_CBFS_NONE
Make sure you have a way of flashing the ROM externally before
selecting this option.

config CPU_UCODE_RAW_BINARY
bool "Add raw microcode binary to CBFS"
config AGESA_UCODE_EXPERIMENTAL
bool "Add microcode patch for AMD fam16h (EXPERIMENTAL)"
help

endchoice
Expand All @@ -183,7 +183,7 @@ config CPU_MICROCODE_HEADER_FILES

config CPU_UCODE_BINARIES
string "Microcode binary path and filename"
depends on CPU_MICROCODE_CBFS_GENERATE || CPU_UCODE_RAW_BINARY
depends on CPU_MICROCODE_CBFS_GENERATE || AGESA_UCODE_EXPERIMENTAL
default ""
help
Some platforms have microcode in the blobs directory, and these can
Expand Down
6 changes: 0 additions & 6 deletions src/cpu/Makefile.inc
View file
Expand Up @@ -20,12 +20,6 @@ ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y)
cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += cpu_microcode_blob.bin
endif

ifeq ($(CONFIG_CPU_UCODE_RAW_BINARY), y)
cbfs-files-y += cpu_microcode_blob.bin
cpu_microcode_blob.bin-file = $(CONFIG_CPU_UCODE_BINARIES)
cpu_microcode_blob.bin-type = microcode
endif

ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
cbfs-files-y += cpu_microcode_blob.bin
cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin
Expand Down
4 changes: 1 addition & 3 deletions src/cpu/allwinner/a10/Makefile.inc
View file
Expand Up @@ -21,11 +21,9 @@ ramstage-y += monotonic_timer.c
ramstage-y += timer.c
ramstage-y += twi.c

ifeq ($(CONFIG_DRIVERS_UART),y)
bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c uart_console.c
bootblock-y += uart.c uart_console.c
romstage-y += uart.c uart_console.c
ramstage-y += uart.c uart_console.c
endif

real-target: $(obj)/BOOT0

Expand Down
4 changes: 0 additions & 4 deletions src/cpu/allwinner/a10/cpu.c
View file
Expand Up @@ -17,13 +17,9 @@
*
*/

#include <console/console.h>
#include <device/device.h>
#include <cpu/cpu.h>
#include <cbmem.h>
#include <symbols.h>


static void cpu_enable_resources(struct device *dev)
{
ram_resource(dev, 0, (uintptr_t)_dram/KiB,
Expand Down
1 change: 0 additions & 1 deletion src/cpu/allwinner/a10/raminit.c
View file
Expand Up @@ -30,7 +30,6 @@
#include "timer.h"

#include <arch/io.h>
#include <console/console.h>
#include <delay.h>

static struct a1x_dramc *const dram = (void *)A1X_DRAMC_BASE;
Expand Down
1 change: 0 additions & 1 deletion src/cpu/amd/agesa/Kconfig
View file
Expand Up @@ -80,6 +80,5 @@ endif # CPU_AMD_AGESA

source src/cpu/amd/agesa/family12/Kconfig
source src/cpu/amd/agesa/family14/Kconfig
source src/cpu/amd/agesa/family15/Kconfig
source src/cpu/amd/agesa/family15tn/Kconfig
source src/cpu/amd/agesa/family16kb/Kconfig
1 change: 1 addition & 0 deletions src/cpu/amd/car/disable_cache_as_ram.c
View file
Expand Up @@ -19,6 +19,7 @@
* WARNING: this file will be used by both any AP cores and core 0 / node 0
*/

#include <arch/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/msr.h>
Expand Down
1 change: 0 additions & 1 deletion src/cpu/amd/car/post_cache_as_ram.c
View file
Expand Up @@ -26,7 +26,6 @@
#include <cpu/amd/msr.h>
#include <arch/acpi.h>
#include <romstage_handoff.h>
#include <cbmem.h>

#include "cpu/amd/car/disable_cache_as_ram.c"

Expand Down
1 change: 0 additions & 1 deletion src/cpu/amd/family_10h-family_15h/init_cpus.h
View file
Expand Up @@ -18,7 +18,6 @@

#include <stdlib.h>
#include <console/console.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
Expand Down
1 change: 0 additions & 1 deletion src/cpu/amd/family_10h-family_15h/processor_name.c
View file
Expand Up @@ -27,7 +27,6 @@
#include <string.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/cpu.h>
#include <cpu/amd/model_10xxx_rev.h>
#include <device/device.h>
#include <device/pci.h>
Expand Down
2 changes: 1 addition & 1 deletion src/cpu/amd/family_10h-family_15h/ram_calc.c
View file
Expand Up @@ -14,7 +14,7 @@
* GNU General Public License for more details.
*/

#include <cpu/cpu.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>

Expand Down
4 changes: 2 additions & 2 deletions src/cpu/amd/microcode/Makefile.inc
View file
@@ -1,2 +1,2 @@
romstage-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode.c
ramstage-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode.c
romstage-y += microcode.c
ramstage-y += microcode.c
5 changes: 0 additions & 5 deletions src/cpu/amd/pi/00630F01/Kconfig
View file
Expand Up @@ -39,9 +39,4 @@ config XIP_ROM_SIZE
hex
default 0x100000

config HIGH_SCRATCH_MEMORY_SIZE
hex
# Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000)
default 0x71000

endif
9 changes: 0 additions & 9 deletions src/cpu/amd/pi/00660F01/Kconfig
View file
Expand Up @@ -39,13 +39,4 @@ config XIP_ROM_SIZE
hex
default 0x100000

config HAVE_INIT_TIMER
bool
default y

config HIGH_SCRATCH_MEMORY_SIZE
hex
# Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000)
default 0xA1000

endif
6 changes: 0 additions & 6 deletions src/cpu/amd/pi/00730F01/Kconfig
View file
Expand Up @@ -16,7 +16,6 @@
config CPU_AMD_PI_00730F01
bool
select X86_AMD_FIXED_MTRRS
select SUPPORT_CPU_UCODE_IN_CBFS

if CPU_AMD_PI_00730F01

Expand All @@ -36,9 +35,4 @@ config XIP_ROM_SIZE
hex
default 0x100000

config HIGH_SCRATCH_MEMORY_SIZE
hex
# Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000)
default 0xA1000

endif
4 changes: 0 additions & 4 deletions src/cpu/amd/pi/00730F01/Makefile.inc
View file
Expand Up @@ -14,14 +14,10 @@
#

romstage-y += fixme.c
romstage-y += update_microcode.c
romstage-y += microcode_fam16h.c

ramstage-y += fixme.c
ramstage-y += chip_name.c
ramstage-y += model_16_init.c
ramstage-y += update_microcode.c
ramstage-y += microcode_fam16h.c

subdirs-y += ../../mtrr
subdirs-y += ../../../x86/tsc
Expand Down
163 changes: 0 additions & 163 deletions src/cpu/amd/pi/00730F01/microcode_fam16h.c
View file

This file was deleted.

56 changes: 0 additions & 56 deletions src/cpu/amd/pi/00730F01/update_microcode.c
View file

This file was deleted.

1 change: 0 additions & 1 deletion src/cpu/amd/pi/amd_late_init.c
View file
Expand Up @@ -15,7 +15,6 @@

#include <arch/acpi.h>
#include <bootstate.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/quadcore/amd_sibling.c
View file
Expand Up @@ -13,9 +13,7 @@
* GNU General Public License for more details.
*/


#include <console/console.h>
#include <cpu/cpu.h>
#include <cpu/x86/lapic.h>
#include <device/device.h>
#include <device/pci.h>
Expand Down
1 change: 1 addition & 0 deletions src/cpu/amd/quadcore/quadcore.c
View file
Expand Up @@ -15,6 +15,7 @@
* GNU General Public License for more details.
*/

#include <arch/cpu.h>
#include <console/console.h>
#include <pc80/mc146818rtc.h>
#if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)
Expand Down
2 changes: 0 additions & 2 deletions src/cpu/amd/smm/smm_init.c
View file
Expand Up @@ -14,9 +14,7 @@
* GNU General Public License for more details.
*/

#include <console/console.h>
#include <arch/io.h>
#include <cpu/cpu.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
Expand Down
4 changes: 0 additions & 4 deletions src/cpu/intel/Kconfig
View file
Expand Up @@ -11,15 +11,11 @@ source src/cpu/intel/model_6fx/Kconfig
source src/cpu/intel/model_1067x/Kconfig
source src/cpu/intel/model_106cx/Kconfig
source src/cpu/intel/model_206ax/Kconfig
source src/cpu/intel/fsp_model_206ax/Kconfig
source src/cpu/intel/fsp_model_406dx/Kconfig
source src/cpu/intel/model_2065x/Kconfig
source src/cpu/intel/model_f0x/Kconfig
source src/cpu/intel/model_f1x/Kconfig
source src/cpu/intel/model_f2x/Kconfig
source src/cpu/intel/model_f3x/Kconfig
source src/cpu/intel/model_f4x/Kconfig
source src/cpu/intel/ep80579/Kconfig
source src/cpu/intel/haswell/Kconfig
# Sockets/Slots
source src/cpu/intel/slot_1/Kconfig
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2 changes: 0 additions & 2 deletions src/cpu/intel/Makefile.inc
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Expand Up @@ -18,8 +18,6 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += model_206ax
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE) += fsp_model_206ax
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_IVYBRIDGE) += fsp_model_206ax
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY) += fsp_model_406dx
subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1
subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA1155) += socket_LGA1155
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1 change: 0 additions & 1 deletion src/cpu/intel/car/romstage.c
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Expand Up @@ -11,7 +11,6 @@
* GNU General Public License for more details.
*/

#include <arch/cpu.h>
#include <console/console.h>
#include <cpu/intel/romstage.h>
#include <cpu/x86/mtrr.h>
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50 changes: 0 additions & 50 deletions src/cpu/intel/fsp_model_206ax/Kconfig
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12 changes: 0 additions & 12 deletions src/cpu/intel/fsp_model_206ax/Makefile.inc
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341 changes: 0 additions & 341 deletions src/cpu/intel/fsp_model_206ax/acpi.c
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97 changes: 0 additions & 97 deletions src/cpu/intel/fsp_model_206ax/acpi/cpu.asl
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31 changes: 0 additions & 31 deletions src/cpu/intel/fsp_model_206ax/chip.h
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77 changes: 0 additions & 77 deletions src/cpu/intel/fsp_model_206ax/finalize.c
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96 changes: 0 additions & 96 deletions src/cpu/intel/fsp_model_206ax/model_206ax.h
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395 changes: 0 additions & 395 deletions src/cpu/intel/fsp_model_206ax/model_206ax_init.c
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1 change: 0 additions & 1 deletion src/cpu/intel/fsp_model_406dx/bootblock.c
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Expand Up @@ -15,7 +15,6 @@
*/

#include <stdint.h>
#include <arch/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/intel/microcode/microcode.c>
#include <cpu/x86/msr.h>
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1 change: 0 additions & 1 deletion src/cpu/intel/haswell/bootblock.c
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Expand Up @@ -14,7 +14,6 @@
*/

#include <stdint.h>
#include <arch/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
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2 changes: 1 addition & 1 deletion src/cpu/intel/haswell/finalize.c
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Expand Up @@ -16,7 +16,7 @@

#include <stdint.h>
#include <stdlib.h>
#include <cpu/cpu.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include "haswell.h"

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2 changes: 0 additions & 2 deletions src/cpu/intel/haswell/romstage.c
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Expand Up @@ -15,11 +15,9 @@

#include <stdint.h>
#include <string.h>
#include <cbfs.h>
#include <console/console.h>
#include <arch/cpu.h>
#include <cf9_reset.h>
#include <cpu/cpu.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
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1 change: 0 additions & 1 deletion src/cpu/intel/haswell/smmrelocate.c
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Expand Up @@ -18,7 +18,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/mp.h>
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1 change: 0 additions & 1 deletion src/cpu/intel/hyperthreading/intel_sibling.c
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Expand Up @@ -12,7 +12,6 @@
*/

#include <console/console.h>
#include <cpu/cpu.h>
#include <cpu/x86/lapic.h>
#include <cpu/intel/hyperthreading.h>
#include <device/device.h>
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2 changes: 1 addition & 1 deletion src/cpu/intel/microcode/microcode.c
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Expand Up @@ -24,7 +24,7 @@
#else
#include <arch/cbfs.h>
#endif
#include <cpu/cpu.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <cpu/intel/microcode.h>
#include <rules.h>
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2 changes: 1 addition & 1 deletion src/cpu/intel/model_2065x/finalize.c
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Expand Up @@ -16,7 +16,7 @@

#include <stdint.h>
#include <stdlib.h>
#include <cpu/cpu.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <cpu/intel/speedstep.h>
#include "model_2065x.h"
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2 changes: 1 addition & 1 deletion src/cpu/intel/model_206ax/finalize.c
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Expand Up @@ -16,7 +16,7 @@

#include <stdint.h>
#include <stdlib.h>
#include <cpu/cpu.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <cpu/intel/speedstep.h>
#include "model_206ax.h"
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1 change: 0 additions & 1 deletion src/cpu/intel/slot_1/l2_cache.c
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Expand Up @@ -40,7 +40,6 @@

#include <stdint.h>
#include <console/console.h>
#include <cpu/cpu.h>
#include <cpu/intel/l2_cache.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/msr.h>
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1 change: 0 additions & 1 deletion src/cpu/intel/smm/gen1/smmrelocate.c
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Expand Up @@ -21,7 +21,6 @@
#include <string.h>
#include <device/device.h>
#include <device/pci.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
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2 changes: 2 additions & 0 deletions src/cpu/intel/socket_mFCPGA478/Kconfig
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Expand Up @@ -5,6 +5,8 @@ if CPU_INTEL_SOCKET_MFCPGA478

config SOCKET_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_INTEL_MODEL_69X
select CPU_INTEL_MODEL_6DX
select CPU_INTEL_MODEL_6EX
select CPU_INTEL_MODEL_6FX
select MMX
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1 change: 1 addition & 0 deletions src/cpu/qemu-x86/Kconfig
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Expand Up @@ -21,3 +21,4 @@ config CPU_QEMU_X86
select ARCH_RAMSTAGE_X86_32
select SMP
select UDELAY_TSC
select C_ENVIRONMENT_BOOTBLOCK
2 changes: 2 additions & 0 deletions src/cpu/qemu-x86/Makefile.inc
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Expand Up @@ -12,6 +12,8 @@
## GNU General Public License for more details.
##

bootblock-y += cache_as_ram_bootblock.S
bootblock-y += bootblock.c
ramstage-y += qemu.c
subdirs-y += ../x86/mtrr
subdirs-y += ../x86/lapic
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35 changes: 35 additions & 0 deletions src/cpu/qemu-x86/bootblock.c
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@@ -0,0 +1,35 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2004 Stefan Reinauer
* Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/

#include <bootblock_common.h>
#include <console/console.h>
#include <cpu/x86/bist.h>

asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist);

asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
{
post_code(0x05);

/* Halt if there was a built in self test failure */
if (bist) {
console_init();
report_bist_failure(bist);
}

/* Call lib/bootblock.c main */
bootblock_main_with_timestamp(base_timestamp, NULL, 0);
}
55 changes: 27 additions & 28 deletions ...rd/emulation/qemu-i440fx/cache_as_ram.inc → src/cpu/qemu-x86/cache_as_ram_bootblock.S
View file
Expand Up @@ -3,6 +3,7 @@
*
* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
* Copyright (C) 2007-2008 coresystems GmbH
* Copyright (C) 2018 Patrick Rudolph <siro@das-labor.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
Expand All @@ -14,14 +15,11 @@
* GNU General Public License for more details.
*/

#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>

#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)

/* Save the BIST result. */
movl %eax, %ebp
.global bootblock_pre_c_entry
bootblock_pre_c_entry:

cache_as_ram:
post_code(0x20)
Expand All @@ -31,33 +29,34 @@ cache_as_ram:
*/

post_code(0x21)
/*
* Set up the stack pointer, use top of real mode (640k) memory.
* This value also keeps the copy_and_run stack out of the way
* of big ramstages. The ramstage will load its own %esp so
* there is no harm in using this value.
*/
movl $0xa0000, %eax
movl %eax, %esp

/* Restore the BIST result. */
movl %ebp, %eax
movl %esp, %ebp
movl $_car_stack_end, %esp
/* Align the stack and keep aligned for call to bootblock_c_entry() */
and $0xfffffff0, %esp
sub $12, %esp

/* Clear the cache memory region. This will also clear CAR GLOBAL */
movl $_car_region_start, %esi
movl %esi, %edi
movl $_car_region_end, %ecx
sub $_car_region_start, %ecx
shr $2, %ecx
xorl %eax, %eax
rep stosl

/* Restore the BIST result and timestamps. */
movd %mm0, %ebx
movd %mm1, %eax
movd %mm2, %edx

pushl %ebx
pushl %edx
pushl %eax

before_romstage:
before_c_entry:
post_code(0x29)
/* Call romstage.c main function. */
call romstage_main

post_code(0x30)

__main:
post_code(POST_PREPARE_RAMSTAGE)
cld /* Clear direction flag. */

call copy_and_run

call bootblock_c_entry_bist
/* Never returns */
.Lhlt:
post_code(POST_DEAD_CODE)
hlt
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2 changes: 1 addition & 1 deletion src/cpu/qemu-x86/qemu.c
View file
Expand Up @@ -35,6 +35,6 @@ static const struct cpu_driver driver __cpu_driver = {
.id_table = cpu_table,
};

struct chip_operations cpu_x86_qemu_ops = {
struct chip_operations cpu_qemu_x86_ops = {
CHIP_NAME("QEMU x86 CPU")
};
4 changes: 1 addition & 3 deletions src/cpu/ti/am335x/Makefile.inc
View file
Expand Up @@ -12,11 +12,9 @@ ramstage-y += monotonic_timer.c
ramstage-y += nand.c
ramstage-y += cbmem.c

ifeq ($(CONFIG_DRIVERS_UART),y)
bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c
bootblock-y += uart.c
romstage-y += uart.c
ramstage-y += uart.c
endif

$(call add-class,omap-header)
$(eval $(call create_class_compiler,omap-header,arm))
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2 changes: 0 additions & 2 deletions src/cpu/via/Kconfig
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@@ -1,3 +1 @@
source src/cpu/via/c3/Kconfig
source src/cpu/via/c7/Kconfig
source src/cpu/via/nano/Kconfig
3 changes: 1 addition & 2 deletions src/cpu/via/nano/update_ucode.c
View file
Expand Up @@ -18,7 +18,6 @@
#include <cpu/x86/msr.h>
#include <console/console.h>
#include <stddef.h>
#include <cpu/cpu.h>
#include <arch/cpu.h>
#include <cbfs.h>

Expand Down Expand Up @@ -74,7 +73,7 @@ static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode)

static void nano_print_ucode_status(ucode_update_status stat)
{
switch(stat)
switch (stat)
{
case UCODE_UPDATE_SUCCESS:
printk(BIOS_INFO, "Microcode update successful.\n");
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1 change: 0 additions & 1 deletion src/cpu/x86/mp_init.c
View file
Expand Up @@ -31,7 +31,6 @@
#include <delay.h>
#include <device/device.h>
#include <device/path.h>
#include <lib.h>
#include <smp/atomic.h>
#include <smp/spinlock.h>
#include <symbols.h>
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1 change: 0 additions & 1 deletion src/cpu/x86/mtrr/mtrr.c
View file
Expand Up @@ -33,7 +33,6 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/lapic.h>
#include <arch/cpu.h>
#include <arch/acpi.h>
#include <memrange.h>
#include <cpu/amd/mtrr.h>
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2 changes: 1 addition & 1 deletion src/cpu/x86/name/name.c
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Expand Up @@ -14,8 +14,8 @@
*/

#include <string.h>
#include <arch/cpu.h>
#include <device/device.h>
#include <cpu/cpu.h>
#include <cpu/x86/name.h>

void fill_processor_name(char *processor_name)
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1 change: 0 additions & 1 deletion src/cpu/x86/pae/pgtbl.c
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Expand Up @@ -16,7 +16,6 @@
#include <cbfs.h>
#include <commonlib/helpers.h>
#include <console/console.h>
#include <cpu/cpu.h>
#include <arch/cpu.h>
#include <cpu/x86/cr.h>
#include <cpu/x86/msr.h>
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2 changes: 1 addition & 1 deletion src/device/device_util.c
View file
Expand Up @@ -168,7 +168,7 @@ const char *dev_path(const struct device *dev)
if (!dev) {
memcpy(buffer, "<null>", 7);
} else {
switch(dev->path.type) {
switch (dev->path.type) {
case DEVICE_PATH_NONE:
memcpy(buffer, "NONE", 5);
break;
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1 change: 0 additions & 1 deletion src/device/hypertransport.c
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Expand Up @@ -20,7 +20,6 @@
* GNU General Public License for more details.
*/

#include <lib.h>
#include <console/console.h>
#include <device/device.h>
#include <device/path.h>
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1 change: 0 additions & 1 deletion src/device/pci_ops_mmconf.c
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Expand Up @@ -11,7 +11,6 @@
* GNU General Public License for more details.
*/

#include <console/console.h>
#include <arch/io.h>
#include <device/pci.h>
#include <device/pci_ids.h>
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2 changes: 1 addition & 1 deletion src/drivers/amd/agesa/state_machine.c
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Expand Up @@ -18,9 +18,9 @@
#include <string.h>

#include <arch/acpi.h>
#include <arch/cpu.h>
#include <bootstate.h>
#include <cbfs.h>
#include <cbmem.h>

#include <northbridge/amd/agesa/state_machine.h>
#include <northbridge/amd/agesa/agesa_helper.h>
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1 change: 0 additions & 1 deletion src/drivers/ams/as3722rtc.c
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Expand Up @@ -14,7 +14,6 @@
*/

#include <bcd.h>
#include <console/console.h>
#include <device/i2c_simple.h>
#include <rtc.h>
#include <stdint.h>
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2 changes: 1 addition & 1 deletion src/drivers/aspeed/common/ast_main.c
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Expand Up @@ -195,7 +195,7 @@ static int ast_detect_chip(struct drm_device *dev, bool *need_post)
}

/* Print stuff for diagnostic purposes */
switch(ast->tx_chip_type) {
switch (ast->tx_chip_type) {
case AST_TX_SIL164:
DRM_INFO("Using Sil164 TMDS transmitter\n");
break;
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6 changes: 6 additions & 0 deletions src/drivers/elog/Kconfig
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Expand Up @@ -36,6 +36,12 @@ config ELOG_CBMEM
but it means that events added at runtime via the SMI handler
will not be reflected in the CBMEM copy of the log.

config ELOG_PRERAM
bool
default n
help
This option will enable event logging from the preram stage.

endif

config ELOG_GSMI
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4 changes: 4 additions & 0 deletions src/drivers/elog/Makefile.inc
View file
@@ -1,3 +1,7 @@
bootblock-$(CONFIG_ELOG_PRERAM) += elog.c
verstage-$(CONFIG_ELOG_PRERAM) += elog.c
romstage-$(CONFIG_ELOG_PRERAM) += elog.c
postcar-$(CONFIG_ELOG_PRERAM) += elog.c
ramstage-$(CONFIG_ELOG) += elog.c

smm-$(CONFIG_ELOG_GSMI) += elog.c gsmi.c
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