35 changes: 27 additions & 8 deletions Documentation/soc/amd/psp_integration.md
View file
Expand Up @@ -117,14 +117,23 @@ implementations currently use combo tables.
+--------------+---------------+------------------+----------------------------+
| Size | 0x04 | 32 | Size of PSP entry in bytes |
+--------------+---------------+------------------+----------------------------+
| Location / | 0x08 | 64 | Location: Physical Address |
| Location / | 0x08 | 62 | Location: Physical Address |
| Value | | | of SPIROM location where |
| | | | corresponding PSP entry |
| | | | located. |
| | | | |
| | | | Value: 64-bit value for the|
| | | | Value: 62-bit value for the|
| | | | PSP Entry |
+--------------+---------------+------------------+----------------------------+
| Address Mode | 0x0F[7:6] | 2 | 00: x86 Physical address |
| | | | 01: offset from start of |
| | | | BIOS (flash offset) |
| | | | 02: offset from start of |
| | | | directory header |
| | | | 03: offset from start of |
| | | | partition |
+--------------+---------------+------------------+----------------------------+
```
### PSP Directory Table Types

Expand Down Expand Up @@ -172,6 +181,10 @@ implementations currently use combo tables.
* Intermediate Key Encryption Key, used to decrypt encrypted firmware images.
This is mandatory in order to support encrypted firmware.

**0x22**: PSP Token Unlock data
* Used to support time-bound Secure Debug unlock during boot. This entry may
be omitted if the Token Unlock debug feature is not required.

**0x24**: Security policy binary
* A security policy is applied to restrict the untrusted access to security
sensitive regions.
Expand Down Expand Up @@ -200,10 +213,6 @@ implementations currently use combo tables.
**0x52**: PSP boot loader usermode OEM application
* Supported only in certain SKUs.

**0x22**: PSP Token Unlock data
* Used to support time-bound Secure Debug unlock during boot. This entry may
be omitted if the Token Unlock debug feature is not required.

### Firmware Version of Binaries

Every firmware binary contains 256 bytes of a PSP Header, which includes
Expand Down Expand Up @@ -302,15 +311,25 @@ The BIOS Directory table structure is slightly different from the PSP Directory:
+--------------+---------------+------------------+----------------------------+
| SubProgram | 0x03[2:0] | 3 | Specify the SubProgram |
+--------------+---------------+------------------+----------------------------+
| Reserved | 0x03[7:3] | 5 | Reserved - Set to zero |
| RomId | 0x03[4:3] | 2 | Which SPI device the |
| | | | content is placed in |
+--------------+---------------+------------------+----------------------------+
| Writeable | 0x03[5] | 1 | Region is writable or read |
| | | | only |
+--------------+---------------+------------------+----------------------------+
| Reserved | 0x03[7:6] | 2 | Reserved - Set to zero |
+--------------+---------------+------------------+----------------------------+
| Size | 0x04 | 32 | Memory Region Size |
+--------------+---------------+------------------+----------------------------+
| Source | 0x08 | 64 | Physical Address of SPIROM |
| Source | 0x08 | 62 | Physical Address of SPIROM |
| Address | | | location where the data for|
| | | | the corresponding entry is |
| | | | located |
+--------------+---------------+------------------+----------------------------+
| Entry Address| 0x0F[7:6] | 2 | Same as Entry Address Mode |
| Mode | | | in PSP directory table |
| | | | entry fields |
+--------------+---------------+------------------+----------------------------+
| Destination | 0x10 | 64 | Destination Address of |
| Address | | | memory location where the |
| | | | data for the corresponding |
Expand Down
2 changes: 1 addition & 1 deletion Documentation/util/ifdtool/layout.md
View file
Expand Up @@ -29,7 +29,7 @@ way to categorize anything required by the SoC but not provided by coreboot.
+------------+------------------+-----------+-------------------------------------------+
| 4 | Platform Data | SI_PDR | |
+------------+------------------+-----------+-------------------------------------------+
| 8 | EC Firmware | SI_EC | Most ChromeOS devices do not use this |
| 8 | EC Firmware | SI_EC | Most ChromeOS devices do not use this |
| | | | region; EC firmware is stored in BIOS |
| | | | region of flash |
+------------+------------------+-----------+-------------------------------------------+
Expand Down
49 changes: 49 additions & 0 deletions LICENSES/BSD-2-Clause-Patent.txt
View file
@@ -0,0 +1,49 @@
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:

1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.

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documentation and/or other materials provided with the distribution.

Subject to the terms and conditions of this license, each copyright
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royalty-free, irrevocable (except for failure to satisfy the conditions
of this license) patent license to make, have made, use, offer to sell,
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necessarily infringed by:

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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 changes: 23 additions & 0 deletions LICENSES/BSD-2-Clause.txt
View file
@@ -0,0 +1,23 @@
Copyright (c) <year> <owner>.

Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:

1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 changes: 31 additions & 0 deletions LICENSES/BSD-4-Clause-UC.txt
View file
@@ -0,0 +1,31 @@
Copyright [various years] The Regents of the University of California.
All rights reserved.

Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:

1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
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3. All advertising materials mentioning features or use of this software
must display the following acknowledgement: This product includes
software developed by the University of California, Berkeley and its
contributors.
4. Neither the name of the University nor the names of its contributors
may be used to endorse or promote products derived from this software
without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ''AS IS'' AND
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGE.
28 changes: 28 additions & 0 deletions LICENSES/CC-PDDC.txt
View file
@@ -0,0 +1,28 @@
The person or persons who have associated work with this document (the
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A certifier has taken reasonable steps to verify the copyright status of
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Dedicator makes this dedication for the benefit of the public at large
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Dedicator recognizes that, once placed in the public domain, the Work
may be freely reproduced, distributed, transmitted, used, modified,
built upon, or otherwise exploited by anyone for any purpose, commercial
or non-commercial, and in any way, including by methods that have not
yet been invented or conceived.
18 changes: 18 additions & 0 deletions LICENSES/HPND-sell-variant.txt
View file
@@ -0,0 +1,18 @@
Permission to use, copy, modify, distribute, and sell this software and
its documentation for any purpose is hereby granted without fee,
provided that the above copyright notice appears in all copies, and that
both that the copyright notice and this permission notice appear in
supporting documentation, and that the name of <copyright holder> <or
related entities> not be used in advertising or publicity pertaining to
distribution of the software without specific, written prior permission
. <copyright holder> makes no representations about the suitability of
this software for any purpose. It is provided "as is" without express or
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<copyright holder> DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS
SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS . IN NO EVENT SHALL <copyright holder> BE LIABLE FOR ANY
SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER
RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF
CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 changes: 20 additions & 0 deletions LICENSES/HPND.txt
View file
@@ -0,0 +1,20 @@
<copyright notice>

Permission to use, copy, modify and distribute this software and its
documentation for any purpose and without fee is hereby granted,
provided that the above copyright notice appear in all copies, and that
both that the copyright notice and this permission notice appear in
supporting documentation , and that the name of <copyright holder> <or
related entities> not be used in advertising or publicity pertaining to
distribution of the software without specific, written prior permission.
<copyright holder> makes no representations about the suitability of
this software for any purpose. It is provided "as is" without express or
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<copyright holder> DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS
SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND
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SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER
RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF
CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
74 changes: 74 additions & 0 deletions LICENSES/exceptions/GCC-exception-3.1.txt
View file
@@ -0,0 +1,74 @@
GCC RUNTIME LIBRARY EXCEPTION

Version 3.1, 31 March 2009

General information: http://www.gnu.org/licenses/gcc-exception.html

Copyright (C) 2009 Free Software Foundation, Inc. <http://fsf.org/>

Everyone is permitted to copy and distribute verbatim copies of this
license document, but changing it is not allowed.

This GCC Runtime Library Exception ("Exception") is an additional
permission under section 7 of the GNU General Public License, version 3
("GPLv3"). It applies to a given file (the "Runtime Library") that bears
a notice placed by the copyright holder of the file stating that the
file is governed by GPLv3 along with this Exception.

When you use GCC to compile a program, GCC may combine portions of
certain GCC header files and runtime libraries with the compiled
program. The purpose of this Exception is to allow compilation of
non-GPL (including proprietary) programs to use, in this way, the header
files and runtime libraries covered by this Exception.

0. Definitions.

A file is an "Independent Module" if it either requires the Runtime
Library for execution after a Compilation Process, or makes use of an
interface provided by the Runtime Library, but is not otherwise based
on the Runtime Library.

"GCC" means a version of the GNU Compiler Collection, with or without
modifications, governed by version 3 (or a specified later version) of
the GNU General Public License (GPL) with the option of using any
subsequent versions published by the FSF.

"GPL-compatible Software" is software whose conditions of propagation,
modification and use would permit combination with GCC in accord with
the license of GCC.

"Target Code" refers to output from any compiler for a real or virtual
target processor architecture, in executable form or suitable for
input to an assembler, loader, linker and/or execution phase.
Notwithstanding that, Target Code does not include data in any format
that is used as a compiler intermediate representation, or used for
producing a compiler intermediate representation.

The "Compilation Process" transforms code entirely represented in
non-intermediate languages designed for human-written code, and/or in
Java Virtual Machine byte code, into Target Code. Thus, for example,
use of source code generators and preprocessors need not be considered
part of the Compilation Process, since the Compilation Process can be
understood as starting with the output of the generators or
preprocessors.

A Compilation Process is "Eligible" if it is done using GCC, alone or
with other GPL-compatible software, or if it is done without using any
work based on GCC. For example, using non-GPL-compatible Software to
optimize any GCC intermediate representations would not qualify as an
Eligible Compilation Process.

1. Grant of Additional Permission.

You have permission to propagate a work of Target Code formed by
combining the Runtime Library with Independent Modules, even if such
propagation would otherwise violate the terms of GPLv3, provided that
all Target Code was generated by Eligible Compilation Processes. You
may then convey such a combination under terms of your choice,
consistent with the licensing of the Independent Modules.

2. No Weakening of GCC Copyleft.

The availability of this Exception does not imply any general
presumption that third-party software is unaffected by the copyleft
requirements of the license of GCC.
12 changes: 12 additions & 0 deletions LICENSES/exceptions/Linux-syscall-note.txt
View file
@@ -0,0 +1,12 @@
NOTE! This copyright does *not* cover user programs that use kernel
services by normal system calls - this is merely considered normal use
of the kernel, and does *not* fall under the heading of "derived work".
Also note that the GPL below is copyrighted by the Free Software
Foundation, but the instance of code that it refers to (the Linux
kernel) is copyrighted by me and others who actually wrote it.

Also note that the only valid version of the GPL as far as the kernel is
concerned is _this_ particular version of the license (ie v2, not v2.2
or v3.x or whatever), unless explicitly otherwise stated.

Linus Torvalds
27 changes: 22 additions & 5 deletions MAINTAINERS
View file
Expand Up @@ -248,6 +248,12 @@ M: Angel Pons <th3fanbus@gmail.com>
S: Maintained
F: src/mainboard/gigabyte/ga-h61m-series/

GOOGLE REX MAINBOARDS
M: Subrata Banik <subratabanik@google.com>
M: Tarun Tuli <taruntuli@google.com>
M: Kapil Porwal <kapilporwal@google.com>
S: Maintained
F: src/mainboard/google/rex/

GOOGLE BRYA MAINBOARDS
M: Tim Wawrzynczak <twawrzynczak@chromium.org>
Expand Down Expand Up @@ -362,7 +368,11 @@ M: Angel Pons <th3fanbus@gmail.com>
S: Maintained
F: src/mainboard/msi/h81m-p33/


MSI MS-7D25 MAINBOARDS
M: Michał Żygowski <michal.zygowski@3mdeb.com>
M: Michał Kopeć <michal.kopec@3mdeb.com>
S: Maintained
F: src/mainboard/msi/ms7d25/

OCP DELTALAKE MAINBOARD
M: Arthur Heymans <arthur@aheymans.xyz>
Expand Down Expand Up @@ -433,7 +443,7 @@ F: src/mainboard/prodrive/hermes/


PURISM MAINBOARDS
M: Matt DeVillier <matt.devillier@puri.sm>
M: Jonathon Hall <jonathon.hall@puri.sm>
S: Supported
F: src/mainboard/purism/

Expand Down Expand Up @@ -646,16 +656,16 @@ S: Maintained
F: src/soc/amd/picasso/
F: src/vendorcode/amd/fsp/picasso/

AMD Sabrina
AMD Mendocino
M: Marshall Dawson <marshalldawson3rd@gmail.com>
M: Felix Held <felix-coreboot@felixheld.de>
M: Jason Glenesk <jason.glenesk@gmail.com>
M: Raul E Rangel <rrangel@chromium.org>
M: Fred Reitberger <reitbergerfred@gmail.com>
M: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
S: Maintained
F: src/soc/amd/sabrina/
F: src/vendorcode/amd/fsp/sabrina/
F: src/soc/amd/mendocino/
F: src/vendorcode/amd/fsp/mendocino/

AMD Stoneyridge
M: Marshall Dawson <marshalldawson3rd@gmail.com>
Expand All @@ -664,6 +674,13 @@ M: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
S: Odd Fixes
F: src/soc/amd/stoneyridge/

INTEL METEORLAKE SOC
M: Subrata Banik <subratabanik@google.com>
M: Tarun Tuli <taruntuli@google.com>
M: Kapil Porwal <kapilporwal@google.com>
S: Maintained
F: src/soc/intel/meteorlake/

INTEL ALDERLAKE SOC
M: Tim Wawrzynczak <twawrzynczak@chromium.org>
S: Maintained
Expand Down
2 changes: 1 addition & 1 deletion Makefile.inc
View file
Expand Up @@ -442,7 +442,7 @@ ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
CFLAGS_common += -Wno-packed-not-aligned
CFLAGS_common += -fconserve-stack
CFLAGS_common += -Wnull-dereference -Wreturn-type
CFLAGS_common += -Wlogical-op -Wduplicated-cond
CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wno-array-compare
# cf. commit f69a99db (coreboot: x86: enable gc-sections)
CFLAGS_common += -Wno-unused-but-set-variable
endif
Expand Down
14 changes: 7 additions & 7 deletions configs/config.msi_ms7d25
View file
@@ -1,19 +1,19 @@
CONFIG_VENDOR_MSI=y
CONFIG_CBFS_SIZE=0x1000000
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_TIANOCORE_BOOT_TIMEOUT=3
CONFIG_EDK2_BOOT_TIMEOUT=3
CONFIG_BOARD_MSI_Z690_A_PRO_WIFI_DDR4=y
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
CONFIG_PCIEXP_HOTPLUG=y
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
CONFIG_POST_DEVICE_PCI_PCIE=y
CONFIG_POST_IO_PORT=0x80
CONFIG_PAYLOAD_TIANOCORE=y
CONFIG_TIANOCORE_REPOSITORY="https://github.com/Dasharo/edk2.git"
CONFIG_TIANOCORE_TAG_OR_REV="origin/dasharo"
CONFIG_TIANOCORE_CBMEM_LOGGING=y
CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC=y
CONFIG_TIANOCORE_SD_MMC_TIMEOUT=1000
CONFIG_PAYLOAD_EDK2=y
CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2.git"
CONFIG_EDK2_TAG_OR_REV="origin/dasharo"
CONFIG_EDK2_CBMEM_LOGGING=y
CONFIG_EDK2_FOLLOW_BGRT_SPEC=y
CONFIG_EDK2_SD_MMC_TIMEOUT=1000
CONFIG_TPM2=y
CONFIG_TPM_MEASURED_BOOT=y
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu1
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.17.0.2"
CONFIG_LOCALVERSION="v4.17.0.3"
CONFIG_VENDOR_PCENGINES=y
CONFIG_CBFS_SIZE=0x00200000
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu2
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.17.0.2"
CONFIG_LOCALVERSION="v4.17.0.3"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,157b"
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu3
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.17.0.2"
CONFIG_LOCALVERSION="v4.17.0.3"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,1539"
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu4
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.17.0.2"
CONFIG_LOCALVERSION="v4.17.0.3"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,1539"
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu5
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.17.0.2"
CONFIG_LOCALVERSION="v4.17.0.3"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,1539"
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu6
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.17.0.2"
CONFIG_LOCALVERSION="v4.17.0.3"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_PXE_ROM_ID="8086,1539"
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu7
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.17.0.2"
CONFIG_LOCALVERSION="v4.17.0.3"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
Expand Down
2 changes: 1 addition & 1 deletion configs/config.system76_gaze15
View file
@@ -1,5 +1,5 @@
CONFIG_VENDOR_SYSTEM76=y
CONFIG_BOARD_SYSTEM76_GAZE15=y
CONFIG_PAYLOAD_TIANOCORE=y
CONFIG_PAYLOAD_EDK2=y
CONFIG_RUN_FSP_GOP=y
CONFIG_SMMSTORE=y
2 changes: 1 addition & 1 deletion configs/config.system76_lemp9
View file
@@ -1,5 +1,5 @@
CONFIG_VENDOR_SYSTEM76=y
CONFIG_BOARD_SYSTEM76_LEMP9=y
CONFIG_PAYLOAD_TIANOCORE=y
CONFIG_PAYLOAD_EDK2=y
CONFIG_RUN_FSP_GOP=y
CONFIG_SMMSTORE=y
2 changes: 1 addition & 1 deletion configs/config.system76_oryp5
View file
@@ -1,6 +1,6 @@
CONFIG_VENDOR_SYSTEM76=y
CONFIG_BOARD_SYSTEM76_ORYP5=y
CONFIG_PAYLOAD_TIANOCORE=y
CONFIG_PAYLOAD_EDK2=y
CONFIG_POST_IO=n
CONFIG_RUN_FSP_GOP=y
CONFIG_SMMSTORE=y
1 change: 1 addition & 0 deletions payloads/Makefile.inc
View file
Expand Up @@ -26,6 +26,7 @@ payloads/external/iPXE \
payloads/external/tint \
payloads/external/sortbootorder \
payloads/external/tianocore \
payloads/external/edk2 \
payloads/external/GRUB2 \
payloads/external/LinuxBoot \
payloads/external/Yabits \
Expand Down
2 changes: 1 addition & 1 deletion payloads/external/.gitignore
View file
Expand Up @@ -3,7 +3,7 @@ FILO/filo/
GRUB2/grub2/
LinuxBoot/linuxboot/
SeaBIOS/seabios/
tianocore/tianocore/
edk2/edk2/
tint/tint/
U-Boot/u-boot/
Memtest86Plus/memtest86plus/
Expand Down
50 changes: 25 additions & 25 deletions payloads/external/Makefile.inc
View file
Expand Up @@ -214,35 +214,35 @@ payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(D
DEPTHCHARGE_REVISION_ID=$(CONFIG_DEPTHCHARGE_REVISION_ID) \
OVERRIDE_DEFCONFIG=$(CONFIG_LP_DEFCONFIG_OVERRIDE)

# Tianocore
# edk2

$(obj)/UEFIPAYLOAD.fd tianocore: $(DOTCONFIG)
$(MAKE) -C payloads/external/tianocore all \
$(obj)/UEFIPAYLOAD.fd edk2: $(DOTCONFIG)
$(MAKE) -C payloads/external/edk2 all \
HOSTCC="$(HOSTCC)" \
CC="$(HOSTCC)" \
CONFIG_TIANOCORE_REPOSITORY=$(CONFIG_TIANOCORE_REPOSITORY) \
CONFIG_TIANOCORE_TAG_OR_REV=$(CONFIG_TIANOCORE_TAG_OR_REV) \
CONFIG_TIANOCORE_UEFIPAYLOAD=$(CONFIG_TIANOCORE_UEFIPAYLOAD) \
CONFIG_TIANOCORE_UPSTREAM=$(CONFIG_TIANOCORE_UPSTREAM) \
CONFIG_TIANOCORE_CUSTOM=$(CONFIG_TIANOCORE_CUSTOM) \
CONFIG_TIANOCORE_CUSTOM_BUILD_PARAMS=$(CONFIG_TIANOCORE_CUSTOM_BUILD_PARAMS) \
CONFIG_TIANOCORE_COREBOOTPAYLOAD=$(CONFIG_TIANOCORE_COREBOOTPAYLOAD) \
CONFIG_TIANOCORE_DEBUG=$(CONFIG_TIANOCORE_DEBUG) \
CONFIG_TIANOCORE_RELEASE=$(CONFIG_TIANOCORE_RELEASE) \
CONFIG_TIANOCORE_ABOVE_4G_MEMORY=$(CONFIG_TIANOCORE_ABOVE_4G_MEMORY) \
CONFIG_TIANOCORE_BOOTSPLASH_FILE=$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
CONFIG_TIANOCORE_BOOT_MANAGER_ESCAPE=$(CONFIG_TIANOCORE_BOOT_MANAGER_ESCAPE) \
CONFIG_TIANOCORE_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) \
CONFIG_TIANOCORE_CBMEM_LOGGING=$(CONFIG_TIANOCORE_CBMEM_LOGGING) \
CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC=$(CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC) \
CONFIG_TIANOCORE_HAVE_EFI_SHELL=$(CONFIG_TIANOCORE_HAVE_EFI_SHELL) \
CONFIG_TIANOCORE_PRIORITIZE_INTERNAL=$(CONFIG_TIANOCORE_PRIORITIZE_INTERNAL) \
CONFIG_TIANOCORE_PS2_SUPPORT=$(CONFIG_TIANOCORE_PS2_SUPPORT) \
CONFIG_TIANOCORE_SERIAL_SUPPORT=$(TIANOCORE_SERIAL_SUPPORT) \
CONFIG_TIANOCORE_SD_MMC_TIMEOUT=$(CONFIG_TIANOCORE_SD_MMC_TIMEOUT) \
CONFIG_TIANOCORE_USE_8254_TIMER=$(CONFIG_TIANOCORE_USE_8254_TIMER) \
CONFIG_EDK2_REPOSITORY=$(CONFIG_EDK2_REPOSITORY) \
CONFIG_EDK2_TAG_OR_REV=$(CONFIG_EDK2_TAG_OR_REV) \
CONFIG_EDK2_UEFIPAYLOAD=$(CONFIG_EDK2_UEFIPAYLOAD) \
CONFIG_EDK2_UPSTREAM=$(CONFIG_EDK2_UPSTREAM) \
CONFIG_EDK2_CUSTOM=$(CONFIG_EDK2_CUSTOM) \
CONFIG_EDK2_CUSTOM_BUILD_PARAMS=$(CONFIG_EDK2_CUSTOM_BUILD_PARAMS) \
CONFIG_EDK2_DEBUG=$(CONFIG_EDK2_DEBUG) \
CONFIG_EDK2_RELEASE=$(CONFIG_EDK2_RELEASE) \
CONFIG_EDK2_ABOVE_4G_MEMORY=$(CONFIG_EDK2_ABOVE_4G_MEMORY) \
CONFIG_EDK2_BOOTSPLASH_FILE=$(CONFIG_EDK2_BOOTSPLASH_FILE) \
CONFIG_EDK2_BOOT_MANAGER_ESCAPE=$(CONFIG_EDK2_BOOT_MANAGER_ESCAPE) \
CONFIG_EDK2_BOOT_TIMEOUT=$(CONFIG_EDK2_BOOT_TIMEOUT) \
CONFIG_EDK2_CBMEM_LOGGING=$(CONFIG_EDK2_CBMEM_LOGGING) \
CONFIG_EDK2_FOLLOW_BGRT_SPEC=$(CONFIG_EDK2_FOLLOW_BGRT_SPEC) \
CONFIG_EDK2_FULL_SCREEN_SETUP=$(CONFIG_EDK2_FULL_SCREEN_SETUP) \
CONFIG_EDK2_HAVE_EFI_SHELL=$(CONFIG_EDK2_HAVE_EFI_SHELL) \
CONFIG_EDK2_PRIORITIZE_INTERNAL=$(CONFIG_EDK2_PRIORITIZE_INTERNAL) \
CONFIG_EDK2_PS2_SUPPORT=$(CONFIG_EDK2_PS2_SUPPORT) \
CONFIG_EDK2_SERIAL_SUPPORT=$(CONFIG_EDK2_SERIAL_SUPPORT) \
CONFIG_EDK2_SD_MMC_TIMEOUT=$(CONFIG_EDK2_SD_MMC_TIMEOUT) \
CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \
CONFIG_ECAM_MMCONF_LENGTH=$(CONFIG_ECAM_MMCONF_LENGTH) \
CONFIG_SMMSTORE_V2=$(CONFIG_SMMSTORE_v2) \
GCC_CC_x86_32=$(GCC_CC_x86_32) \
GCC_CC_x86_64=$(GCC_CC_x86_64) \
GCC_CC_arm=$(GCC_CC_arm) \
Expand All @@ -252,7 +252,7 @@ $(obj)/UEFIPAYLOAD.fd tianocore: $(DOTCONFIG)
OBJCOPY_arm=$(OBJCOPY_arm) \
OBJCOPY_arm64=$(OBJCOPY_arm64) \
MFLAGS= MAKEFLAGS=
mv payloads/external/tianocore/output/UEFIPAYLOAD.fd $@
mv payloads/external/edk2/output/UEFIPAYLOAD.fd $@

# FILO

Expand Down
131 changes: 59 additions & 72 deletions payloads/external/tianocore/Kconfig → payloads/external/edk2/Kconfig
View file
@@ -1,87 +1,77 @@
if PAYLOAD_TIANOCORE
if PAYLOAD_EDK2

config PAYLOAD_FILE
string "Tianocore binary"
string "edk2 binary"
default "$(obj)/UEFIPAYLOAD.fd"
help
The result of a UefiPayloadPkg build

choice
prompt "Tianocore payload"
default TIANOCORE_UEFIPAYLOAD
prompt "Tianocore's EDK II payload"
default EDK2_UEFIPAYLOAD
help
Select which type of payload Tianocore will build (default is UefiPayload)
UefiPayload: MrChromebox's customized fork of Tianocore which works on most
Select which type of payload edk2 will build (default is UefiPayload)
UefiPayload: MrChromebox's customized fork of edk2 which works on most
x86_64 devices
Upstream: Use upstream Tianocore payload from https://github.com/tianocore/edk2
CorebootPayload: MrChromebox's customized fork of the deprecated CorebootPayloadPkg
Tianocore build target. It may work better on some older hardware (eg, x230)
which does not work properly with the UefiPayloadPkg options.
Upstream: Use upstream edk2 payload from https://github.com/tianocore/edk2

config TIANOCORE_UEFIPAYLOAD
config EDK2_UEFIPAYLOAD
bool "UEFIPayload"
help
Select this option to build using MrChromebox's custom Tianocore fork,
Select this option to build using MrChromebox's custom edk2 fork,
which incorporates fixes/improvements from System 76's and 9elements' trees.

config TIANOCORE_UPSTREAM
config EDK2_UPSTREAM
bool "Upstream"
help
Select this option if you want to use upstream EDK2 to build Tianocore.
Select this option if you want to use upstream edk2 to build edk2.

config TIANOCORE_COREBOOTPAYLOAD
bool "CorebootPayload"
help
Select this option to build using MrChromebox's older (now deprecated)
CorebootPayloadPkg-based Tianocore branch

config TIANOCORE_CUSTOM
config EDK2_CUSTOM
bool "Custom"
help
Specify your own edk2 repository and branch to use.

endchoice

config TIANOCORE_REPOSITORY
config EDK2_REPOSITORY
string "URL to git repository for edk2"
default "https://github.com/tianocore/edk2" if TIANOCORE_UPSTREAM
default "https://github.com/mrchromebox/edk2" if TIANOCORE_UEFIPAYLOAD || TIANOCORE_COREBOOTPAYLOAD
default "https://github.com/tianocore/edk2" if EDK2_UPSTREAM
default "https://github.com/mrchromebox/edk2" if EDK2_UEFIPAYLOAD
help
coreboot supports an array of build options which can be found below. These options
will only have an effect if the relevant options exist in the target repository.

config TIANOCORE_TAG_OR_REV
config EDK2_TAG_OR_REV
string "Insert a commit's SHA-1 or a branch name"
default "origin/uefipayload_202107" if TIANOCORE_UEFIPAYLOAD
default "origin/master" if TIANOCORE_UPSTREAM
default "origin/coreboot_fb" if TIANOCORE_COREBOOTPAYLOAD
default "origin/uefipayload_202207" if EDK2_UEFIPAYLOAD
default "origin/master" if EDK2_UPSTREAM
help
The commit's SHA-1 or branch name of the revision to use. This must exist in
TIANOCORE_REPOSITORY, and in the case of a branch name, prefixed with origin i.e.
EDK2_REPOSITORY, and in the case of a branch name, prefixed with origin i.e.
"origin/uefipayload_202202"

choice
prompt "Tianocore build"
default TIANOCORE_RELEASE
prompt "edk2 build"
default EDK2_RELEASE
help
Select whether to generate a debug or release build for
Tianocore; default is to generate a release build.
edk2; default is to generate a release build.

config TIANOCORE_DEBUG
bool "Generate Tianocore debug build"
config EDK2_DEBUG
bool "Generate edk2 debug build"
help
Generate a debug build.

config TIANOCORE_RELEASE
bool "Generate Tianocore release build"
config EDK2_RELEASE
bool "Generate edk2 release build"
help
Generate a release build.

endchoice

if TIANOCORE_UEFIPAYLOAD || TIANOCORE_CUSTOM || TIANOCORE_UPSTREAM
if EDK2_UEFIPAYLOAD || EDK2_CUSTOM || EDK2_UPSTREAM

config TIANOCORE_ABOVE_4G_MEMORY
config EDK2_ABOVE_4G_MEMORY
bool "Enable above 4G memory"
default n
help
Expand All @@ -91,10 +81,9 @@ config TIANOCORE_ABOVE_4G_MEMORY
Disabling memory above 4G is useful for bootloaders that are not
fully 64-bit aware such as Qubes R4.0.4 bootloader.


config TIANOCORE_BOOTSPLASH_FILE
string "Tianocore Bootsplash path and filename"
default "Documentation/coreboot_logo.svg"
config EDK2_BOOTSPLASH_FILE
string "edk2 Bootsplash path and filename"
default "Documentation/coreboot_logo.bmp"
help
The path and filename of the file to use as graphical bootsplash
image. If this option is not configured, the default
Expand All @@ -104,7 +93,7 @@ config TIANOCORE_BOOTSPLASH_FILE
can be found [here](https://imagemagick.org/script/formats.php).

The build process will automatically convert this to the format that
EDK2 requires, which is an uncompressed BMP, in BMP3 format. It does
edk2 requires, which is an uncompressed BMP, in BMP3 format. It does
this using imagemagick (`convert splosh.bmp BMP3:splash.bmp`).

The newly formatted file will be the dimensions size as the original
Expand All @@ -127,90 +116,88 @@ config TIANOCORE_BOOTSPLASH_FILE
If an absolute path is not given, the path will assumed to be
relative to the coreboot root directory.

config TIANOCORE_BOOT_MANAGER_ESCAPE
config EDK2_BOOT_MANAGER_ESCAPE
bool "Use Escape key for Boot Manager"
default n
help
Use Escape as the hot-key to access the Boot Manager. This replaces
the default key of F2.

config TIANOCORE_BOOT_TIMEOUT
config EDK2_BOOT_TIMEOUT
int "Set the timeout for boot menu prompt"
default 2
help
The length of time in seconds for which the boot splash/menu prompt will be displayed.
For boards with an internal display, the default value of 2s is generally sufficient.
For boards with an external display, a value of 5s is generally sufficient.

config TIANOCORE_CBMEM_LOGGING
bool "Enable Tianocore logging to CBMEM"
config EDK2_CBMEM_LOGGING
bool "Enable edk2 logging to CBMEM"
help
Select this option if you want to enable Tianocore logging to CBMEM.
Select this option if you want to enable edk2 logging to CBMEM.
You may want to increase the default cbmem buffer size when selecting
this option, especially if using a debug (vs release) build.
Selecting this option will increase the payload size in CBFS by 0x10000.

config TIANOCORE_FOLLOW_BGRT_SPEC
config EDK2_FOLLOW_BGRT_SPEC
bool "Center logo 38.2% from the top of screen"
default n
help
Follow the BGRT Specification implemented by Microsoft and
the Boot Logo 38.2% will be vertically centered 38.2% from
the top of the display.

config TIANOCORE_HAVE_EFI_SHELL
config EDK2_FULL_SCREEN_SETUP
bool "Use the full screen for the edk2 frontpage"
default y
help
Allow edk2 to use the full screen to display the frontpage
(aka "Boot Menu"). With this option disable, it will be
limited to 640x480.

config EDK2_HAVE_EFI_SHELL
bool "Include EFI Shell"
default y
help
Include the EFI shell Binary

config TIANOCORE_PRIORITIZE_INTERNAL
config EDK2_PRIORITIZE_INTERNAL
bool "Prioritize internal boot devices"
default y
help
Prioritize internal boot devices over external devices

config TIANOCORE_PS2_SUPPORT
config EDK2_PS2_SUPPORT
bool "Support PS/2 Keyboards"
default y
help
Include support for PS/2 keyboards

config TIANOCORE_SD_MMC_TIMEOUT
config EDK2_SD_MMC_TIMEOUT
int "Timeout in ms for initializing SD and eMMC devices"
default 10
help
The amount of time allowed to initialize the SD Card reader and/or eMMC drive.
Most only require 10ms, but certain readers can take 1s.

config TIANOCORE_SERIAL_SUPPORT
config EDK2_SERIAL_SUPPORT
bool "Support serial output"
default y if TIANOCORE_DEBUG
default y if EDK2_DEBUG
default n
help
Enable serial port output in edk2. Serial output limits the performance of edk2's
FrontPage.

endif

if TIANOCORE_COREBOOTPAYLOAD

config TIANOCORE_USE_8254_TIMER
bool "TianoCore 8254 Timer"
config EDK2_CUSTOM_BUILD_PARAMS
string "edk2 additional custom build parameters"
default "-D VARIABLE_SUPPORT=SMMSTORE" if EDK2_UEFIPAYLOAD && SMMSTORE_V2
help
Use 8254 Timer for legacy support.
edk2 has build options that are not modified by coreboot, and these can be
found in `UefiPayloadPkg/UefiPayloadPkg.dsc`. Forks may also support
additional build options that should have been upstreamed but have not.

endif

if TIANOCORE_CUSTOM

config TIANOCORE_CUSTOM_BUILD_PARAMS
string "TianoCore additional custom build parameters"
help
Custom TianoCore forks may have different sets of parameters passed
to build command. You may specify additional parameters to the custom
TianoCore build

endif
This option can support both macros `-D` and Pcds `--pcd`.

endif
6 changes: 3 additions & 3 deletions payloads/external/tianocore/Kconfig.name → payloads/external/edk2/Kconfig.name
View file
@@ -1,9 +1,9 @@
config PAYLOAD_TIANOCORE
bool "Tianocore payload"
config PAYLOAD_EDK2
bool "edk2 payload"
depends on ARCH_X86 || ARCH_ARM64
help
Select this option if you want to build a coreboot image
with a Tianocore payload. If you don't know what this is
with a edk2 payload. If you don't know what this is
about, just leave it enabled.

See https://coreboot.org/Payloads for more information.
189 changes: 189 additions & 0 deletions payloads/external/edk2/Makefile
View file
@@ -0,0 +1,189 @@
## SPDX-License-Identifier: GPL-2.0-only

# force the shell to bash - the edksetup.sh script doesn't work with dash
export SHELL := env bash

project_name = edk2
project_dir = $(CURDIR)/$(word 3,$(subst /, ,$(CONFIG_EDK2_REPOSITORY)))

BUILD_STR = -a IA32 -a X64 -t COREBOOT
BUILD_STR += -p UefiPayloadPkg/UefiPayloadPkg.dsc
BUILD_STR += -D BOOTLOADER=COREBOOT -q

#
# EDK II has the following build options relevant to coreboot:
#
#
# OPTION = DEFAULT_VALUE
#
# ABOVE_4G_MEMORY = TRUE
ifneq ($(CONFIG_EDK2_ABOVE_4G_MEMORY),y)
BUILD_STR += -D ABOVE_4G_MEMORY=FALSE
endif
# BOOTSPLASH_IMAGE = FALSE
ifneq ($(CONFIG_EDK2_BOOTSPLASH_FILE),)
BUILD_STR += -D BOOTSPLASH_IMAGE=TRUE
endif
# BOOT_MANAGER_ESCAPE = FALSE
ifeq ($(CONFIG_EDK2_BOOT_MANAGER_ESCAPE),y)
BUILD_STR += -D BOOT_MANAGER_ESCAPE=TRUE
endif
# BUILD_TARGETS = DEBUG
ifeq ($(CONFIG_EDK2_RELEASE),y)
BUILD_STR += -b RELEASE
endif
# DISABLE_SERIAL_TERMINAL = FALSE
ifneq ($(CONFIG_EDK2_SERIAL_SUPPORT),y)
BUILD_STR += -D DISABLE_SERIAL_TERMINAL=TRUE
endif
# FOLLOW_BGRT_SPEC = FALSE
ifeq ($(CONFIG_EDK2_FOLLOW_BGRT_SPEC),y)
BUILD_STR += -D FOLLOW_BGRT_SPEC=TRUE
endif
# PCIE_BASE_ADDRESS = 0
ifneq ($(CONFIG_ECAM_MMCONF_LENGTH),)
BUILD_STR += --pcd gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS)
endif
# PCIE_BASE_LENGTH = 0
ifneq ($(CONFIG_ECAM_MMCONF_LENGTH),)
BUILD_STR += --pcd gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize=$(CONFIG_ECAM_MMCONF_LENGTH)
endif
# PRIORITIZE_INTERNAL = FALSE
ifeq ($(CONFIG_EDK2_PRIORITIZE_INTERNAL),y)
BUILD_STR += -D PRIORITIZE_INTERNAL=TRUE
endif
# PS2_KEYBOARD_ENABLE = FALSE
ifeq ($(CONFIG_EDK2_PS2_SUPPORT),y)
BUILD_STR += -D PS2_KEYBOARD_ENABLE=TRUE
endif
# PLATFORM_BOOT_TIMEOUT = 3
ifneq ($(CONFIG_EDK2_BOOT_TIMEOUT),)
BUILD_STR += -D PLATFORM_BOOT_TIMEOUT=$(CONFIG_EDK2_BOOT_TIMEOUT)
endif
# SIO_BUS_ENABLE = FALSE
ifeq ($(CONFIG_EDK2_PS2_SUPPORT),y)
BUILD_STR += -D SIO_BUS_ENABLE=TRUE
endif
# SHELL_TYPE = BUILD_SHELL
ifneq ($(CONFIG_EDK2_HAVE_EFI_SHELL),y)
BUILD_STR += -D SHELL_TYPE=NONE
endif
# USE_CBMEM_FOR_CONSOLE = FALSE
ifeq ($(CONFIG_EDK2_CBMEM_LOGGING),y)
BUILD_STR += -D USE_CBMEM_FOR_CONSOLE=TRUE
endif
# SD_MMC_TIMEOUT = 1000000
ifneq ($(CONFIG_EDK2_SD_MMC_TIMEOUT),)
BUILD_STR += -D SD_MMC_TIMEOUT=$(shell echo $$(( $(CONFIG_EDK2_SD_MMC_TIMEOUT) * 1000)) )
endif

#
# EDKII has the below PCDs that are relevant to coreboot:
#
# Allows EDKII to use the full framebuffer
ifeq ($(CONFIG_EDK2_FULL_SCREEN_SETUP),y)
BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow=0
BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn=0
BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow=0
BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn=0
endif

bootloader = $(word 8,$(subst /, ,$(BUILD_STR)))

ifneq ($(CONFIG_EDK2_CUSTOM_BUILD_PARAMS),)
BUILD_STR += $(CONFIG_EDK2_CUSTOM_BUILD_PARAMS)
endif

all: clean build

$(project_dir):
echo " Cloning $(project_name) from $(CONFIG_EDK2_REPOSITORY)"
git clone $(CONFIG_EDK2_REPOSITORY) $(project_dir); \
cd $(project_dir);

update: $(project_dir)
if [ ! -d "$(project_dir)" ]; then \
git clone $(CONFIG_EDK2_REPOSITORY) $(project_dir); \
fi
cd $(project_dir); \
git checkout MdeModulePkg/Logo/Logo.bmp > /dev/null 2>&1 || true; \
echo " Fetching new commits from $(CONFIG_EDK2_REPOSITORY)"; \
git fetch origin 2>/dev/null; \
if ! git rev-parse --verify -q $(CONFIG_EDK2_TAG_OR_REV) >/dev/null; then \
echo " $(CONFIG_EDK2_TAG_OR_REV) is not a valid git reference"; \
exit 1; \
fi; \
if git status --ignore-submodules=dirty | grep -q clean; then \
echo " Checking out $(project_name) revision $(CONFIG_EDK2_TAG_OR_REV)"; \
git checkout --detach $(CONFIG_EDK2_TAG_OR_REV) -f; \
else \
echo " Working directory not clean; will not overwrite"; \
fi; \
git submodule update --init --checkout

logo: $(project_dir)
case "$(CONFIG_EDK2_BOOTSPLASH_FILE)" in \
"") ;; \
/*) convert -background None $(CONFIG_EDK2_BOOTSPLASH_FILE) \
BMP3:$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
*) convert -background None $(top)/$(CONFIG_EDK2_BOOTSPLASH_FILE) \
BMP3:$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
esac \

checktools:
echo -n "EDK2: Checking uuid-dev:"
echo "#include <uuid/uuid.h>" > libtest.c
echo "int main(int argc, char **argv) { (void) argc; (void) argv; return 0; }" >> libtest.c
$(HOSTCC) $(HOSTCCFLAGS) libtest.c -o libtest >/dev/null 2>&1 && echo " Found!" || \
( echo " Not found!"; \
echo "ERROR: please_install uuid-dev (libuuid-devel)"; exit 1 )
rm -rf libtest.c libtest
echo -n "EDK2: Checking nasm:"
type nasm > /dev/null 2>&1 && echo " Found!" || \
( echo " Not found!"; echo "ERROR: Please install nasm."; exit 1 )
echo -n "EDK2: Checking imagemagick:"
-convert -size 1x1 xc: test.png &> /dev/null;
if [ -f test.png ]; then \
rm test.png && echo " Found!"; \
else \
echo " Not found!"; \
echo "ERROR: Please install imagemagick"; \
exit 1; \
fi

print:
echo " ##### $(project_name) Build Summary #####"
echo " Repository: $(CONFIG_EDK2_REPOSITORY)"
echo " Branch: $(CONFIG_EDK2_TAG_OR_REV)"
echo " $(BUILD_STR)" | \
sed -e 's/--/-/g' -e 's/-/\n /g' | sort | sed \
-e 's/a /Architecture: /g' \
-e 's/b /Release: /g' \
-e 's/D /Option: /g' \
-e 's/pcd /Pcd: /g' \
-e 's/p /Payload: /g' \
-e 's/q /Build: Quiet/' \
-e 's/s /Build: Silent/' \
-e 's/t /Toolchain: /'

build: update print logo checktools
unset CC; $(MAKE) -C $(project_dir)/BaseTools 2>&1
cd $(project_dir); \
export EDK_TOOLS_PATH=$(project_dir)/BaseTools; \
export WORKSPACE=$(project_dir); \
. ./edksetup.sh BaseTools; \
grep -q "COREBOOT" $(project_dir)/Conf/tools_def.txt; \
if [ $$? -ne 0 ]; then \
cat ../tools_def.txt >> $(project_dir)/Conf/tools_def.txt; \
fi; \
build $(BUILD_STR); \
mkdir -p $(project_dir)/../output; \
mv $(project_dir)/Build/$(bootloader)*/*/FV/UEFIPAYLOAD.fd $(project_dir)/../output/UEFIPAYLOAD.fd; \

clean:
test -d $(project_dir) && (cd $(project_dir); rm -rf Build; rm -f Conf/tools_def.txt) || exit 0

distclean:
rm -rf */

.PHONY: all update checktools config build clean distclean logo
2 changes: 1 addition & 1 deletion payloads/external/tianocore/tools_def.txt → payloads/external/edk2/tools_def.txt
View file
Expand Up @@ -15,7 +15,7 @@
#

#The following has been adapted from the BaseTools/Conf/tools_def.template file
#and is used to direct the Tianocore build to use coreboot's crossgcc toolchain
#and is used to direct the edk2 build to use coreboot's crossgcc toolchain
#rather than the host machine's toolchain

DEFINE COREBOOT_IA32_PREFIX = ENV(GCC_CC_x86_32)
Expand Down
79 changes: 19 additions & 60 deletions payloads/external/tianocore/Makefile
View file
Expand Up @@ -40,22 +40,10 @@ endif
ifeq ($(CONFIG_TIANOCORE_RELEASE),y)
BUILD_STR += -b RELEASE
endif
# DISABLE_SERIAL_TERMINAL = FALSE
ifneq ($(CONFIG_TIANOCORE_SERIAL_SUPPORT),y)
BUILD_STR += -D DISABLE_SERIAL_TERMINAL=TRUE
endif
# FOLLOW_BGRT_SPEC = FALSE
ifeq ($(CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC),y)
BUILD_STR += -D FOLLOW_BGRT_SPEC=TRUE
endif
# PCIE_BASE_ADDRESS = 0
ifneq ($(CONFIG_ECAM_MMCONF_LENGTH),)
BUILD_STR += --pcd gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS)
endif
# PCIE_BASE_LENGTH = 0
ifneq ($(CONFIG_ECAM_MMCONF_LENGTH),)
BUILD_STR += --pcd gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize=$(CONFIG_ECAM_MMCONF_LENGTH)
endif
# PRIORITIZE_INTERNAL = FALSE
ifeq ($(CONFIG_TIANOCORE_PRIORITIZE_INTERNAL),y)
BUILD_STR += -D PRIORITIZE_INTERNAL=TRUE
Expand All @@ -82,29 +70,19 @@ BUILD_STR += -D USE_CBMEM_FOR_CONSOLE=TRUE
endif
# SD_MMC_TIMEOUT = 1000000
ifneq ($(CONFIG_TIANOCORE_SD_MMC_TIMEOUT),)
BUILD_STR += -D SD_MMC_TIMEOUT=$(call int-multiply, $(CONFIG_TIANOCORE_SD_MMC_TIMEOUT) 1000)
BUILD_STR += -D SD_MMC_TIMEOUT=$(CONFIG_TIANOCORE_SD_MMC_TIMEOUT)
endif
#
# EDKII has the below PCDs that are revalant to coreboot:
#
# Allows EDKII to use the full framebuffer
BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow=0
BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn=0
BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow=0
BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn=0
#
# The below are legacy options only available in CorebootPayloadPkg:
#
# PCIE_BASE = 0
ifeq ($(CONFIG_TIANOCORE_COREBOOTPAYLOAD),y)
ifneq ($(CONFIG_ECAM_MMCONF_BASE_ADDRESS),)
BUILD_STR += -D PCIE_BASE=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS)
endif
# USE_HPET_TIMER = FALSE
ifeq ($(CONFIG_TIANOCORE_USE_8254_TIMER),y)
BUILD_STR += -D USE_HPET_TIMER=TRUE
endif
endif # CONFIG_TIANOCORE_COREBOOTPAYLOAD

bootloader = $(word 8,$(subst /, ,$(BUILD_STR)))

Expand Down Expand Up @@ -140,48 +118,29 @@ update: $(project_dir)
fi; \
git submodule update --init --checkout

logo: $(project_dir)/edk2
case "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" in \
/*) convert -background None $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
BMP3:$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
*) convert -background None $(top)/$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
BMP3:$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
esac \

checktools:
echo -n "EDK2: Checking uuid-dev:"
echo "Checking uuid-dev..."
echo "#include <uuid/uuid.h>" > libtest.c
echo "int main(int argc, char **argv) { (void) argc; (void) argv; return 0; }" >> libtest.c
$(HOSTCC) $(HOSTCCFLAGS) libtest.c -o libtest >/dev/null 2>&1 && echo " Found!" || \
( echo " Not found!"; \
echo "ERROR: please_install uuid-dev (libuuid-devel)"; exit 1 )
$(HOSTCC) $(HOSTCCFLAGS) libtest.c -o libtest >/dev/null 2>&1 && echo " found uuid-dev." || \
( echo " Not found."; echo "ERROR: please_install uuid-dev (libuuid-devel)"; exit 1 )
rm -rf libtest.c libtest
echo -n "EDK2: Checking nasm:"
type nasm > /dev/null 2>&1 && echo " Found!" || \
( echo " Not found!"; echo "ERROR: Please install nasm."; exit 1 )
echo -n "EDK2: Checking imagemagick:"
-convert -size 1x1 xc: test.png &> /dev/null;
if [ -f test.png ]; then \
rm test.png && echo " Found!"; \
else \
echo " Not found!"; \
echo "ERROR: Please install imagemagick"; \
exit 1; \
fi
echo "Checking nasm..."
type nasm > /dev/null 2>&1 && echo " found nasm." || \
( echo " Not found."; echo "Error: Please install nasm."; exit 1 )

build: update logo checktools
echo " ##### $(project_name) Build Summary #####"
echo " Repository: $(CONFIG_TIANOCORE_REPOSITORY)"
echo " Branch: $(CONFIG_TIANOCORE_TAG_OR_REV)"
echo " $(BUILD_STR)" | \
sed 's/-/\n /g' | sort | sed \
-e 's/a /Architecture: /g' \
-e 's/b /Release: /g' \
-e 's/D /Option: /g' \
-e 's/p /Payload: /g' \
-e 's/q /Build: Quiet/' \
-e 's/t /Toolchain: /'
build: update checktools
unset CC; $(MAKE) -C $(project_dir)/BaseTools 2>&1
echo " build $(project_name) $(CONFIG_TIANOCORE_TAG_OR_REV)"
if [ -n "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" ]; then \
echo " Copying custom bootsplash image"; \
case "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" in \
/*) convert $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
BMP3:$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
*) convert $(top)/$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
BMP3:$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
esac \
fi; \
cd $(project_dir); \
export EDK_TOOLS_PATH=$(project_dir)/BaseTools; \
export WORKSPACE=$(project_dir); \
Expand All @@ -201,4 +160,4 @@ clean:
distclean:
rm -rf */

.PHONY: all update checktools config build clean distclean logo
.PHONY: all update checktools config build clean distclean
5 changes: 5 additions & 0 deletions payloads/libpayload/Kconfig
View file
Expand Up @@ -418,6 +418,11 @@ config PCIE_MEDIATEK
depends on PCI && !PCI_IO_OPS
default n

config PCIE_QCOM
bool "Support for PCIe devices on Qualcomm platforms"
depends on PCI && !PCI_IO_OPS
default n

config NVRAM
bool "Support for reading/writing NVRAM bytes"
depends on ARCH_X86 # for now
Expand Down
2 changes: 2 additions & 0 deletions payloads/libpayload/configs/config.herobrine
View file
Expand Up @@ -3,3 +3,5 @@ CONFIG_LP_ARCH_ARM64=y
CONFIG_LP_TIMER_ARM64_ARCH=y
CONFIG_LP_SERIAL_CONSOLE=y
CONFIG_LP_QUALCOMM_QUPV3_SERIAL_CONSOLE=y
CONFIG_LP_PCI=y
CONFIG_LP_PCIE_QCOM=y
1 change: 1 addition & 0 deletions payloads/libpayload/drivers/Makefile.inc
View file
Expand Up @@ -37,6 +37,7 @@ libc-$(CONFIG_LP_PCI) += pci_map_bus_ops.c
endif

libc-$(CONFIG_LP_PCIE_MEDIATEK) += pcie_mediatek.c
libc-$(CONFIG_LP_PCIE_QCOM) += pci_qcom.c

libc-$(CONFIG_LP_SPEAKER) += speaker.c

Expand Down
126 changes: 126 additions & 0 deletions payloads/libpayload/drivers/pci_qcom.c
View file
@@ -0,0 +1,126 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <libpayload.h>
#include <pci.h>

/*
* iATU Unroll-specific register definitions
*/
#define PCIE_ATU_UNR_REGION_CTRL1 0x00
#define PCIE_ATU_UNR_REGION_CTRL2 0x04
#define PCIE_ATU_UNR_LOWER_BASE 0x08
#define PCIE_ATU_UNR_UPPER_BASE 0x0C
#define PCIE_ATU_UNR_LIMIT 0x10
#define PCIE_ATU_UNR_LOWER_TARGET 0x14
#define PCIE_ATU_UNR_UPPER_TARGET 0x18
#define PCIE_ATU_REGION_INDEX0 0x0
#define PCIE_ATU_TYPE_CFG0 0x4
#define PCIE_ATU_TYPE_CFG1 0x5
#define PCIE_ATU_ENABLE BIT(31)
#define ATU_CTRL2 PCIE_ATU_UNR_REGION_CTRL2
#define ATU_ENABLE PCIE_ATU_ENABLE

#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
#define LINK_WAIT_IATU_US 1000
#define LINK_WAIT_MAX_IATU_RETRIES 5

/* Register address builder */
#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) ((region) << 9)

#define lower_32_bits(n) ((u32)(n))
#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16))

/*
* ATU & endpoint config space base address offsets relative to
* PCIe controller base address.
*/
#define QCOM_ATU_BASE_OFFSET 0x1000
#define QCOM_EP_CFG_OFFSET 0x100000
#define QCOM_EP_CFG_SIZE 0x1000 /* 4K */

static void dw_pcie_writel_iatu(void *atu_base, unsigned short index,
uint32_t reg, uint32_t val)
{
uint32_t offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);

write32(atu_base + offset + reg, val);
}

static uint32_t dw_pcie_readl_iatu(void *atu_base, unsigned short index,
uint32_t reg)
{
uint32_t offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);

return read32(atu_base + offset + reg);
}

static void dw_pcie_prog_outbound_atu(void *atu_base, unsigned short index,
unsigned int type, uint64_t cfg_addr,
uint64_t pcie_addr, uint32_t cfg_size)
{
dw_pcie_writel_iatu(atu_base, index, PCIE_ATU_UNR_LOWER_BASE,
lower_32_bits(cfg_addr));
dw_pcie_writel_iatu(atu_base, index, PCIE_ATU_UNR_UPPER_BASE,
upper_32_bits(cfg_addr));
dw_pcie_writel_iatu(atu_base, index, PCIE_ATU_UNR_LIMIT,
lower_32_bits(cfg_addr + cfg_size - 1));
dw_pcie_writel_iatu(atu_base, index, PCIE_ATU_UNR_LOWER_TARGET,
lower_32_bits(pcie_addr));
dw_pcie_writel_iatu(atu_base, index, PCIE_ATU_UNR_UPPER_TARGET,
upper_32_bits(pcie_addr));
dw_pcie_writel_iatu(atu_base, index, PCIE_ATU_UNR_REGION_CTRL1, type);
dw_pcie_writel_iatu(atu_base, index, PCIE_ATU_UNR_REGION_CTRL2,
PCIE_ATU_ENABLE);
/*
* Make sure ATU enable takes effect before any subsequent config
* and I/O accesses.
*/
if (retry(LINK_WAIT_MAX_IATU_RETRIES,
(dw_pcie_readl_iatu(atu_base, index, ATU_CTRL2) & ATU_ENABLE),
udelay(LINK_WAIT_IATU_US)))
return;

printf("outbound iATU is couldn't be enabled after 5ms\n");
}

/* Get PCIe MMIO configuration space base address */
uintptr_t pci_map_bus(pcidev_t dev)
{
unsigned int atu_type, busdev;
uint32_t config_size;
void *cntrlr_base, *config_base, *atu_base;
unsigned int current_bus = PCI_BUS(dev);
unsigned int devfn = (PCI_SLOT(dev) << 3) | PCI_FUNC(dev);
static pcidev_t current_dev;

/*
* Extract PCIe controller base from coreboot and derive the ATU and
* endpoint config base addresses from it.
*/
cntrlr_base = (void *)lib_sysinfo.pcie_ctrl_base;
config_base = (void *)cntrlr_base + QCOM_EP_CFG_OFFSET;
config_size = (uint32_t)QCOM_EP_CFG_SIZE;
atu_base = (void *)cntrlr_base + QCOM_ATU_BASE_OFFSET;

/*
* Cache the dev. For same dev, ATU mapping is not needed for each
* request.
*/
if (current_dev == dev)
goto out;

current_dev = dev;

busdev = PCIE_ATU_BUS(current_bus) |
PCIE_ATU_DEV(PCI_SLOT(dev)) |
PCIE_ATU_FUNC(PCI_FUNC(dev));

atu_type = current_bus == 1 ? PCIE_ATU_TYPE_CFG0 : PCIE_ATU_TYPE_CFG1;

dw_pcie_prog_outbound_atu(atu_base, PCIE_ATU_REGION_INDEX0, atu_type,
(uint64_t)config_base, busdev, config_size);
out:
return (uintptr_t)config_base + (QCOM_EP_CFG_SIZE * devfn);
}
2 changes: 1 addition & 1 deletion payloads/libpayload/drivers/usb/dwc2.h
View file
Expand Up @@ -17,6 +17,6 @@
#include <usb/usb.h>

hci_t *dwc2_init(void *bar);
void dwc2_rh_init (usbdev_t *dev);
void dwc2_rh_init(usbdev_t *dev);

#endif
32 changes: 16 additions & 16 deletions payloads/libpayload/drivers/usb/ehci.c
View file
Expand Up @@ -119,17 +119,17 @@ static void dump_qh(ehci_qh_t *cur)
}
#endif

static void ehci_start (hci_t *controller)
static void ehci_start(hci_t *controller)
{
EHCI_INST(controller)->operation->usbcmd |= HC_OP_RS;
}

static void ehci_stop (hci_t *controller)
static void ehci_stop(hci_t *controller)
{
EHCI_INST(controller)->operation->usbcmd &= ~HC_OP_RS;
}

static void ehci_reset (hci_t *controller)
static void ehci_reset(hci_t *controller)
{
short count = 0;
ehci_stop(controller);
Expand All @@ -148,7 +148,7 @@ static void ehci_reset (hci_t *controller)
usb_debug("ehci_reset(): reset failed!\n");
}

static void ehci_reinit (hci_t *controller)
static void ehci_reinit(hci_t *controller)
{
}

Expand All @@ -174,7 +174,7 @@ static int ehci_set_periodic_schedule(ehci_t *ehcic, int enable)
return 0;
}

static void ehci_shutdown (hci_t *controller)
static void ehci_shutdown(hci_t *controller)
{
detach_controller(controller);

Expand All @@ -192,7 +192,7 @@ static void ehci_shutdown (hci_t *controller)
free(controller);
}

enum { EHCI_OUT=0, EHCI_IN=1, EHCI_SETUP=2 };
enum { EHCI_OUT = 0, EHCI_IN = 1, EHCI_SETUP = 2 };

/* returns handled bytes. assumes that the fields it writes are empty on entry */
static int fill_td(qtd_t *td, void* data, int datalen)
Expand Down Expand Up @@ -341,7 +341,7 @@ static int ehci_process_async_schedule(
return result;
}

static int ehci_bulk (endpoint_t *ep, int size, u8 *src, int finalize)
static int ehci_bulk(endpoint_t *ep, int size, u8 *src, int finalize)
{
int result = 0;
u8 *end = src + size;
Expand Down Expand Up @@ -430,7 +430,7 @@ static int ehci_bulk (endpoint_t *ep, int size, u8 *src, int finalize)
}

/* FIXME: Handle control transfers as 3 QHs, so the 2nd stage can be >0x4000 bytes */
static int ehci_control (usbdev_t *dev, direction_t dir, int drlen, void *setup,
static int ehci_control(usbdev_t *dev, direction_t dir, int drlen, void *setup,
int dalen, u8 *src)
{
u8 *data = src;
Expand Down Expand Up @@ -771,11 +771,11 @@ static u8 *ehci_poll_intr_queue(void *const queue)
}

hci_t *
ehci_init (unsigned long physical_bar)
ehci_init(unsigned long physical_bar)
{
int i;
hci_t *controller = new_controller ();
controller->instance = xzalloc(sizeof (ehci_t));
hci_t *controller = new_controller();
controller->instance = xzalloc(sizeof(ehci_t));
controller->reg_base = (uintptr_t)physical_bar;
controller->type = EHCI;
controller->start = ehci_start;
Expand All @@ -791,7 +791,7 @@ ehci_init (unsigned long physical_bar)
controller->create_intr_queue = ehci_create_intr_queue;
controller->destroy_intr_queue = ehci_destroy_intr_queue;
controller->poll_intr_queue = ehci_poll_intr_queue;
init_device_entry (controller, 0);
init_device_entry(controller, 0);

EHCI_INST(controller)->capabilities = phys_to_virt(physical_bar);
EHCI_INST(controller)->operation = (hc_op_t *)(phys_to_virt(physical_bar) + EHCI_INST(controller)->capabilities->caplength);
Expand Down Expand Up @@ -848,23 +848,23 @@ ehci_init (unsigned long physical_bar)

controller->devices[0]->controller = controller;
controller->devices[0]->init = ehci_rh_init;
controller->devices[0]->init (controller->devices[0]);
controller->devices[0]->init(controller->devices[0]);

return controller;
}

#if CONFIG(LP_USB_PCI)
hci_t *
ehci_pci_init (pcidev_t addr)
ehci_pci_init(pcidev_t addr)
{
hci_t *controller;
u32 reg_base;

u16 pci_command = pci_read_config16(addr, PCI_COMMAND);
pci_command = (pci_command | PCI_COMMAND_MEMORY) & ~PCI_COMMAND_IO ;
pci_command = (pci_command | PCI_COMMAND_MEMORY) & ~PCI_COMMAND_IO;
pci_write_config16(addr, PCI_COMMAND, pci_command);

reg_base = pci_read_config32 (addr, USBBASE);
reg_base = pci_read_config32(addr, USBBASE);

/* default value for frame length adjust */
pci_write_config8(addr, FLADJ, FLADJ_framelength(60000));
Expand Down
6 changes: 3 additions & 3 deletions payloads/libpayload/drivers/usb/ehci.h
View file
Expand Up @@ -32,9 +32,9 @@
#include <pci.h>
#include <usb/usb.h>

hci_t *ehci_pci_init (pcidev_t addr);
hci_t *ehci_init (unsigned long physical_bar);
hci_t *ehci_pci_init(pcidev_t addr);
hci_t *ehci_init(unsigned long physical_bar);

void ehci_rh_init (usbdev_t *dev);
void ehci_rh_init(usbdev_t *dev);

#endif
30 changes: 15 additions & 15 deletions payloads/libpayload/drivers/usb/ehci_rh.c
View file
Expand Up @@ -46,7 +46,7 @@ typedef struct {
#define RH_INST(dev) ((rh_inst_t*)(dev)->data)

static void
ehci_rh_destroy (usbdev_t *dev)
ehci_rh_destroy(usbdev_t *dev)
{
int port;

Expand All @@ -59,12 +59,12 @@ ehci_rh_destroy (usbdev_t *dev)
}
}

free (RH_INST(dev)->devices);
free (RH_INST(dev));
free(RH_INST(dev)->devices);
free(RH_INST(dev));
}

static void
ehci_rh_hand_over_port (usbdev_t *dev, int port)
ehci_rh_hand_over_port(usbdev_t *dev, int port)
{
usb_debug("giving up port %x, it's USB1\n", port+1);

Expand All @@ -89,14 +89,14 @@ ehci_rh_hand_over_port (usbdev_t *dev, int port)
}

static void
ehci_rh_scanport (usbdev_t *dev, int port)
ehci_rh_scanport(usbdev_t *dev, int port)
{
usb_speed port_speed;

if (RH_INST(dev)->devices[port]!=-1) {
if (RH_INST(dev)->devices[port] != -1) {
usb_debug("Unregister device at port %x\n", port+1);
usb_detach_device(dev->controller, RH_INST(dev)->devices[port]);
RH_INST(dev)->devices[port]=-1;
RH_INST(dev)->devices[port] = -1;
}
/* device connected, handle */
if (RH_INST(dev)->ports[port] & P_CURR_CONN_STATUS) {
Expand Down Expand Up @@ -153,26 +153,26 @@ ehci_rh_scanport (usbdev_t *dev, int port)
}

static int
ehci_rh_report_port_changes (usbdev_t *dev)
ehci_rh_report_port_changes(usbdev_t *dev)
{
int i;
for (i=0; i<RH_INST(dev)->n_ports; i++) {
for (i = 0; i < RH_INST(dev)->n_ports; i++) {
if (RH_INST(dev)->ports[i] & P_CONN_STATUS_CHANGE)
return i;
}
return -1;
}

static void
ehci_rh_poll (usbdev_t *dev)
ehci_rh_poll(usbdev_t *dev)
{
int port;
while ((port = ehci_rh_report_port_changes (dev)) != -1)
ehci_rh_scanport (dev, port);
while ((port = ehci_rh_report_port_changes(dev)) != -1)
ehci_rh_scanport(dev, port);
}

void
ehci_rh_init (usbdev_t *dev)
ehci_rh_init(usbdev_t *dev)
{
int i;
dev->destroy = ehci_rh_destroy;
Expand All @@ -192,7 +192,7 @@ ehci_rh_init (usbdev_t *dev)
& HCS_PORT_POWER_CONTROL) {
usb_debug("host controller has port power control, "
"giving power to all ports.\n");
for (i=0; i < RH_INST(dev)->n_ports; i++)
for (i = 0; i < RH_INST(dev)->n_ports; i++)
RH_INST(dev)->ports[i] |= P_PP;
}
mdelay(20); // ehci spec 2.3.9
Expand All @@ -201,7 +201,7 @@ ehci_rh_init (usbdev_t *dev)
dev->address = 0;
dev->hub = -1;
dev->port = -1;
for (i=0; i < RH_INST(dev)->n_ports; i++) {
for (i = 0; i < RH_INST(dev)->n_ports; i++) {
RH_INST(dev)->devices[i] = -1;
ehci_rh_scanport(dev, i);
}
Expand Down
2 changes: 1 addition & 1 deletion payloads/libpayload/drivers/usb/generic_hub.h
View file
Expand Up @@ -45,7 +45,7 @@ typedef struct generic_hub_ops {
/* returns 1 if the port is enabled */
int (*port_enabled)(usbdev_t *, int port);
/* returns speed if port is enabled, negative value if not */
usb_speed (*port_speed)(usbdev_t *, int port);
usb_speed(*port_speed)(usbdev_t *, int port);

/* enables (powers up) a port (optional) */
int (*enable_port)(usbdev_t *, int port);
Expand Down
118 changes: 59 additions & 59 deletions payloads/libpayload/drivers/usb/ohci.c
View file
Expand Up @@ -34,21 +34,21 @@
#include "ohci_private.h"
#include "ohci.h"

static void ohci_start (hci_t *controller);
static void ohci_stop (hci_t *controller);
static void ohci_reset (hci_t *controller);
static void ohci_shutdown (hci_t *controller);
static int ohci_bulk (endpoint_t *ep, int size, u8 *data, int finalize);
static int ohci_control (usbdev_t *dev, direction_t dir, int drlen, void *devreq,
static void ohci_start(hci_t *controller);
static void ohci_stop(hci_t *controller);
static void ohci_reset(hci_t *controller);
static void ohci_shutdown(hci_t *controller);
static int ohci_bulk(endpoint_t *ep, int size, u8 *data, int finalize);
static int ohci_control(usbdev_t *dev, direction_t dir, int drlen, void *devreq,
int dalen, u8 *data);
static void* ohci_create_intr_queue (endpoint_t *ep, int reqsize, int reqcount, int reqtiming);
static void ohci_destroy_intr_queue (endpoint_t *ep, void *queue);
static u8* ohci_poll_intr_queue (void *queue);
static void* ohci_create_intr_queue(endpoint_t *ep, int reqsize, int reqcount, int reqtiming);
static void ohci_destroy_intr_queue(endpoint_t *ep, void *queue);
static u8* ohci_poll_intr_queue(void *queue);
static int ohci_process_done_queue(ohci_t *ohci, int spew_debug);

#ifdef USB_DEBUG
static void
dump_td (td_t *cur)
dump_td(td_t *cur)
{
usb_debug("+---------------------------------------------------+\n");
if (((cur->config & (3UL << 19)) >> 19) == 0)
Expand Down Expand Up @@ -81,7 +81,7 @@ dump_td (td_t *cur)
}

static void
dump_ed (ed_t *cur)
dump_ed(ed_t *cur)
{
td_t *tmp_td = NULL;
usb_debug("+===================================================+\n");
Expand Down Expand Up @@ -120,7 +120,7 @@ dump_ed (ed_t *cur)
#endif

static void
ohci_reset (hci_t *controller)
ohci_reset(hci_t *controller)
{
if (controller == NULL)
return;
Expand All @@ -132,7 +132,7 @@ ohci_reset (hci_t *controller)
}

static void
ohci_reinit (hci_t *controller)
ohci_reinit(hci_t *controller)
{
}

Expand Down Expand Up @@ -167,12 +167,12 @@ static const char *direction[] = {
#endif

hci_t *
ohci_init (unsigned long physical_bar)
ohci_init(unsigned long physical_bar)
{
int i;

hci_t *controller = new_controller ();
controller->instance = xzalloc(sizeof (ohci_t));
hci_t *controller = new_controller();
controller->instance = xzalloc(sizeof(ohci_t));
controller->reg_base = (uintptr_t)physical_bar;
controller->type = OHCI;
controller->start = ohci_start;
Expand All @@ -188,33 +188,33 @@ ohci_init (unsigned long physical_bar)
controller->create_intr_queue = ohci_create_intr_queue;
controller->destroy_intr_queue = ohci_destroy_intr_queue;
controller->poll_intr_queue = ohci_poll_intr_queue;
init_device_entry (controller, 0);
OHCI_INST (controller)->roothub = controller->devices[0];
init_device_entry(controller, 0);
OHCI_INST(controller)->roothub = controller->devices[0];

OHCI_INST (controller)->opreg = (opreg_t*)phys_to_virt(physical_bar);
usb_debug("OHCI Version %x.%x\n", (OHCI_INST (controller)->opreg->HcRevision >> 4) & 0xf, OHCI_INST (controller)->opreg->HcRevision & 0xf);
OHCI_INST(controller)->opreg = (opreg_t*)phys_to_virt(physical_bar);
usb_debug("OHCI Version %x.%x\n", (OHCI_INST(controller)->opreg->HcRevision >> 4) & 0xf, OHCI_INST(controller)->opreg->HcRevision & 0xf);

if ((OHCI_INST (controller)->opreg->HcControl & HostControllerFunctionalStateMask) == USBReset) {
if ((OHCI_INST(controller)->opreg->HcControl & HostControllerFunctionalStateMask) == USBReset) {
/* cold boot */
OHCI_INST (controller)->opreg->HcControl &= ~RemoteWakeupConnected;
OHCI_INST (controller)->opreg->HcFmInterval = (11999 * FrameInterval) | ((((11999 - 210)*6)/7) * FSLargestDataPacket);
OHCI_INST(controller)->opreg->HcControl &= ~RemoteWakeupConnected;
OHCI_INST(controller)->opreg->HcFmInterval = (11999 * FrameInterval) | ((((11999 - 210)*6)/7) * FSLargestDataPacket);
/* TODO: right value for PowerOnToPowerGoodTime ? */
OHCI_INST (controller)->opreg->HcRhDescriptorA = NoPowerSwitching | NoOverCurrentProtection | (10 * PowerOnToPowerGoodTime);
OHCI_INST (controller)->opreg->HcRhDescriptorB = (0 * DeviceRemovable);
OHCI_INST(controller)->opreg->HcRhDescriptorA = NoPowerSwitching | NoOverCurrentProtection | (10 * PowerOnToPowerGoodTime);
OHCI_INST(controller)->opreg->HcRhDescriptorB = (0 * DeviceRemovable);
udelay(100); /* TODO: reset asserting according to USB spec */
} else if ((OHCI_INST (controller)->opreg->HcControl & HostControllerFunctionalStateMask) != USBOperational) {
OHCI_INST (controller)->opreg->HcControl = (OHCI_INST (controller)->opreg->HcControl & ~HostControllerFunctionalStateMask) | USBResume;
} else if ((OHCI_INST(controller)->opreg->HcControl & HostControllerFunctionalStateMask) != USBOperational) {
OHCI_INST(controller)->opreg->HcControl = (OHCI_INST(controller)->opreg->HcControl & ~HostControllerFunctionalStateMask) | USBResume;
udelay(100); /* TODO: resume time according to USB spec */
}
int interval = OHCI_INST (controller)->opreg->HcFmInterval;
int interval = OHCI_INST(controller)->opreg->HcFmInterval;

OHCI_INST (controller)->opreg->HcCommandStatus = HostControllerReset;
udelay (10); /* at most 10us for reset to complete. State must be set to Operational within 2ms (5.1.1.4) */
OHCI_INST (controller)->opreg->HcFmInterval = interval;
OHCI_INST (controller)->hcca = dma_memalign(256, 256);
OHCI_INST(controller)->opreg->HcCommandStatus = HostControllerReset;
udelay(10); /* at most 10us for reset to complete. State must be set to Operational within 2ms (5.1.1.4) */
OHCI_INST(controller)->opreg->HcFmInterval = interval;
OHCI_INST(controller)->hcca = dma_memalign(256, 256);
if (!OHCI_INST(controller)->hcca)
fatal("Not enough DMA memory for OHCI HCCA.\n");
memset((void*)OHCI_INST (controller)->hcca, 0, 256);
memset((void*)OHCI_INST(controller)->hcca, 0, 256);

if (dma_initialized()) {
OHCI_INST(controller)->dma_buffer = dma_memalign(4096, DMA_SIZE);
Expand All @@ -230,66 +230,66 @@ ohci_init (unsigned long physical_bar)
memset((void *)periodic_ed, 0, sizeof(*periodic_ed));
for (i = 0; i < 32; ++i)
intr_table[i] = virt_to_phys(periodic_ed);
OHCI_INST (controller)->periodic_ed = periodic_ed;
OHCI_INST(controller)->periodic_ed = periodic_ed;

OHCI_INST (controller)->opreg->HcHCCA = virt_to_phys(OHCI_INST (controller)->hcca);
OHCI_INST(controller)->opreg->HcHCCA = virt_to_phys(OHCI_INST(controller)->hcca);
/* Make sure periodic schedule is enabled. */
OHCI_INST (controller)->opreg->HcControl |= PeriodicListEnable;
OHCI_INST (controller)->opreg->HcControl &= ~IsochronousEnable; // unused by this driver
OHCI_INST(controller)->opreg->HcControl |= PeriodicListEnable;
OHCI_INST(controller)->opreg->HcControl &= ~IsochronousEnable; // unused by this driver
// disable everything, contrary to what OHCI spec says in 5.1.1.4, as we don't need IRQs
OHCI_INST (controller)->opreg->HcInterruptEnable = 1 << 31;
OHCI_INST (controller)->opreg->HcInterruptDisable = ~(1 << 31);
OHCI_INST (controller)->opreg->HcInterruptStatus = ~0;
OHCI_INST (controller)->opreg->HcPeriodicStart = (((OHCI_INST (controller)->opreg->HcFmInterval & FrameIntervalMask) / 10) * 9);
OHCI_INST (controller)->opreg->HcControl = (OHCI_INST (controller)->opreg->HcControl & ~HostControllerFunctionalStateMask) | USBOperational;
OHCI_INST(controller)->opreg->HcInterruptEnable = 1 << 31;
OHCI_INST(controller)->opreg->HcInterruptDisable = ~(1 << 31);
OHCI_INST(controller)->opreg->HcInterruptStatus = ~0;
OHCI_INST(controller)->opreg->HcPeriodicStart = (((OHCI_INST(controller)->opreg->HcFmInterval & FrameIntervalMask) / 10) * 9);
OHCI_INST(controller)->opreg->HcControl = (OHCI_INST(controller)->opreg->HcControl & ~HostControllerFunctionalStateMask) | USBOperational;

mdelay(100);

controller->devices[0]->controller = controller;
controller->devices[0]->init = ohci_rh_init;
controller->devices[0]->init (controller->devices[0]);
controller->devices[0]->init(controller->devices[0]);
return controller;
}

#if CONFIG(LP_USB_PCI)
hci_t *
ohci_pci_init (pcidev_t addr)
ohci_pci_init(pcidev_t addr)
{
u32 reg_base;

/* regarding OHCI spec, Appendix A, BAR_OHCI register description, Table A-4
* BASE ADDRESS only [31-12] bits. All other usually 0, but not all.
* OHCI mandates MMIO, so bit 0 is clear */
reg_base = pci_read_config32 (addr, 0x10) & 0xfffff000;
reg_base = pci_read_config32(addr, 0x10) & 0xfffff000;

return ohci_init((unsigned long)reg_base);
}
#endif

static void
ohci_shutdown (hci_t *controller)
ohci_shutdown(hci_t *controller)
{
if (controller == 0)
return;
detach_controller (controller);
detach_controller(controller);
ohci_stop(controller);
ohci_reset(controller);
free (OHCI_INST (controller)->hcca);
free ((void *)OHCI_INST (controller)->periodic_ed);
free (OHCI_INST (controller));
free (controller);
free(OHCI_INST(controller)->hcca);
free((void *)OHCI_INST(controller)->periodic_ed);
free(OHCI_INST(controller));
free(controller);
}

static void
ohci_start (hci_t *controller)
ohci_start(hci_t *controller)
{
OHCI_INST (controller)->opreg->HcControl |= PeriodicListEnable;
OHCI_INST(controller)->opreg->HcControl |= PeriodicListEnable;
}

static void
ohci_stop (hci_t *controller)
ohci_stop(hci_t *controller)
{
OHCI_INST (controller)->opreg->HcControl &= ~PeriodicListEnable;
OHCI_INST(controller)->opreg->HcControl &= ~PeriodicListEnable;
}

#define OHCI_SLEEP_TIME_US 1000
Expand Down Expand Up @@ -330,7 +330,7 @@ wait_for_ed(usbdev_t *dev, ed_t *head, int pages)
}

static void
ohci_free_ed (ed_t *const head)
ohci_free_ed(ed_t *const head)
{
/* In case the transfer canceled, we have to free unprocessed TDs. */
while ((head->head_pointer & ~0x3) != head->tail_pointer) {
Expand All @@ -351,7 +351,7 @@ ohci_free_ed (ed_t *const head)
}

static int
ohci_control (usbdev_t *dev, direction_t dir, int drlen, void *setup, int dalen,
ohci_control(usbdev_t *dev, direction_t dir, int drlen, void *setup, int dalen,
unsigned char *src)
{
u8 *data = src;
Expand Down Expand Up @@ -501,7 +501,7 @@ ohci_control (usbdev_t *dev, direction_t dir, int drlen, void *setup, int dalen,

/* finalize == 1: if data is of packet aligned size, add a zero length packet */
static int
ohci_bulk (endpoint_t *ep, int dalen, u8 *src, int finalize)
ohci_bulk(endpoint_t *ep, int dalen, u8 *src, int finalize)
{
int i;
td_t *cur, *next;
Expand Down Expand Up @@ -763,7 +763,7 @@ ohci_destroy_intr_queue(endpoint_t *const ep, void *const q_)
/* Remove interrupt queue from periodic table. */
ohci_t *const ohci = OHCI_INST(ep->dev->controller);
u32 *const intr_table = ohci->hcca->HccaInterruptTable;
for (i=0; i < 32; ++i) {
for (i = 0; i < 32; ++i) {
if (intr_table[i] == virt_to_phys(intrq))
intr_table[i] = virt_to_phys(ohci->periodic_ed);
}
Expand Down
6 changes: 3 additions & 3 deletions payloads/libpayload/drivers/usb/ohci.h
View file
Expand Up @@ -32,9 +32,9 @@
#include <pci.h>
#include <usb/usb.h>

hci_t *ohci_pci_init (pcidev_t addr);
hci_t *ohci_init (unsigned long physical_bar);
hci_t *ohci_pci_init(pcidev_t addr);
hci_t *ohci_init(unsigned long physical_bar);

void ohci_rh_init (usbdev_t *dev);
void ohci_rh_init(usbdev_t *dev);

#endif
2 changes: 1 addition & 1 deletion payloads/libpayload/drivers/usb/ohci_private.h
View file
Expand Up @@ -262,6 +262,6 @@
void *dma_buffer;
} ohci_t;

typedef enum { OHCI_SETUP=0, OHCI_OUT=1, OHCI_IN=2, OHCI_FROM_TD=3 } ohci_pid_t;
typedef enum { OHCI_SETUP = 0, OHCI_OUT = 1, OHCI_IN = 2, OHCI_FROM_TD = 3 } ohci_pid_t;

#endif
76 changes: 38 additions & 38 deletions payloads/libpayload/drivers/usb/ohci_rh.c
View file
Expand Up @@ -40,7 +40,7 @@ typedef struct {
#define RH_INST(dev) ((rh_inst_t*)(dev)->data)

static void
ohci_rh_enable_port (usbdev_t *dev, int port)
ohci_rh_enable_port(usbdev_t *dev, int port)
{
/* Reset RH port should hold 50ms with pulses of at least 10ms and
* gaps of at most 3ms (usb20 spec 7.1.7.5).
Expand All @@ -54,15 +54,15 @@ ohci_rh_enable_port (usbdev_t *dev, int port)
return;

/* start reset */
OHCI_INST (dev->controller)->opreg->HcRhPortStatus[port] =
OHCI_INST(dev->controller)->opreg->HcRhPortStatus[port] =
SetPortReset;
int timeout = 200; /* timeout after 200 * 500us == 100ms */
while ((OHCI_INST (dev->controller)->opreg->HcRhPortStatus[port]
while ((OHCI_INST(dev->controller)->opreg->HcRhPortStatus[port]
& PortResetStatus)
&& timeout--) {
udelay(500); total_delay--;
}
if (OHCI_INST (dev->controller)->opreg->HcRhPortStatus[port]
if (OHCI_INST(dev->controller)->opreg->HcRhPortStatus[port]
& PortResetStatus) {
usb_debug("Warning: root-hub port reset timed out.\n");
break;
Expand All @@ -72,67 +72,67 @@ ohci_rh_enable_port (usbdev_t *dev, int port)
"should be at least 10ms.\n",
(200-timeout)/2);
/* clear reset status change */
OHCI_INST (dev->controller)->opreg->HcRhPortStatus[port] =
OHCI_INST(dev->controller)->opreg->HcRhPortStatus[port] =
PortResetStatusChange;
usb_debug ("rh port reset finished after %dms.\n", (200-timeout)/2);
usb_debug("rh port reset finished after %dms.\n", (200-timeout)/2);
}
}

/* disable root hub */
static void
ohci_rh_disable_port (usbdev_t *dev, int port)
ohci_rh_disable_port(usbdev_t *dev, int port)
{
if (RH_INST (dev)->port[port] != -1) {
usb_detach_device(dev->controller, RH_INST (dev)->port[port]);
RH_INST (dev)->port[port] = -1;
if (RH_INST(dev)->port[port] != -1) {
usb_detach_device(dev->controller, RH_INST(dev)->port[port]);
RH_INST(dev)->port[port] = -1;
}

OHCI_INST (dev->controller)->opreg->HcRhPortStatus[port] = ClearPortEnable; // disable port
OHCI_INST(dev->controller)->opreg->HcRhPortStatus[port] = ClearPortEnable; // disable port
int timeout = 50; /* timeout after 50 * 100us == 5ms */
while ((OHCI_INST (dev->controller)->opreg->HcRhPortStatus[port]
while ((OHCI_INST(dev->controller)->opreg->HcRhPortStatus[port]
& PortEnableStatus)
&& timeout--) {
udelay(100);
}
}

static void
ohci_rh_scanport (usbdev_t *dev, int port)
ohci_rh_scanport(usbdev_t *dev, int port)
{
if (port >= RH_INST(dev)->numports) {
usb_debug("Invalid port %d\n", port);
return;
}

/* device registered, and device change logged, so something must have happened */
if (RH_INST (dev)->port[port] != -1) {
usb_detach_device(dev->controller, RH_INST (dev)->port[port]);
RH_INST (dev)->port[port] = -1;
if (RH_INST(dev)->port[port] != -1) {
usb_detach_device(dev->controller, RH_INST(dev)->port[port]);
RH_INST(dev)->port[port] = -1;
}

/* no device attached
previously registered devices are detached, nothing left to do */
if (!(OHCI_INST(dev->controller)->opreg->HcRhPortStatus[port] & CurrentConnectStatus))
return;

OHCI_INST (dev->controller)->opreg->HcRhPortStatus[port] = ConnectStatusChange; // clear port state change
ohci_rh_enable_port (dev, port);
OHCI_INST(dev->controller)->opreg->HcRhPortStatus[port] = ConnectStatusChange; // clear port state change
ohci_rh_enable_port(dev, port);

mdelay(100); // wait for signal to stabilize

if (!(OHCI_INST(dev->controller)->opreg->HcRhPortStatus[port] & PortEnableStatus)) {
usb_debug ("port enable failed\n");
usb_debug("port enable failed\n");
return;
}

usb_speed speed = (OHCI_INST(dev->controller)->opreg->HcRhPortStatus[port] & LowSpeedDeviceAttached) != 0;
RH_INST (dev)->port[port] = usb_attach_device(dev->controller, dev->address, port, speed);
RH_INST(dev)->port[port] = usb_attach_device(dev->controller, dev->address, port, speed);
}

static int
ohci_rh_report_port_changes (usbdev_t *dev)
ohci_rh_report_port_changes(usbdev_t *dev)
{
ohci_t *const ohcic = OHCI_INST (dev->controller);
ohci_t *const ohcic = OHCI_INST(dev->controller);

int i;

Expand All @@ -150,18 +150,18 @@ ohci_rh_report_port_changes (usbdev_t *dev)
}

static void
ohci_rh_destroy (usbdev_t *dev)
ohci_rh_destroy(usbdev_t *dev)
{
int i;
for (i = 0; i < RH_INST (dev)->numports; i++)
ohci_rh_disable_port (dev, i);
free (RH_INST (dev));
for (i = 0; i < RH_INST(dev)->numports; i++)
ohci_rh_disable_port(dev, i);
free(RH_INST(dev));
}

static void
ohci_rh_poll (usbdev_t *dev)
ohci_rh_poll(usbdev_t *dev)
{
ohci_t *const ohcic = OHCI_INST (dev->controller);
ohci_t *const ohcic = OHCI_INST(dev->controller);

int port;

Expand All @@ -172,26 +172,26 @@ ohci_rh_poll (usbdev_t *dev)
usb_debug("root hub status change\n");

/* Scan ports with changed connection status. */
while ((port = ohci_rh_report_port_changes (dev)) != -1)
ohci_rh_scanport (dev, port);
while ((port = ohci_rh_report_port_changes(dev)) != -1)
ohci_rh_scanport(dev, port);
}

void
ohci_rh_init (usbdev_t *dev)
ohci_rh_init(usbdev_t *dev)
{
int i;

dev->destroy = ohci_rh_destroy;
dev->poll = ohci_rh_poll;

dev->data = xmalloc (sizeof (rh_inst_t));
RH_INST (dev)->numports = OHCI_INST (dev->controller)->opreg->HcRhDescriptorA & NumberDownstreamPortsMask;
RH_INST (dev)->port = xmalloc(sizeof(int) * RH_INST (dev)->numports);
usb_debug("%d ports registered\n", RH_INST (dev)->numports);
dev->data = xmalloc(sizeof(rh_inst_t));
RH_INST(dev)->numports = OHCI_INST(dev->controller)->opreg->HcRhDescriptorA & NumberDownstreamPortsMask;
RH_INST(dev)->port = xmalloc(sizeof(int) * RH_INST(dev)->numports);
usb_debug("%d ports registered\n", RH_INST(dev)->numports);

for (i = 0; i < RH_INST (dev)->numports; i++) {
ohci_rh_enable_port (dev, i);
RH_INST (dev)->port[i] = -1;
for (i = 0; i < RH_INST(dev)->numports; i++) {
ohci_rh_enable_port(dev, i);
RH_INST(dev)->port[i] = -1;
}

/* we can set them here because a root hub _really_ shouldn't
Expand Down
284 changes: 142 additions & 142 deletions payloads/libpayload/drivers/usb/uhci.c
View file

Large diffs are not rendered by default.

4 changes: 2 additions & 2 deletions payloads/libpayload/drivers/usb/uhci.h
View file
Expand Up @@ -32,8 +32,8 @@
#include <pci.h>
#include <usb/usb.h>

hci_t *uhci_pci_init (pcidev_t addr);
hci_t *uhci_pci_init(pcidev_t addr);

void uhci_rh_init (usbdev_t *dev);
void uhci_rh_init(usbdev_t *dev);

#endif
12 changes: 6 additions & 6 deletions payloads/libpayload/drivers/usb/uhci_private.h
View file
Expand Up @@ -80,12 +80,12 @@ typedef struct {
0x12
} usbreg;

void uhci_reg_write32 (hci_t *ctrl, usbreg reg, u32 value);
u32 uhci_reg_read32 (hci_t *ctrl, usbreg reg);
void uhci_reg_write16 (hci_t *ctrl, usbreg reg, u16 value);
u16 uhci_reg_read16 (hci_t *ctrl, usbreg reg);
void uhci_reg_write8 (hci_t *ctrl, usbreg reg, u8 value);
u8 uhci_reg_read8 (hci_t *ctrl, usbreg reg);
void uhci_reg_write32(hci_t *ctrl, usbreg reg, u32 value);
u32 uhci_reg_read32(hci_t *ctrl, usbreg reg);
void uhci_reg_write16(hci_t *ctrl, usbreg reg, u16 value);
u16 uhci_reg_read16(hci_t *ctrl, usbreg reg);
void uhci_reg_write8(hci_t *ctrl, usbreg reg, u8 value);
u8 uhci_reg_read8(hci_t *ctrl, usbreg reg);

typedef struct uhci {
flistp_t *framelistptr;
Expand Down
72 changes: 36 additions & 36 deletions payloads/libpayload/drivers/usb/uhci_rh.c
View file
Expand Up @@ -39,7 +39,7 @@ typedef struct {
#define RH_INST(dev) ((rh_inst_t*)(dev)->data)

static void
uhci_rh_enable_port (usbdev_t *dev, int port)
uhci_rh_enable_port(usbdev_t *dev, int port)
{
u16 value;
hci_t *controller = dev->controller;
Expand All @@ -57,18 +57,18 @@ uhci_rh_enable_port (usbdev_t *dev, int port)

uhci_reg_write16(controller, port,
uhci_reg_read16(controller, port) | 1 << 9); /* reset */
mdelay (30); // >10ms
mdelay(30); // >10ms
uhci_reg_write16(controller, port,
uhci_reg_read16(controller, port) & ~(1 << 9));
mdelay (1); // >5.3us per spec, <3ms because some devices make trouble
mdelay(1); // >5.3us per spec, <3ms because some devices make trouble

uhci_reg_write16(controller, port,
uhci_reg_read16(controller, port) | 1 << 2); /* enable */
/* wait for controller to enable port */
/* TOTEST: how long to wait? 100ms for now */
int timeout = 200; /* time out after 200 * 500us == 100ms */
do {
value = uhci_reg_read16 (controller, port);
value = uhci_reg_read16(controller, port);
udelay(500); timeout--;
} while (((value & (1 << 2)) == 0) && (value & 0x01) && timeout);
if (!timeout)
Expand All @@ -77,7 +77,7 @@ uhci_rh_enable_port (usbdev_t *dev, int port)

/* disable root hub */
static void
uhci_rh_disable_port (usbdev_t *dev, int port)
uhci_rh_disable_port(usbdev_t *dev, int port)
{
hci_t *controller = dev->controller;
if (port == 1)
Expand All @@ -95,15 +95,15 @@ uhci_rh_disable_port (usbdev_t *dev, int port)
/* TOTEST: how long to wait? 100ms for now */
int timeout = 200; /* time out after 200 * 500us == 100ms */
do {
value = uhci_reg_read16 (controller, port);
value = uhci_reg_read16(controller, port);
udelay(500); timeout--;
} while (((value & (1 << 2)) != 0) && timeout);
if (!timeout)
usb_debug("Warning: uhci_rh: port disabling timed out.\n");
}

static void
uhci_rh_scanport (usbdev_t *dev, int port)
uhci_rh_scanport(usbdev_t *dev, int port)
{
int portsc, offset;
if (port == 1) {
Expand All @@ -116,54 +116,54 @@ uhci_rh_scanport (usbdev_t *dev, int port)
usb_debug("Invalid port %d\n", port);
return;
}
int devno = RH_INST (dev)->port[offset];
int devno = RH_INST(dev)->port[offset];
if ((devno != -1) && (dev->controller->devices[devno] != 0)) {
usb_detach_device(dev->controller, devno);
RH_INST (dev)->port[offset] = -1;
RH_INST(dev)->port[offset] = -1;
}
uhci_reg_write16(dev->controller, portsc,
uhci_reg_read16(dev->controller, portsc) | (1 << 3) | (1 << 2)); // clear port state change, enable port

mdelay(100); // wait for signal to stabilize

if ((uhci_reg_read16 (dev->controller, portsc) & 1) != 0) {
if ((uhci_reg_read16(dev->controller, portsc) & 1) != 0) {
// device attached

uhci_rh_disable_port (dev, port);
uhci_rh_enable_port (dev, port);
uhci_rh_disable_port(dev, port);
uhci_rh_enable_port(dev, port);

usb_speed speed = ((uhci_reg_read16 (dev->controller, portsc) >> 8) & 1);
usb_speed speed = ((uhci_reg_read16(dev->controller, portsc) >> 8) & 1);

RH_INST (dev)->port[offset] = usb_attach_device(dev->controller, dev->address, portsc, speed);
RH_INST(dev)->port[offset] = usb_attach_device(dev->controller, dev->address, portsc, speed);
}
}

static int
uhci_rh_report_port_changes (usbdev_t *dev)
uhci_rh_report_port_changes(usbdev_t *dev)
{
u16 stored, real;

stored = (RH_INST (dev)->port[0] == -1);
real = ((uhci_reg_read16 (dev->controller, PORTSC1) & 1) == 0);
stored = (RH_INST(dev)->port[0] == -1);
real = ((uhci_reg_read16(dev->controller, PORTSC1) & 1) == 0);
if (stored != real) {
usb_debug("change on port 1\n");
return 1;
}

stored = (RH_INST (dev)->port[1] == -1);
real = ((uhci_reg_read16 (dev->controller, PORTSC2) & 1) == 0);
stored = (RH_INST(dev)->port[1] == -1);
real = ((uhci_reg_read16(dev->controller, PORTSC2) & 1) == 0);
if (stored != real) {
usb_debug("change on port 2\n");
return 2;
}

// maybe detach+attach happened between two scans?

if ((uhci_reg_read16 (dev->controller, PORTSC1) & 2) > 0) {
if ((uhci_reg_read16(dev->controller, PORTSC1) & 2) > 0) {
usb_debug("possibly re-attached on port 1\n");
return 1;
}
if ((uhci_reg_read16 (dev->controller, PORTSC2) & 2) > 0) {
if ((uhci_reg_read16(dev->controller, PORTSC2) & 2) > 0) {
usb_debug("possibly re-attached on port 2\n");
return 2;
}
Expand All @@ -173,35 +173,35 @@ uhci_rh_report_port_changes (usbdev_t *dev)
}

static void
uhci_rh_destroy (usbdev_t *dev)
uhci_rh_destroy(usbdev_t *dev)
{
usb_detach_device (dev->controller, 1);
usb_detach_device (dev->controller, 2);
uhci_rh_disable_port (dev, 1);
uhci_rh_disable_port (dev, 2);
free (RH_INST (dev));
usb_detach_device(dev->controller, 1);
usb_detach_device(dev->controller, 2);
uhci_rh_disable_port(dev, 1);
uhci_rh_disable_port(dev, 2);
free(RH_INST(dev));
}

static void
uhci_rh_poll (usbdev_t *dev)
uhci_rh_poll(usbdev_t *dev)
{
int port;
while ((port = uhci_rh_report_port_changes (dev)) != -1)
uhci_rh_scanport (dev, port);
while ((port = uhci_rh_report_port_changes(dev)) != -1)
uhci_rh_scanport(dev, port);
}

void
uhci_rh_init (usbdev_t *dev)
uhci_rh_init(usbdev_t *dev)
{
dev->destroy = uhci_rh_destroy;
dev->poll = uhci_rh_poll;

uhci_rh_enable_port (dev, 1);
uhci_rh_enable_port (dev, 2);
dev->data = xmalloc (sizeof (rh_inst_t));
uhci_rh_enable_port(dev, 1);
uhci_rh_enable_port(dev, 2);
dev->data = xmalloc(sizeof(rh_inst_t));

RH_INST (dev)->port[0] = -1;
RH_INST (dev)->port[1] = -1;
RH_INST(dev)->port[0] = -1;
RH_INST(dev)->port[1] = -1;

/* we can set them here because a root hub _really_ shouldn't
appear elsewhere */
Expand Down
142 changes: 71 additions & 71 deletions payloads/libpayload/drivers/usb/usb.c
View file

Large diffs are not rendered by default.

8 changes: 4 additions & 4 deletions payloads/libpayload/drivers/usb/usb_dev.c
View file
Expand Up @@ -29,22 +29,22 @@
#include <usb/usb.h>

static void
usb_nop_destroy (usbdev_t *dev)
usb_nop_destroy(usbdev_t *dev)
{
usb_nop_init (dev);
usb_nop_init(dev);
dev->address = -1;
dev->hub = -1;
dev->port = -1;
}

static void
usb_nop_poll (usbdev_t *dev)
usb_nop_poll(usbdev_t *dev)
{
return;
}

void
usb_nop_init (usbdev_t *dev)
usb_nop_init(usbdev_t *dev)
{
dev->descriptor = NULL;
dev->configuration = NULL;
Expand Down
64 changes: 32 additions & 32 deletions payloads/libpayload/drivers/usb/usbhid.c
View file
Expand Up @@ -62,7 +62,7 @@ typedef struct {
#define HID_INST(dev) ((usbhid_inst_t*)(dev)->data)

static void
usb_hid_destroy (usbdev_t *dev)
usb_hid_destroy(usbdev_t *dev)
{
if (HID_INST(dev)->queue) {
int i;
Expand All @@ -82,7 +82,7 @@ usb_hid_destroy (usbdev_t *dev)
free(HID_INST(dev)->descriptor);
HID_INST(dev)->descriptor = NULL;

free (dev->data);
free(dev->data);
}

/* keybuffer is global to all USB keyboards */
Expand Down Expand Up @@ -268,14 +268,14 @@ usb_hid_process_keyboard_event(usbhid_inst_t *const inst,
if (current->modifiers & 0x01) /* Left-Ctrl */ modifiers |= KB_MOD_CTRL;
if (current->modifiers & 0x02) /* Left-Shift */ modifiers |= KB_MOD_SHIFT;
if (current->modifiers & 0x04) /* Left-Alt */ modifiers |= KB_MOD_ALT;
if (current->modifiers & 0x08) /* Left-GUI */ ;
if (current->modifiers & 0x08) /* Left-GUI */;
if (current->modifiers & 0x10) /* Right-Ctrl */ modifiers |= KB_MOD_CTRL;
if (current->modifiers & 0x20) /* Right-Shift */ modifiers |= KB_MOD_SHIFT;
if (current->modifiers & 0x40) /* Right-AltGr */ modifiers |= KB_MOD_ALT;
if (current->modifiers & 0x80) /* Right-GUI */ ;
if (current->modifiers & 0x80) /* Right-GUI */;

if ((current->modifiers & 0x05) && ((current->keys[0] == 0x4c) ||
(current->keys[0]==0x63))) {
(current->keys[0] == 0x63))) {
/* vulcan nerve pinch */
if (reset_handler)
reset_handler();
Expand All @@ -297,14 +297,14 @@ usb_hid_process_keyboard_event(usbhid_inst_t *const inst,

inst->lastkeypress = 0;

for (i=0; i<6; i++) {
for (i = 0; i < 6; i++) {
int j;
int skip = 0;
// No more keys? skip
if (current->keys[i] == 0)
return;

for (j=0; j<6; j++) {
for (j = 0; j < 6; j++) {
if (current->keys[i] == previous->keys[j]) {
skip = 1;
break;
Expand All @@ -328,7 +328,7 @@ usb_hid_process_keyboard_event(usbhid_inst_t *const inst,

if (keypress == -1) {
/* Debug: Print unknown keys */
usb_debug ("usbhid: <%x> %x [ %x %x %x %x %x %x ] %d\n",
usb_debug("usbhid: <%x> %x [ %x %x %x %x %x %x ] %d\n",
current->modifiers, current->repeats,
current->keys[0], current->keys[1],
current->keys[2], current->keys[3],
Expand All @@ -347,20 +347,20 @@ usb_hid_process_keyboard_event(usbhid_inst_t *const inst,
}

static void
usb_hid_poll (usbdev_t *dev)
usb_hid_poll(usbdev_t *dev)
{
usb_hid_keyboard_event_t current;
const u8 *buf;

while ((buf=dev->controller->poll_intr_queue (HID_INST(dev)->queue))) {
while ((buf = dev->controller->poll_intr_queue (HID_INST(dev)->queue))) {
memcpy(&current.buffer, buf, 8);
usb_hid_process_keyboard_event(HID_INST(dev), &current);
HID_INST(dev)->previous = current;
}
}

static void
usb_hid_set_idle (usbdev_t *dev, interface_descriptor_t *interface, u16 duration)
usb_hid_set_idle(usbdev_t *dev, interface_descriptor_t *interface, u16 duration)
{
dev_req_t dr;
dr.data_dir = host_to_device;
Expand All @@ -370,11 +370,11 @@ usb_hid_set_idle (usbdev_t *dev, interface_descriptor_t *interface, u16 duration
dr.wValue = (duration >> 2) << 8;
dr.wIndex = interface->bInterfaceNumber;
dr.wLength = 0;
dev->controller->control (dev, OUT, sizeof (dev_req_t), &dr, 0, 0);
dev->controller->control(dev, OUT, sizeof(dev_req_t), &dr, 0, 0);
}

static void
usb_hid_set_protocol (usbdev_t *dev, interface_descriptor_t *interface, hid_proto proto)
usb_hid_set_protocol(usbdev_t *dev, interface_descriptor_t *interface, hid_proto proto)
{
dev_req_t dr;
dr.data_dir = host_to_device;
Expand All @@ -384,7 +384,7 @@ usb_hid_set_protocol (usbdev_t *dev, interface_descriptor_t *interface, hid_prot
dr.wValue = proto;
dr.wIndex = interface->bInterfaceNumber;
dr.wLength = 0;
dev->controller->control (dev, OUT, sizeof (dev_req_t), &dr, 0, 0);
dev->controller->control(dev, OUT, sizeof(dev_req_t), &dr, 0, 0);
}

static struct console_input_driver cons = {
Expand All @@ -393,12 +393,12 @@ static struct console_input_driver cons = {
.input_type = CONSOLE_INPUT_TYPE_USB,
};

static int usb_hid_set_layout (const char *country)
static int usb_hid_set_layout(const char *country)
{
/* FIXME should be per keyboard */
int i;

for (i=0; i<ARRAY_SIZE(keyboard_layouts); i++) {
for (i = 0; i < ARRAY_SIZE(keyboard_layouts); i++) {
if (strncmp(keyboard_layouts[i].country, country,
strlen(keyboard_layouts[i].country)))
continue;
Expand All @@ -417,45 +417,45 @@ static int usb_hid_set_layout (const char *country)
}

void
usb_hid_init (usbdev_t *dev)
usb_hid_init(usbdev_t *dev)
{

static int installed = 0;
if (!installed) {
installed = 1;
console_add_input_driver (&cons);
console_add_input_driver(&cons);
}

configuration_descriptor_t *cd = (configuration_descriptor_t*)dev->configuration;
interface_descriptor_t *interface = (interface_descriptor_t*)(((char *) cd) + cd->bLength);

if (interface->bInterfaceSubClass == hid_subclass_boot) {
u8 countrycode;
usb_debug (" supports boot interface..\n");
usb_debug (" it's a %s\n",
usb_debug(" supports boot interface..\n");
usb_debug(" it's a %s\n",
boot_protos[interface->bInterfaceProtocol]);
switch (interface->bInterfaceProtocol) {
case hid_boot_proto_keyboard:
dev->data = xzalloc (sizeof (usbhid_inst_t));
usb_debug (" configuring...\n");
dev->data = xzalloc(sizeof(usbhid_inst_t));
usb_debug(" configuring...\n");
usb_hid_set_protocol(dev, interface, hid_proto_boot);
usb_hid_set_idle(dev, interface, KEYBOARD_REPEAT_MS);
usb_debug (" activating...\n");
usb_debug(" activating...\n");

hid_descriptor_t *desc = malloc(sizeof(hid_descriptor_t));
if (!desc || get_descriptor(dev, gen_bmRequestType(
device_to_host, standard_type, iface_recp),
0x21, 0, desc, sizeof(*desc)) != sizeof(*desc)) {
usb_debug ("get_descriptor(HID) failed\n");
usb_detach_device (dev->controller, dev->address);
usb_debug("get_descriptor(HID) failed\n");
usb_detach_device(dev->controller, dev->address);
return;
}
HID_INST (dev)->descriptor = desc;
HID_INST(dev)->descriptor = desc;
countrycode = desc->bCountryCode;
/* 35 countries defined: */
if (countrycode >= ARRAY_SIZE(countries))
countrycode = 0;
usb_debug (" Keyboard has %s layout (country code %02x)\n",
usb_debug(" Keyboard has %s layout (country code %02x)\n",
countries[countrycode][0], countrycode);

/* Set keyboard layout accordingly */
Expand All @@ -473,15 +473,15 @@ usb_hid_init (usbdev_t *dev)
break;
}
if (i >= dev->num_endp) {
usb_debug ("Could not find HID endpoint\n");
usb_detach_device (dev->controller, dev->address);
usb_debug("Could not find HID endpoint\n");
usb_detach_device(dev->controller, dev->address);
return;
}
usb_debug (" found endpoint %x for interrupt-in\n", i);
usb_debug(" found endpoint %x for interrupt-in\n", i);
/* 20 buffers of 8 bytes, for every 10 msecs */
HID_INST(dev)->queue = dev->controller->create_intr_queue (&dev->endpoints[i], 8, 20, 10);
HID_INST(dev)->queue = dev->controller->create_intr_queue(&dev->endpoints[i], 8, 20, 10);
keycount = 0;
usb_debug (" configuration done.\n");
usb_debug(" configuration done.\n");
break;
case hid_boot_proto_mouse:
usb_debug("NOTICE: USB mice are not supported.\n");
Expand Down
14 changes: 7 additions & 7 deletions payloads/libpayload/drivers/usb/usbhub.c
View file
Expand Up @@ -72,11 +72,11 @@ static int
usb_hub_port_status_changed(usbdev_t *const dev, const int port)
{
unsigned short buf[2];
int ret = get_status (dev, port, DR_PORT, sizeof(buf), buf);
int ret = get_status(dev, port, DR_PORT, sizeof(buf), buf);
if (ret >= 0) {
ret = buf[1] & PORT_CONNECTION;
if (ret)
clear_feature (dev, port, SEL_C_PORT_CONNECTION,
clear_feature(dev, port, SEL_C_PORT_CONNECTION,
DR_PORT);
}
return ret;
Expand All @@ -86,7 +86,7 @@ static int
usb_hub_port_connected(usbdev_t *const dev, const int port)
{
unsigned short buf[2];
int ret = get_status (dev, port, DR_PORT, sizeof(buf), buf);
int ret = get_status(dev, port, DR_PORT, sizeof(buf), buf);
if (ret >= 0)
ret = buf[0] & PORT_CONNECTION;
return ret;
Expand All @@ -96,7 +96,7 @@ static int
usb_hub_port_in_reset(usbdev_t *const dev, const int port)
{
unsigned short buf[2];
int ret = get_status (dev, port, DR_PORT, sizeof(buf), buf);
int ret = get_status(dev, port, DR_PORT, sizeof(buf), buf);
if (ret >= 0)
ret = buf[0] & PORT_RESET;
return ret;
Expand All @@ -106,7 +106,7 @@ static int
usb_hub_port_enabled(usbdev_t *const dev, const int port)
{
unsigned short buf[2];
int ret = get_status (dev, port, DR_PORT, sizeof(buf), buf);
int ret = get_status(dev, port, DR_PORT, sizeof(buf), buf);
if (ret >= 0)
ret = buf[0] & PORT_ENABLE;
return ret;
Expand All @@ -116,7 +116,7 @@ static usb_speed
usb_hub_port_speed(usbdev_t *const dev, const int port)
{
unsigned short buf[2];
int ret = get_status (dev, port, DR_PORT, sizeof(buf), buf);
int ret = get_status(dev, port, DR_PORT, sizeof(buf), buf);
if (ret >= 0 && (buf[0] & PORT_ENABLE)) {
/* SuperSpeed hubs can only have SuperSpeed devices. */
if (is_usb_speed_ss(dev->speed))
Expand Down Expand Up @@ -144,7 +144,7 @@ usb_hub_enable_port(usbdev_t *const dev, const int port)
static int
usb_hub_start_port_reset(usbdev_t *const dev, const int port)
{
return set_feature (dev, port, SEL_PORT_RESET, DR_PORT);
return set_feature(dev, port, SEL_PORT_RESET, DR_PORT);
}

static void usb_hub_set_hub_depth(usbdev_t *const dev)
Expand Down
4 changes: 2 additions & 2 deletions payloads/libpayload/drivers/usb/usbinit.c
View file
Expand Up @@ -52,7 +52,7 @@ static int usb_controller_initialize(int bus, int dev, int func)
pcidev_t pci_device;
u32 pciid;

pci_device = PCI_DEV (bus, dev, func);
pci_device = PCI_DEV(bus, dev, func);
class = pci_read_config32(pci_device, 8);
pciid = pci_read_config32(pci_device, 0);

Expand All @@ -73,7 +73,7 @@ static int usb_controller_initialize(int bus, int dev, int func)
case 0x00:
#if CONFIG(LP_USB_UHCI)
usb_debug("UHCI controller\n");
uhci_pci_init (pci_device);
uhci_pci_init(pci_device);
#else
usb_debug("UHCI controller (not supported)\n");
#endif
Expand Down