diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md
@@ -31,7 +31,7 @@ Look at the [flashing tutorial] and the board-specific section.
 These issues apply to all boards. Have a look at the board-specific issues, too.
 
 - TianoCore doesn't work with Aspeed NGI, as it's text mode only (Fix is WIP CB:35726)
-- MRC caching does not work with cold boot
+- MRC caching does not work on cold boot with Intel SPS (see [Intel FSP2.0])
 
 ## ToDo
 

diff --git a/Documentation/releases/checklist.md b/Documentation/releases/checklist.md
@@ -56,22 +56,24 @@ be more frequent than was needed, so we scaled it back to twice a year.
       and to update the release notes
 - [ ] Update the topic in the irc channel with the date of the upcoming
       release
+- [ ] Finalize release notes (as much as possible), without specifying
+      release commit ids
 
 ### Day of release
-- [ ] Update release notes, without specifying release commit ids
 - [ ] Select a commit ID to base the release upon, announce to IRC,
       ask for testing.
 - [ ] Test the commit selected for release
+- [ ] Update release notes with actual commit id, push to repo
 - [ ] Run release script
 - [ ] Test the release from the actual release tarballs
 - [ ] Push signed Tag to repo
 - [ ] Announce that the release tag is done on IRC
-- [ ] Update release notes with actual commit id, push to repo
 - [ ] Upload release files to web server
 - [ ] Upload crossgcc sources to web server
 - [ ] Update download page to point to files, push to repo
 - [ ] Write and publish blog post with release notes.
 - [ ] Update the topic in the irc channel that the release is done.
+- [ ] Announce the release to the mailing list
 
 ## Pre-Release tasks
 Announce the upcoming release to the mailing list release 2 weeks ahead
@@ -82,9 +84,7 @@ release notes that are in the making and ask people to test the hardware
 they have to make sure it's working with the current master branch,
 from which the release will ultimately be derived from.
 
-People should also be encouraged to provide additions to the
-release notes, for example by putting them on some [collaborative
-editor](https://www.piratenpad.de).
+People should be encouraged to provide additions to the release notes.
 
 The final release notes will reside in coreboot's Documentation/releases
 directory, so asking for additions to that through the regular Gerrit

diff --git a/Documentation/releases/coreboot-4.11-relnotes.md b/Documentation/releases/coreboot-4.11-relnotes.md
@@ -1,35 +1,133 @@
-Upcoming release - coreboot 4.11
-================================
+coreboot 4.11
+=============
 
-The 4.11 release is planned for October 2019
+coreboot 4.11 was released on November 19th.
 
-Update this document with changes that should be in the release
-notes.
-* Please use Markdown.
-* See the [4.9](coreboot-4.9-relnotes.md) and [4.10](coreboot-4.10-relnotes.md)
-  release notes for the general format.
-* The chip and board additions and removals will be updated right
-  before the release, so those do not need to be added.
+This release cycle was a bit shorter to get closer to our regular
+schedule of releasing in spring and autumn.
+
+Since 4.10 there were 1630 new commits by over 130 developers.
+Of these, about 30 contributed to coreboot for the first time.
+
+Thank you to all contributors who made 4.11 what it is and welcome
+to the project to all new contributors!
 
 Clean Up
 --------
+
+The past few months saw lots of cleanup across the source tree:
+
+The included headers in source files were stripped down to avoid reading
+unused headers, and unused code fragments, duplicate preprocessor symbols
+and configuration options were eliminated. Even ACPI got its share
+of attention, making our tables and bytecode more standards compliant
+than ever.
+
+The code across Intel's chipsets was unified some more into drivers for
+common function blocks, an effort we're more confident will succeed now
+that Intel itself is driving it.
+
+Chipset work
+------------
+
+Most activity in the last couple months was on Intel support,
+specifically the Kaby Lake and Cannon Lake drivers were extended
+for the generations following them.
+
+On ARM, the Mediatek 8173 chipset support saw significant work while
+the AMD side worked on getting Picasso support in.
+
+But everything else also saw some action, the relatively old
+(e.g. Intel GM45, Via VX900), the tiny (RISC-V) and the obscure
+(Quark).
+
+Verified Boot
+-------------
+
+The vboot feature that Chromebooks brought into coreboot was extended
+to work on devices that weren't specially adapted for it: In addition
+to its original device family it's now supported on various Lenovo
+laptops, Open Compute Project systems and Siemens industrial machines.
+
+Eltan's support for measured boot continues to be integrated with
+vboot, sharing data structures and generally working together where
+possible.
+
+New devices
+-----------
+
+With 4.11 there's the beginning of support for Intel Tiger Lake and
+Qualcomm's SC7180 SoCs, while we removed the unmaintained support
+for Allwinner's A10 SoC.
+
+There are also 25 new mainboards in our tree:
+
+* AMD PADMELON
+* ASUS P5QL-EM
+* EMULATION QEMU-AARCH64
+* GOOGLE AKEMI
+* GOOGLE ARCADA CML
+* GOOGLE DAMU
+* GOOGLE DOOD
+* GOOGLE DRALLION
+* GOOGLE DRATINI
+* GOOGLE JACUZZI
+* GOOGLE JUNIPER
+* GOOGLE KAKADU
+* GOOGLE KAPPA
+* GOOGLE PUFF
+* GOOGLE SARIEN CML
+* GOOGLE TREEYA
+* GOOGLE TROGDOR
+* LENOVO R60
+* LENOVO T410
+* LENOVO THINKPAD T440P
+* LENOVO X301
+* RAZER BLADE-STEALTH KBL
+* SIEMENS MC-APL6
+* SUPERMICRO X11SSH-TF
+* SUPERMICRO X11SSM-F
+
+In addition to the Cubieboard (which uses the A10 SoC), we also
+removed Google Hatch WHL.
+
+Deprecations
+------------
+
 Because there was only a single developer board (AMD Torpedo)
 using AGESA family 12h, and because there were multiple,
 unique Coverity issues with it, the associated vendorcode will
 be removed shortly after this release.
 
+Support for the MIPS architecture will also be removed shortly after
+this release as the only board in the tree was a discontinued development
+board and no other work has picked up MIPS support, so it's very likely
+broken already.
+
+After more than a year of planning and following the announcement in
+coreboot 4.10, platforms not using relocatable ramstage, a C bootblock
+and, on systems using Cache as RAM, a postcar stage, won't be supported
+going forward.
+
 Significant changes
 -------------------
 
-### Add significant changes here
-
 ### `__PRE_RAM__` is deprecated
 
-Preprocessor use of `defined(__PRE_RAM_)` have been mostly replaced with
+Preprocessor use of `defined(__PRE_RAM__)` have been mostly replaced with
 `if (ENV_ROMSTAGE_OR_BEFORE)` or the inverse `if (ENV_RAMSTAGE)`.
 
 The remaining cases and `-D__PRE_RAM__` are to be removed soon after release.
 
+### `__BOOTBLOCK__` et.al. are converted
+
+This applies to all `ENV_xxx` definitions found in `<rules.h>`.
+
+Write code without preprocessor directives whenever possible, replacing
+`#ifdef __BOOTBLOCK__` with  `if (ENV_BOOTBLOCK)`
+
+In cases where preprocessor is needed use `#if ENV_BOOTBLOCK` instead.
+
 ### `CAR_GLOBAL` is removed where possible
 
 For all platform code with `NO_CAR_GLOBAL_MIGRATION=y`, any `CAR_GLOBAL`
@@ -40,3 +138,76 @@ removed soon after release.
 
 Significant refactoring has bee done to achieve some consistency across platforms
 and to reduce code duplication.
+
+### Build system amenities ###
+
+The build system now has an `all` class of source files to remove the need to
+list source files for each and every source class (romstage, ramstage, ...)
+
+The site-local/ mechanism became more robust.
+
+### Stricter coding standards to improve security ###
+
+The build now fails on variable length arrays (that make it way too easy to
+smash a stack) and case statements falling through without a note that it is
+intentional.
+
+### Shorter file headers ###
+
+This project is still under way, but we started moving author information
+from individual files into the global AUTHORS file (and there's the git
+history for more details).
+
+In the future, we also want to replace the license headers (lots of lines)
+in each file with spdx identifiers (one line) and so we added a LICENSES/
+directory that contains the full text of all the licenses that are used
+throughout our tree.
+
+### Variant creation scripts ###
+
+To ease the creation of variant boards, `util/mainboard/` now contains
+scripts to generate a new variant to a given board. These are still
+specific to google/hatch at this time, but they're written with the idea
+of becoming more generally useful.
+
+### Payloads ###
+
+Payload integration has been updated, coreinfo learned to cope with
+UPPER CASE commands and libpayload knows how to deal with USB3 hubs.
+
+### Added VBOOT support to the following platforms:
+
+* intel/gm45
+* intel/nehalem
+
+### Moved the following platforms to C_ENVIRONMENT_BOOTBLOCK:
+
+* intel/i945
+* intel/x4x
+* intel/gm45
+* intel/nehalem
+* intel/sandybridge
+* intel/braswell
+
+### libgfxinit ###
+
+Most notable, dynamic CDClk configuration was added to libgfxinit,
+to support higher resolution displays without changes in the static
+configuration. It also received some fixes for better DP and eDP
+compatibility, better error recovery for Intel's fickle GMBus and
+updated platform support:
+* Correct HDMI clock limit for G45.
+* DP support for Ibex Peak (Ironlake graphics).
+* Fixed scaling on eDP for Broadwell.
+* Support for ULX variants of Haswell and later.
+* Support for Kaby, Amber, Coffee and Whiskey Lake.
+
+### Other
+* Did cleanups around TSC timer
+* Improved automatic VR configuration on SKL/KBL
+* Filled additional fields in SMBIOS type 4
+* Removed magic value replay from Intel Nehalem/ibexpeak code base
+* Added OpenSBI on RISCV platforms
+* Did more preparations for Intel TXT support
+* Did more preparations for x86_64 stage support
+* Added SSDT generator for arbitrary SuperIO chips based on devicetree.cb
diff --git a/Documentation/releases/coreboot-4.12-relnotes.md b/Documentation/releases/coreboot-4.12-relnotes.md
@@ -0,0 +1,20 @@
+Upcoming release - coreboot 4.12
+================================
+
+The 4.12 release is planned for April 2020
+
+Update this document with changes that should be in the release
+notes.
+* Please use Markdown.
+* See the past few release notes for the general format.
+* The chip and board additions and removals will be updated right
+  before the release, so those do not need to be added.
+
+Significant changes
+-------------------
+
+### SMMSTORE is now production ready
+
+See [smmstore](../drivers/smmstore.md) for the documentation on the API.
+
+### Add significant changes here
diff --git a/Documentation/releases/index.md b/Documentation/releases/index.md
@@ -11,6 +11,7 @@ Release notes for previous releases
 * [4.8 - May 2018](coreboot-4.8.1-relnotes.md)
 * [4.9 - December 2018](coreboot-4.9-relnotes.md)
 * [4.10 - July 2019](coreboot-4.10-relnotes.md)
+* [4.11 - November 2019](coreboot-4.11-relnotes.md)
 
 The checklist contains instructions to ensure that a release covers all
 important things and provides a reliable format for tarballs, branch
@@ -22,4 +23,4 @@ Upcoming release
 ----------------
 
 Please add to the release notes as changes are added:
-* [4.11 - October 2019](coreboot-4.11-relnotes.md)
+* [4.12 - April 2020](coreboot-4.12-relnotes.md)
diff --git a/Documentation/security/vboot/index.md b/Documentation/security/vboot/index.md
@@ -186,6 +186,26 @@ In addition to adding the coreboot files into the read-only region,
 enabling vboot causes the build script to add the read/write files into
 coreboot file systems in *FW_MAIN_A* and *FW_MAIN_B*.
 
+**RO_REGION_ONLY**  
+
+The files added to this list will only be placed in the read-only region and
+not into the read/write coreboot file systems in *FW_MAIN_A* and *FW_MAIN_B*.
+
+**VBOOT_ENABLE_CBFS_FALLBACK**  
+
+Normally coreboot will use the active read/write coreboot file system for all
+of it's file access when VBOOT is active and is not in recovery mode.
+
+When the `VBOOT_ENABLE_CBFS_FALLBACK` option is enabled the cbfs file system will
+first try to locate a file in the active read/write file system. If the file
+doesn't exist here the file system will try to locate the file in the read-only
+file system.
+
+This option can be used to prevent duplication of static data. Files can be
+removed from the read/write partitions by adding them to the `RO_REGION_ONLY`
+config. If a file needs to be changed in a later stage simply remove it from
+this list.
+
 ***
 
 ## Signing the coreboot Image

diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md
@@ -34,6 +34,11 @@ those are fixed. If possible a workaround is described here as well.
   * Workaround: none
   * Issue on public tracker: [Issue 22]
 
+* MRC forces memory re-training on cold boot on boards with Intel SPS
+  * Releases 3.7.1, 3.7.6
+  * Workaround: Flash Intel ME instead of SPS
+  * Issue on public tracker: [Issue 41]
+
 ### BraswellFsp
 * Internal UART can't be disabled using PcdEnableHsuart*
   * Release MR2
@@ -66,4 +71,5 @@ those are fixed. If possible a workaround is described here as well.
 [Issue 15]: https://github.com/IntelFsp/FSP/issues/15
 [Issue 22]: https://github.com/IntelFsp/FSP/issues/22
 [Issue 35]: https://github.com/IntelFsp/FSP/issues/35
+[Issue 41]: https://github.com/IntelFsp/FSP/issues/41
 
diff --git a/Documentation/tutorial/part2.md b/Documentation/tutorial/part2.md
@@ -157,10 +157,10 @@ commit, you wish to make changes to it, running `git commit --amend` allows
 you to take back your commit and amend it.
 
 When you are done with your commit, run `git push` to push your commit to
-coreboot.org. **Note:** To submit as a draft, use
-`git push origin HEAD:refs/drafts/master`. Submitting as a draft means that
-your commit will be on coreboot.org, but is only visible to those you add
-as reviewers.
+coreboot.org. **Note:** To submit as a private patch, use
+`git push origin HEAD:refs/for/master%private`. Submitting as a private patch
+means that your commit will be on review.coreboot.org, but is only visible to
+yourself and those you add as reviewers.
 
 This has been a quick primer on how to submit a change to Gerrit for review
 using git. You may wish to review the [Gerrit code review workflow
@@ -227,9 +227,6 @@ explained in the extended description.
 
 When ready, select 'Commit' again. Once all errors have been satisfied
 and the commit succeeds, move to the command line and run `git push`.
-**Note:** To submit as a draft, use `git push origin HEAD:refs/drafts/master`.
-Submitting as a draft means that your commit will be on coreboot.org, but is
-only visible to those you add as reviewers.
 
 ## Part 5: Getting your commit reviewed
 

diff --git a/Documentation/util.md b/Documentation/util.md
@@ -14,9 +14,6 @@ settings. `Perl`
 platform. `C`
 * __autoport__ - Automated porting coreboot to Sandy Bridge/Ivy Bridge
 platforms `Go`
-* __bimgtool__ - A simple tool which generates and verifies boot images
-in the BIMG format, used in systems designed by Imagination
-Technologies, for example the Pistachio SoC. `C`
 * __bincfg__ - Compiler/Decompiler for data blobs with specs `Lex`
 `Yacc`
 * __board_status__ - Tools to collect logs and upload them to the board

diff --git a/MAINTAINERS b/MAINTAINERS
@@ -217,18 +217,10 @@ F:	src/mainboard/google/parrot/
 F:	src/mainboard/google/slippy/
 F:	src/mainboard/google/stout/
 
-OCP MAINBOARDS
-M:	Philipp Deppenwiese <zaolin.daisuki@gmail.com>
-M:	Patrick Rudolph <patrick.rudolph@9elements.com>
-S:	Supported
-F:	src/mainboard/ocp/wedge100s/
-F:	src/mainboard/ocp/monolake/
-
 OPENCELLULAR MAINBOARDS
 M:	Philipp Deppenwiese <zaolin.daisuki@gmail.com>
 M:	Patrick Rudolph <patrick.rudolph@9elements.com>
 S:	Supported
-F:	src/mainboard/opencellular/rotundu/
 F:	src/mainboard/opencellular/elgon/
 
 PURISM MAINBOARDS
@@ -242,30 +234,6 @@ S:	Maintained
 F:	src/mainboard/samsung/lumpy/
 F:	src/mainboard/samsung/stumpy/
 
-INTEL MINNOWBOARD MAX MAINBOARD
-M:	Huang Jin <huang.jin@intel.com>
-M:	York Yang <york.yang@intel.com>
-S:	Supported
-F:	src/mainboard/intel/minnowmax/
-
-INTEL FSP BAYTRAIL CHIP & CRBs
-M:	Huang Jin <huang.jin@intel.com>
-M:	York Yang <york.yang@intel.com>
-M:	Philipp Deppenwiese <zaolin.daisuki@gmail.com>
-S:	Supported
-F:	src/soc/intel/fsp_baytrail/
-F:	src/vendorcode/intel/fsp1_0/baytrail/
-F:	src/mainboard/intel/bakersport_fsp/
-F:	src/mainboard/intel/bayleybay_fsp/
-
-INTEL FSP BROADWELL-DE SOC & CRB
-M:	York Yang <york.yang@intel.com>
-M:	Philipp Deppenwiese <zaolin.daisuki@gmail.com>
-S:	Supported
-F:	src/soc/intel/fsp_broadwell_de/
-F:	src/vendorcode/intel/fsp1_0/broadwell_de/
-F:	src/mainboard/intel/camelbackmountain_fsp/
-
 INTEL FSP DENVERTON-NS SOC & HARCUVAR CRB
 M:	Vanessa Eusebio <vanessa.f.eusebio@intel.com>
 M:	David Guckian <david.guckian@intel.com>
@@ -274,24 +242,6 @@ F:	src/mainboard/intel/harcuvar/
 F:	src/soc/intel/denverton_ns/
 F:	src/vendorcode/intel/fsp/fsp2_0/denverton_ns/
 
-FSP 1.0 RANGELEY & CRB
-M:	David Guckian <david.guckian@intel.com>
-M:	Fei Wang <fei.z.wang@intel.com>
-S:	Supported
-F:	src/cpu/intel/fsp_model_406dx/
-F:	src/northbridge/intel/fsp_rangeley/
-F:	src/southbridge/intel/fsp_rangeley/
-F:	src/vendorcode/intel/fsp1_0/rangeley/
-F:	src/mainboard/intel/mohonpeak/
-
-INTEL FSP 1.0
-M:	Huang Jin <huang.jin@intel.com>
-M:	York Yang <york.yang@intel.com>
-M:	Philipp Deppenwiese <zaolin.daisuki@gmail.com>
-S:	Supported
-F:	src/drivers/intel/fsp1_0/
-F:	src/vendorcode/intel/fsp1_0/broadwell_de/
-
 INTEL FSP 1.1
 M:	Lee Leahy <leroy.p.leahy@intel.com>
 M:	Huang Jin <huang.jin@intel.com>
@@ -332,22 +282,6 @@ M:	Tristan Corrick <tristan@corrick.kiwi>
 S:	Maintained
 F:	src/mainboard/asrock/h81m-hds/
 
-ASUS KFSN4-DRE & KFSN4-DRE_K8 MAINBOARDS
-M:	Timothy Pearson <tpearson@raptorengineeringinc.com>
-S:	Supported
-F:	src/mainboard/asus/kfsn4-dre/
-F:	src/mainboard/asus/kfsn4-dre_k8/
-
-ASUS KCMA-D8 MAINBOARD
-M:	Timothy Pearson <tpearson@raptorengineeringinc.com>
-S:	Supported
-F:	src/mainboard/asus/kcma-d8/
-
-ASUS KGPE-D16 MAINBOARD
-M:	Timothy Pearson <tpearson@raptorengineeringinc.com>
-S:	Supported
-F:	src/mainboard/asus/kgpe-d16/
-
 ASUS MAXIMUS IV GENE-Z MAINBOARD
 M:	Tristan Corrick <tristan@corrick.kiwi>
 S:	Maintained
@@ -383,8 +317,6 @@ SIEMENS MC_xxxx MAINBOARDS
 M:	Werner Zeh <werner.zeh@siemens.com>
 S:	Maintained
 F:	src/mainboard/siemens/mc_apl1/
-F:	src/mainboard/siemens/mc_bdx1/
-F:	src/mainboard/siemens/mc_tcu3/
 
 SUPERMICRO X10SLM+-F MAINBOARD
 M:	Tristan Corrick <tristan@corrick.kiwi>
@@ -402,30 +334,18 @@ M:	Wim Vervoorn <wvervoorn@eltan.com>
 S:	Maintained
 F:	src/mainboard/facebook/fbg1701/
 
+FACEBOOK MONOLITH MAINBOARD
+M:	Frans Hendriks <fhendriks@eltan.com>
+M:	Wim Vervoorn <wvervoorn@eltan.com>
+S:	Maintained
+F:	src/mainboard/facebook/monolith/
+
 PORTWELL PQ-M107 MAINBOARD
 M:	Frans Hendriks <fhendriks@eltan.com>
 M:	Wim Vervoorn <wvervoorn@eltan.com>
 S:	Maintained
 F:	src/mainboard/portwell/m107/
 
-AMD FAMILY10H & FAMILY15H (NON-AGESA) CPUS & NORTHBRIDGE
-M:	Timothy Pearson <tpearson@raptorengineeringinc.com>
-S:	Supported
-F:	src/cpu/amd/family_10h-family_15h/
-F:	src/northbridge/amd/amdfam10/
-F:	src/northbridge/amd/amdmct/
-F:	src/northbridge/amd/amdht/
-
-AMD SB700 (NON-CIMX) SOUTHBRIDGE
-M:	Timothy Pearson <tpearson@raptorengineeringinc.com>
-S:	Supported
-F:	src/southbridge/amd/sb700/
-
-AMD SR5650 SOUTHBRIDGE
-M:	Timothy Pearson <tpearson@raptorengineeringinc.com>
-S:	Supported
-F:	src/southbridge/amd/sr5650/
-
 ASPEED AST2050 DRIVER & COMMON CODE
 M:	Timothy Pearson <tpearson@raptorengineeringinc.com>
 S:	Supported
@@ -477,12 +397,6 @@ F:	util/arm_boot_tools/
 F:	util/exynos/
 F:	util/ipqheader/
 
-MIPS ARCHITECTURE
-F:	src/arch/mips/
-F:	src/cpu/mips/
-F:	src/soc/imgtec/
-F:	util/bimgtool/
-
 X86 ARCHITECTURE
 F:	src/arch/x86/
 F:	src/cpu/x86/
@@ -508,11 +422,6 @@ F:	src/northbridge/amd/
 F:	src/southbridge/amd/
 F:	src/include/cpu/amd/
 
-VIA SUPPORT
-F:	src/cpu/via/
-F:	src/northbridge/via/
-F:	src/southbridge/via/
-
 LINT SCRIPTS
 M:	Patrick Georgi <patrick@georgi-clan.de>
 M:	Martin Roth <gaumless@gmail.com>

diff --git a/Makefile b/Makefile
@@ -119,7 +119,7 @@ help_coreboot help::
 
 # This include must come _before_ the pattern rules below!
 # Order _does_ matter for pattern rules.
-include $(srck)/Makefile
+include $(srck)/Makefile.inc
 
 # Three cases where we don't need fully populated $(obj) lists:
 # 1. when no .config exists

diff --git a/Makefile.inc b/Makefile.inc
@@ -182,9 +182,9 @@ ramstage-postprocess=$$(eval DEPENDENCIES+=$$(addsuffix .d,$$(basename $(1)))) \
 	$(eval $(d)ramstage.a: $(call files-in-dir,$(d),$(filter-out %.ld,$(1))); rm -f $$@ && $(AR_ramstage) rcsT $$@ $$^ ) \
 	$(eval ramstage-objs:=$(d)ramstage.a $(filter-out $(filter-out %.ld, $(call files-in-dir,$(d),$(1))),$(ramstage-objs))))
 
-decompressor-generic-ccopts += -D__PRE_RAM__ -D__DECOMPRESSOR__
-bootblock-generic-ccopts += -D__PRE_RAM__ -D__BOOTBLOCK__
-romstage-generic-ccopts += -D__PRE_RAM__ -D__ROMSTAGE__
+decompressor-generic-ccopts += -D__DECOMPRESSOR__
+bootblock-generic-ccopts += -D__BOOTBLOCK__
+romstage-generic-ccopts += -D__ROMSTAGE__
 ramstage-generic-ccopts += -D__RAMSTAGE__
 ifeq ($(CONFIG_TRACE),y)
 ramstage-c-ccopts += -finstrument-functions
@@ -226,7 +226,7 @@ $(foreach type,ads adb, \
 # Add handler to copy linker scripts
 define generic-objs_ld_template_gen
 de$(EMPTY)fine $(1)-objs_ld_template
-$$(call src-to-obj,$1,$$(1).ld): $$(1).ld $(obj)/config.h
+$$(call src-to-obj,$1,$$(1).ld): $$(1).ld $(obj)/config.h $(obj)/fmap_config.h
 	@printf "    CP         $$$$(subst $$$$(obj)/,,$$$$(@))\n"
 	$$(CC_$(1)) -MMD $$(CPPFLAGS_$(1)) $$($(1)-ld-ccopts) $(PREPROCESS_ONLY) -include $(obj)/config.h -MT $$$$@ -o $$$$@ $$$$<
 en$(EMPTY)def
@@ -258,7 +258,10 @@ endef
 # ResourceTemplate is the correct code.
 # As it's valid ASL, disable the warning.
 EMPTY_RESOURCE_TEMPLATE_WARNING = 3150
-IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING)
+# Redundant offset remarks are not useful in any way and are masking useful
+# ones that might indicate an issue so it is better to hide them.
+REDUNDANT_OFFSET_REMARK = 2158
+IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK)
 
 define asl_template
 $(CONFIG_CBFS_PREFIX)/$(1).aml-file = $(obj)/$(1).aml
@@ -416,6 +419,7 @@ CFLAGS_common += -fno-delete-null-pointer-checks
 ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
 CFLAGS_common += -Wno-packed-not-aligned
 CFLAGS_common += -fconserve-stack
+CFLAGS_common += -Wnull-dereference -Wreturn-type
 # cf. commit f69a99db (coreboot: x86: enable gc-sections)
 CFLAGS_common += -Wno-unused-but-set-variable
 endif
@@ -484,7 +488,7 @@ endif
 
 additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/ifdtool \
 		   $(objutil)/options $(objutil)/amdfwtool \
-		   $(objutil)/cbootimage $(objutil)/bimgtool
+		   $(objutil)/cbootimage
 
 export $(COREBOOT_EXPORTS)
 
@@ -577,11 +581,6 @@ FUTILITY?=$(objutil)/futility/futility
 
 subdirs-y += util/nvidia
 
-BIMGTOOL:=$(objutil)/bimgtool/bimgtool
-$(BIMGTOOL): $(top)/util/bimgtool/bimgtool.c
-	@printf "    HOSTCC     $(subst $(obj)/,,$(@))\n"
-	$(HOSTCC) $(HOSTCFLAGS) -o $@ $<
-
 $(obj)/config.h: $(objutil)/kconfig/conf
 
 #######################################################################

diff --git a/README.md b/README.md
@@ -34,7 +34,6 @@ coreboot supports a wide range of chipsets, devices, and mainboards.
 For details please consult:
 
  * <https://www.coreboot.org/Supported_Motherboards>
- * <https://www.coreboot.org/Supported_Chipsets_and_Devices>
 
 
 Build Requirements

diff --git a/configs/config.facebook_fbg1701 b/configs/config.facebook_fbg1701
@@ -0,0 +1,12 @@
+CONFIG_VENDOR_FACEBOOK=y
+CONFIG_C_ENV_BOOTBLOCK_SIZE=0x6000
+CONFIG_ONBOARD_SAMSUNG_MEM=y
+CONFIG_CPU_MICROCODE_CBFS_LOC=0xFFF8B000
+CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
+CONFIG_CPU_UCODE_BINARIES="3rdparty/intel-microcode/intel-ucode/06-4c-04"
+CONFIG_VENDORCODE_ELTAN_MBOOT=y
+CONFIG_VENDORCODE_ELTAN_VBOOT=y
+CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_FILE="3rdparty/vboot/tests/devkeys-acc/key_hadoken.vbpubk2"
+CONFIG_RUN_FSP_GOP=y
+CONFIG_DISPLAY_HOBS=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
diff --git a/configs/config.google_meep_cros b/configs/config.google_meep_cros
@@ -0,0 +1,41 @@
+CONFIG_VENDOR_GOOGLE=y
+CONFIG_BOARD_GOOGLE_MEEP=y
+
+CONFIG_PAYLOAD_NONE=y
+CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SMM=y
+CONFIG_USE_BLOBS=y
+CONFIG_ANY_TOOLCHAIN=y
+
+# Chrome OS
+CONFIG_CHROMEOS=y
+CONFIG_HAS_RECOVERY_MRC_CACHE=y
+CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN=y
+
+# Event Logging
+CONFIG_CMOS_POST=y
+CONFIG_CMOS_POST_EXTRA=y
+CONFIG_CMOS_POST_OFFSET=0x70
+CONFIG_COLLECT_TIMESTAMPS=y
+CONFIG_ELOG=y
+CONFIG_ELOG_GSMI=y
+CONFIG_ELOG_BOOT_COUNT=y
+CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET=144
+
+# Firmware Support Package
+CONFIG_ADD_FSP_BINARIES=y
+# CONFIG_RUN_FSP_GOP is not set
+
+# Management Engine
+# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
+
+# CONFIG_CONSOLE_SERIAL is not set
+
+CONFIG_FATAL_ASSERTS=y
+CONFIG_CONSOLE_SERIAL=y
+CONFIG_CONSOLE_SERIAL_115200=y
+# CONFIG_DRIVERS_UART_8250IO is not set
+# GLK specific setting to auto select all the correct settings.
+CONFIG_UART_DEBUG=y
+CONFIG_NO_BOOTBLOCK_CONSOLE=y
diff --git a/configs/config.intel.cfl_rvp11_fsp_car b/configs/config.intel.cfl_rvp11_fsp_car
@@ -0,0 +1,9 @@
+CONFIG_USE_BLOBS=y
+CONFIG_VENDOR_INTEL=y
+CONFIG_INTEL_GMA_VBT_FILE="3rdparty/fsp/CoffeeLakeFspBinPkg/SampleCode/Vbt/Vbt.bin"
+CONFIG_BOARD_INTEL_COFFEELAKE_RVP11=y
+CONFIG_ADD_FSP_BINARIES=y
+CONFIG_USE_CANNONLAKE_FSP_CAR=y
+CONFIG_RUN_FSP_GOP=y
+CONFIG_FSP_USE_REPO=y
+CONFIG_PAYLOAD_NONE=y
diff --git a/configs/config.pcengines_apu1 b/configs/config.pcengines_apu1
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.10.0.3"
+CONFIG_LOCALVERSION="v4.11.0.1"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_NO_GFX_INIT=y

diff --git a/configs/config.pcengines_apu2 b/configs/config.pcengines_apu2
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.10.0.3"
+CONFIG_LOCALVERSION="v4.11.0.1"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU2=y

diff --git a/configs/config.pcengines_apu2_vboot b/configs/config.pcengines_apu2_vboot
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.10.0.3"
+CONFIG_LOCALVERSION="v4.11.0.1"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_VBOOT=y

diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu3
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.10.0.3"
+CONFIG_LOCALVERSION="v4.11.0.1"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU3=y

diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_apu4
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.10.0.3"
+CONFIG_LOCALVERSION="v4.11.0.1"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU4=y

diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu5
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="v4.10.0.3"
+CONFIG_LOCALVERSION="v4.11.0.1"
 CONFIG_VENDOR_PCENGINES=y
 CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
 CONFIG_BOARD_PCENGINES_APU5=y

diff --git a/payloads/external/GRUB2/Makefile b/payloads/external/GRUB2/Makefile
@@ -17,7 +17,8 @@ checkout:
 	echo "    GIT        GRUB2 $(NAME-y)"
 	test -d $(project_dir) || git clone $(project_git_repo) $(project_dir)
 	git -C $(project_dir) fetch
-ifeq ("$(shell git -C $(project_dir) status --ignored=no --untracked-files=no --porcelain)",)
+ifeq ("$(shell test -d $(project_dir) && \
+	(git -C $(project_dir) status --ignored=no --untracked-files=no --porcelain))",)
 	git -C $(project_dir) checkout -f $(TAG-y)
 else
 	echo "WARNING: index/tree not clean, skipping update / force checkout."

diff --git a/payloads/external/LinuxBoot/Kconfig b/payloads/external/LinuxBoot/Kconfig
@@ -117,7 +117,6 @@ config LINUXBOOT_KERNEL_ARCH_DEFAULT_CONFIG
 
 config LINUXBOOT_KERNEL_CUSTOM_CONFIG
 	bool "Custom (def)config file"
-	help
 
 endchoice
 

diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc
@@ -29,10 +29,10 @@ endif
 ifeq ($(CONFIG_PAYLOAD_DEPTHCHARGE),y)
 PAYLOAD_CONFIG=payloads/external/depthcharge/depthcharge/.config
 $(PAYLOAD_CONFIG): payloads/external/depthcharge/depthcharge/build/depthcharge.elf
-ifneq ($(CONFIG_MAINBOARD_DEPTHCHARGE),)
-  BOARD=$(CONFIG_MAINBOARD_DEPTHCHARGE)
-else
+ifeq ($(call strip_quotes,$(CONFIG_MAINBOARD_DEPTHCHARGE))),)
   BOARD=$(call ws_to_under,$(call strip_quotes,$(call tolower,$(CONFIG_MAINBOARD_PART_NUMBER))))
+else
+  BOARD=$(CONFIG_MAINBOARD_DEPTHCHARGE)
 endif
 #TODO: Figure out version
 endif

diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig
@@ -114,11 +114,6 @@ config ARCH_ARM64
         help
           Support the ARM64 architecture
 
-config ARCH_MIPS
-	bool "MIPS"
-	help
-	  Support the MIPS architecture
-
 endchoice
 
 config MULTIBOOT
@@ -147,12 +142,11 @@ config BASE_ADDRESS
 	hex "Base address"
 	default 0x04000000 if ARCH_ARM
 	default 0x80100000 if ARCH_ARM64
-	default 0x00000000 if ARCH_MIPS
 	default 0x00100000 if ARCH_X86
 	help
 	  This is the base address for the payload.
 
-	  If unsure, set to 0x00100000 on x86, 0x00000000 on MIPS,
+	  If unsure, set to 0x00100000 on x86,
 	  0x04000000 on ARM or 0x80100000 on ARM64.
 
 endmenu
@@ -452,5 +446,4 @@ config IO_ADDRESS_SPACE
 
 source "arch/arm/Kconfig"
 source "arch/arm64/Kconfig"
-source "arch/mips/Kconfig"
 source "arch/x86/Kconfig"
diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile
@@ -95,7 +95,6 @@ include $(HAVE_DOTCONFIG)
 
 ARCHDIR-$(CONFIG_LP_ARCH_ARM)     := arm
 ARCHDIR-$(CONFIG_LP_ARCH_ARM64)   := arm64
-ARCHDIR-$(CONFIG_LP_ARCH_MIPS)    := mips
 ARCHDIR-$(CONFIG_LP_ARCH_X86)     := x86
 
 ARCH-y := $(ARCHDIR-y)
@@ -105,7 +104,6 @@ ARCH-y := $(ARCHDIR-y)
 ARCH-$(CONFIG_LP_ARCH_ARM)     := arm
 ARCH-$(CONFIG_LP_ARCH_ARM64)   := arm64
 ARCH-$(CONFIG_LP_ARCH_X86)     := x86_32
-ARCH-$(CONFIG_LP_ARCH_MIPS)    := mips
 
 # Three cases where we don't need fully populated $(obj) lists:
 # 1. when no .config exists

diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc
@@ -33,7 +33,6 @@ export KERNELVERSION      := 0.2.0
 
 ARCHDIR-$(CONFIG_LP_ARCH_ARM)     := arm
 ARCHDIR-$(CONFIG_LP_ARCH_ARM64)   := arm64
-ARCHDIR-$(CONFIG_LP_ARCH_MIPS)    := mips
 ARCHDIR-$(CONFIG_LP_ARCH_X86)     := x86
 DESTDIR ?= install
 

diff --git a/payloads/libpayload/arch/arm64/exception.c b/payloads/libpayload/arch/arm64/exception.c
@@ -31,7 +31,7 @@
 #include <libpayload.h>
 #include <stdint.h>
 
-u64 exception_stack[0x200] __attribute__((aligned(16)));
+u64 exception_stack[2*KiB] __attribute__((aligned(16)));
 u64 *exception_stack_end = exception_stack + ARRAY_SIZE(exception_stack);
 extern unsigned int test_exc;
 

diff --git a/payloads/libpayload/arch/mips/Kconfig b/payloads/libpayload/arch/mips/Kconfig
diff --git a/payloads/libpayload/arch/mips/Makefile.inc b/payloads/libpayload/arch/mips/Makefile.inc
diff --git a/payloads/libpayload/arch/mips/cache.c b/payloads/libpayload/arch/mips/cache.c
diff --git a/payloads/libpayload/arch/mips/coreboot.c b/payloads/libpayload/arch/mips/coreboot.c
diff --git a/payloads/libpayload/arch/mips/dummy_media.c b/payloads/libpayload/arch/mips/dummy_media.c
diff --git a/payloads/libpayload/arch/mips/exception.c b/payloads/libpayload/arch/mips/exception.c
diff --git a/payloads/libpayload/arch/mips/exception_asm.S b/payloads/libpayload/arch/mips/exception_asm.S
diff --git a/payloads/libpayload/arch/mips/gdb.c b/payloads/libpayload/arch/mips/gdb.c
diff --git a/payloads/libpayload/arch/mips/head.S b/payloads/libpayload/arch/mips/head.S
diff --git a/payloads/libpayload/arch/mips/libpayload.ldscript b/payloads/libpayload/arch/mips/libpayload.ldscript
diff --git a/payloads/libpayload/arch/mips/main.c b/payloads/libpayload/arch/mips/main.c
diff --git a/payloads/libpayload/arch/mips/selfboot.c b/payloads/libpayload/arch/mips/selfboot.c
diff --git a/payloads/libpayload/arch/mips/string.c b/payloads/libpayload/arch/mips/string.c
diff --git a/payloads/libpayload/arch/mips/sysinfo.c b/payloads/libpayload/arch/mips/sysinfo.c
diff --git a/payloads/libpayload/arch/mips/timer.c b/payloads/libpayload/arch/mips/timer.c
diff --git a/payloads/libpayload/arch/mips/util.S b/payloads/libpayload/arch/mips/util.S
diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc
@@ -80,12 +80,6 @@ if [ "$CONFIG_LP_ARCH_ARM64" = "y" ]; then
   _ARCHEXTRA=""
   _ARCH=arm64
 fi
-if [ "$CONFIG_LP_ARCH_MIPS" = "y" ]; then
-  _ARCHINCDIR=$_INCDIR/mips
-  _ARCHLIBDIR=$_LIBDIR/mips
-  _ARCHEXTRA=""
-  _ARCH=mips
-fi
 if [ "$CONFIG_LP_ARCH_X86" = "y" ]; then
   _ARCHINCDIR=$_INCDIR/x86
   _ARCHLIBDIR=$_LIBDIR/x86
@@ -170,9 +164,7 @@ if [ $DOLINK -eq 0 ]; then
 
     $DEFAULT_CC $CMDLINE $_CFLAGS
 else
-    if [ -z "${CONFIG_LP_ARCH_MIPS}" ]; then
-        _LIBGCC=`$DEFAULT_CC $_ARCHEXTRA -print-libgcc-file-name`
-    fi
+    _LIBGCC=`$DEFAULT_CC $_ARCHEXTRA -print-libgcc-file-name`
     if [ -f $_ARCHLIBDIR/head.o ]; then
 	    HEAD_O=$_ARCHLIBDIR/head.o
     elif [ -f $BASE/../build/head.o ]; then

diff --git a/payloads/libpayload/configs/config.trogdor b/payloads/libpayload/configs/config.trogdor
@@ -0,0 +1,6 @@
+CONFIG_LP_CHROMEOS=y
+CONFIG_LP_ARCH_ARM64=y
+CONFIG_LP_TIMER_ARM64_ARCH=y
+CONFIG_LP_USB=y
+CONFIG_LP_USB_EHCI=y
+CONFIG_LP_USB_XHCI=y
diff --git a/payloads/libpayload/configs/defconfig-mips b/payloads/libpayload/configs/defconfig-mips
diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc
@@ -54,7 +54,6 @@ ifneq ($(CONFIG_LP_TIMER_GENERIC_HZ),0)
 libc-y += timer/generic.c
 endif
 libc-$(CONFIG_LP_TIMER_RDTSC) += timer/rdtsc.c
-libc-$(CONFIG_LP_TIMER_IMG_PISTACHIO) += timer/img_pistachio.c
 libc-$(CONFIG_LP_TIMER_ARM64_ARCH) += timer/arm64_arch_timer.c
 
 # Video console drivers

diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c
@@ -35,6 +35,7 @@
 #include "i8042.h"
 
 #define POWER_BUTTON         0x90
+#define MEDIA_KEY_PREFIX     0xE0
 
 struct layout_maps {
 	const char *country;
@@ -43,6 +44,7 @@ struct layout_maps {
 
 static struct layout_maps *map;
 static int modifier = 0;
+int (*media_key_mapping_callback)(char ch);
 
 static struct layout_maps keyboard_layouts[] = {
 #if CONFIG(LP_PC_KEYBOARD_LAYOUT_US)
@@ -230,6 +232,11 @@ int keyboard_getmodifier(void)
 	return modifier;
 }
 
+void initialize_keyboard_media_key_mapping_callback(int (*media_key_mapper)(char))
+{
+	media_key_mapping_callback = media_key_mapper;
+}
+
 int keyboard_getchar(void)
 {
 	unsigned char ch;
@@ -239,6 +246,10 @@ int keyboard_getchar(void)
 	while (!keyboard_havechar()) ;
 
 	ch = keyboard_get_scancode();
+	if ((media_key_mapping_callback != NULL) && (ch == MEDIA_KEY_PREFIX)) {
+		ch = keyboard_get_scancode();
+		return media_key_mapping_callback(ch);
+	}
 
 	if (!(ch & 0x80) && ch < 0x59) {
 		shift =

diff --git a/payloads/libpayload/drivers/timer/Kconfig b/payloads/libpayload/drivers/timer/Kconfig
@@ -50,9 +50,6 @@ config TIMER_RK3288
 config TIMER_RK3399
 	bool "Timer for Rockchip RK3399"
 
-config TIMER_IMG_PISTACHIO
-	bool "Timer for IMG Pistachio"
-
 config TIMER_MTK
 	bool "Timer for MediaTek"
 

diff --git a/payloads/libpayload/drivers/timer/img_pistachio.c b/payloads/libpayload/drivers/timer/img_pistachio.c
diff --git a/payloads/libpayload/drivers/udc/chipidea.c b/payloads/libpayload/drivers/udc/chipidea.c
@@ -140,7 +140,7 @@ static void chipidea_halt_ep(struct usbdev_ctrl *this, int ep, int in_dir)
 	writel(1 << ep_to_bits(ep, in_dir), &p->opreg->epflush);
 	while (readl(&p->opreg->epflush))
 		;
-	clrbits_le32(&p->opreg->epctrl[ep], 1 << (7 + (in_dir ? 16 : 0)));
+	clrbits32(&p->opreg->epctrl[ep], 1 << (7 + (in_dir ? 16 : 0)));
 
 	while (!SIMPLEQ_EMPTY(&p->job_queue[ep][in_dir])) {
 		struct job *job = SIMPLEQ_FIRST(&p->job_queue[ep][in_dir]);
@@ -161,7 +161,7 @@ static void chipidea_start_ep(struct usbdev_ctrl *this,
 	in_dir = in_dir ? 1 : 0;
 	debug("enabling %d-%d (type %d)\n", ep, in_dir, ep_type);
 	/* enable endpoint, reset data toggle */
-	setbits_le32(&p->opreg->epctrl[ep],
+	setbits32(&p->opreg->epctrl[ep],
 		((1 << 7) | (1 << 6) | (ep_type << 2)) << (in_dir*16));
 	p->ep_busy[ep][in_dir] = 0;
 	this->ep_mps[ep][in_dir] = mps;
@@ -456,17 +456,17 @@ static void chipidea_stall(struct usbdev_ctrl *this,
 	in_dir = in_dir ? 1 : 0;
 	if (set) {
 		if (in_dir)
-			setbits_le32(ctrl, 1 << 16);
+			setbits32(ctrl, 1 << 16);
 		else
-			setbits_le32(ctrl, 1 << 0);
+			setbits32(ctrl, 1 << 0);
 	} else {
 		/* reset STALL bit, reset data toggle */
 		if (in_dir) {
-			setbits_le32(ctrl, 1 << 22);
-			clrbits_le32(ctrl, 1 << 16);
+			setbits32(ctrl, 1 << 22);
+			clrbits32(ctrl, 1 << 16);
 		} else {
-			setbits_le32(ctrl, 1 << 6);
-			clrbits_le32(ctrl, 1 << 0);
+			setbits32(ctrl, 1 << 6);
+			clrbits32(ctrl, 1 << 0);
 		}
 	}
 	this->ep_halted[ep][in_dir] = set;

diff --git a/payloads/libpayload/drivers/usb/usbmsc.c b/payloads/libpayload/drivers/usb/usbmsc.c
@@ -232,9 +232,9 @@ get_csw (endpoint_t *ep, csw_t *csw)
 
 	if (ret < 0) {
 		clear_stall (ep);
-		if (ctrlr->bulk (ep, sizeof (csw_t), (u8 *) csw, 1) < 0) {
+		ret = ctrlr->bulk (ep, sizeof (csw_t), (u8 *) csw, 1);
+		if (ret < 0)
 			return reset_transport (ep->dev);
-		}
 	}
 	if (ret != sizeof(csw_t) || csw->dCSWTag != tag ||
 	    csw->dCSWSignature != csw_signature) {

diff --git a/payloads/libpayload/include/endian.h b/payloads/libpayload/include/endian.h
@@ -34,23 +34,6 @@
 #include <arch/types.h>
 #include <libpayload-config.h>
 
-static inline uint16_t swap_bytes16(uint16_t in)
-{
-	return ((in & 0xFF) << 8) | ((in & 0xFF00) >> 8);
-}
-
-static inline uint32_t swap_bytes32(uint32_t in)
-{
-	return ((in & 0xFF) << 24) | ((in & 0xFF00) << 8) |
-		((in & 0xFF0000) >> 8) | ((in & 0xFF000000) >> 24);
-}
-
-static inline uint64_t swap_bytes64(uint64_t in)
-{
-	return ((uint64_t)swap_bytes32((uint32_t)in) << 32) |
-		((uint64_t)swap_bytes32((uint32_t)(in >> 32)));
-}
-
 /* Endian functions from glibc 2.9 / BSD "endian.h" */
 
 #if CONFIG(LP_BIG_ENDIAN)
@@ -59,15 +42,15 @@ static inline uint64_t swap_bytes64(uint64_t in)
 #define htobe32(in) (in)
 #define htobe64(in) (in)
 
-#define htole16(in) swap_bytes16(in)
-#define htole32(in) swap_bytes32(in)
-#define htole64(in) swap_bytes64(in)
+#define htole16(in) ((uint16_t)__builtin_bswap16(in))
+#define htole32(in) ((uint32_t)__builtin_bswap32(in))
+#define htole64(in) ((uint64_t)__builtin_bswap64(in))
 
 #elif CONFIG(LP_LITTLE_ENDIAN)
 
-#define htobe16(in) swap_bytes16(in)
-#define htobe32(in) swap_bytes32(in)
-#define htobe64(in) swap_bytes64(in)
+#define htobe16(in) ((uint16_t)__builtin_bswap16(in))
+#define htobe32(in) ((uint32_t)__builtin_bswap32(in))
+#define htobe64(in) ((uint64_t)__builtin_bswap64(in))
 
 #define htole16(in) (in)
 #define htole32(in) (in)
@@ -181,18 +164,47 @@ static inline void le32enc(void *pp, uint32_t u)
 
 /* Handy bit manipulation macros */
 
-#define clrsetbits_le32(addr, clear, set) writel(htole32((le32toh(readl(addr)) \
-	& ~(clear)) | (set)), (addr))
-#define setbits_le32(addr, set) writel(htole32(le32toh(readl(addr)) \
-	| (set)), (addr))
-#define clrbits_le32(addr, clear) writel(htole32(le32toh(readl(addr)) \
-	& ~(clear)), (addr))
-
-#define clrsetbits_be32(addr, clear, set) writel(htobe32((be32toh(readl(addr)) \
-	& ~(clear)) | (set)), (addr))
-#define setbits_be32(addr, set) writel(htobe32(be32toh(readl(addr)) \
-	| (set)), (addr))
-#define clrbits_be32(addr, clear) writel(htobe32(be32toh(readl(addr)) \
-	& ~(clear)), (addr))
+#define __clrsetbits(endian, bits, addr, clear, set) \
+	write##bits(addr, hto##endian##bits((endian##bits##toh( \
+		read##bits(addr)) & ~((uint##bits##_t)(clear))) | (set)))
+
+#define clrbits_le64(addr, clear)	__clrsetbits(le, 64, addr, clear, 0)
+#define clrbits_be64(addr, clear)	__clrsetbits(be, 64, addr, clear, 0)
+#define clrbits_le32(addr, clear)	__clrsetbits(le, 32, addr, clear, 0)
+#define clrbits_be32(addr, clear)	__clrsetbits(be, 32, addr, clear, 0)
+#define clrbits_le16(addr, clear)	__clrsetbits(le, 16, addr, clear, 0)
+#define clrbits_be16(addr, clear)	__clrsetbits(be, 16, addr, clear, 0)
+
+#define setbits_le64(addr, set)		__clrsetbits(le, 64, addr, 0, set)
+#define setbits_be64(addr, set)		__clrsetbits(be, 64, addr, 0, set)
+#define setbits_le32(addr, set)		__clrsetbits(le, 32, addr, 0, set)
+#define setbits_be32(addr, set)		__clrsetbits(be, 32, addr, 0, set)
+#define setbits_le16(addr, set)		__clrsetbits(le, 16, addr, 0, set)
+#define setbits_be16(addr, set)		__clrsetbits(be, 16, addr, 0, set)
+
+#define clrsetbits_le64(addr, clear, set) __clrsetbits(le, 64, addr, clear, set)
+#define clrsetbits_be64(addr, clear, set) __clrsetbits(be, 64, addr, clear, set)
+#define clrsetbits_le32(addr, clear, set) __clrsetbits(le, 32, addr, clear, set)
+#define clrsetbits_be32(addr, clear, set) __clrsetbits(be, 32, addr, clear, set)
+#define clrsetbits_le16(addr, clear, set) __clrsetbits(le, 16, addr, clear, set)
+#define clrsetbits_be16(addr, clear, set) __clrsetbits(be, 16, addr, clear, set)
+
+#define __clrsetbits_impl(bits, addr, clear, set) write##bits(addr, \
+	(read##bits(addr) & ~((uint##bits##_t)(clear))) | (set))
+
+#define clrsetbits8(addr, clear, set)	__clrsetbits_impl(8, addr, clear, set)
+#define clrsetbits16(addr, clear, set)	__clrsetbits_impl(16, addr, clear, set)
+#define clrsetbits32(addr, clear, set)	__clrsetbits_impl(32, addr, clear, set)
+#define clrsetbits64(addr, clear, set)	__clrsetbits_impl(64, addr, clear, set)
+
+#define setbits8(addr, set)		clrsetbits8(addr, 0, set)
+#define setbits16(addr, set)		clrsetbits16(addr, 0, set)
+#define setbits32(addr, set)		clrsetbits32(addr, 0, set)
+#define setbits64(addr, set)		clrsetbits64(addr, 0, set)
+
+#define clrbits8(addr, clear)		clrsetbits8(addr, clear, 0)
+#define clrbits16(addr, clear)		clrsetbits16(addr, clear, 0)
+#define clrbits32(addr, clear)		clrsetbits32(addr, clear, 0)
+#define clrbits64(addr, clear)		clrsetbits64(addr, clear, 0)
 
 #endif /* _ENDIAN_H_ */
diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h
@@ -85,6 +85,7 @@
 #define MAX(a, b) __CMP(a, b, >)
 
 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+#define BIT(x)	(1ul << (x))
 
 #define DIV_ROUND_UP(x, y) ({ \
 	typeof(x) _div_local_x = (x); \
@@ -187,6 +188,7 @@ unsigned char keyboard_get_scancode(void);
 int keyboard_getchar(void);
 int keyboard_set_layout(char *country);
 int keyboard_getmodifier(void);
+void initialize_keyboard_media_key_mapping_callback(int (*media_key_mapper)(char));
 
 enum KEYBOARD_MODIFIERS {
 	KB_MOD_SHIFT = (1 << 0),
@@ -457,7 +459,7 @@ void buffer_to_fifo32_prefix(void *buffer, u32 prefix, int prefsz, size_t size,
 static inline void buffer_to_fifo32(void *buffer, size_t size, void *fifo,
 				    int fifo_stride, int fifo_width)
 {
-	buffer_to_fifo32_prefix(buffer, size, 0, 0, fifo,
+	buffer_to_fifo32_prefix(buffer, 0, 0, size, fifo,
 				fifo_stride, fifo_width);
 }
 #endif

diff --git a/payloads/libpayload/include/mips/arch/byteorder.h b/payloads/libpayload/include/mips/arch/byteorder.h
diff --git a/payloads/libpayload/include/mips/arch/cache.h b/payloads/libpayload/include/mips/arch/cache.h
diff --git a/payloads/libpayload/include/mips/arch/cpu.h b/payloads/libpayload/include/mips/arch/cpu.h
diff --git a/payloads/libpayload/include/mips/arch/exception.h b/payloads/libpayload/include/mips/arch/exception.h
diff --git a/payloads/libpayload/include/mips/arch/io.h b/payloads/libpayload/include/mips/arch/io.h
diff --git a/payloads/libpayload/include/mips/arch/stdint.h b/payloads/libpayload/include/mips/arch/stdint.h
diff --git a/payloads/libpayload/include/mips/arch/types.h b/payloads/libpayload/include/mips/arch/types.h
diff --git a/payloads/libpayload/include/mips/arch/virtual.h b/payloads/libpayload/include/mips/arch/virtual.h
diff --git a/payloads/libpayload/include/swab.h b/payloads/libpayload/include/swab.h
diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
@@ -96,7 +96,6 @@ struct sysinfo_t {
 	struct cb_mainboard *mainboard;
 
 	void *vboot_workbuf;
-	uint32_t vboot_workbuf_size;
 
 #if CONFIG(LP_ARCH_X86)
 	int x86_rom_var_mtrr_index;

diff --git a/payloads/libpayload/libc/64bit_div.c b/payloads/libpayload/libc/64bit_div.c
diff --git a/payloads/libpayload/libc/Makefile.inc b/payloads/libpayload/libc/Makefile.inc
@@ -39,7 +39,3 @@ libc-$(CONFIG_LP_LIBC) += hexdump.c
 libc-$(CONFIG_LP_LIBC) += die.c
 libc-$(CONFIG_LP_LIBC) += coreboot.c
 libc-$(CONFIG_LP_LIBC) += fmap.c
-
-ifeq ($(CONFIG_LP_ARCH_MIPS),y)
-libc-$(CONFIG_LP_LIBC) += 64bit_div.c
-endif
diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c
@@ -86,10 +86,7 @@ static void cb_parse_serial(void *ptr, struct sysinfo_t *info)
 
 static void cb_parse_vboot_workbuf(unsigned char *ptr, struct sysinfo_t *info)
 {
-	struct lb_range *vbwb = (struct lb_range *)ptr;
-
-	info->vboot_workbuf = (void *)(uintptr_t)vbwb->range_start;
-	info->vboot_workbuf_size = vbwb->range_size;
+	info->vboot_workbuf = get_cbmem_ptr(ptr);
 }
 
 static void cb_parse_vbnv(unsigned char *ptr, struct sysinfo_t *info)

diff --git a/payloads/libpayload/sample/Makefile b/payloads/libpayload/sample/Makefile
@@ -34,7 +34,6 @@ include ../.xcompile
 ARCH-$(CONFIG_LP_ARCH_ARM)   := arm
 ARCH-$(CONFIG_LP_ARCH_X86)   := x86_32
 ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64
-ARCH-$(CONFIG_LP_ARCH_MIPS)  := mips
 
 CC := $(CC_$(ARCH-y))
 AS := $(AS_$(ARCH-y))
-Original file line number
+Diff line change
@@ Expand Up / @@ -117,7 +117,6 @@ config LINUXBOOT_KERNEL_ARCH_DEFAULT_CONFIG @@
     config LINUXBOOT_KERNEL_CUSTOM_CONFIG
     	bool "Custom (def)config file"
-    	help
     endchoice
@@ Expand Down @@