62 changes: 42 additions & 20 deletions MAINTAINERS
View file
Expand Up @@ -137,6 +137,14 @@ Maintainers List (try to look for most precise areas first)
# Mainboards
################################################################################

AMD family 17h and 19h reference boards
M: Marshall Dawson <marshalldawson3rd@gmail.com>
M: Felix Held <felix-coreboot@felixheld.de>
M: Jason Glenesk <jason.glenesk@gmail.com>
S: Maintained
F: src/mainboard/amd/majolica/
F: src/mainboard/amd/mandolin/

APPLE MAINBOARDS
M: Evgeny Zinoviev <me@ch1p.io>
S: Maintained
Expand Down Expand Up @@ -233,19 +241,19 @@ F: src/mainboard/facebook/monolith/
GETAC P470 MAINBOARD
M: Patrick Georgi <patrick@georgi.software>
S: Maintained
F: src/mainboard/getac/p470
F: src/mainboard/getac/p470/



GIGABYTE GA-G41M-ES2L MAINBOARD
M: Damien Zammit <damien@zamaudio.com>
S: Odd Fixes
F: src/mainboard/gigabyte/ga-g41m-es2l
F: src/mainboard/gigabyte/ga-g41m-es2l/

GIGABYTE GA-H61M SERIES MAINBOARDS
M: Angel Pons <th3fanbus@gmail.com>
S: Maintained
F: src/mainboard/gigabyte/ga-h61m-series
F: src/mainboard/gigabyte/ga-h61m-series/



Expand Down Expand Up @@ -273,7 +281,7 @@ F: src/mainboard/google/stout/
INTEL D510MO MAINBOARD
M: Damien Zammit <damien@zamaudio.com>
S: Odd Fixes
F: src/mainboard/intel/d510mo
F: src/mainboard/intel/d510mo/

INTEL STRAGO MAINBOARD
M: Hannah Williams <hannah.williams@intel.com>
Expand Down Expand Up @@ -314,7 +322,7 @@ LIBRETREND LT1000 MAINBOARD
M: Piotr Król <piotr.krol@3mdeb.com>
M: Michał Żygowski <michal.zygowski@3mdeb.com>
S: Maintained
F: src/mainboard/libretrend/lt1000
F: src/mainboard/libretrend/lt1000/


OCP DELTALAKE MAINBOARD
Expand All @@ -325,7 +333,7 @@ M: Morgan Jang <Morgan_Jang@wiwynn.com>
M: Ryback Hung <<Ryback.Hung@quantatw.com>
M: Bryant Ou <Bryant.Ou@quantatw.com>
S: Supported
F: src/mainboard/ocp/deltalake
F: src/mainboard/ocp/deltalake/

OCP TIOGAPASS MAINBOARD
M: Jonathan Zhang <jonzhang@fb.com>
Expand All @@ -335,7 +343,7 @@ M: Morgan Jang <Morgan_Jang@wiwynn.com>
M: Ryback Hung <<Ryback.Hung@quantatw.com>
M: Bryant Ou <Bryant.Ou@quantatw.com>
S: Maintained
F: src/mainboard/ocp/tiogapass
F: src/mainboard/ocp/tiogapass/



Expand Down Expand Up @@ -375,14 +383,14 @@ PRODRIVE HERMES MAINBOARD
M: Christian Walter <christian.walter@9elements.com>
M: Patrick Rudolph <patrick.rudolph@9elements.com>
S: Maintained
F: src/mainboard/prodrive/hermes
F: src/mainboard/prodrive/hermes/



PURISM MAINBOARDS
M: Matt DeVillier <matt.devillier@puri.sm>
S: Supported
F: src/mainboard/purism
F: src/mainboard/purism/



Expand Down Expand Up @@ -551,13 +559,27 @@ F: src/drivers/intel/fsp2_0/
# Systems on a Chip
################################################################################

AMD Cezanne
M: Marshall Dawson <marshalldawson3rd@gmail.com>
M: Felix Held <felix-coreboot@felixheld.de>
M: Jason Glenesk <jason.glenesk@gmail.com>
S: Maintained
F: src/soc/amd/cezanne/

AMD common SoC code
M: Marshall Dawson <marshalldawson3rd@gmail.com>
M: Felix Held <felix-coreboot@felixheld.de>
M: Jason Glenesk <jason.glenesk@gmail.com>
S: Maintained
F: src/soc/amd/common/

AMD Picasso
M: Marshall Dawson <marshalldawson3rd@gmail.com>
M: Felix Held <felix-coreboot@felixheld.de>
M: Jason Glenesk <jason.glenesk@gmail.com>
S: Maintained
F: src/soc/amd/picasso
F: src/vendorcode/amd/fsp/picasso
F: src/soc/amd/picasso/
F: src/vendorcode/amd/fsp/picasso/

INTEL APOLLOLAKE_SOC
M: Andrey Petrov <andrey.petrov@gmail.com>
Expand All @@ -569,8 +591,8 @@ M: Piotr Król <piotr.krol@3mdeb.com>
M: Michał Żygowski <michal.zygowski@3mdeb.com>
M: Frans Hendriks <fhendriks@eltan.com>
S: Maintained
F: /src/soc/intel/braswell
F: /src/vendorcode/intel/fsp/fsp1_1/braswell
F: /src/soc/intel/braswell/
F: /src/vendorcode/intel/fsp/fsp1_1/braswell/

INTEL Xeon Sacalable Processor Family
M: Jonathan Zhang <jonzhang@fb.com>
Expand All @@ -581,13 +603,13 @@ M: Ryback Hung <<Ryback.Hung@quantatw.com>
M: Bryant Ou <Bryant.Ou@quantatw.com>
S: Supported
F: src/soc/intel/xeon_sp
F: src/vendorcode/intel/fsp/fsp2_0/skylake_sp
F: src/vendorcode/intel/fsp/fsp2_0/copperlake_sp
F: src/vendorcode/intel/fsp/fsp2_0/skylake_sp/
F: src/vendorcode/intel/fsp/fsp2_0/copperlake_sp/

MEDIATEK SOCS
M: Hung-Te Lin <hungte@chromium.org>
S: Supported
F: src/soc/mediatek
F: src/soc/mediatek/

ORPHANED ARM SOCS
S: Orphaned
Expand Down Expand Up @@ -615,13 +637,13 @@ F: payloads/coreinfo/
EXTERNAL PAYLOADS INTEGRATION
M: Stefan Reinauer <stefan.reinauer@coreboot.org>
M: Martin Roth <gaumless@gmail.com>
F: payloads/external
F: payloads/external/

LINUXBOOT PAYLOAD INTEGRATION
M: Christian Walter <christian.walter@9elements.com>
M: Marcello Sylvester Bauer <info@marcellobauer.com>
S: Supported
F: payloads/external/LinuxBoot
F: payloads/external/LinuxBoot/

################################################################################
# Utilities
Expand Down Expand Up @@ -751,7 +773,7 @@ TPM SUPPORT
M: Christian Walter <christian.walter@9elements.com>
S: Supported
F: src/drivers/*/tpm/
F: src/security/tpm
F: src/security/tpm/

SUPERIOS & SUPERIOTOOL
M: Felix Held <felix-coreboot@felixheld.de>
Expand All @@ -769,7 +791,7 @@ ELTAN VENDORCODE
M: Frans Hendriks <fhendriks@eltan.com>
M: Wim Vervoorn <wvervoorn@eltan.com>
S: Maintained
F: src/vendorcode/eltan
F: src/vendorcode/eltan/

MISSING: TIMERS / DELAYS

Expand Down
94 changes: 38 additions & 56 deletions Makefile.inc
View file
Expand Up @@ -183,9 +183,6 @@ decompressor-generic-ccopts += -D__DECOMPRESSOR__
bootblock-generic-ccopts += -D__BOOTBLOCK__
romstage-generic-ccopts += -D__ROMSTAGE__
ramstage-generic-ccopts += -D__RAMSTAGE__
ifeq ($(CONFIG_TRACE),y)
ramstage-c-ccopts += -finstrument-functions
endif
ifeq ($(CONFIG_COVERAGE),y)
ramstage-c-ccopts += -fprofile-arcs -ftest-coverage
endif
Expand Down Expand Up @@ -336,9 +333,9 @@ endef
# arg2: binary file
cbfs-files-processor-struct= \
$(eval $(2): $(1) $(obj)/build.h $(KCONFIG_AUTOHEADER); \
printf " CC+STRIP $(@)\n"; \
printf " CC+STRIP $(1)\n"; \
$(CC_ramstage) -MMD $(CPPFLAGS_ramstage) $(CFLAGS_ramstage) $$(ramstage-c-ccopts) -include $(KCONFIG_AUTOHEADER) -MT $(2) -o $(2).tmp -c $(1) && \
$(OBJCOPY_ramstage) -O binary $(2).tmp $(2); \
$(OBJCOPY_ramstage) -O binary --set-section-flags .bss*=alloc,contents,load $(2).tmp $(2); \
rm -f $(2).tmp) \
$(eval DEPENDENCIES += $(2).d)

Expand Down Expand Up @@ -533,6 +530,12 @@ $(build_h): $$(shell $$(build_h_check))
build-dirs $(objcbfs) $(objgenerated):
mkdir -p $(objcbfs) $(objgenerated)

$(obj)/build_info:
@echo 'COREBOOT_VERSION: $(call strip_quotes,$(KERNELVERSION))' > $@.tmp
@echo 'MAINBOARD_VENDOR: $(call strip_quotes,$(CONFIG_MAINBOARD_VENDOR))' >> $@.tmp
@echo 'MAINBOARD_PART_NUMBER: $(call strip_quotes,$(CONFIG_MAINBOARD_PART_NUMBER))' >> $@.tmp
mv $@.tmp $@

#######################################################################
# Build the tools
CBFSTOOL:=$(objutil)/cbfstool/cbfstool
Expand Down Expand Up @@ -733,16 +736,6 @@ TXTIBB :=

endif

ifeq ($(CONFIG_INTEL_CBNT_SUPPORT),y)

CBNTIBB := --cbnt

else

CBNTIBB :=

endif # CONFIG_INTEL_CBNT_SUPPORT

ifeq ($(CONFIG_COMPRESS_BOOTBLOCK),y)

$(objcbfs)/bootblock.lz4: $(objcbfs)/bootblock.elf $(objutil)/cbfstool/cbfs-compression-tool
Expand Down Expand Up @@ -836,6 +829,10 @@ endif

# cbfs-add-cmd-for-region
# $(call cbfs-add-cmd-for-region,file in extract_nth format,region name)
#
# CBFSTOOL_ADD_CMD_OPTIONS can be used by arch/SoC/mainboard to supply
# add commands with any additional arguments for cbfstool.
# Example: --ext-win-base <base> --ext-win-size <size>
define cbfs-add-cmd-for-region
$(CBFSTOOL) $@.tmp \
add$(if $(filter stage,$(call extract_nth,3,$(1))),-stage)$(if \
Expand All @@ -850,8 +847,8 @@ define cbfs-add-cmd-for-region
-r $(2) \
$(if $(call extract_nth,6,$(1)),-a $(call extract_nth,6,$(file)), \
$(if $(call extract_nth,5,$(file)),-b $(call extract_nth,5,$(file)))) \
$(call extract_nth,7,$(1))

$(call extract_nth,7,$(1)) \
$(CBFSTOOL_ADD_CMD_OPTIONS)

endef
# Empty line before endef is necessary so cbfs-add-cmd-for-region ends in a
Expand Down Expand Up @@ -975,6 +972,16 @@ else
FMAP_SMMSTORE_ENTRY :=
endif

ifeq ($(CONFIG_SPD_CACHE_IN_FMAP),y)
FMAP_SPD_CACHE_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x4000)
FMAP_SPD_CACHE_SIZE := $(call int-multiply, $(CONFIG_DIMM_MAX) $(CONFIG_DIMM_SPD_SIZE))
FMAP_SPD_CACHE_SIZE := $(call int-align, $(FMAP_SPD_CACHE_SIZE), 0x1000)
FMAP_SPD_CACHE_ENTRY := $(CONFIG_SPD_CACHE_FMAP_NAME)@$(FMAP_SPD_CACHE_BASE) $(FMAP_SPD_CACHE_SIZE)
FMAP_CURRENT_BASE := $(call int-add, $(FMAP_SPD_CACHE_BASE) $(FMAP_SPD_CACHE_SIZE))
else
FMAP_SPD_CACHE_ENTRY :=
endif

#
# X86 FMAP region
#
Expand Down Expand Up @@ -1051,6 +1058,7 @@ $(obj)/fmap.fmd: $(top)/Makefile.inc $(DEFAULT_FLASHMAP) $(obj)/config.h
-e "s,##CONSOLE_ENTRY##,$(FMAP_CONSOLE_ENTRY)," \
-e "s,##MRC_CACHE_ENTRY##,$(FMAP_MRC_CACHE_ENTRY)," \
-e "s,##SMMSTORE_ENTRY##,$(FMAP_SMMSTORE_ENTRY)," \
-e "s,##SPD_CACHE_ENTRY##,$(FMAP_SPD_CACHE_ENTRY)," \
-e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \
-e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \
$(DEFAULT_FLASHMAP) > $@.tmp
Expand Down Expand Up @@ -1084,9 +1092,9 @@ ifeq ($(CONFIG_ARCH_X86),y)
-n bootblock \
-t bootblock \
$(TXTIBB) \
$(CBNTIBB) \
-b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) \
$(TS_OPTIONS)
$(TS_OPTIONS) \
$(CBFSTOOL_ADD_CMD_OPTIONS)
else # ifeq ($(CONFIG_ARCH_X86),y)
$(CBFSTOOL) $@.tmp write -u \
-r BOOTBLOCK \
Expand All @@ -1098,10 +1106,11 @@ else # ifeq ($(CONFIG_ARCH_X86),y)
-f $@.tmp.2 \
-n "header pointer" \
-t "cbfs header" \
-b -4
-b -4 \
$(CBFSTOOL_ADD_CMD_OPTIONS)
rm -f $@.tmp.2
endif # ifeq ($(CONFIG_ARCH_X86),y)
$(CBFSTOOL) $@.tmp add-master-header $(TS_OPTIONS)
$(CBFSTOOL) $@.tmp add-master-header $(TS_OPTIONS) $(CBFSTOOL_ADD_CMD_OPTIONS)
$(prebuild-files) true
mv $@.tmp $@
else # ifneq ($(CONFIG_UPDATE_IMAGE),y)
Expand All @@ -1121,8 +1130,6 @@ $(REFCODE_BLOB): $(RMODTOOL)
$(RMODTOOL) -i $(CONFIG_REFCODE_BLOB_FILE) -o $@
endif

FIT_ENTRY=$(call strip_quotes, $(CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG))

ifeq ($(CONFIG_HAVE_RAMSTAGE),y)
RAMSTAGE=$(objcbfs)/ramstage.elf
else
Expand All @@ -1136,42 +1143,13 @@ $(obj)/coreboot.rom: $(obj)/coreboot.pre $(RAMSTAGE) $(CBFSTOOL) $$(INTERMEDIATE
dd if=/dev/zero bs=$(call _toint,$(CONFIG_ROM_SIZE)) count=1 2> /dev/null | tr '\000' '\377' > $@.tmp
dd if=$(obj)/coreboot.pre of=$@.tmp bs=8192 conv=notrunc 2> /dev/null
ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
ifneq ($(CONFIG_UPDATE_IMAGE),y) # never update the bootblock
ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
@printf " UPDATE-FIT\n"
$(IFITTOOL) -f $@.tmp -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \
-r COREBOOT
endif
ifeq ($(CONFIG_USE_CPU_MICROCODE_CBFS_BINS),y)
@printf " UPDATE-FIT\n"
$(IFITTOOL) -f $@.tmp -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \
-r COREBOOT
endif
# Print final FIT table
$(IFITTOOL) -f $@.tmp -D -r COREBOOT

# Second FIT in TOP_SWAP bootblock
# Print final TS BOOTBLOCK FIT table
ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y)
# INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG adds a region as first ucode into the seconds bootblock
ifneq ($(FIT_ENTRY),)
@printf " UPDATE-FIT2\n"
$(IFITTOOL) -f $@.tmp -A -n $(FIT_ENTRY) -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \
$(TS_OPTIONS) -r COREBOOT
endif
ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
@printf " UPDATE-FIT2\n"
$(IFITTOOL) -f $@.tmp -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \
$(TS_OPTIONS) -r COREBOOT
endif
ifeq ($(CONFIG_USE_CPU_MICROCODE_CBFS_BINS),y)
@printf " UPDATE-FIT2\n"
$(IFITTOOL) -f $@.tmp -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \
$(TS_OPTIONS) -r COREBOOT
endif
@printf " TOP SWAP FIT table\n"
$(IFITTOOL) -f $@.tmp -D $(TS_OPTIONS) -r COREBOOT

endif

endif # !CONFIG_UPDATE_IMAGE
endif # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK
endif # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE
ifeq ($(CONFIG_AGESA_UCODE_EXPERIMENTAL),y)
dd if=$(CONFIG_CPU_UCODE_BINARIES) of=$@.tmp bs=1 seek=6665692 count=3424 conv=notrunc 2> /dev/null
Expand Down Expand Up @@ -1239,6 +1217,10 @@ cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += revision
revision-file := $(obj)/build.h
revision-type := raw

cbfs-files-y += build_info
build_info-file := $(obj)/build_info
build_info-type := raw

BOOTSPLASH_SUFFIX=$(suffix $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)))
cbfs-files-$(CONFIG_BOOTSPLASH_IMAGE) += bootsplash$(BOOTSPLASH_SUFFIX)
bootsplash$(BOOTSPLASH_SUFFIX)-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE))
Expand Down
38 changes: 38 additions & 0 deletions configs/config.asus_p8z77-v_lx2.debug_smmstore_hotplug_yabel_em100
View file
@@ -0,0 +1,38 @@
# Not meant for actual use, but rather to build-test individual options.
# If keeping this combination of options buildable becomes too hard in
# the future, then this config can be split into several smaller chunks.
# Exercises, among other things:
# + PCIe hotplug
# + Fatal assertions
# + Debug options
# + SMMSTORE
# + YABEL
# + VESA framebuffer
# + EM100 support
CONFIG_VENDOR_ASUS=y
CONFIG_CBFS_SIZE=0x200000
CONFIG_BOARD_ASUS_P8Z77_V_LX2=y
CONFIG_PCIEXP_L1_SUB_STATE=y
CONFIG_PCIEXP_CLK_PM=y
# CONFIG_S3_VGA_ROM_RUN is not set
CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES=y
CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS=y
CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF=y
CONFIG_VGA_ROM_RUN=y
CONFIG_PCI_OPTION_ROM_RUN_YABEL=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_VBE_LINEAR_FRAMEBUFFER=y
CONFIG_PCIEXP_HOTPLUG=y
CONFIG_SMMSTORE=y
CONFIG_FATAL_ASSERTS=y
CONFIG_DEBUG_CBFS=y
CONFIG_DEBUG_RAM_SETUP=y
CONFIG_DEBUG_SMBUS=y
CONFIG_DEBUG_SMI=y
CONFIG_DEBUG_MALLOC=y
CONFIG_DEBUG_CONSOLE_INIT=y
CONFIG_DEBUG_SPI_FLASH=y
CONFIG_DEBUG_BOOT_STATE=y
CONFIG_DEBUG_ADA_CODE=y
CONFIG_HAVE_EM100_SUPPORT=y
CONFIG_EM100=y
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu1
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.13.0.1"
CONFIG_LOCALVERSION="v4.13.0.2"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_NO_GFX_INIT=y
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu2
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.13.0.1"
CONFIG_LOCALVERSION="v4.13.0.2"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU2=y
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu3
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.13.0.1"
CONFIG_LOCALVERSION="v4.13.0.2"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU3=y
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu4
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.13.0.1"
CONFIG_LOCALVERSION="v4.13.0.2"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU4=y
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu5
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.13.0.1"
CONFIG_LOCALVERSION="v4.13.0.2"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU5=y
Expand Down
2 changes: 1 addition & 1 deletion configs/config.pcengines_apu6
View file
@@ -1,4 +1,4 @@
CONFIG_LOCALVERSION="v4.13.0.1"
CONFIG_LOCALVERSION="v4.13.0.2"
CONFIG_VENDOR_PCENGINES=y
CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/seabios_config"
CONFIG_BOARD_PCENGINES_APU6=y
Expand Down
5 changes: 5 additions & 0 deletions payloads/libpayload/arch/arm64/mmu.c
View file
Expand Up @@ -705,3 +705,8 @@ void mmu_presysinfo_enable(void)
mmu_init(&usedmem_ranges);
mmu_enable();
}

const struct mmu_ranges *mmu_get_used_ranges(void)
{
return &usedmem_ranges;
}
8 changes: 8 additions & 0 deletions payloads/libpayload/include/arm64/arch/mmu.h
View file
Expand Up @@ -194,4 +194,12 @@ struct mmu_memrange* mmu_init_ranges_from_sysinfo(struct memrange *cb_ranges,
*/
void mmu_presysinfo_memory_used(uint64_t base, uint64_t size);
void mmu_presysinfo_enable(void);

/*
* Functions for exposing the used memory ranges to payloads. The ranges contain
* all used memory ranges that are actually used by payload. i.e. _start -> _end
* in linker script, the coreboot tables and framebuffer/DMA allocated in MMU
* initialization.
*/
const struct mmu_ranges *mmu_get_used_ranges(void);
#endif // __ARCH_ARM64_MMU_H__
13 changes: 13 additions & 0 deletions payloads/libpayload/include/coreboot_tables.h
View file
Expand Up @@ -261,12 +261,25 @@ struct cb_x86_rom_mtrr {
uint32_t index;
};

/* Memory map windows to translate addresses between SPI flash space and host address space. */
struct flash_mmap_window {
uint32_t flash_base;
uint32_t host_base;
uint32_t size;
};

struct cb_spi_flash {
uint32_t tag;
uint32_t size;
uint32_t flash_size;
uint32_t sector_size;
uint32_t erase_cmd;
/*
* Number of mmap windows used by the platform to decode addresses between SPI flash
* space and host address space. This determines the number of entries in mmap_table.
*/
uint32_t mmap_count;
struct flash_mmap_window mmap_table[0];
};

struct cb_boot_media_params {
Expand Down
5 changes: 5 additions & 0 deletions payloads/libpayload/include/sysinfo.h
View file
Expand Up @@ -40,6 +40,9 @@
/* Up to 10 MAC addresses */
#define SYSINFO_MAX_MACS 10

/* Maximum of 2 MMAP windows for decoding SPI flash. */
#define SYSINFO_MAX_MMAP_WINDOWS 2

#include <coreboot_tables.h>

/*
Expand Down Expand Up @@ -126,6 +129,8 @@ struct sysinfo_t {
uint32_t size;
uint32_t sector_size;
uint32_t erase_cmd;
uint32_t mmap_window_count;
struct flash_mmap_window mmap_table[SYSINFO_MAX_MMAP_WINDOWS];
} spi_flash;
uint64_t fmap_offset;
uint64_t cbfs_offset;
Expand Down
7 changes: 7 additions & 0 deletions payloads/libpayload/libc/coreboot.c
View file
Expand Up @@ -211,6 +211,13 @@ static void cb_parse_spi_flash(void *ptr, struct sysinfo_t *info)
info->spi_flash.size = flash->flash_size;
info->spi_flash.sector_size = flash->sector_size;
info->spi_flash.erase_cmd = flash->erase_cmd;

if (flash->mmap_count == 0)
return;

info->spi_flash.mmap_window_count = MIN(flash->mmap_count, SYSINFO_MAX_MMAP_WINDOWS);
memcpy(info->spi_flash.mmap_table, flash->mmap_table,
info->spi_flash.mmap_window_count * sizeof(struct flash_mmap_window));
}

static void cb_parse_boot_media_params(unsigned char *ptr,
Expand Down
19 changes: 4 additions & 15 deletions src/Kconfig
View file
Expand Up @@ -905,7 +905,7 @@ config DEBUG_PERIODIC_SMI
# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
# printk(BIOS_DEBUG, ...) calls.
config DEBUG_MALLOC
prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL
bool
default n
help
Expand All @@ -917,7 +917,7 @@ config DEBUG_MALLOC

# Only visible if DEBUG_SPEW (8) is set.
config DEBUG_RESOURCES
bool "Output verbose PCI MEM and IO resource debug messages" if DEFAULT_CONSOLE_LOGLEVEL_8
bool "Output verbose PCI MEM and IO resource debug messages" if DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL
default n
help
This option enables additional PCI memory and IO debug messages.
Expand All @@ -939,7 +939,7 @@ config DEBUG_CONSOLE_INIT
# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
# printk(BIOS_DEBUG, ...) calls.
config REALMODE_DEBUG
prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 || CONSOLE_OVERRIDE_LOGLEVEL
bool
default n
depends on PCI_OPTION_ROM_RUN_REALMODE
Expand Down Expand Up @@ -1113,23 +1113,12 @@ config DEBUG_INTEL_ME
is present on Intel 6-series chipsets.
endif

config TRACE
bool "Trace function calls"
default n
help
If enabled, every function will print information to console once
the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
of calling function. Please note some printk related functions
are omitted from trace to have good looking console dumps.

config DEBUG_FUNC
bool "Enable function entry and exit reporting macros" if DEFAULT_CONSOLE_LOGLEVEL_8
default n
help
This option enables additional function entry and exit debug messages
for select functions. If supported, this is less output than
the TRACE option.
for select functions.
Note: This option will increase the size of the coreboot image.
If unsure, say N.

Expand Down
7 changes: 2 additions & 5 deletions src/acpi/acpi.c
View file
Expand Up @@ -1340,9 +1340,7 @@ unsigned long write_acpi_tables(unsigned long start)
return fw;
}

dsdt_file = cbfs_boot_map_with_leak(
CONFIG_CBFS_PREFIX "/dsdt.aml",
CBFS_TYPE_RAW, &dsdt_size);
dsdt_file = cbfs_map(CONFIG_CBFS_PREFIX "/dsdt.aml", &dsdt_size);
if (!dsdt_file) {
printk(BIOS_ERR, "No DSDT file, skipping ACPI tables\n");
return current;
Expand All @@ -1355,8 +1353,7 @@ unsigned long write_acpi_tables(unsigned long start)
return current;
}

slic_file = cbfs_boot_map_with_leak(CONFIG_CBFS_PREFIX "/slic",
CBFS_TYPE_RAW, &slic_size);
slic_file = cbfs_map(CONFIG_CBFS_PREFIX "/slic", &slic_size);
if (slic_file
&& (slic_file->length > slic_size
|| slic_file->length < sizeof(acpi_header_t)
Expand Down
4 changes: 4 additions & 0 deletions src/acpi/acpigen.c
View file
Expand Up @@ -291,6 +291,10 @@ void acpigen_emit_namestring(const char *namepath)
int dotcount = 0, i;
int dotpos = 0;

/* Check for NULL pointer */
if (!namepath)
return;

/* We can start with a '\'. */
if (namepath[0] == '\\') {
acpigen_emit_byte('\\');
Expand Down
5 changes: 0 additions & 5 deletions src/arch/arm/Makefile.inc
View file
Expand Up @@ -27,11 +27,6 @@ endif # CONFIG_ARCH_ARM

ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARM),y)

decompressor-y += id.S
bootblock-y += id.S
$(call src-to-obj,decompressor,$(dir)/id.S): $(obj)/build.h
$(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h

decompressor-y += boot.c
bootblock-y += boot.c
decompressor-y += div0.c
Expand Down
22 changes: 0 additions & 22 deletions src/arch/arm/id.S
View file

This file was deleted.

4 changes: 0 additions & 4 deletions src/arch/arm64/Makefile.inc
View file
Expand Up @@ -26,10 +26,6 @@ decompressor-y += div0.c
bootblock-y += div0.c
decompressor-y += eabi_compat.c
bootblock-y += eabi_compat.c
decompressor-y += id.S
bootblock-y += id.S
$(call src-to-obj,decompressor,$(dir)/id.S): $(obj)/build.h
$(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h

decompressor-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c
bootblock-$(CONFIG_ARM64_USE_ARCH_TIMER) += arch_timer.c
Expand Down
22 changes: 0 additions & 22 deletions src/arch/arm64/id.S
View file

This file was deleted.

24 changes: 0 additions & 24 deletions src/arch/ppc64/bootblock.S
View file
Expand Up @@ -8,27 +8,3 @@
.org 0x100, 0xff
_start:
b _start
.section ".id", "a", %progbits

.section ".id", "a", @progbits

.globl __id_start
__id_start:
ver:
.asciz "4" //COREBOOT_VERSION
vendor:
.asciz "qemu" //CONFIG_MAINBOARD_VENDOR
part:
.asciz "1" //CONFIG_MAINBOARD_PART_NUMBER
/* Reverse offset to the vendor id */
.long __id_end + CONFIG_ID_SECTION_OFFSET - ver
/* Reverse offset to the vendor id */
.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor
/* Reverse offset to the part number */
.long __id_end + CONFIG_ID_SECTION_OFFSET - part
/* of this romimage */
.long CONFIG_ROM_SIZE
.globl __id_end

__id_end:
.previous
8 changes: 0 additions & 8 deletions src/arch/ppc64/id.ld
View file

This file was deleted.

4 changes: 0 additions & 4 deletions src/arch/ppc64/prologue.inc
View file

This file was deleted.

11 changes: 7 additions & 4 deletions src/arch/x86/Kconfig
View file
Expand Up @@ -144,6 +144,13 @@ config PRERAM_CBMEM_CONSOLE_SIZE
help
Increase this value if preram cbmem console is getting truncated

config CBFS_MCACHE_SIZE
hex
depends on !NO_CBFS_MCACHE
default 0x2000
help
Increase this value if you see CBFS mcache overflow warnings.

config PC80_SYSTEM
bool
default y if ARCH_X86
Expand Down Expand Up @@ -179,10 +186,6 @@ config HPET_ADDRESS
hex
default 0xfed00000 if !HPET_ADDRESS_OVERRIDE

config ID_SECTION_OFFSET
hex
default 0x80

# 64KiB default bootblock size
config C_ENV_BOOTBLOCK_SIZE
hex
Expand Down
3 changes: 1 addition & 2 deletions src/arch/x86/Makefile.inc
View file
Expand Up @@ -98,6 +98,7 @@ bootblock-y += memmove.c
bootblock-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c
bootblock-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
bootblock-$(CONFIG_BOOTBLOCK_NORMAL) += bootblock_normal.c
bootblock-y += gdt_init.S
bootblock-y += id.S
bootblock-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c

Expand Down Expand Up @@ -160,8 +161,6 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y)

romstage-y += boot.c
romstage-y += post.c
# gdt_init.S is included by entry32.inc when romstage is the first C
# environment.
romstage-y += gdt_init.S
romstage-y += cpu_common.c
romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
Expand Down
35 changes: 35 additions & 0 deletions src/arch/x86/bootblock.ld
View file
@@ -0,0 +1,35 @@
/* SPDX-License-Identifier: GPL-2.0-only */

gdtptr_offset = gdtptr & 0xffff;
nullidt_offset = nullidt & 0xffff;

/* Symbol _start16bit must be aligned to 4kB to start AP CPUs with
* Startup IPI message without RAM.
*/
#if CONFIG(SIPI_VECTOR_IN_ROM)
_bogus = ASSERT((_start16bit & 0xfff) == 0, "Symbol _start16bit is not at 4 KiB boundary");
ap_sipi_vector_in_rom = (_start16bit >> 12) & 0xff;
#endif

SECTIONS {
/* Trigger an error if I have an unusable start address */
_bogus = ASSERT(_start16bit >= 0xffff0000, "_start16bit too low. Please report.");

. = _ID_SECTION;
.id (.): {
KEEP(*(.id));
}
_ID_SECTION = 0xffffff80 - SIZEOF(.id);

. = 0xffffffc0;
.fit_pointer (.): {
KEEP(*(.fit_pointer));
}

. = 0xfffffff0;
.reset . : {
*(.reset);
. = 15;
BYTE(0x00);
}
}
2 changes: 1 addition & 1 deletion src/arch/x86/bootblock_crt0.S
View file
Expand Up @@ -10,7 +10,7 @@

#include <cpu/x86/cr.h>

.section .text
.section .text._start

/*
* Include the old code for reset vector and protected mode entry. That code has
Expand Down
2 changes: 1 addition & 1 deletion src/arch/x86/bootblock_normal.c
View file
Expand Up @@ -18,7 +18,7 @@ int legacy_romstage_selector(struct prog *romstage)
const char *boot_candidate;
size_t stages_len;

boot_candidate = cbfs_boot_map_with_leak("coreboot-stages", CBFS_TYPE_RAW, &stages_len);
boot_candidate = cbfs_map("coreboot-stages", &stages_len);
if (!boot_candidate)
boot_candidate = default_filenames;

Expand Down
10 changes: 2 additions & 8 deletions src/arch/x86/c_start.S
View file
Expand Up @@ -142,10 +142,10 @@ gdtaddr:

/* This is the gdt for GCC part of coreboot.
* It is different from the gdt in ASM part of coreboot
* which is defined in entry32.inc
* which is defined in gdt_init.S
*
* When the machine is initially started, we use a very simple
* gdt from ROM (that in entry32.inc) which only contains those
* gdt from ROM (that in gdt_init.S) which only contains those
* entries we need for protected mode.
*
* When we're executing code from RAM, we want to do more complex
Expand Down Expand Up @@ -235,10 +235,4 @@ setCodeSelectorLongJump:
# restore rsp, it might not have been 16-byte aligned on entry
mov %rdx, %rsp
ret

.previous
.code64
#else
.previous
.code32
#endif
7 changes: 7 additions & 0 deletions src/arch/x86/car.ld
View file
Expand Up @@ -48,6 +48,9 @@

TIMESTAMP(., 0x200)

#if !CONFIG(NO_CBFS_MCACHE)
CBFS_MCACHE(., CONFIG_CBFS_MCACHE_SIZE)
#endif
#if !CONFIG(NO_FMAP_CACHE)
FMAP_CACHE(., FMAP_SIZE)
#endif
Expand Down Expand Up @@ -117,3 +120,7 @@ _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) <= CONFIG_DC
_bogus2 = ASSERT(_pagetables == ALIGN(_pagetables, 4096), "_pagetables aren't 4KiB aligned");
#endif
_bogus3 = ASSERT(CONFIG_DCACHE_BSP_STACK_SIZE > 0x0, "BSP stack size not configured");
#if CONFIG(NO_XIP_EARLY_STAGES) && (ENV_ROMSTAGE || ENV_VERSTAGE)
_bogus4 = ASSERT(_eprogram <= _car_region_end, "Stage end too high !");
_bogus5 = ASSERT(_program >= _car_unallocated_start, "Stage start too low!");
#endif
28 changes: 12 additions & 16 deletions src/arch/x86/id.S
View file
Expand Up @@ -2,27 +2,23 @@

#include <build.h>

.section ".id", "a", @progbits
.section ".id", "a", @progbits

.globl __id_start
__id_start:
ver:
.asciz COREBOOT_VERSION
vendor:
.asciz CONFIG_MAINBOARD_VENDOR
part:
.asciz CONFIG_MAINBOARD_PART_NUMBER
.long __id_end + CONFIG_ID_SECTION_OFFSET - ver /* Reverse offset to the
*vendor id
*/
.long __id_end + CONFIG_ID_SECTION_OFFSET - vendor /* Reverse offset to the
* vendor id
*/
.long __id_end + CONFIG_ID_SECTION_OFFSET - part /* Reverse offset to the
* part number
*/
.long CONFIG_ROM_SIZE /* Size of this romimage */
.globl __id_end

__id_end:
.previous
#if ENV_X86_64
.long 0xffffffff - ver + 1 /* Reverse offset to the version */
.long 0xffffffff - vendor + 1 /* Reverse offset to the vendor id */
.long 0xffffffff - part + 1 /* Reverse offset to the part number */
#else
.long - ver /* Reverse offset to the version */
.long - vendor /* Reverse offset to the vendor id */
.long - part /* Reverse offset to the part number */
#endif

.long CONFIG_ROM_SIZE /* Size of this romimage */
8 changes: 0 additions & 8 deletions src/arch/x86/id.ld
View file

This file was deleted.

70 changes: 70 additions & 0 deletions src/arch/x86/include/mode_switch.h
View file
@@ -0,0 +1,70 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <stddef.h>
#include <stdint.h>

#if ENV_X86_64
int protected_mode_call_narg(uint32_t arg_count,
uint32_t func_ptr,
uint32_t opt_arg1,
uint32_t opt_arg2);

/*
* Drops into protected mode and calls the function, which must have been compiled for x86_32.
* After the function returns it enters long mode again.
* The function pointer destination must be below 4GiB in physical memory.
*
* The called function doesn't have arguments and returns an int.
*/
static inline int protected_mode_call(void *func)
{
return protected_mode_call_narg(0, (uintptr_t)func, 0, 0);
}

/*
* Drops into protected mode and calls the function, which must have been compiled for x86_32.
* After the function returns it enters long mode again.
* The function pointer destination must be below 4GiB in physical memory.
* Only the lower 32bits of the argument are passed to the called function.
*
* The called function have one argument and returns an int.
*/
static inline int protected_mode_call_1arg(void *func, uint32_t arg1)
{
return protected_mode_call_narg(1, (uintptr_t)func, arg1, 0);
}

/*
* Drops into protected mode and calls the function, which must have been compiled for x86_32.
* After the function returns it enters long mode again.
* The function pointer destination must be below 4GiB in physical memory.
* Only the lower 32bits of the argument are passed to the called function.
*
* The called function has two arguments and returns an int.
*/
static inline int protected_mode_call_2arg(void *func, uint32_t arg1, uint32_t arg2)
{
return protected_mode_call_narg(2, (uintptr_t)func, arg1, arg2);
}
#else
static inline int protected_mode_call(void *func)
{
int (*doit)(void) = func;

return doit();
}

static inline int protected_mode_call_1arg(void *func, uint32_t arg1)
{
int (*doit)(uint32_t arg1) = func;

return doit(arg1);
}

static inline int protected_mode_call_2arg(void *func, uint32_t arg1, uint32_t arg2)
{
int (*doit)(uint32_t arg1, uint32_t arg2) = func;

return doit(arg1, arg2);
}
#endif
8 changes: 1 addition & 7 deletions src/arch/x86/memlayout.ld
View file
Expand Up @@ -39,11 +39,5 @@ SECTIONS
}

#if ENV_BOOTBLOCK
/* Bootblock specific scripts which provide more SECTION directives. */
#include <cpu/x86/16bit/entry16.ld>
#include <cpu/x86/16bit/reset16.ld>
#include <arch/x86/id.ld>
#if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE)
#include <cpu/intel/fit/fit.ld>
#endif
#include <arch/x86/bootblock.ld>
#endif /* ENV_BOOTBLOCK */
10 changes: 10 additions & 0 deletions src/arch/x86/mmap_boot.c
View file
Expand Up @@ -2,6 +2,7 @@

#include <boot_device.h>
#include <endian.h>
#include <spi_flash.h>

/* The ROM is memory mapped just below 4GiB. Form a pointer for the base. */
#define rom_base ((void *)(uintptr_t)(0x100000000ULL-CONFIG_ROM_SIZE))
Expand All @@ -13,3 +14,12 @@ const struct region_device *boot_device_ro(void)
{
return &boot_dev.rdev;
}

uint32_t spi_flash_get_mmap_windows(struct flash_mmap_window *table)
{
table->flash_base = 0;
table->host_base = (uint32_t)(uintptr_t)rom_base;
table->size = CONFIG_ROM_SIZE;

return 1;
}
2 changes: 1 addition & 1 deletion src/arch/x86/smbios.c
View file
Expand Up @@ -414,7 +414,7 @@ static int smbios_write_type0(unsigned long *current, int handle)
#if CONFIG(CHROMEOS) && CONFIG(HAVE_ACPI_TABLES)
u32 version_offset = (u32)smbios_string_table_len(t->eos);
/* SMBIOS offsets start at 1 rather than 0 */
chromeos_get_chromeos_acpi()->vbt10 = (u32)t->eos + (version_offset - 1);
chromeos_get_chromeos_acpi()->vbt10 = (uintptr_t)t->eos + (version_offset - 1);
#endif
t->bios_version = smbios_add_string(t->eos, get_bios_version());
uint32_t rom_size = CONFIG_ROM_SIZE;
Expand Down
6 changes: 3 additions & 3 deletions src/commonlib/bsd/cbfs_mcache.c
View file
Expand Up @@ -95,7 +95,7 @@ cb_err_t cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const char *
const void *end = mcache + mcache_size;
const void *current = mcache;

while (current + sizeof(uint32_t) < end) {
while (current + sizeof(uint32_t) <= end) {
const union mcache_entry *entry = current;

if (entry->magic == MCACHE_MAGIC_END)
Expand All @@ -106,8 +106,8 @@ cb_err_t cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const char *
assert(entry->magic == MCACHE_MAGIC_FILE);
const uint32_t data_offset = be32toh(entry->file.h.offset);
const uint32_t data_length = be32toh(entry->file.h.len);
if (namesize <= data_offset - offsetof(union cbfs_mdata, filename) &&
memcmp(name, entry->file.filename, namesize) == 0) {
if (namesize <= data_offset - offsetof(union cbfs_mdata, h.filename) &&
memcmp(name, entry->file.h.filename, namesize) == 0) {
LOG("Found '%s' @%#x size %#x in mcache @%p\n",
name, entry->offset, data_length, current);
*data_offset_out = entry->offset + data_offset;
Expand Down
41 changes: 36 additions & 5 deletions src/commonlib/bsd/cbfs_private.c
View file
Expand Up @@ -46,7 +46,7 @@ cb_err_t cbfs_walk(cbfs_dev_t dev, cb_err_t (*walker)(cbfs_dev_t dev, size_t off
const uint32_t data_offset = be32toh(mdata.h.offset);
const uint32_t data_length = be32toh(mdata.h.len);
const uint32_t type = be32toh(mdata.h.type);
const bool empty = (type == CBFS_TYPE_DELETED || type == CBFS_TYPE_DELETED2);
const bool empty = (type == CBFS_TYPE_DELETED || type == CBFS_TYPE_NULL);

DEBUG("Found CBFS header @%#zx (type %d, attr +%#x, data +%#x, length %#x)\n",
offset, type, attr_offset, data_offset, data_length);
Expand Down Expand Up @@ -75,7 +75,7 @@ cb_err_t cbfs_walk(cbfs_dev_t dev, cb_err_t (*walker)(cbfs_dev_t dev, size_t off
if (cbfs_dev_read(dev, mdata.raw + sizeof(mdata.h),
offset + sizeof(mdata.h), todo) != todo)
return CB_CBFS_IO;
DEBUG("File name: '%s'\n", mdata.filename);
DEBUG("File name: '%s'\n", mdata.h.filename);

if (do_hash && !empty && vb2_digest_extend(&dc, mdata.raw, data_offset))
return CB_ERR;
Expand Down Expand Up @@ -134,10 +134,9 @@ static cb_err_t lookup_walker(cbfs_dev_t dev, size_t offset, const union cbfs_md
size_t already_read, void *arg)
{
struct cbfs_lookup_args *args = arg;

/* Check if the name we're looking for could fit, then we can safely memcmp() it. */
if (args->namesize > already_read - offsetof(union cbfs_mdata, filename) ||
memcmp(args->name, mdata->filename, args->namesize) != 0)
if (args->namesize > already_read - offsetof(union cbfs_mdata, h.filename) ||
memcmp(args->name, mdata->h.filename, args->namesize) != 0)
return CB_CBFS_NOT_FOUND;

LOG("Found '%s' @%#zx size %#x\n", args->name, offset, be32toh(mdata->h.len));
Expand All @@ -159,3 +158,35 @@ cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_o
};
return cbfs_walk(dev, lookup_walker, &args, metadata_hash, 0);
}

const void *cbfs_find_attr(const union cbfs_mdata *mdata, uint32_t attr_tag, size_t size_check)
{
uint32_t offset = be32toh(mdata->h.attributes_offset);
uint32_t end = be32toh(mdata->h.offset);

if (!offset)
return NULL;

while (offset + sizeof(struct cbfs_file_attribute) <= end) {
const struct cbfs_file_attribute *attr = (const void *)mdata->raw + offset;
const uint32_t tag = be32toh(attr->tag);
const uint32_t len = be32toh(attr->len);

if (offset + len > end) {
ERROR("Attribute %s[%u] overflows end of metadata\n",
mdata->h.filename, tag);
return NULL;
}
if (tag == attr_tag) {
if (size_check && len != size_check) {
ERROR("Attribute %s[%u] size mismatch: %u != %zu\n",
mdata->h.filename, tag, len, size_check);
return NULL;
}
return attr;
}
offset += len;
}

return NULL;
}
11 changes: 6 additions & 5 deletions src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h
View file
Expand Up @@ -48,12 +48,8 @@
* avoid byte-order confusion, fields should always and only be converted to host byte order at
* exactly the time they are read from one of these structures into their own separate variable.
*/
#define CBFS_METADATA_MAX_SIZE 256
union cbfs_mdata {
struct {
struct cbfs_file h;
char filename[];
};
struct cbfs_file h;
uint8_t raw[CBFS_METADATA_MAX_SIZE];
};

Expand Down Expand Up @@ -134,4 +130,9 @@ cb_err_t cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const char *
/* Returns the amount of bytes actually used by the CBFS metadata cache in |mcache|. */
size_t cbfs_mcache_real_size(const void *mcache, size_t mcache_size);

/* Finds a CBFS attribute in a metadata block. Attribute returned as-is (still big-endian).
If |size| is not 0, will check that it matches the length of the attribute (if found)...
else caller is responsible for checking the |len| field to avoid reading out-of-bounds. */
const void *cbfs_find_attr(const union cbfs_mdata *mdata, uint32_t attr_tag, size_t size_check);

#endif /* _COMMONLIB_BSD_CBFS_PRIVATE_H_ */
120 changes: 66 additions & 54 deletions src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h
View file
Expand Up @@ -6,45 +6,40 @@
#include <stdint.h>
#include <vb2_sha.h>

/** These are standard values for the known compression
algorithms that coreboot knows about for stages and
payloads. Of course, other CBFS users can use whatever
values they want, as long as they understand them. */

#define CBFS_COMPRESS_NONE 0
#define CBFS_COMPRESS_LZMA 1
#define CBFS_COMPRESS_LZ4 2

/** These are standard component types for well known
components (i.e - those that coreboot needs to consume.
Users are welcome to use any other value for their
components */

#define CBFS_TYPE_DELETED 0x00000000
#define CBFS_TYPE_DELETED2 0xffffffff
#define CBFS_TYPE_BOOTBLOCK 0x01
#define CBFS_TYPE_STAGE 0x10
#define CBFS_TYPE_SELF 0x20
#define CBFS_TYPE_FIT 0x21
#define CBFS_TYPE_OPTIONROM 0x30
#define CBFS_TYPE_BOOTSPLASH 0x40
#define CBFS_TYPE_RAW 0x50
#define CBFS_TYPE_VSA 0x51
#define CBFS_TYPE_MBI 0x52
#define CBFS_TYPE_MICROCODE 0x53
#define CBFS_TYPE_FSP 0x60
#define CBFS_TYPE_MRC 0x61
#define CBFS_TYPE_MMA 0x62
#define CBFS_TYPE_EFI 0x63
#define CBFS_TYPE_STRUCT 0x70
#define CBFS_COMPONENT_CMOS_DEFAULT 0xaa
#define CBFS_TYPE_SPD 0xab
#define CBFS_TYPE_MRC_CACHE 0xac
#define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa

#define CBFS_HEADER_MAGIC 0x4F524243
#define CBFS_HEADER_VERSION1 0x31313131
#define CBFS_HEADER_VERSION2 0x31313132
enum cbfs_compression {
CBFS_COMPRESS_NONE = 0,
CBFS_COMPRESS_LZMA = 1,
CBFS_COMPRESS_LZ4 = 2,
};

enum cbfs_type {
CBFS_TYPE_DELETED = 0x00000000,
CBFS_TYPE_NULL = 0xffffffff,
CBFS_TYPE_BOOTBLOCK = 0x01,
CBFS_TYPE_CBFSHEADER = 0x02,
CBFS_TYPE_STAGE = 0x10,
CBFS_TYPE_SELF = 0x20,
CBFS_TYPE_FIT = 0x21,
CBFS_TYPE_OPTIONROM = 0x30,
CBFS_TYPE_BOOTSPLASH = 0x40,
CBFS_TYPE_RAW = 0x50,
CBFS_TYPE_VSA = 0x51,
CBFS_TYPE_MBI = 0x52,
CBFS_TYPE_MICROCODE = 0x53,
CBFS_TYPE_FSP = 0x60,
CBFS_TYPE_MRC = 0x61,
CBFS_TYPE_MMA = 0x62,
CBFS_TYPE_EFI = 0x63,
CBFS_TYPE_STRUCT = 0x70,
CBFS_TYPE_CMOS_DEFAULT = 0xaa,
CBFS_TYPE_SPD = 0xab,
CBFS_TYPE_MRC_CACHE = 0xac,
CBFS_TYPE_CMOS_LAYOUT = 0x01aa,
};

#define CBFS_HEADER_MAGIC 0x4F524243 /* BE: 'ORBC' */
#define CBFS_HEADER_VERSION1 0x31313131 /* BE: '1111' */
#define CBFS_HEADER_VERSION2 0x31313132 /* BE: '1112' */
#define CBFS_HEADER_VERSION CBFS_HEADER_VERSION2

/* this is the master cbfs header - it must be located somewhere available
Expand All @@ -68,9 +63,15 @@ struct cbfs_header {
/* "Unknown" refers to CBFS headers version 1,
* before the architecture was defined (i.e., x86 only).
*/
#define CBFS_ARCHITECTURE_UNKNOWN 0xFFFFFFFF
#define CBFS_ARCHITECTURE_X86 0x00000001
#define CBFS_ARCHITECTURE_ARM 0x00000010
enum cbfs_architecture {
CBFS_ARCHITECTURE_UNKNOWN = 0xFFFFFFFF,
CBFS_ARCHITECTURE_X86 = 0x00000001,
CBFS_ARCHITECTURE_ARM = 0x00000010,
CBFS_ARCHITECTURE_AARCH64 = 0x0000aa64,
CBFS_ARCHITECTURE_MIPS = 0x00000100, /* deprecated */
CBFS_ARCHITECTURE_RISCV = 0xc001d0de,
CBFS_ARCHITECTURE_PPC64 = 0x407570ff,
};

/** This is a component header - every entry in the CBFS
will have this header.
Expand All @@ -88,15 +89,21 @@ struct cbfs_header {
*/

#define CBFS_FILE_MAGIC "LARCHIVE"
#define CBFS_METADATA_MAX_SIZE 256

struct cbfs_file {
char magic[8];
uint32_t len;
uint32_t type;
uint32_t attributes_offset;
uint32_t offset;
char filename[0];
} __packed;

#if defined __GNUC__ && (__GNUC__ * 100 + __GNUC_MINOR__) >= 406
_Static_assert(sizeof(struct cbfs_file) == 24, "cbfs_file size mismatch");
#endif

/* The common fields of extended cbfs file attributes.
Attributes are expected to start with tag/len, then append their
specific fields. */
Expand All @@ -109,13 +116,16 @@ struct cbfs_file_attribute {

/* Depending on how the header was initialized, it may be backed with 0x00 or
* 0xff. Support both. */
#define CBFS_FILE_ATTR_TAG_UNUSED 0
#define CBFS_FILE_ATTR_TAG_UNUSED2 0xffffffff
#define CBFS_FILE_ATTR_TAG_COMPRESSION 0x42435a4c
#define CBFS_FILE_ATTR_TAG_HASH 0x68736148
#define CBFS_FILE_ATTR_TAG_POSITION 0x42435350 /* PSCB */
#define CBFS_FILE_ATTR_TAG_ALIGNMENT 0x42434c41 /* ALCB */
#define CBFS_FILE_ATTR_TAG_IBB 0x32494242 /* Initial BootBlock */
enum cbfs_file_attr_tag {
CBFS_FILE_ATTR_TAG_UNUSED = 0,
CBFS_FILE_ATTR_TAG_UNUSED2 = 0xffffffff,
CBFS_FILE_ATTR_TAG_COMPRESSION = 0x42435a4c, /* BE: 'BCZL' */
CBFS_FILE_ATTR_TAG_HASH = 0x68736148, /* BE: 'hsaH' */
CBFS_FILE_ATTR_TAG_POSITION = 0x42435350, /* BE: 'BCSP' */
CBFS_FILE_ATTR_TAG_ALIGNMENT = 0x42434c41, /* BE: 'BCLA' */
CBFS_FILE_ATTR_TAG_IBB = 0x32494242, /* BE: '2IBB' */
CBFS_FILE_ATTR_TAG_PADDING = 0x47444150, /* BE: 'GNDP' */
};

struct cbfs_file_attr_compression {
uint32_t tag;
Expand Down Expand Up @@ -176,11 +186,13 @@ struct cbfs_payload {
struct cbfs_payload_segment segments;
};

#define PAYLOAD_SEGMENT_CODE 0x434F4445
#define PAYLOAD_SEGMENT_DATA 0x44415441
#define PAYLOAD_SEGMENT_BSS 0x42535320
#define PAYLOAD_SEGMENT_PARAMS 0x50415241
#define PAYLOAD_SEGMENT_ENTRY 0x454E5452
enum cbfs_payload_segment_type {
PAYLOAD_SEGMENT_CODE = 0x434F4445, /* BE: 'CODE' */
PAYLOAD_SEGMENT_DATA = 0x44415441, /* BE: 'DATA' */
PAYLOAD_SEGMENT_BSS = 0x42535320, /* BE: 'BSS ' */
PAYLOAD_SEGMENT_PARAMS = 0x50415241, /* BE: 'PARA' */
PAYLOAD_SEGMENT_ENTRY = 0x454E5452, /* BE: 'ENTR' */
};

struct cbfs_optionrom {
uint32_t compression;
Expand Down
34 changes: 34 additions & 0 deletions src/commonlib/bsd/include/commonlib/bsd/metadata_hash.h
View file
@@ -0,0 +1,34 @@
/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */

#ifndef _COMMONLIB_BSD_METADATA_HASH_H_
#define _COMMONLIB_BSD_METADATA_HASH_H_

#include <stdint.h>
#include <vb2_sha.h>

/* This structure is embedded somewhere in the (uncompressed) bootblock. */
struct metadata_hash_anchor {
uint8_t magic[8];
struct vb2_hash cbfs_hash;
/* NOTE: This is just reserving space. sizeof(struct vb2_hash) may change between
configurations/versions and cannot be relied upon, so the FMAP hash must be placed
right after the actual data for the particular CBFS hash algorithm used ends. */
uint8_t reserved_space_for_fmap_hash[VB2_MAX_DIGEST_SIZE];
} __packed;

/* Always use this function to figure out the actual location of the FMAP hash. It always uses
the same algorithm as the CBFS hash. */
static inline uint8_t *metadata_hash_anchor_fmap_hash(struct metadata_hash_anchor *anchor)
{
return anchor->cbfs_hash.raw + vb2_digest_size(anchor->cbfs_hash.algo);
}

/*
* Do not use this constant anywhere else in coreboot code to ensure the bit pattern really only
* appears once in the CBFS image. The only coreboot file allowed to use this is
* src/lib/metadata_anchor.c to define the actual anchor data structure. It is defined here so
* that it can be shared with cbfstool (which may use it freely).
*/
#define DO_NOT_USE_METADATA_HASH_ANCHOR_MAGIC_DO_NOT_USE "\xadMdtHsh\x15"

#endif /* _COMMONLIB_BSD_MASTER_HASH_H_ */
2 changes: 1 addition & 1 deletion src/commonlib/cbfs.c
View file
Expand Up @@ -335,7 +335,7 @@ int cbfs_vb2_hash_contents(const struct region_device *cbfs,
if (cbfsf_file_type(fh, &ftype))
return VB2_ERROR_UNKNOWN;

if (ftype == CBFS_TYPE_DELETED || ftype == CBFS_TYPE_DELETED2)
if (ftype == CBFS_TYPE_DELETED || ftype == CBFS_TYPE_NULL)
continue;

rv = cbfs_extend_hash_with_offset(&ctx, cbfs, &fh->data);
Expand Down
1 change: 1 addition & 0 deletions src/commonlib/include/commonlib/cbmem_id.h
View file
Expand Up @@ -26,6 +26,7 @@
#define CBMEM_ID_IGD_OPREGION 0x4f444749
#define CBMEM_ID_IMD_ROOT 0xff4017ff
#define CBMEM_ID_IMD_SMALL 0x53a11439
#define CBMEM_ID_MDATA_HASH 0x6873484D
#define CBMEM_ID_MEMINFO 0x494D454D
#define CBMEM_ID_MMA_DATA 0x4D4D4144
#define CBMEM_ID_MMC_STATUS 0x4d4d4353
Expand Down
14 changes: 14 additions & 0 deletions src/commonlib/include/commonlib/coreboot_tables.h
View file
Expand Up @@ -349,12 +349,26 @@ struct lb_x86_rom_mtrr {
uint32_t index;
};

/* Memory map windows to translate addresses between SPI flash space and host address space. */
struct flash_mmap_window {
uint32_t flash_base;
uint32_t host_base;
uint32_t size;
};

struct lb_spi_flash {
uint32_t tag;
uint32_t size;
uint32_t flash_size;
uint32_t sector_size;
uint32_t erase_cmd;
/*
* Number of mmap windows used by the platform to decode addresses between SPI flash
* space and host address space. This determines the number of entries in mmap_table.
*/

uint32_t mmap_count;
struct flash_mmap_window mmap_table[0];
};

struct lb_boot_media_params {
Expand Down
63 changes: 38 additions & 25 deletions src/commonlib/include/commonlib/region.h
View file
Expand Up @@ -6,6 +6,7 @@
#include <sys/types.h>
#include <stddef.h>
#include <stdbool.h>
#include <commonlib/bsd/helpers.h>
#include <commonlib/mem_pool.h>

/*
Expand Down Expand Up @@ -210,53 +211,65 @@ void mmap_helper_device_init(struct mmap_helper_region_device *mdev,
void *mmap_helper_rdev_mmap(const struct region_device *, size_t, size_t);
int mmap_helper_rdev_munmap(const struct region_device *, void *);

/* A translated region device provides the ability to publish a region device
* in one address space and use an access mechanism within another address
* space. The sub region is the window within the 1st address space and
* the request is modified prior to accessing the second address space
* provided by access_dev. */
struct xlate_region_device {
/*
* A translated region device provides the ability to publish a region device in one address
* space and use an access mechanism within another address space. The sub region is the window
* within the 1st address space and the request is modified prior to accessing the second
* address space provided by access_dev.
*
* Each xlate_region_device can support multiple translation windows described using
* xlate_window structure. The windows need not be contiguous in either address space. However,
* this poses restrictions on the operations being performed i.e. callers cannot perform
* operations across multiple windows of a translated region device. It is possible to support
* readat/writeat/eraseat by translating them into multiple calls one to access device in each
* window. However, mmap support is tricky because the caller expects that the memory mapped
* region is contiguous in both address spaces. Thus, to keep the semantics consistent for all
* region ops, xlate_region_device does not support any operations across the window
* boundary.
*
* Note: The platform is expected to ensure that the fmap description does not place any
* section (that will be operated using the translated region device) across multiple windows.
*/
struct xlate_window {
const struct region_device *access_dev;
struct region sub_region;
};

struct xlate_region_device {
size_t window_count;
const struct xlate_window *window_arr;
struct region_device rdev;
};

extern const struct region_device_ops xlate_rdev_ro_ops;

extern const struct region_device_ops xlate_rdev_rw_ops;

#define XLATE_REGION_DEV_INIT(access_dev_, sub_offset_, sub_size_, \
parent_sz_, ops_) \
#define XLATE_REGION_DEV_INIT(window_arr_, parent_sz_, ops_) \
{ \
.access_dev = access_dev_, \
.sub_region = { \
.offset = (sub_offset_), \
.size = (sub_size_), \
}, \
.window_count = ARRAY_SIZE(window_arr_), \
.window_arr = window_arr_, \
.rdev = REGION_DEV_INIT((ops_), 0, (parent_sz_)), \
}

#define XLATE_REGION_DEV_RO_INIT(access_dev_, sub_offset_, sub_size_, \
parent_sz_) \
XLATE_REGION_DEV_INIT(access_dev_, sub_offset_, \
sub_size_, parent_sz_, &xlate_rdev_ro_ops), \
#define XLATE_REGION_DEV_RO_INIT(window_arr_, parent_sz_) \
XLATE_REGION_DEV_INIT(window_arr_, parent_sz_, &xlate_rdev_ro_ops)

#define XLATE_REGION_DEV_RW_INIT(access_dev_, sub_offset_, sub_size_, \
parent_sz_) \
XLATE_REGION_DEV_INIT(access_dev_, sub_offset_, \
sub_size_, parent_sz_, &xlate_rdev_rw_ops), \
#define XLATE_REGION_DEV_RW_INIT(window_count_, window_arr_, parent_sz_) \
XLATE_REGION_DEV_INIT(window_arr_, parent_sz_, &xlate_rdev_rw_ops)

/* Helper to dynamically initialize xlate region device. */
void xlate_region_device_ro_init(struct xlate_region_device *xdev,
const struct region_device *access_dev,
size_t sub_offset, size_t sub_size,
size_t window_count, const struct xlate_window *window_arr,
size_t parent_size);

void xlate_region_device_rw_init(struct xlate_region_device *xdev,
const struct region_device *access_dev,
size_t sub_offset, size_t sub_size,
size_t window_count, const struct xlate_window *window_arr,
size_t parent_size);

void xlate_window_init(struct xlate_window *window, const struct region_device *access_dev,
size_t sub_region_offset, size_t sub_region_size);

/* This type can be used for incoherent access where the read and write
* operations are backed by separate drivers. An example is x86 systems
* with memory mapped media for reading but use a spi flash driver for
Expand Down
92 changes: 61 additions & 31 deletions src/commonlib/region.c
View file
Expand Up @@ -188,33 +188,37 @@ void region_device_init(struct region_device *rdev,

static void xlate_region_device_init(struct xlate_region_device *xdev,
const struct region_device_ops *ops,
const struct region_device *access_dev,
size_t sub_offset, size_t sub_size,
size_t window_count, const struct xlate_window *window_arr,
size_t parent_size)
{
memset(xdev, 0, sizeof(*xdev));
xdev->access_dev = access_dev;
xdev->sub_region.offset = sub_offset;
xdev->sub_region.size = sub_size;
xdev->window_count = window_count;
xdev->window_arr = window_arr;
region_device_init(&xdev->rdev, ops, 0, parent_size);
}

void xlate_region_device_ro_init(struct xlate_region_device *xdev,
const struct region_device *access_dev,
size_t sub_offset, size_t sub_size,
size_t window_count, const struct xlate_window *window_arr,
size_t parent_size)
{
xlate_region_device_init(xdev, &xlate_rdev_ro_ops, access_dev,
sub_offset, sub_size, parent_size);
xlate_region_device_init(xdev, &xlate_rdev_ro_ops, window_count, window_arr,
parent_size);
}

void xlate_region_device_rw_init(struct xlate_region_device *xdev,
const struct region_device *access_dev,
size_t sub_offset, size_t sub_size,
size_t window_count, const struct xlate_window *window_arr,
size_t parent_size)
{
xlate_region_device_init(xdev, &xlate_rdev_rw_ops, access_dev,
sub_offset, sub_size, parent_size);
xlate_region_device_init(xdev, &xlate_rdev_rw_ops, window_count, window_arr,
parent_size);
}

void xlate_window_init(struct xlate_window *window, const struct region_device *access_dev,
size_t sub_region_offset, size_t sub_region_size)
{
window->access_dev = access_dev;
window->sub_region.offset = sub_region_offset;
window->sub_region.size = sub_region_size;
}

static void *mdev_mmap(const struct region_device *rd, size_t offset,
Expand Down Expand Up @@ -321,6 +325,21 @@ int mmap_helper_rdev_munmap(const struct region_device *rd, void *mapping)
return 0;
}

static const struct xlate_window *xlate_find_window(const struct xlate_region_device *xldev,
const struct region *req)
{
size_t i;
const struct xlate_window *xlwindow;

for (i = 0; i < xldev->window_count; i++) {
xlwindow = &xldev->window_arr[i];
if (region_is_subregion(&xlwindow->sub_region, req))
return xlwindow;
}

return NULL;
}

static void *xlate_mmap(const struct region_device *rd, size_t offset,
size_t size)
{
Expand All @@ -329,24 +348,29 @@ static void *xlate_mmap(const struct region_device *rd, size_t offset,
.offset = offset,
.size = size,
};
const struct xlate_window *xlwindow;

xldev = container_of(rd, __typeof__(*xldev), rdev);

if (!region_is_subregion(&xldev->sub_region, &req))
xlwindow = xlate_find_window(xldev, &req);
if (!xlwindow)
return NULL;

offset -= region_offset(&xldev->sub_region);
offset -= region_offset(&xlwindow->sub_region);

return rdev_mmap(xldev->access_dev, offset, size);
return rdev_mmap(xlwindow->access_dev, offset, size);
}

static int xlate_munmap(const struct region_device *rd, void *mapping)
static int xlate_munmap(const struct region_device *rd __unused, void *mapping __unused)
{
const struct xlate_region_device *xldev;

xldev = container_of(rd, __typeof__(*xldev), rdev);

return rdev_munmap(xldev->access_dev, mapping);
/*
* xlate_region_device does not keep track of the access device that was used to service
* a mmap request. So, munmap does not do anything. If munmap functionality is required,
* then xlate_region_device will have to be updated to accept some pre-allocated space
* from caller to keep track of the mapping requests. Since xlate_region_device is only
* used for memory mapped boot media on the backend right now, skipping munmap is fine.
*/
return 0;
}

static ssize_t xlate_readat(const struct region_device *rd, void *b,
Expand All @@ -356,16 +380,18 @@ static ssize_t xlate_readat(const struct region_device *rd, void *b,
.offset = offset,
.size = size,
};
const struct xlate_window *xlwindow;
const struct xlate_region_device *xldev;

xldev = container_of(rd, __typeof__(*xldev), rdev);

if (!region_is_subregion(&xldev->sub_region, &req))
xlwindow = xlate_find_window(xldev, &req);
if (!xlwindow)
return -1;

offset -= region_offset(&xldev->sub_region);
offset -= region_offset(&xlwindow->sub_region);

return rdev_readat(xldev->access_dev, b, offset, size);
return rdev_readat(xlwindow->access_dev, b, offset, size);
}

static ssize_t xlate_writeat(const struct region_device *rd, const void *b,
Expand All @@ -375,16 +401,18 @@ static ssize_t xlate_writeat(const struct region_device *rd, const void *b,
.offset = offset,
.size = size,
};
const struct xlate_window *xlwindow;
const struct xlate_region_device *xldev;

xldev = container_of(rd, __typeof__(*xldev), rdev);

if (!region_is_subregion(&xldev->sub_region, &req))
xlwindow = xlate_find_window(xldev, &req);
if (!xlwindow)
return -1;

offset -= region_offset(&xldev->sub_region);
offset -= region_offset(&xlwindow->sub_region);

return rdev_writeat(xldev->access_dev, b, offset, size);
return rdev_writeat(xlwindow->access_dev, b, offset, size);
}

static ssize_t xlate_eraseat(const struct region_device *rd,
Expand All @@ -394,16 +422,18 @@ static ssize_t xlate_eraseat(const struct region_device *rd,
.offset = offset,
.size = size,
};
const struct xlate_window *xlwindow;
const struct xlate_region_device *xldev;

xldev = container_of(rd, __typeof__(*xldev), rdev);

if (!region_is_subregion(&xldev->sub_region, &req))
xlwindow = xlate_find_window(xldev, &req);
if (!xlwindow)
return -1;

offset -= region_offset(&xldev->sub_region);
offset -= region_offset(&xlwindow->sub_region);

return rdev_eraseat(xldev->access_dev, offset, size);
return rdev_eraseat(xlwindow->access_dev, offset, size);
}

const struct region_device_ops xlate_rdev_ro_ops = {
Expand Down
3 changes: 0 additions & 3 deletions src/console/printk.c
View file
Expand Up @@ -10,7 +10,6 @@
#include <console/vtxprintf.h>
#include <smp/spinlock.h>
#include <smp/node.h>
#include <trace.h>
#include <timer.h>

DECLARE_SPIN_LOCK(console_lock)
Expand Down Expand Up @@ -81,7 +80,6 @@ int do_vprintk(int msg_level, const char *fmt, va_list args)
if (log_this < CONSOLE_LOG_FAST)
return 0;

DISABLE_TRACE;
spin_lock(&console_lock);

console_time_run();
Expand All @@ -96,7 +94,6 @@ int do_vprintk(int msg_level, const char *fmt, va_list args)
console_time_stop();

spin_unlock(&console_lock);
ENABLE_TRACE;

return i;
}
Expand Down
5 changes: 0 additions & 5 deletions src/console/vsprintf.c
View file
Expand Up @@ -2,7 +2,6 @@

#include <console/vtxprintf.h>
#include <string.h>
#include <trace.h>

struct vsnprintf_context {
char *str_buf;
Expand All @@ -24,16 +23,12 @@ int vsnprintf(char *buf, size_t size, const char *fmt, va_list args)
int i;
struct vsnprintf_context ctx;

DISABLE_TRACE;

ctx.str_buf = buf;
ctx.buf_limit = size ? size - 1 : 0;
i = vtxprintf(str_tx_byte, fmt, args, &ctx);
if (size)
*ctx.str_buf = '\0';

ENABLE_TRACE;

return i;
}

Expand Down
3 changes: 1 addition & 2 deletions src/cpu/amd/pi/00730F01/update_microcode.c
View file
Expand Up @@ -115,8 +115,7 @@ void amd_update_microcode_from_cbfs(void)
size_t ucode_len;
uint16_t equivalent_processor_rev_id = get_equivalent_processor_rev_id();

ucode = cbfs_boot_map_with_leak("cpu_microcode_blob.bin",
CBFS_TYPE_MICROCODE, &ucode_len);
ucode = cbfs_map("cpu_microcode_blob.bin", &ucode_len);
if (!ucode) {
printk(BIOS_WARNING, "cpu_microcode_blob.bin not found. Skipping updates.\n");
return;
Expand Down
28 changes: 28 additions & 0 deletions src/cpu/intel/fit/Makefile.inc
View file
@@ -1 +1,29 @@
bootblock-y += fit.S

FIT_ENTRY=$(call strip_quotes, $(CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG))

ifneq ($(CONFIG_UPDATE_IMAGE),y) # never update the bootblock

ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE),y)

INTERMEDIATE+=add_mcu_fit
add_mcu_fit: $(obj)/coreboot.pre $(IFITTOOL)
@printf " UPDATE-FIT Microcode\n"
$(IFITTOOL) -f $< -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -r COREBOOT

# Second FIT in TOP_SWAP bootblock
ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y)

INTERMEDIATE+=add_ts_mcu_fit
add_ts_mcu_fit: $(obj)/coreboot.pre $(IFITTOOL)
@printf " UPDATE-FIT Top Swap: Microcode\n"
ifneq ($(FIT_ENTRY),)
$(IFITTOOL) -f $< -A -n $(FIT_ENTRY) -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) $(TS_OPTIONS) -r COREBOOT
endif # FIT_ENTRY
$(IFITTOOL) -f $< -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) $(TS_OPTIONS) -r COREBOOT

endif # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK

endif # CONFIG_CPU_MICROCODE_CBFS_NONE

endif # CONFIG_UPDATE_IMAGE
2 changes: 0 additions & 2 deletions src/cpu/intel/fit/fit.S
View file
Expand Up @@ -6,7 +6,6 @@
fit_pointer:
.long fit_table
.long 0
.previous

.section .text
.align 16
Expand All @@ -29,4 +28,3 @@ fit_table:
.byte 0x7d
.fill CONFIG_CPU_INTEL_NUM_FIT_ENTRIES*16
fit_table_end:
.previous
8 changes: 0 additions & 8 deletions src/cpu/intel/fit/fit.ld
View file

This file was deleted.

4 changes: 1 addition & 3 deletions src/cpu/intel/microcode/microcode.c
View file
Expand Up @@ -126,9 +126,7 @@ const void *intel_microcode_find(void)
unsigned int x86_model, x86_family;
msr_t msr;

ucode_updates = cbfs_boot_map_with_leak(MICROCODE_CBFS_FILE,
CBFS_TYPE_MICROCODE,
&microcode_len);
ucode_updates = cbfs_map(MICROCODE_CBFS_FILE, &microcode_len);
if (ucode_updates == NULL)
return NULL;

Expand Down
1 change: 1 addition & 0 deletions src/cpu/intel/microcode/microcode_asm.S
View file
Expand Up @@ -43,6 +43,7 @@
* if the revision of the update is newer than what is installed
*/

.code32
.section .text
.global update_bsp_microcode

Expand Down
6 changes: 6 additions & 0 deletions src/cpu/intel/model_206ax/model_206ax.h
View file
Expand Up @@ -3,6 +3,7 @@
#ifndef _CPU_INTEL_MODEL_206AX_H
#define _CPU_INTEL_MODEL_206AX_H

#include <arch/cpu.h>
#include <stdint.h>

/* SandyBridge/IvyBridge bus clock is fixed at 100MHz */
Expand Down Expand Up @@ -88,4 +89,9 @@ void set_power_limits(u8 power_limit_1_time);
int cpu_config_tdp_levels(void);
int get_platform_id(void);

static inline u8 cpu_stepping(void)
{
return cpuid_eax(1) & 0xf;
}

#endif
40 changes: 39 additions & 1 deletion src/cpu/qemu-x86/Kconfig
View file
Expand Up @@ -5,10 +5,48 @@ config CPU_QEMU_X86
select UDELAY_TSC
select TSC_MONOTONIC_TIMER
select UNKNOWN_TSC_RATE
select SMM_ASEG

if CPU_QEMU_X86

# coreboot i440fx does not support SMM
choice
prompt "AP init"
default CPU_QEMU_X86_LAPIC_INIT

config CPU_QEMU_X86_LAPIC_INIT
bool "Legacy serial LAPIC init"

config CPU_QEMU_X86_PARALLEL_MP
bool "Parallel MP init"
select PARALLEL_MP

endchoice

choice
prompt "SMM support"
default CPU_QEMU_X86_ASEG_SMM
depends on BOARD_EMULATION_QEMU_X86_Q35

config CPU_QEMU_X86_NO_SMM
bool "No SMM"
select NO_SMM

config CPU_QEMU_X86_ASEG_SMM
bool "SMM in ASEG"
depends on !PARALLEL_MP
select SMM_ASEG

#config CPU_QEMU_X86_TSEG_SMM
# bool "SMM in TSEG"
# select SMM_TSEG

endchoice

config MAX_CPUS
int
default 4 if SMM_ASEG
default 32

config CPU_QEMU_X86_64
bool "Experimental 64bit support"
select ARCH_ALL_STAGES_X86_64
Expand Down
15 changes: 4 additions & 11 deletions src/cpu/x86/16bit/entry16.inc
View file
Expand Up @@ -108,7 +108,7 @@ _start16bit:
movw $nullidt_offset, %bx
subw %ax, %bx
lidt %cs:(%bx)
movw $gdtptr16_offset, %bx
movw $gdtptr_offset, %bx
subw %ax, %bx
lgdtl %cs:(%bx)

Expand All @@ -124,22 +124,15 @@ _start16bit:
ljmpl $ROM_CODE_SEG, $__protected_start

/**
* The gdt is defined in entry32.inc, it has a 4 Gb code segment
* The gdt is defined in gdt_init.S, it has a 4 Gb code segment
* at 0x08, and a 4 GB data segment at 0x10;
*/
.align 4
.globl gdtptr16
gdtptr16:
.word gdt_end - gdt -1 /* compute the table limit */
.long gdt /* we know the offset */
__gdtptr:
.long gdtptr

.align 4
.globl nullidt
nullidt:
.word 0 /* limit */
.long 0
.word 0

.globl _estart16bit
_estart16bit:
.code32
12 changes: 0 additions & 12 deletions src/cpu/x86/16bit/entry16.ld
View file

This file was deleted.

18 changes: 0 additions & 18 deletions src/cpu/x86/16bit/reset16.ld
View file

This file was deleted.

21 changes: 1 addition & 20 deletions src/cpu/x86/32bit/entry32.inc
View file
Expand Up @@ -4,33 +4,14 @@

#include <arch/rom_segs.h>
#include <cpu/x86/post_code.h>
#include <arch/x86/gdt_init.S>

.code32
/*
* When we come here we are in protected mode. We expand
* the stack and copies the data segment from ROM to the
* memory.
*
* After that, we call the chipset bootstrap routine that
* does what is left of the chipset initialization.
*
* When we come here we are in protected mode.
* NOTE aligned to 4 so that we are sure that the prefetch
* cache will be reloaded.
*
* In the bootblock there is already a ljmp to __protected_start and
* the reset vector jumps to symbol _start16bit in entry16.inc from
* the reset vectors's symbol which is _start. Therefore, don't
* expose the _start symbol for bootblock.
*/
.align 4
#if !ENV_BOOTBLOCK
.globl _start
_start:
#endif

lgdt %cs:gdtptr
ljmp $ROM_CODE_SEG, $__protected_start

__protected_start:
/* Save the BIST value */
Expand Down
10 changes: 10 additions & 0 deletions src/cpu/x86/64bit/entry64.inc
View file
Expand Up @@ -16,7 +16,12 @@
#endif

#include <cpu/x86/msr.h>
#if defined(__RAMSTAGE__)
#include <arch/ram_segs.h>
#else
#include <arch/rom_segs.h>
#endif


setup_longmode:
/* Get page table address */
Expand All @@ -42,7 +47,12 @@ setup_longmode:
movl %eax, %cr0

/* use long jump to switch to 64-bit code segment */
#if defined(__RAMSTAGE__)
ljmp $RAM_CODE_SEG64, $__longmode_start
#else
ljmp $ROM_CODE_SEG64, $__longmode_start

#endif
.code64
__longmode_start:

Expand Down
3 changes: 2 additions & 1 deletion src/cpu/x86/64bit/exit32.inc
View file
Expand Up @@ -23,9 +23,10 @@
#endif

drop_longmode:
#if !ENV_CACHE_AS_RAM
/* Ensure cache is clean. */
wbinvd

#endif
/* Set 32-bit code segment and ss */
mov $CODE_SEG, %rcx
/* SetCodeSelector32 will drop us to protected mode on return */
Expand Down
70 changes: 70 additions & 0 deletions src/cpu/x86/64bit/mode_switch.S
View file
@@ -0,0 +1,70 @@
/* SPDX-License-Identifier: GPL-2.0-only */

.text
.code64
.section ".text.protected_mode_call", "ax", @progbits
.globl protected_mode_call_narg
protected_mode_call_narg:

push %rbp
mov %rsp, %rbp
/* Preserve registers */
push %rbx
push %r12
push %r13
push %r14
push %r15

/* Arguments to stack */
push %rdi
push %rsi
push %rdx
push %rcx

#include <cpu/x86/64bit/exit32.inc>

movl -48(%ebp), %eax /* Argument count */
movl -64(%ebp), %edx /* Argument 0 */
movl -72(%ebp), %ecx /* Argument 1 */

/* Align the stack */
andl $0xFFFFFFF0, %esp
test %eax, %eax
je 1f /* Zero arguments */

subl $1, %eax
test %eax, %eax
je 2f /* One argument */

/* Two arguments */
subl $8, %esp
pushl %ecx /* Argument 1 */
pushl %edx /* Argument 0 */
jmp 1f
2:
subl $12, %esp
pushl %edx /* Argument 0 */

1:
movl -56(%ebp), %ebx /* Function to call */
call *%ebx
movl %eax, %ebx

/* Preserves ebx */
#include <cpu/x86/64bit/entry64.inc>

/* Place return value in rax */
movl %ebx, %eax

/* Restore registers */
mov -40(%rbp), %r15
mov -32(%rbp), %r14
mov -24(%rbp), %r13
mov -16(%rbp), %r12
mov -8(%rbp), %rbx

/* Restore stack pointer */
mov %rbp, %rsp
pop %rbp

ret
3 changes: 3 additions & 0 deletions src/cpu/x86/Makefile.inc
View file
@@ -1,4 +1,7 @@
subdirs-y += pae

all-$(CONFIG_ARCH_ALL_STAGES_X86_64) += 64bit/mode_switch.S

subdirs-$(CONFIG_PARALLEL_MP) += name
ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c
ramstage-y += backup_default_smm.c
Expand Down
1 change: 1 addition & 0 deletions src/cpu/x86/early_reset.S
View file
Expand Up @@ -7,6 +7,7 @@

#include <cpu/x86/mtrr.h>

.code32
.section .text
.global check_mtrr

Expand Down
13 changes: 13 additions & 0 deletions src/cpu/x86/lapic/secondary.S
View file
Expand Up @@ -33,7 +33,11 @@ _secondary_start:
_secondary_gdt_addr:
gdtaddr:
.word 0 /* the table limit */
#if ENV_X86_64
.quad 0
#else
.long 0 /* we know the offset */
#endif

_secondary_start_end:

Expand All @@ -54,14 +58,23 @@ __ap_protected_start:
/* Load the Interrupt descriptor table */
lidt idtarg

#if ENV_X86_64
/* entry64.inc preserves ebx. */
#include <cpu/x86/64bit/entry64.inc>
mov secondary_stack, %rsp
andl $0xfffffff0, %esp
mov secondary_cpu_index, %rdi
#else
/* Set the stack pointer, and flag that we are done */
xorl %eax, %eax
movl secondary_stack, %esp

andl $0xfffffff0, %esp
sub $12, %esp /* maintain 16-byte alignment for the call below */
movl secondary_cpu_index, %edi
pushl %edi
movl %eax, secondary_stack
#endif

call secondary_cpu_init
1: hlt
Expand Down
15 changes: 15 additions & 0 deletions src/cpu/x86/sipi_vector.S
View file
Expand Up @@ -5,6 +5,8 @@
#include <cpu/x86/msr.h>
#include <arch/ram_segs.h>

#define __RAMSTAGE__

/* The SIPI vector is responsible for initializing the APs in the system. It
* loads microcode, sets up MSRs, and enables caching before calling into
* C code. */
Expand Down Expand Up @@ -192,11 +194,24 @@ load_msr:
mov %eax, %cr4
#endif

#ifdef __x86_64__
/* entry64.inc preserves ebx. */
#include <cpu/x86/64bit/entry64.inc>

mov %rsi, %rdi /* cpu_num */

movl c_handler, %eax
call *%rax
#else
/* c_handler(cpu_num), preserve proper stack alignment */
sub $12, %esp
push %esi /* cpu_num */

mov c_handler, %eax
call *%eax
#endif


halt_jump:
hlt
jmp halt_jump
14 changes: 7 additions & 7 deletions src/cpu/x86/smm/smm_module_loaderv2.c
View file
Expand Up @@ -221,7 +221,7 @@ u32 smm_get_cpu_smbase(unsigned int cpu_num)
*/

static int smm_place_entry_code(uintptr_t smbase, unsigned int num_cpus,
unsigned int stack_top, const struct smm_loader_params *params)
uintptr_t stack_top, const struct smm_loader_params *params)
{
unsigned int i;
unsigned int size;
Expand All @@ -235,7 +235,7 @@ static int smm_place_entry_code(uintptr_t smbase, unsigned int num_cpus,
if (cpus[num_cpus - 1].smbase +
params->smm_main_entry_offset < stack_top) {
printk(BIOS_ERR, "%s: stack encroachment\n", __func__);
printk(BIOS_ERR, "%s: smbase %zx, stack_top %x\n",
printk(BIOS_ERR, "%s: smbase %zx, stack_top %lx\n",
__func__, cpus[num_cpus].smbase, stack_top);
return 0;
}
Expand All @@ -245,7 +245,7 @@ static int smm_place_entry_code(uintptr_t smbase, unsigned int num_cpus,
return 0;
}

printk(BIOS_INFO, "%s: smbase %zx, stack_top %x\n",
printk(BIOS_INFO, "%s: smbase %zx, stack_top %lx\n",
__func__, cpus[num_cpus-1].smbase, stack_top);

/* start at 1, the first CPU stub code is already there */
Expand Down Expand Up @@ -311,9 +311,9 @@ static int smm_stub_place_staggered_entry_points(char *base,
* sets up the stack, and then jumps to common SMI handler
*/
if (params->num_concurrent_save_states > 1 || stub_entry_offset != 0) {
rc = smm_place_entry_code((unsigned int)base,
params->num_concurrent_save_states,
(unsigned int)params->stack_top, params);
rc = smm_place_entry_code((uintptr_t)base,
params->num_concurrent_save_states,
(uintptr_t)params->stack_top, params);
}
return rc;
}
Expand Down Expand Up @@ -384,7 +384,7 @@ static int smm_module_setup_stub(void *smbase, size_t smm_size,
/* The save state size encroached over the first SMM entry point. */
if (size <= params->smm_main_entry_offset) {
printk(BIOS_ERR, "%s: encroachment over SMM entry point\n", __func__);
printk(BIOS_ERR, "%s: state save size: %zx : smm_entry_offset -> %x\n",
printk(BIOS_ERR, "%s: state save size: %zx : smm_entry_offset -> %lx\n",
__func__, size, params->smm_main_entry_offset);
return -1;
}
Expand Down
5 changes: 4 additions & 1 deletion src/cpu/x86/smm/smm_stub.S
View file
Expand Up @@ -91,7 +91,7 @@ smm_relocate_gdt:

/* gdt selector 0x18, flat code segment (64-bit) */
.word 0xffff, 0x0000
.byte 0x00, 0x9b, 0xcf, 0x00
.byte 0x00, 0x9b, 0xaf, 0x00

/* gdt selector 0x20 tss segment */
.word 0xffff, 0x0000
Expand Down Expand Up @@ -144,6 +144,9 @@ smm_trampoline32:
movl stack_size, %eax
subl %eax, %ebx /* %ebx(stack_top) - size = %ebx(stack_bottom) */
movl %ebx, (%ebx)
#if ENV_X86_64
movl $0, 4(%ebx)
#endif

/* Create stack frame by pushing a NULL stack base pointer */
pushl $0x0
Expand Down
2 changes: 1 addition & 1 deletion src/device/Makefile.inc
View file
Expand Up @@ -8,7 +8,7 @@ ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_64) += pnp_device.c
ramstage-y += smbus_ops.c

ifeq ($(CONFIG_AZALIA_PLUGIN_SUPPORT),y)
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/hda_verb.c)
endif

bootblock-y += device_const.c
Expand Down
66 changes: 49 additions & 17 deletions src/device/azalia_device.c
View file
Expand Up @@ -7,7 +7,7 @@
#include <device/mmio.h>
#include <delay.h>

static int set_bits(void *port, u32 mask, u32 val)
int azalia_set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
Expand All @@ -34,13 +34,24 @@ static int set_bits(void *port, u32 mask, u32 val)
return 0;
}

int azalia_enter_reset(u8 *base)
{
/* Set bit 0 to 0 to enter reset state (BAR + 0x8)[0] */
return azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0);
}

int azalia_exit_reset(u8 *base)
{
/* Set bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
return azalia_set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST);
}

static int codec_detect(u8 *base)
{
u32 reg32;
int count;

/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0)
if (azalia_exit_reset(base) < 0)
goto no_codec;

/* clear STATESTS bits (BAR + 0xe)[2:0] */
Expand All @@ -61,12 +72,10 @@ static int codec_detect(u8 *base)
if (!count)
goto no_codec;

/* Set Bit 0 to 0 to enter reset state (BAR + 0x8)[0] */
if (set_bits(base + HDA_GCTL_REG, 1, 0) < 0)
if (azalia_enter_reset(base) < 0)
goto no_codec;

/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
if (set_bits(base + HDA_GCTL_REG, 1, HDA_GCTL_CRST) < 0)
if (azalia_exit_reset(base) < 0)
goto no_codec;

/* Read in Codec location (BAR + 0xe)[2..0] */
Expand All @@ -80,25 +89,48 @@ static int codec_detect(u8 *base)
no_codec:
/* Codec Not found */
/* Put HDA back in reset (BAR + 0x8) [0] */
set_bits(base + HDA_GCTL_REG, 1, 0);
azalia_set_bits(base + HDA_GCTL_REG, 1, 0);
printk(BIOS_DEBUG, "azalia_audio: No codec!\n");
return 0;
}

static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb)
/*
* Find a specific entry within a verb table
*
* @param verb_table: verb table data
* @param verb_table_bytes: verb table size in bytes
* @param viddid: vendor/device to search for
* @param verb: pointer to entry within table
*
* Returns size of the entry within the verb table,
* Returns 0 if the entry is not found
*
* The HDA verb table is composed of dwords. A set of 4 dwords is
* grouped together to form a "jack" descriptor.
* Bits 31:28 - Codec Address
* Bits 27:20 - NID
* Bits 19:8 - Verb ID
* Bits 7:0 - Payload
*
* coreboot groups different codec verb tables into a single table
* and prefixes each with a specific header consisting of 3
* dword entries:
* 1 - Codec Vendor/Device ID
* 2 - Subsystem ID
* 3 - Number of jacks (groups of 4 dwords) for this codec
*/
u32 azalia_find_verb(const u32 *verb_table, u32 verb_table_bytes, u32 viddid, const u32 **verb)
{
printk(BIOS_DEBUG, "azalia_audio: dev=%s\n", dev_path(dev));
printk(BIOS_DEBUG, "azalia_audio: Reading viddid=%x\n", viddid);

int idx = 0;

while (idx < (cim_verb_data_size / sizeof(u32))) {
u32 verb_size = 4 * cim_verb_data[idx + 2]; // in u32
if (cim_verb_data[idx] != viddid) {
while (idx < (verb_table_bytes / sizeof(u32))) {
/* Header contains the number of jacks, aka groups of 4 dwords */
u32 verb_size = 4 * verb_table[idx + 2];
if (verb_table[idx] != viddid) {
idx += verb_size + 3; // skip verb + header
continue;
}
*verb = &cim_verb_data[idx + 3];
*verb = &verb_table[idx + 3];
return verb_size;
}

Expand Down Expand Up @@ -182,7 +214,7 @@ static void codec_init(struct device *dev, u8 *base, int addr)
/* 2 */
reg32 = read32(base + HDA_IR_REG);
printk(BIOS_DEBUG, "azalia_audio: codec viddid: %08x\n", reg32);
verb_size = find_verb(dev, reg32, &verb);
verb_size = azalia_find_verb(cim_verb_data, cim_verb_data_size, reg32, &verb);

if (!verb_size) {
printk(BIOS_DEBUG, "azalia_audio: No verb!\n");
Expand Down
52 changes: 19 additions & 33 deletions src/device/oprom/realmode/x86.c
View file
Expand Up @@ -12,6 +12,7 @@
#include <pc80/i8254.h>
#include <string.h>
#include <vbe.h>
#include <framebuffer_info.h>

/* we use x86emu's register file representation */
#include <x86emu/regs.h>
Expand Down Expand Up @@ -208,11 +209,6 @@ static void setup_realmode_idt(void)
static vbe_mode_info_t mode_info;
static int mode_info_valid;

static int vbe_mode_info_valid(void)
{
return mode_info_valid;
}

const vbe_mode_info_t *vbe_mode_info(void)
{
if (!mode_info_valid || !mode_info.vesa.phys_base_ptr)
Expand Down Expand Up @@ -351,6 +347,24 @@ void vbe_set_graphics(void)
}

vbe_set_mode(&mode_info);
const struct lb_framebuffer fb = {
.physical_address = mode_info.vesa.phys_base_ptr,
.x_resolution = le16_to_cpu(mode_info.vesa.x_resolution),
.y_resolution = le16_to_cpu(mode_info.vesa.y_resolution),
.bytes_per_line = le16_to_cpu(mode_info.vesa.bytes_per_scanline),
.bits_per_pixel = mode_info.vesa.bits_per_pixel,
.red_mask_pos = mode_info.vesa.red_mask_pos,
.red_mask_size = mode_info.vesa.red_mask_size,
.green_mask_pos = mode_info.vesa.green_mask_pos,
.green_mask_size = mode_info.vesa.green_mask_size,
.blue_mask_pos = mode_info.vesa.blue_mask_pos,
.blue_mask_size = mode_info.vesa.blue_mask_size,
.reserved_mask_pos = mode_info.vesa.reserved_mask_pos,
.reserved_mask_size = mode_info.vesa.reserved_mask_size,
.orientation = LB_FB_ORIENTATION_NORMAL,
};

fb_add_framebuffer_info_ex(&fb);
}

void vbe_textmode_console(void)
Expand All @@ -362,34 +376,6 @@ void vbe_textmode_console(void)
die("\nError: In %s function\n", __func__);
}

int fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
{
if (!vbe_mode_info_valid())
return -1;

framebuffer->physical_address = mode_info.vesa.phys_base_ptr;

framebuffer->x_resolution = le16_to_cpu(mode_info.vesa.x_resolution);
framebuffer->y_resolution = le16_to_cpu(mode_info.vesa.y_resolution);
framebuffer->bytes_per_line =
le16_to_cpu(mode_info.vesa.bytes_per_scanline);
framebuffer->bits_per_pixel = mode_info.vesa.bits_per_pixel;

framebuffer->red_mask_pos = mode_info.vesa.red_mask_pos;
framebuffer->red_mask_size = mode_info.vesa.red_mask_size;

framebuffer->green_mask_pos = mode_info.vesa.green_mask_pos;
framebuffer->green_mask_size = mode_info.vesa.green_mask_size;

framebuffer->blue_mask_pos = mode_info.vesa.blue_mask_pos;
framebuffer->blue_mask_size = mode_info.vesa.blue_mask_size;

framebuffer->reserved_mask_pos = mode_info.vesa.reserved_mask_pos;
framebuffer->reserved_mask_size = mode_info.vesa.reserved_mask_size;

return 0;
}

#endif

void run_bios(struct device *dev, unsigned long addr)
Expand Down
50 changes: 19 additions & 31 deletions src/device/oprom/yabel/vbe.c
View file
Expand Up @@ -33,6 +33,7 @@
*****************************************************************************/

#include <boot/coreboot_tables.h>
#include <framebuffer_info.h>
#include <string.h>
#include <types.h>

Expand Down Expand Up @@ -163,11 +164,6 @@ vbe_info(vbe_info_t * info)

static int mode_info_valid;

static int vbe_mode_info_valid(void)
{
return mode_info_valid;
}

// VBE Function 01h
static u8
vbe_get_mode_info(vbe_mode_info_t * mode_info)
Expand Down Expand Up @@ -747,33 +743,25 @@ void vbe_set_graphics(void)
mode_info.video_mode = (1 << 14) | CONFIG_FRAMEBUFFER_VESA_MODE;
vbe_get_mode_info(&mode_info);
vbe_set_mode(&mode_info);
}

int fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
{
if (!vbe_mode_info_valid())
return -1;

framebuffer->physical_address = le32_to_cpu(mode_info.vesa.phys_base_ptr);

framebuffer->x_resolution = le16_to_cpu(mode_info.vesa.x_resolution);
framebuffer->y_resolution = le16_to_cpu(mode_info.vesa.y_resolution);
framebuffer->bytes_per_line = le16_to_cpu(mode_info.vesa.bytes_per_scanline);
framebuffer->bits_per_pixel = mode_info.vesa.bits_per_pixel;

framebuffer->red_mask_pos = mode_info.vesa.red_mask_pos;
framebuffer->red_mask_size = mode_info.vesa.red_mask_size;

framebuffer->green_mask_pos = mode_info.vesa.green_mask_pos;
framebuffer->green_mask_size = mode_info.vesa.green_mask_size;

framebuffer->blue_mask_pos = mode_info.vesa.blue_mask_pos;
framebuffer->blue_mask_size = mode_info.vesa.blue_mask_size;

framebuffer->reserved_mask_pos = mode_info.vesa.reserved_mask_pos;
framebuffer->reserved_mask_size = mode_info.vesa.reserved_mask_size;

return 0;
const struct lb_framebuffer fb = {
.physical_address = mode_info.vesa.phys_base_ptr,
.x_resolution = le16_to_cpu(mode_info.vesa.x_resolution),
.y_resolution = le16_to_cpu(mode_info.vesa.y_resolution),
.bytes_per_line = le16_to_cpu(mode_info.vesa.bytes_per_scanline),
.bits_per_pixel = mode_info.vesa.bits_per_pixel,
.red_mask_pos = mode_info.vesa.red_mask_pos,
.red_mask_size = mode_info.vesa.red_mask_size,
.green_mask_pos = mode_info.vesa.green_mask_pos,
.green_mask_size = mode_info.vesa.green_mask_size,
.blue_mask_pos = mode_info.vesa.blue_mask_pos,
.blue_mask_size = mode_info.vesa.blue_mask_size,
.reserved_mask_pos = mode_info.vesa.reserved_mask_pos,
.reserved_mask_size = mode_info.vesa.reserved_mask_size,
.orientation = LB_FB_ORIENTATION_NORMAL,
};

fb_add_framebuffer_info_ex(&fb);
}

void vbe_textmode_console(void)
Expand Down
4 changes: 1 addition & 3 deletions src/drivers/amd/agesa/def_callouts.c
View file
Expand Up @@ -121,9 +121,7 @@ AGESA_STATUS agesa_RunFuncOnAp (UINT32 Func, UINTN Data, VOID *ConfigPtr)
AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINTN FchData, VOID *ConfigPrt)
{
GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt;
pVbiosImageInfo->ImagePtr = cbfs_boot_map_with_leak(
"pci"CONFIG_VGA_BIOS_ID".rom",
CBFS_TYPE_OPTIONROM, NULL);
pVbiosImageInfo->ImagePtr = cbfs_map("pci"CONFIG_VGA_BIOS_ID".rom", NULL);
/* printk(BIOS_DEBUG, "IMGptr=%x\n", pVbiosImageInfo->ImagePtr); */
return pVbiosImageInfo->ImagePtr == NULL ? AGESA_WARNING : AGESA_SUCCESS;
}
Expand Down
3 changes: 1 addition & 2 deletions src/drivers/amd/agesa/state_machine.c
View file
Expand Up @@ -30,8 +30,7 @@ static void agesa_locate_image(AMD_CONFIG_PARAMS *StdHeader)
const void *agesa, *image;
size_t file_size;

agesa = cbfs_boot_map_with_leak((const char *)CONFIG_AGESA_CBFS_NAME,
CBFS_TYPE_RAW, &file_size);
agesa = cbfs_map((const char *)CONFIG_AGESA_CBFS_NAME, &file_size);
if (agesa == NULL)
return;

Expand Down
9 changes: 5 additions & 4 deletions src/drivers/aspeed/common/ast_mode_corebootfb.c
View file
Expand Up @@ -6,6 +6,7 @@
#include <console/console.h>
#include <edid.h>
#include <device/pci_def.h>
#include <framebuffer_info.h>

#include "ast_drv.h"

Expand All @@ -32,7 +33,7 @@ int ast_crtc_do_set_base(struct drm_crtc *crtc)
return -ENOMEM;
}

fb->mmio_addr = (u32)res2mmio(res, 4095, 4095);
fb->mmio_addr = (uintptr_t)res2mmio(res, 4095, 4095);

ast_set_offset_reg(crtc);
ast_set_start_address_crt1(ast, fb->mmio_addr);
Expand Down Expand Up @@ -200,7 +201,7 @@ int ast_driver_framebuffer_init(struct drm_device *dev, int flags)
return ret;
}

/* Updated edid for set_vbe_mode_info_valid */
/* Updated edid for fb_fill_framebuffer_info */
edid.x_resolution = edid.mode.ha;
edid.y_resolution = edid.mode.va;
edid.framebuffer_bits_per_pixel = format.cpp[0] * 8;
Expand All @@ -227,10 +228,10 @@ int ast_driver_framebuffer_init(struct drm_device *dev, int flags)
ast_hide_cursor(&crtc);

/* Advertise new mode */
set_vbe_mode_info_valid(&edid, fb.mmio_addr);
fb_new_framebuffer_info_from_edid(&edid, fb.mmio_addr);

/* Clear display */
memset((void *)fb.mmio_addr, 0, edid.bytes_per_line * edid.y_resolution);
memset((void *)(uintptr_t)fb.mmio_addr, 0, edid.bytes_per_line * edid.y_resolution);

return 0;
}
5 changes: 3 additions & 2 deletions src/drivers/crb/tpm.c
View file
Expand Up @@ -43,10 +43,11 @@ static void crb_readControlArea(void)
control_area.cancel = read32(CRB_REG(cur_loc, CRB_REG_CANCEL));
control_area.interrupt_control = read64(CRB_REG(cur_loc, CRB_REG_INT_CTRL));
control_area.command_size = read32(CRB_REG(cur_loc, CRB_REG_CMD_SIZE));
control_area.command_bfr = (void *)(uint32_t)read64(CRB_REG(cur_loc, CRB_REG_CMD_ADDR));
control_area.command_bfr =
(void *)(uintptr_t)read64(CRB_REG(cur_loc, CRB_REG_CMD_ADDR));
control_area.response_size = read32(CRB_REG(cur_loc, CRB_REG_RESP_SIZE));
control_area.response_bfr =
(void *)(uint32_t)read64(CRB_REG(cur_loc, CRB_REG_RESP_ADDR));
(void *)(uintptr_t)read64(CRB_REG(cur_loc, CRB_REG_RESP_ADDR));
}

/* Wait for Reg to be expected Value */
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/crb/tpm.h
View file
Expand Up @@ -6,7 +6,7 @@
#define TPM_CRB_BASE_ADDRESS CONFIG_CRB_TPM_BASE_ADDRESS

#define CRB_REG(LOCTY, REG) \
(void *)(CONFIG_CRB_TPM_BASE_ADDRESS + (LOCTY << 12) + REG)
(void *)(uintptr_t)(CONFIG_CRB_TPM_BASE_ADDRESS + (LOCTY << 12) + REG)

/* hardware registers */
#define CRB_REG_LOC_STATE 0x00
Expand Down
12 changes: 3 additions & 9 deletions src/drivers/emulation/qemu/bochs.c
View file
@@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#include <stdint.h>
#include <edid.h>
#include <arch/io.h>
#include <console/console.h>
#include <device/device.h>
Expand All @@ -10,6 +9,7 @@
#include <device/pci_ids.h>
#include <pc80/vga.h>
#include <pc80/vga_io.h>
#include <framebuffer_info.h>

/* VGA init. We use the Bochs VESA VBE extensions */
#define VBE_DISPI_IOPORT_INDEX 0x01CE
Expand Down Expand Up @@ -82,7 +82,6 @@ static struct resource res_legacy = {

static void bochs_init_linear_fb(struct device *dev)
{
struct edid edid;
struct resource *res_fb, *res_io;
int id, mem, bar;

Expand Down Expand Up @@ -139,13 +138,8 @@ static void bochs_init_linear_fb(struct device *dev)

bochs_vga_write(res_io, 0, 0x20); /* disable blanking */

/* setup coreboot framebuffer */
edid.mode.ha = width;
edid.mode.va = height;
edid.panel_bits_per_color = 8;
edid.panel_bits_per_pixel = 24;
edid_set_framebuffer_bits_per_pixel(&edid, 32, 0);
set_vbe_mode_info_valid(&edid, res_fb->base);
/* Advertise new mode */
fb_add_framebuffer_info(res_fb->base, width, height, 4 * width, 32);
}

static void bochs_init_text_mode(struct device *dev)
Expand Down
10 changes: 2 additions & 8 deletions src/drivers/emulation/qemu/cirrus.c
View file
@@ -1,13 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */

#include <stdint.h>
#include <edid.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <pc80/vga.h>
#include <pc80/vga_io.h>
#include <framebuffer_info.h>

static int width = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_XRES;
static int height = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_YRES;
Expand Down Expand Up @@ -299,13 +299,7 @@ static void cirrus_init_linear_fb(struct device *dev)
vga_sr_write (CIRRUS_SR_EXTENDED_MODE, sr_ext);
write_hidden_dac (hidden_dac);

struct edid edid;
edid.mode.ha = width;
edid.mode.va = height;
edid.panel_bits_per_color = 8;
edid.panel_bits_per_pixel = 24;
edid_set_framebuffer_bits_per_pixel(&edid, 32, 0);
set_vbe_mode_info_valid(&edid, addr);
fb_add_framebuffer_info(addr, width, height, 4 * width, 32);
}

static void cirrus_init_text_mode(struct device *dev)
Expand Down
17 changes: 13 additions & 4 deletions src/drivers/genesyslogic/gl9755/gl9755.c
View file
Expand Up @@ -10,15 +10,24 @@
#include <device/pci_ids.h>
#include "gl9755.h"

static void gl9755_init(struct device *dev)
static void gl9755_enable(struct device *dev)
{
printk(BIOS_INFO, "GL9755: init\n");
pci_dev_init(dev);
uint32_t reg;

printk(BIOS_INFO, "GL9755: configure ASPM and LTR\n");

/* Set Vendor Config to be configurable */
pci_or_config32(dev, CFG, CFG_EN);

/* Set LTR value */
pci_write_config32(dev, LTR, NO_SNOOP_SCALE|NO_SNOOP_VALUE|SNOOP_SCALE|SNOOP_VALUE);

/* Adjust L1 exit latency to enable ASPM */
reg = pci_read_config32(dev, CFG2);
reg &= ~CFG2_LAT_L1_MASK;
reg |= CFG2_LAT_L1_64US;
pci_write_config32(dev, CFG2, reg);

/* Set Vendor Config to be non-configurable */
pci_and_config32(dev, CFG, ~CFG_EN);
}
Expand All @@ -28,7 +37,7 @@ static struct device_operations gl9755_ops = {
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.ops_pci = &pci_dev_ops_pci,
.init = gl9755_init,
.enable = gl9755_enable
};

static const unsigned short pci_device_ids[] = {
Expand Down
8 changes: 8 additions & 0 deletions src/drivers/genesyslogic/gl9755/gl9755.h
View file
@@ -1,11 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0-only */

#ifndef DRIVERS_GENESYSLOGIC_GL9755_H
#define DRIVERS_GENESYSLOGIC_GL9755_H

/* Definitions for Genesys Logic GL9755 */

#define CFG 0x800
#define CFG_EN 0x1
#define CFG2 0x48
#define CFG2_LAT_L1_MASK ((0x7 << 12) | (0x7 << 3))
#define CFG2_LAT_L1_64US ((0x6 << 12) | (0x6 << 3))
#define LTR 0x5C
#define SNOOP_VALUE 0x25
#define SNOOP_SCALE (0x3 << 10)
#define NO_SNOOP_VALUE (0x25 << 16)
#define NO_SNOOP_SCALE (0x3 << 26)

#endif /* DRIVERS_GENESYSLOGIC_GL9755_H */
15 changes: 15 additions & 0 deletions src/drivers/i2c/nct7802y/nct7802y.c
View file
Expand Up @@ -2,10 +2,24 @@

#include <console/console.h>
#include <device/device.h>
#include <types.h>

#include "nct7802y.h"
#include "chip.h"

static void nct7802y_init_sensors(struct device *const dev)
{
const struct drivers_i2c_nct7802y_config *const config = dev->chip_info;
unsigned int i;
u8 value = 0;

for (i = 0; i < NCT7802Y_RTD_CNT; ++i)
value |= MODE_SELECTION_RTDx(i, config->sensors.rtd[i]);
if (config->sensors.local_enable)
value |= MODE_SELECTION_LTD_EN;
nct7802y_write(dev, MODE_SELECTION, value);
}

static void nct7802y_init(struct device *const dev)
{
if (!dev->chip_info) {
Expand All @@ -15,6 +29,7 @@ static void nct7802y_init(struct device *const dev)
}

nct7802y_init_peci(dev);
nct7802y_init_sensors(dev);
nct7802y_init_fan(dev);
}

Expand Down
7 changes: 0 additions & 7 deletions src/drivers/i2c/nct7802y/nct7802y_fan.c
View file
Expand Up @@ -78,13 +78,6 @@ void nct7802y_init_fan(struct device *const dev)
init_fan(dev, &config->fan[i], i);
}

value = 0;
for (i = 0; i < NCT7802Y_RTD_CNT; ++i)
value |= MODE_SELECTION_RTDx(i, config->sensors.rtd[i]);
if (config->sensors.local_enable)
value |= MODE_SELECTION_LTD_EN;
nct7802y_write(dev, MODE_SELECTION, value);

switch (config->on_pecierror) {
case PECI_ERROR_KEEP:
value = CLOSE_LOOP_FAN_PECI_ERR_CURR;
Expand Down
55 changes: 32 additions & 23 deletions src/drivers/i2c/sx9324/registers.h
View file
Expand Up @@ -4,29 +4,6 @@
#error "define REGISTER(NAME) before including this file"
#endif

REGISTER(reg_gnrl_ctrl0);
REGISTER(reg_gnrl_ctrl1);

REGISTER(reg_afe_ctrl0);
REGISTER(reg_afe_ctrl1);
REGISTER(reg_afe_ctrl2);
REGISTER(reg_afe_ctrl3);
REGISTER(reg_afe_ctrl4);
REGISTER(reg_afe_ctrl5);
REGISTER(reg_afe_ctrl6);
REGISTER(reg_afe_ctrl7);
REGISTER(reg_afe_ctrl8);
REGISTER(reg_afe_ctrl9);

REGISTER(reg_prox_ctrl0);
REGISTER(reg_prox_ctrl1);
REGISTER(reg_prox_ctrl2);
REGISTER(reg_prox_ctrl3);
REGISTER(reg_prox_ctrl4);
REGISTER(reg_prox_ctrl5);
REGISTER(reg_prox_ctrl6);
REGISTER(reg_prox_ctrl7);

REGISTER(reg_adv_ctrl0);
REGISTER(reg_adv_ctrl1);
REGISTER(reg_adv_ctrl2);
Expand All @@ -48,3 +25,35 @@ REGISTER(reg_adv_ctrl17);
REGISTER(reg_adv_ctrl18);
REGISTER(reg_adv_ctrl19);
REGISTER(reg_adv_ctrl20);

REGISTER(reg_afe_ctrl0);
REGISTER(reg_afe_ctrl1);
REGISTER(reg_afe_ctrl2);
REGISTER(reg_afe_ctrl3);
REGISTER(reg_afe_ctrl4);
REGISTER(reg_afe_ctrl5);
REGISTER(reg_afe_ctrl6);
REGISTER(reg_afe_ctrl7);
REGISTER(reg_afe_ctrl8);
REGISTER(reg_afe_ctrl9);

REGISTER(reg_afe_ph0);
REGISTER(reg_afe_ph1);
REGISTER(reg_afe_ph2);
REGISTER(reg_afe_ph3);

REGISTER(reg_gnrl_ctrl0);
REGISTER(reg_gnrl_ctrl1);

REGISTER(reg_irq_msk);
REGISTER(reg_irq_cfg0);
REGISTER(reg_irq_cfg2);

REGISTER(reg_prox_ctrl0);
REGISTER(reg_prox_ctrl1);
REGISTER(reg_prox_ctrl2);
REGISTER(reg_prox_ctrl3);
REGISTER(reg_prox_ctrl4);
REGISTER(reg_prox_ctrl5);
REGISTER(reg_prox_ctrl6);
REGISTER(reg_prox_ctrl7);
3 changes: 1 addition & 2 deletions src/drivers/i2c/tpm/Kconfig
View file
Expand Up @@ -41,8 +41,7 @@ config DRIVER_TPM_I2C_ADDR
depends on I2C_TPM

config DRIVER_I2C_TPM_ACPI
depends on I2C_TPM
bool "Generate I2C TPM ACPI device"
bool "Generate I2C TPM ACPI device" if I2C_TPM
default y if ARCH_X86 && I2C_TPM
default n

Expand Down
1 change: 0 additions & 1 deletion src/drivers/intel/fsp1_1/Makefile.inc
View file
Expand Up @@ -18,7 +18,6 @@ romstage-y += raminit.c
romstage-y += romstage.c
romstage-$(CONFIG_MMA) += mma_core.c

ramstage-$(CONFIG_RUN_FSP_GOP) += fsp_gop.c
ramstage-y += fsp_relocate.c
ramstage-y += fsp_util.c
ramstage-y += hob.c
Expand Down
2 changes: 1 addition & 1 deletion src/drivers/intel/fsp1_1/cache_as_ram.S
View file
Expand Up @@ -132,7 +132,7 @@ CAR_init_done:
cmp $0, %eax
jne halt2

/* Setup bootloader stack */
/* Setup bootblock stack */
movl $_ecar_stack, %esp

/*
Expand Down
38 changes: 0 additions & 38 deletions src/drivers/intel/fsp1_1/fsp_gop.c
View file

This file was deleted.

4 changes: 2 additions & 2 deletions src/drivers/intel/fsp1_1/logo.c
View file
Expand Up @@ -13,8 +13,8 @@ const struct cbmem_entry *fsp_load_logo(UINT32 *logo_ptr, UINT32 *logo_size)
if (logo_entry) {
logo_buffer = cbmem_entry_start(logo_entry);
if (logo_buffer) {
*logo_size = cbfs_boot_load_file("logo.bmp", (void *)logo_buffer,
1 * MiB, CBFS_TYPE_RAW);
*logo_size = cbfs_load("logo.bmp", (void *)logo_buffer,
1 * MiB);
if (*logo_size)
*logo_ptr = (UINT32)logo_buffer;
}
Expand Down
23 changes: 23 additions & 0 deletions src/drivers/intel/fsp1_1/ramstage.c
View file
Expand Up @@ -5,6 +5,7 @@
#include <console/console.h>
#include <fsp/ramstage.h>
#include <fsp/util.h>
#include <framebuffer_info.h>
#include <lib.h>
#include <stage_cache.h>
#include <string.h>
Expand Down Expand Up @@ -116,6 +117,28 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
gfx_set_init_done(1);
#endif

if (CONFIG(RUN_FSP_GOP)) {
const EFI_GUID vbt_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID;
u32 *vbt_hob;

void *hob_list_ptr = get_hob_list();
vbt_hob = get_next_guid_hob(&vbt_guid, hob_list_ptr);
if (vbt_hob == NULL) {
printk(BIOS_ERR, "FSP_ERR: Graphics Data HOB is not present\n");
} else {
EFI_PEI_GRAPHICS_INFO_HOB *gop;

printk(BIOS_DEBUG, "FSP_DEBUG: Graphics Data HOB present\n");
gop = GET_GUID_HOB_DATA(vbt_hob);

fb_add_framebuffer_info(gop->FrameBufferBase,
gop->GraphicsMode.HorizontalResolution,
gop->GraphicsMode.VerticalResolution,
gop->GraphicsMode.PixelsPerScanLine * 4,
32);
}
}

display_hob_info(fsp_info_header);
soc_after_silicon_init();
}
Expand Down